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38 * EMX_TXD: Maximum number of Transmit Descriptors
39 * Valid Range: 256-4096 for others
41 * This value is the number of transmit descriptors allocated by the driver.
42 * Increasing this value allows the driver to queue more transmits. Each
43 * descriptor is 16 bytes.
44 * Since TDLEN should be multiple of 128bytes, the number of transmit
45 * desscriptors should meet the following condition.
46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
48 #define EMX_MIN_TXD 256
49 #define EMX_MAX_TXD 4096
50 #define EMX_DEFAULT_TXD 512
53 * EMX_RXD - Maximum number of receive Descriptors
54 * Valid Range: 256-4096 for others
56 * This value is the number of receive descriptors allocated by the driver.
57 * Increasing this value allows the driver to buffer more incoming packets.
58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
59 * descriptor. The maximum MTU size is 16110.
60 * Since TDLEN should be multiple of 128bytes, the number of transmit
61 * desscriptors should meet the following condition.
62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
64 #define EMX_MIN_RXD 256
65 #define EMX_MAX_RXD 4096
66 #define EMX_DEFAULT_RXD 512
69 * Receive Interrupt Delay Timer (Packet Timer)
72 * RDTR and RADV are deprecated; use ITR instead. They are only used to
73 * workaround hardware bug on certain 82573 based NICs.
75 #define EMX_RDTR_82573 32
78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
81 * RDTR and RADV are deprecated; use ITR instead. They are only used to
82 * workaround hardware bug on certain 82573 based NICs.
84 #define EMX_RADV_82573 64
87 * This parameter controls the duration of transmit watchdog timer.
89 #define EMX_TX_TIMEOUT 5
91 /* One for TX csum offloading desc, the other 2 are reserved */
92 #define EMX_TX_RESERVED 3
94 /* Large enough for 64K TSO segment */
95 #define EMX_TX_SPARE 33
97 #define EMX_TX_OACTIVE_MAX 64
99 /* Interrupt throttle rate */
100 #define EMX_DEFAULT_ITR 6000
102 /* Number of segments sent before writing to TX related registers */
103 #define EMX_DEFAULT_TXWREG 8
106 * This parameter controls whether or not autonegotation is enabled.
107 * 0 - Disable autonegotiation
108 * 1 - Enable autonegotiation
110 #define EMX_DO_AUTO_NEG 1
112 /* Tunables -- End */
114 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
115 ADVERTISE_10_FULL | \
116 ADVERTISE_100_HALF | \
117 ADVERTISE_100_FULL | \
120 #define EMX_AUTO_ALL_MODES 0
122 /* PHY master/slave setting */
123 #define EMX_MASTER_SLAVE e1000_ms_hw_default
126 * Micellaneous constants
128 #define EMX_VENDOR_ID 0x8086
130 #define EMX_BAR_MEM PCIR_BAR(0)
131 #define EMX_BAR_FLASH PCIR_BAR(1)
133 #define EMX_JUMBO_PBA 0x00000028
134 #define EMX_DEFAULT_PBA 0x00000030
135 #define EMX_SMARTSPEED_DOWNSHIFT 3
136 #define EMX_SMARTSPEED_MAX 15
137 #define EMX_MAX_INTR 10
139 #define EMX_MCAST_ADDR_MAX 128
140 #define EMX_FC_PAUSE_TIME 1000
141 #define EMX_EEPROM_APME 0x400;
144 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
145 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
146 * also optimize cache line size effect. H/W supports up to cache line size 128.
148 #define EMX_DBA_ALIGN 128
151 * Speed mode bit in TARC0.
152 * 82571EB/82572EI only, used to improve small packet transmit performance.
154 #define EMX_TARC_SPEED_MODE (1 << 21)
157 * Multiple TX queues arbitration count mask in TARC0/TARC1.
159 #define EMX_TARC_COUNT_MASK 0x7f
161 #define EMX_MAX_SCATTER 64
162 #define EMX_TSO_SIZE (IP_MAXPACKET + \
163 sizeof(struct ether_vlan_header))
164 #define EMX_MAX_SEGSIZE PAGE_SIZE
165 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */
167 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
170 * 82574 has a nonstandard address for EIAC
171 * and since its only used in MSIX, and in
172 * the em driver only 82574 uses MSIX we can
173 * solve it just using this define.
175 #define EMX_EIAC 0x000DC
177 #define EMX_NRSSRK 10
178 #define EMX_RSSRK_SIZE 4
179 #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \
180 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \
181 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \
182 key[(i) * EMX_RSSRK_SIZE + 3] << 24)
185 #define EMX_RETA_SIZE 4
186 #define EMX_RETA_RINGIDX_SHIFT 7
188 #define EMX_RDRTABLE_SIZE (EMX_NRETA * EMX_RETA_SIZE)
190 #define EMX_NRX_RING 2
191 #define EMX_NTX_RING 2
192 #define EMX_NSERIALIZE 5
194 typedef union e1000_rx_desc_extended emx_rxdesc_t;
196 #define rxd_bufaddr read.buffer_addr /* 64bits */
197 #define rxd_length wb.upper.length /* 16bits */
198 #define rxd_vlan wb.upper.vlan /* 16bits */
199 #define rxd_staterr wb.upper.status_error /* 32bits */
200 #define rxd_mrq wb.lower.mrq /* 32bits */
201 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */
203 #define EMX_RXDMRQ_RSSTYPE_MASK 0xf
204 #define EMX_RXDMRQ_NO_HASH 0
205 #define EMX_RXDMRQ_IPV4_TCP 1
206 #define EMX_RXDMRQ_IPV4 2
207 #define EMX_RXDMRQ_IPV6_TCP 3
208 #define EMX_RXDMRQ_IPV6 5
213 struct lwkt_serialize rx_serialize;
214 struct emx_softc *sc;
218 * Receive definitions
220 * we have an array of num_rx_desc rx_desc (handled by the
221 * controller), and paired with an array of rx_buffers
222 * (at rx_buffer_area).
223 * The next pair to check on receive is at offset next_rx_desc_to_check
225 emx_rxdesc_t *rx_desc;
226 uint32_t next_rx_desc_to_check;
228 struct emx_rxbuf *rx_buf;
230 bus_dmamap_t rx_sparemap;
233 * First/last mbuf pointers, for
234 * collecting multisegment RX packets.
240 unsigned long rx_pkts;
242 bus_dma_tag_t rx_desc_dtag;
243 bus_dmamap_t rx_desc_dmap;
244 bus_addr_t rx_desc_paddr;
248 struct lwkt_serialize tx_serialize;
249 struct emx_softc *sc;
250 struct ifaltq_subque *ifsq;
253 #define EMX_TX_RUNNING 100
254 #define EMX_TX_RUNNING_DEC 25
256 #define EMX_TXFLAG_TSO_PULLEX 0x1
257 #define EMX_TXFLAG_ENABLED 0x2
258 #define EMX_TXFLAG_FORCECTX 0x4
261 * Transmit definitions
263 * We have an array of num_tx_desc descriptors (handled
264 * by the controller) paired with an array of tx_buffers
265 * (at tx_buffer_area).
266 * The index of the next available descriptor is next_avail_tx_desc.
267 * The number of remaining tx_desc is num_tx_desc_avail.
269 struct e1000_tx_desc *tx_desc_base;
270 struct emx_txbuf *tx_buf;
271 uint32_t next_avail_tx_desc;
272 uint32_t next_tx_to_clean;
273 int num_tx_desc_avail;
275 bus_dma_tag_t txtag; /* dma tag for tx */
280 /* Saved csum offloading context information */
285 int csum_thlen; /* TSO */
286 int csum_mss; /* TSO */
287 int csum_pktlen; /* TSO */
289 uint32_t csum_txd_upper;
290 uint32_t csum_txd_lower;
295 * Variables used to reduce TX interrupt rate and
296 * number of device's TX ring write requests.
299 * Number of TX descriptors setup so far.
302 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
303 * in the last TX descriptor of the packet, and
304 * tx_nsegs will be reset to 0. So TX interrupt and
305 * TX ring write request should be generated roughly
306 * every tx_int_nsegs TX descriptors.
309 * Index of the TX descriptors which have RS bit set,
310 * i.e. DD bit will be set on this TX descriptor after
311 * the data of the TX descriptor are transfered to
312 * hardware's internal packet buffer. Only the TX
313 * descriptors listed in tx_dd[] will be checked upon
314 * TX interrupt. This array is used as circular ring.
316 * tx_dd_tail, tx_dd_head:
317 * Tail and head index of valid elements in tx_dd[].
318 * tx_dd_tail == tx_dd_head means there is no valid
319 * elements in tx_dd[]. tx_dd_tail points to the position
320 * which is one beyond the last valid element in tx_dd[].
321 * tx_dd_head points to the first valid element in
328 #define EMX_TXDD_MAX 64
329 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */
330 int tx_dd[EMX_TXDD_MAX];
332 struct ifsubq_watchdog tx_watchdog;
333 struct callout tx_gc_timer;
336 unsigned long tx_pkts;
337 unsigned long tso_segments;
338 unsigned long tso_ctx_reused;
341 bus_dma_tag_t tx_desc_dtag;
342 bus_dmamap_t tx_desc_dmap;
343 bus_addr_t tx_desc_paddr;
347 struct arpcom arpcom;
350 #define EMX_FLAG_SHARED_INTR 0x0001
351 #define EMX_FLAG_HAS_MGMT 0x0004
352 #define EMX_FLAG_HAS_AMT 0x0008
353 #define EMX_FLAG_HW_CTRL 0x0010
355 /* DragonFly operating-system-specific structures. */
356 struct e1000_osdep osdep;
359 bus_dma_tag_t parent_dtag;
361 struct resource *memory;
364 struct resource *flash;
367 struct resource *intr_res;
372 struct ifmedia media;
373 struct callout timer;
376 /* WOL register value */
379 /* Multicast array memory */
382 /* Info about the board itself */
385 uint16_t link_duplex;
387 int int_throttle_ceil;
389 struct lwkt_serialize main_serialize;
390 struct lwkt_serialize *serializes[EMX_NSERIALIZE];
394 struct emx_txdata tx_data[EMX_NTX_RING];
398 struct emx_rxdata rx_data[EMX_NRX_RING];
402 /* Misc stats maintained by the driver */
403 unsigned long rx_overruns;
405 struct e1000_hw_stats stats;
407 struct if_ringmap *rx_rmap;
408 struct if_ringmap *tx_rmap;
409 int rdr_table[EMX_RDRTABLE_SIZE];
423 #define EMX_IS_OACTIVE(tdata) \
424 ((tdata)->num_tx_desc_avail <= (tdata)->oact_tx_desc)
426 #define EMX_INC_TXDD_IDX(idx) \
428 if (++(idx) == EMX_TXDD_MAX) \
432 #endif /* !_IF_EMX_H_ */