2 * Copyright (c) 2010, LSI Corp.
4 * Author : Manjunath Ranganathaiah
5 * Support: freebsdraid@lsi.com
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of the <ORGANIZATION> nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/tws/tws_hdm.c,v 1.3 2007/05/09 04:16:32 mrangana Exp $
38 #include <dev/raid/tws/tws.h>
39 #include <dev/raid/tws/tws_services.h>
40 #include <dev/raid/tws/tws_hdm.h>
43 int tws_use_32bit_sgls=0;
44 extern u_int64_t mfa_base;
45 extern struct tws_request *tws_get_request(struct tws_softc *sc,
47 extern void tws_q_insert_tail(struct tws_softc *sc, struct tws_request *req,
49 extern struct tws_request * tws_q_remove_request(struct tws_softc *sc,
50 struct tws_request *req, u_int8_t q_type );
52 extern void tws_cmd_complete(struct tws_request *req);
53 extern void tws_print_stats(void *arg);
54 extern int tws_send_scsi_cmd(struct tws_softc *sc, int cmd);
55 extern int tws_set_param(struct tws_softc *sc, u_int32_t table_id,
56 u_int32_t param_id, u_int32_t param_size, void *data);
57 extern int tws_get_param(struct tws_softc *sc, u_int32_t table_id,
58 u_int32_t param_id, u_int32_t param_size, void *data);
59 extern void tws_reset(void *arg);
61 int tws_init_connect(struct tws_softc *sc, u_int16_t mc);
62 int tws_init_ctlr(struct tws_softc *sc);
63 int tws_submit_command(struct tws_softc *sc, struct tws_request *req);
64 void tws_nop_cmd(void *arg);
65 u_int16_t tws_poll4_response(struct tws_softc *sc, u_int64_t *mfa);
66 boolean tws_get_response(struct tws_softc *sc, u_int16_t *req_id,
68 boolean tws_ctlr_ready(struct tws_softc *sc);
69 void tws_turn_on_interrupts(struct tws_softc *sc);
70 void tws_turn_off_interrupts(struct tws_softc *sc);
71 boolean tws_ctlr_reset(struct tws_softc *sc);
72 void tws_assert_soft_reset(struct tws_softc *sc);
74 int tws_send_generic_cmd(struct tws_softc *sc, u_int8_t opcode);
75 void tws_fetch_aen(void *arg);
76 void tws_disable_db_intr(struct tws_softc *sc);
77 void tws_enable_db_intr(struct tws_softc *sc);
78 void tws_aen_synctime_with_host(struct tws_softc *sc);
79 void tws_init_obfl_q(struct tws_softc *sc);
80 void tws_display_ctlr_info(struct tws_softc *sc);
83 tws_init_ctlr(struct tws_softc *sc)
88 TWS_TRACE_DEBUG(sc, "entry", sc, sc->is64bit);
89 sc->obfl_q_overrun = false;
90 if ( tws_init_connect(sc, tws_queue_depth) )
92 TWS_TRACE_DEBUG(sc, "initConnect failed", 0, sc->is64bit);
99 regh = tws_read_reg(sc, TWS_I2O0_IOPOBQPH, 4);
100 regl = tws_read_reg(sc, TWS_I2O0_IOPOBQPL, 4);
101 reg = (((u_int64_t)regh) << 32) | regl;
102 TWS_TRACE_DEBUG(sc, "host outbound clenup",reg, regl);
103 if ( regh == TWS_FIFO_EMPTY32 )
108 tws_display_ctlr_info(sc);
109 tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4);
110 tws_turn_on_interrupts(sc);
115 tws_init_obfl_q(struct tws_softc *sc)
119 u_int32_t paddrh, paddrl, status;
121 TWS_TRACE_DEBUG(sc, "entry", 0, sc->obfl_q_overrun);
123 while ( i < tws_queue_depth ) {
124 if ( !sc->sense_bufs[i].posted ) {
125 paddr = sc->sense_bufs[i].hdr_pkt_phy;
126 paddrh = (u_int32_t)( paddr>>32);
127 paddrl = (u_int32_t) paddr;
128 tws_write_reg(sc, TWS_I2O0_HOBQPH, paddrh, 4);
129 tws_write_reg(sc, TWS_I2O0_HOBQPL, paddrl, 4);
131 status = tws_read_reg(sc, TWS_I2O0_STATUS, 4);
132 if ( status & TWS_BIT13 ) {
133 TWS_TRACE_DEBUG(sc, "OBFL Overrun", status, TWS_I2O0_STATUS);
134 sc->obfl_q_overrun = true;
137 sc->sense_bufs[i].posted = true;
142 if ( i == tws_queue_depth )
143 sc->obfl_q_overrun = false;
147 tws_init_connect(struct tws_softc *sc, u_int16_t mcreadits )
149 struct tws_request *req;
150 struct tws_cmd_init_connect *initc;
154 TWS_TRACE_DEBUG(sc, "entry", 0, mcreadits);
155 req = tws_get_request(sc, TWS_INTERNAL_CMD_REQ);
158 TWS_TRACE_DEBUG(sc, "no requests", 0, 0);
162 tws_swap16(0xbeef); /* just for test */
163 tws_swap32(0xdeadbeef); /* just for test */
164 tws_swap64(0xdeadbeef); /* just for test */
165 initc = &(req->cmd_pkt->cmd.pkt_g.init_connect);
166 /* req->cmd_pkt->hdr.header_desc.size_header = 128; */
168 initc->res1__opcode =
169 BUILD_RES__OPCODE(0, TWS_FW_CMD_INIT_CONNECTION);
171 initc->request_id = req->request_id;
172 initc->message_credits = mcreadits;
173 initc->features |= TWS_BIT_EXTEND;
174 if ( sc->is64bit && !tws_use_32bit_sgls )
175 initc->features |= TWS_64BIT_SG_ADDRESSES;
176 /* assuming set features is always on */
179 initc->fw_srl = sc->cinfo.working_srl = TWS_CURRENT_FW_SRL;
180 initc->fw_arch_id = 0;
181 initc->fw_branch = sc->cinfo.working_branch = 0;
182 initc->fw_build = sc->cinfo.working_build = 0;
184 req->error_code = tws_submit_command(sc, req);
185 reqid = tws_poll4_response(sc, &mfa);
186 if ( reqid != TWS_INVALID_REQID && reqid == req->request_id ) {
187 sc->cinfo.fw_on_ctlr_srl = initc->fw_srl;
188 sc->cinfo.fw_on_ctlr_branch = initc->fw_branch;
189 sc->cinfo.fw_on_ctlr_build = initc->fw_build;
190 sc->stats.reqs_out++;
191 lockmgr(&sc->gen_lock, LK_EXCLUSIVE);
192 req->state = TWS_REQ_STATE_FREE;
193 lockmgr(&sc->gen_lock, LK_RELEASE);
197 * REVISIT::If init connect fails we need to reset the ctlr
200 TWS_TRACE(sc, "unexpected req_id ", reqid, 0);
201 TWS_TRACE(sc, "INITCONNECT FAILED", reqid, 0);
208 tws_display_ctlr_info(struct tws_softc *sc)
211 uint8_t fw_ver[16], bios_ver[16], ctlr_model[16], num_phys=0;
214 error[0] = tws_get_param(sc, TWS_PARAM_PHYS_TABLE,
215 TWS_PARAM_CONTROLLER_PHYS_COUNT, 1, &num_phys);
216 error[1] = tws_get_param(sc, TWS_PARAM_VERSION_TABLE,
217 TWS_PARAM_VERSION_FW, 16, fw_ver);
218 error[2] = tws_get_param(sc, TWS_PARAM_VERSION_TABLE,
219 TWS_PARAM_VERSION_BIOS, 16, bios_ver);
220 error[3] = tws_get_param(sc, TWS_PARAM_VERSION_TABLE,
221 TWS_PARAM_CTLR_MODEL, 16, ctlr_model);
223 if ( !error[0] && !error[1] && !error[2] && !error[3] ) {
224 device_printf( sc->tws_dev,
225 "Controller details: Model %.16s, %d Phys, Firmware %.16s, BIOS %.16s\n",
226 ctlr_model, num_phys, fw_ver, bios_ver);
232 tws_send_generic_cmd(struct tws_softc *sc, u_int8_t opcode)
234 struct tws_request *req;
235 struct tws_cmd_generic *cmd;
237 TWS_TRACE_DEBUG(sc, "entry", sc, opcode);
238 req = tws_get_request(sc, TWS_INTERNAL_CMD_REQ);
241 TWS_TRACE_DEBUG(sc, "no requests", 0, 0);
245 cmd = &(req->cmd_pkt->cmd.pkt_g.generic);
246 bzero(cmd, sizeof(struct tws_cmd_generic));
247 /* req->cmd_pkt->hdr.header_desc.size_header = 128; */
248 req->cb = tws_cmd_complete;
250 cmd->sgl_off__opcode = BUILD_RES__OPCODE(0, opcode);
252 cmd->request_id = req->request_id;
253 cmd->host_id__unit = 0;
258 req->error_code = tws_submit_command(sc, req);
266 tws_submit_command(struct tws_softc *sc, struct tws_request *req)
268 u_int32_t regl, regh;
272 * mfa register read and write must be in order.
273 * Get the io_lock to protect against simultinous
276 lockmgr(&sc->io_lock, LK_EXCLUSIVE);
278 if ( sc->obfl_q_overrun ) {
282 #ifdef TWS_PULL_MODE_ENABLE
283 regh = (u_int32_t)(req->cmd_pkt_phy >> 32);
284 /* regh = regh | TWS_MSG_ACC_MASK; */
287 regl = (u_int32_t)req->cmd_pkt_phy;
288 regl = regl | TWS_BIT0;
291 regh = tws_read_reg(sc, TWS_I2O0_HIBQPH, 4);
294 regl = tws_read_reg(sc, TWS_I2O0_HIBQPL, 4);
298 lockmgr(&sc->io_lock, LK_RELEASE);
300 if ( mfa == TWS_FIFO_EMPTY ) {
301 TWS_TRACE_DEBUG(sc, "inbound fifo empty", mfa, 0);
304 * Generaly we should not get here.
305 * If the fifo was empty we can't do any thing much
308 return(TWS_REQ_ERR_PEND_NOMFA);
312 #ifndef TWS_PULL_MODE_ENABLE
313 for (int i=mfa; i<(sizeof(struct tws_command_packet)+ mfa -
314 sizeof( struct tws_command_header)); i++) {
316 bus_space_write_1(sc->bus_mfa_tag, sc->bus_mfa_handle,i,
317 ((u_int8_t *)&req->cmd_pkt->cmd)[i-mfa]);
322 if ( req->type == TWS_SCSI_IO_REQ ) {
323 lockmgr(&sc->q_lock, LK_EXCLUSIVE);
324 tws_q_insert_tail(sc, req, TWS_BUSY_Q);
325 lockmgr(&sc->q_lock, LK_RELEASE);
329 * mfa register read and write must be in order.
330 * Get the io_lock to protect against simultinous
333 lockmgr(&sc->io_lock, LK_EXCLUSIVE);
335 tws_write_reg(sc, TWS_I2O0_HIBQPH, regh, 4);
336 tws_write_reg(sc, TWS_I2O0_HIBQPL, regl, 4);
339 lockmgr(&sc->io_lock, LK_RELEASE);
341 return(TWS_REQ_SUBMIT_SUCCESS);
346 * returns true if the respose was available othewise, false.
347 * In the case of error the arg mfa will contain the address and
348 * req_id will be TWS_INVALID_REQID
351 tws_get_response(struct tws_softc *sc, u_int16_t *req_id, u_int64_t *mfa)
353 u_int64_t out_mfa=0, val=0;
354 struct tws_outbound_response out_res;
356 *req_id = TWS_INVALID_REQID;
357 out_mfa = (u_int64_t)tws_read_reg(sc, TWS_I2O0_HOBQPH, 4);
359 if ( out_mfa == TWS_FIFO_EMPTY32 ) {
363 out_mfa = out_mfa << 32;
364 val = tws_read_reg(sc, TWS_I2O0_HOBQPL, 4);
365 out_mfa = out_mfa | val;
367 out_res = *(struct tws_outbound_response *)&out_mfa;
369 if ( !out_res.not_mfa ) {
373 *req_id = out_res.request_id;
383 tws_poll4_response(struct tws_softc *sc, u_int64_t *mfa)
388 endt = TWS_LOCAL_TIME + TWS_POLL_TIMEOUT;
390 if(tws_get_response(sc, &req_id, mfa)) {
392 if ( req_id == TWS_INVALID_REQID ) {
393 TWS_TRACE_DEBUG(sc, "invalid req_id", 0, req_id);
394 return(TWS_INVALID_REQID);
398 } while (TWS_LOCAL_TIME <= endt);
399 TWS_TRACE_DEBUG(sc, "poll timeout", 0, 0);
400 return(TWS_INVALID_REQID);
404 tws_ctlr_ready(struct tws_softc *sc)
408 reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);
409 if ( reg & TWS_BIT13 )
416 tws_turn_on_interrupts(struct tws_softc *sc)
419 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
420 /* turn on responce and db interrupt only */
421 tws_write_reg(sc, TWS_I2O0_HIMASK, TWS_BIT0, 4);
426 tws_turn_off_interrupts(struct tws_softc *sc)
429 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
431 tws_write_reg(sc, TWS_I2O0_HIMASK, ~0, 4);
436 tws_disable_db_intr(struct tws_softc *sc)
440 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
441 reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);
442 reg = reg | TWS_BIT2;
443 tws_write_reg(sc, TWS_I2O0_HIMASK, reg, 4);
447 tws_enable_db_intr(struct tws_softc *sc)
451 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
452 reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);
453 reg = reg & ~TWS_BIT2;
454 tws_write_reg(sc, TWS_I2O0_HIMASK, reg, 4);
458 tws_ctlr_reset(struct tws_softc *sc)
465 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
467 tws_assert_soft_reset(sc);
470 reg = tws_read_reg(sc, TWS_I2O0_SCRPD3, 4);
471 } while ( reg & TWS_BIT13 );
473 endt = TWS_LOCAL_TIME + TWS_RESET_TIMEOUT;
475 if(tws_ctlr_ready(sc))
477 } while (TWS_LOCAL_TIME <= endt);
483 tws_assert_soft_reset(struct tws_softc *sc)
487 reg = tws_read_reg(sc, TWS_I2O0_HIBDB, 4);
488 TWS_TRACE_DEBUG(sc, "in bound door bell read ", reg, TWS_I2O0_HIBDB);
489 tws_write_reg(sc, TWS_I2O0_HIBDB, reg | TWS_BIT8, 4);
494 tws_fetch_aen(void *arg)
496 struct tws_softc *sc = (struct tws_softc *)arg;
499 TWS_TRACE_DEBUG(sc, "entry", 0, 0);
501 if ((error = tws_send_scsi_cmd(sc, 0x03 /* REQUEST_SENSE */))) {
502 TWS_TRACE_DEBUG(sc, "aen fetch send in progress", 0, 0);
507 tws_aen_synctime_with_host(struct tws_softc *sc)
513 TWS_TRACE_DEBUG(sc, "entry", sc, 0);
515 sync_time = (TWS_LOCAL_TIME - (3 * 86400)) % 604800;
516 TWS_TRACE_DEBUG(sc, "sync_time,ts", sync_time, time_second);
517 TWS_TRACE_DEBUG(sc, "utc_offset", utc_offset(), 0);
518 error = tws_set_param(sc, TWS_PARAM_TIME_TABLE, TWS_PARAM_TIME_SCHED_TIME,
521 TWS_TRACE_DEBUG(sc, "set param failed", sync_time, error);
524 TUNABLE_INT("hw.tws.use_32bit_sgls", &tws_use_32bit_sgls);