gitweb.dragonflybsd.org Git - dragonfly.git/blob - sys/platform/vkernel64/x86

1 /*

4 *

5 * This code is derived from software contributed to The DragonFly Project

6 * by Matthew Dillon <dillon@backplane.com>

7 *

8 * Redistribution and use in source and binary forms, with or without

9 * modification, are permitted provided that the following conditions

10 * are met:

11 *

12 * 1. Redistributions of source code must retain the above copyright

13 * notice, this list of conditions and the following disclaimer.

14 * 2. Redistributions in binary form must reproduce the above copyright

15 * notice, this list of conditions and the following disclaimer in

16 * the documentation and/or other materials provided with the

17 * distribution.

18 * 3. Neither the name of The DragonFly Project nor the names of its

19 * contributors may be used to endorse or promote products derived

20 * from this software without specific, prior written permission.

21 *

22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,

27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,

28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT

32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

33 * SUCH DAMAGE.

34 *

37 *

38 * This code is derived from software contributed to Berkeley by

39 * William Jolitz.

40 *

41 * Redistribution and use in source and binary forms, with or without

42 * modification, are permitted provided that the following conditions

43 * are met:

44 * 1. Redistributions of source code must retain the above copyright

45 * notice, this list of conditions and the following disclaimer.

46 * 2. Redistributions in binary form must reproduce the above copyright

47 * notice, this list of conditions and the following disclaimer in the

48 * documentation and/or other materials provided with the distribution.

49 * 3. Neither the name of the University nor the names of its contributors

50 * may be used to endorse or promote products derived from this software

51 * without specific prior written permission.

52 *

53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND

54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE

57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS

59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)

60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT

61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY

62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

63 * SUCH DAMAGE.

64 *

65 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $

66 */

67

68 #include <sys/rtprio.h>

69

70 #include <machine/asmacros.h>

71 #include <machine/segments.h>

72

73 #include <machine/pmap.h>

74 #include <machine/lock.h>

75

76 #define CHECKNZ(expr, scratch_reg) \

77 movq expr, scratch_reg; testq scratch_reg, scratch_reg; jnz 7f; int $3; 7:

78

79 #include "assym.s"

80

81 #define MPLOCKED lock ;

82

83 .data

84

85 .globl panic

86 .globl lwkt_switch_return

87

88 #if defined(SWTCH_OPTIM_STATS)

89 .globl swtch_optim_stats, tlb_flush_count

90 swtch_optim_stats: .long 0 /* number of _swtch_optims */

91 tlb_flush_count: .long 0

92 #endif

93

94 .text

95

96

97 /*

98 * cpu_heavy_switch(struct thread *next_thread)

99 *

100 * Switch from the current thread to a new thread. This entry

101 * is normally called via the thread->td_switch function, and will

102 * only be called when the current thread is a heavy weight process.

103 *

104 * Some instructions have been reordered to reduce pipeline stalls.

105 *

106 * YYY disable interrupts once giant is removed.

107 */

108 ENTRY(cpu_heavy_switch)

109 /*

110 * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15).

111 */

112 movq PCPU(curthread),%rcx

113 /* On top of the stack is the return adress. */

114 movq (%rsp),%rax /* (reorder optimization) */

115 movq TD_PCB(%rcx),%rdx /* RDX = PCB */

116 movq %rax,PCB_RIP(%rdx) /* return PC may be modified */

117 movq %rbx,PCB_RBX(%rdx)

118 movq %rsp,PCB_RSP(%rdx)

119 movq %rbp,PCB_RBP(%rdx)

120 movq %r12,PCB_R12(%rdx)

121 movq %r13,PCB_R13(%rdx)

122 movq %r14,PCB_R14(%rdx)

123 movq %r15,PCB_R15(%rdx)

124

125 /*

126 * Clear the cpu bit in the pmap active mask. The restore

127 * function will set the bit in the pmap active mask.

128 *

129 * Special case: when switching between threads sharing the

130 * same vmspace if we avoid clearing the bit we do not have

131 * to reload %cr3 (if we clear the bit we could race page

132 * table ops done by other threads and would have to reload

133 * %cr3, because those ops will not know to IPI us).

134 */

135 movq %rcx,%rbx /* RBX = oldthread */

136 movq TD_LWP(%rcx),%rcx /* RCX = oldlwp */

137 movq TD_LWP(%rdi),%r13 /* R13 = newlwp */

138 movq LWP_VMSPACE(%rcx), %rcx /* RCX = oldvmspace */

139 testq %r13,%r13 /* might not be a heavy */

140 jz 1f

141 cmpq LWP_VMSPACE(%r13),%rcx /* same vmspace? */

142 je 2f

143 1:

144 movq PCPU(other_cpus)+0, %rax

145 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+0(%rcx)

146 movq PCPU(other_cpus)+8, %rax

147 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+8(%rcx)

148 movq PCPU(other_cpus)+16, %rax

149 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+16(%rcx)

150 movq PCPU(other_cpus)+24, %rax

151 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+24(%rcx)

152 2:

153

154 /*

155 * Push the LWKT switch restore function, which resumes a heavy

156 * weight process. Note that the LWKT switcher is based on

157 * TD_SP, while the heavy weight process switcher is based on

158 * PCB_RSP. TD_SP is usually two ints pushed relative to

159 * PCB_RSP. We push the flags for later restore by cpu_heavy_restore.

160 */

161 pushfq

162 movq $cpu_heavy_restore, %rax

163 pushq %rax

164 movq %rsp,TD_SP(%rbx)

165

166 /*

167 * Save debug regs if necessary

168 */

169 movq PCB_FLAGS(%rdx),%rax

170 andq $PCB_DBREGS,%rax

171 jz 1f /* no, skip over */

172 movq %dr7,%rax /* yes, do the save */

173 movq %rax,PCB_DR7(%rdx)

174 /* JG correct value? */

175 andq $0x0000fc00, %rax /* disable all watchpoints */

176 movq %rax,%dr7

177 movq %dr6,%rax

178 movq %rax,PCB_DR6(%rdx)

179 movq %dr3,%rax

180 movq %rax,PCB_DR3(%rdx)

181 movq %dr2,%rax

182 movq %rax,PCB_DR2(%rdx)

183 movq %dr1,%rax

184 movq %rax,PCB_DR1(%rdx)

185 movq %dr0,%rax

186 movq %rax,PCB_DR0(%rdx)

187 1:

188

189 #if 1

190 /*

191 * Save the FP state if we have used the FP. Note that calling

192 * npxsave will NULL out PCPU(npxthread).

193 */

194 cmpq %rbx,PCPU(npxthread)

195 jne 1f

196 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */

197 movq TD_SAVEFPU(%rbx),%rdi

198 call npxsave /* do it in a big C function */

199 movq %r12,%rdi /* restore %rdi */

200 1:

201 #endif

202

203 /*

204 * Switch to the next thread, which was passed as an argument

205 * to cpu_heavy_switch(). The argument is in %rdi.

206 * Set the current thread, load the stack pointer,

207 * and 'ret' into the switch-restore function.

208 *

209 * The switch restore function expects the new thread to be in %rax

210 * and the old one to be in %rbx.

211 *

212 * There is a one-instruction window where curthread is the new

213 * thread but %rsp still points to the old thread's stack, but

214 * we are protected by a critical section so it is ok.

215 */

216 movq %rdi,%rax /* RAX = newtd, RBX = oldtd */

217 movq %rax,PCPU(curthread)

218 movq TD_SP(%rax),%rsp

219 CHECKNZ((%rsp), %r9)

220 ret

221 END(cpu_heavy_switch)

222

223 /*

224 * cpu_exit_switch(struct thread *next)

225 *

226 * The switch function is changed to this when a thread is going away

227 * for good. We have to ensure that the MMU state is not cached, and

228 * we don't bother saving the existing thread state before switching.

229 *

230 * At this point we are in a critical section and this cpu owns the

231 * thread's token, which serves as an interlock until the switchout is

232 * complete.

233 */

234 ENTRY(cpu_exit_switch)

235 /*

236 * Get us out of the vmspace

237 */

238 #if 0

239 movq KPML4phys,%rcx

240 movq %cr3,%rax

241 cmpq %rcx,%rax

242 je 1f

243 /* JG no increment of statistics counters? see cpu_heavy_restore */

244 movq %rcx,%cr3

245 1:

246 #endif

247 movq PCPU(curthread),%rbx

248

249 /*

250 * If this is a process/lwp, deactivate the pmap after we've

251 * switched it out.

252 */

253 movq TD_LWP(%rbx),%rcx

254 testq %rcx,%rcx

255 jz 2f

256 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */

257 movq PCPU(other_cpus)+0, %rax

258 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+0(%rcx)

259 movq PCPU(other_cpus)+8, %rax

260 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+8(%rcx)

261 movq PCPU(other_cpus)+16, %rax

262 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+16(%rcx)

263 movq PCPU(other_cpus)+24, %rax

264 MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE+24(%rcx)

265 2:

266 /*

267 * Switch to the next thread. RET into the restore function, which

268 * expects the new thread in RAX and the old in RBX.

269 *

270 * There is a one-instruction window where curthread is the new

271 * thread but %rsp still points to the old thread's stack, but

272 * we are protected by a critical section so it is ok.

273 */

274 movq %rdi,%rax

275 movq %rax,PCPU(curthread)

276 movq TD_SP(%rax),%rsp

277 CHECKNZ((%rsp), %r9)

278 ret

279 END(cpu_exit_switch)

280

281 /*

282 * cpu_heavy_restore() (current thread in %rax on entry, %rbx is old thread)

283 *

284 * Restore the thread after an LWKT switch. This entry is normally

285 * called via the LWKT switch restore function, which was pulled

286 * off the thread stack and jumped to.

287 *

288 * This entry is only called if the thread was previously saved

289 * using cpu_heavy_switch() (the heavy weight process thread switcher),

290 * or when a new process is initially scheduled.

291 *

292 * NOTE: The lwp may be in any state, not necessarily LSRUN, because

293 * a preemption switch may interrupt the process and then return via

294 * cpu_heavy_restore.

295 *

296 * YYY theoretically we do not have to restore everything here, a lot

297 * of this junk can wait until we return to usermode. But for now

298 * we restore everything.

299 *

300 * YYY the PCB crap is really crap, it makes startup a bitch because

301 * we can't switch away.

302 *

303 * YYY note: spl check is done in mi_switch when it splx()'s.

304 */

305

306 ENTRY(cpu_heavy_restore)

307 popfq

308 movq TD_PCB(%rax),%rdx /* RDX = PCB */

309

310 #if defined(SWTCH_OPTIM_STATS)

311 incl _swtch_optim_stats

312 #endif

313 /*

314 * Tell the pmap that our cpu is using the VMSPACE now. We cannot

315 * safely test/reload %cr3 until after we have set the bit in the

316 * pmap (remember, we do not hold the MP lock in the switch code).

317 */

318 movq TD_LWP(%rax),%rcx

319 movq LWP_VMSPACE(%rcx), %rcx /* RCX = vmspace */

320

321 movq PCPU(cpumask)+0, %rsi

322 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+0(%rcx)

323 movq PCPU(cpumask)+8, %rsi

324 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+8(%rcx)

325 movq PCPU(cpumask)+16, %rsi

326 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+16(%rcx)

327 movq PCPU(cpumask)+24, %rsi

328 MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE+24(%rcx)

329

330 movl VM_PMAP+PM_ACTIVE_LOCK(%rcx),%esi

331 testl $CPULOCK_EXCL,%esi

332 jz 1f

333

334 movq %rax,%r12 /* save newthread ptr */

335 movq %rcx,%rdi /* (found to be set) */

336 call pmap_interlock_wait /* pmap_interlock_wait(%rdi:vm) */

337 movq %r12,%rax

338 movq TD_PCB(%rax),%rdx /* RDX = PCB */

339 1:

340 /*

341 * Restore the MMU address space. If it is the same as the last

342 * thread we don't have to invalidate the tlb (i.e. reload cr3).

343 * YYY which naturally also means that the PM_ACTIVE bit had better

344 * already have been set before we set it above, check? YYY

345 */

346 #if 0

347 movq %cr3,%rsi

348 movq PCB_CR3(%rdx),%rcx

349 cmpq %rsi,%rcx

350 je 4f

351 #if defined(SWTCH_OPTIM_STATS)

352 decl _swtch_optim_stats

353 incl _tlb_flush_count

354 #endif

355 movq %rcx,%cr3

356 4:

357 #endif

358 /*

359 * NOTE: %rbx is the previous thread and %rax is the new thread.

360 * %rbx is retained throughout so we can return it.

361 *

362 * lwkt_switch[_return] is responsible for handling TDF_RUNNING.

363 */

364

365 #if 0

366 /*

367 * Deal with the PCB extension, restore the private tss

368 */

369 movq PCB_EXT(%rdx),%rdi /* check for a PCB extension */

370 movq $1,%rcx /* maybe mark use of a private tss */

371 testq %rdi,%rdi

372 #if 0 /* JG */

373 jnz 2f

374 #endif

375

376 /* JG

377 * Going back to the common_tss. We may need to update TSS_ESP0

378 * which sets the top of the supervisor stack when entering from

379 * usermode. The PCB is at the top of the stack but we need another

380 * 16 bytes to take vm86 into account.

381 */

382 leaq -16(%rdx),%rcx

383 movq %rcx, PCPU(common_tss) + TSS_RSP0

384 movq %rcx, PCPU(rsp0)

385

386 #if 0 /* JG */

387 cmpl $0,PCPU(private_tss) /* don't have to reload if */

388 je 3f /* already using the common TSS */

389

390 /* JG? */

391 subq %rcx,%rcx /* unmark use of private tss */

392

393 /*

394 * Get the address of the common TSS descriptor for the ltr.

395 * There is no way to get the address of a segment-accessed variable

396 * so we store a self-referential pointer at the base of the per-cpu

397 * data area and add the appropriate offset.

398 */

399 /* JG movl? */

400 movq $gd_common_tssd, %rdi

401 /* JG name for "%gs:0"? */

402 addq %gs:0, %rdi

403

404 /*

405 * Move the correct TSS descriptor into the GDT slot, then reload

406 * ltr.

407 */

408 2:

409 /* JG */

410 movl %rcx,PCPU(private_tss) /* mark/unmark private tss */

411 movq PCPU(tss_gdt), %rcx /* entry in GDT */

412 movq 0(%rdi), %rax

413 movq %rax, 0(%rcx)

414 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */

415 ltr %si

416 #endif

417

418 3:

419 #endif

420 #if 0

421 /*

422 * Restore the user %gs and %fs

423 */

424 movq PCB_FSBASE(%rdx),%r9

425 cmpq PCPU(user_fs),%r9

426 je 4f

427 movq %rdx,%r10

428 movq %r9,PCPU(user_fs)

429 movl $MSR_FSBASE,%ecx

430 movl PCB_FSBASE(%r10),%eax

431 movl PCB_FSBASE+4(%r10),%edx

432 wrmsr

433 movq %r10,%rdx

434 4:

435 movq PCB_GSBASE(%rdx),%r9

436 cmpq PCPU(user_gs),%r9

437 je 5f

438 movq %rdx,%r10

439 movq %r9,PCPU(user_gs)

440 movl $MSR_KGSBASE,%ecx /* later swapgs moves it to GSBASE */

441 movl PCB_GSBASE(%r10),%eax

442 movl PCB_GSBASE+4(%r10),%edx

443 wrmsr

444 movq %r10,%rdx

445 5:

446 #endif

447

448 /*

449 * Restore general registers. %rbx is restored later.

450 */

451 movq PCB_RSP(%rdx), %rsp

452 movq PCB_RBP(%rdx), %rbp

453 movq PCB_R12(%rdx), %r12

454 movq PCB_R13(%rdx), %r13

455 movq PCB_R14(%rdx), %r14

456 movq PCB_R15(%rdx), %r15

457 movq PCB_RIP(%rdx), %rax

458 movq %rax, (%rsp)

459

460 #if 0

461 /*

462 * Restore the user LDT if we have one

463 */

464 cmpl $0, PCB_USERLDT(%edx)

465 jnz 1f

466 movl _default_ldt,%eax

467 cmpl PCPU(currentldt),%eax

468 je 2f

469 lldt _default_ldt

470 movl %eax,PCPU(currentldt)

471 jmp 2f

472 1: pushl %edx

473 call set_user_ldt

474 popl %edx

475 2:

476 #endif

477 #if 0

478 /*

479 * Restore the user TLS if we have one

480 */

481 pushl %edx

482 call set_user_TLS

483 popl %edx

484 #endif

485

486 /*

487 * Restore the DEBUG register state if necessary.

488 */

489 movq PCB_FLAGS(%rdx),%rax

490 andq $PCB_DBREGS,%rax

491 jz 1f /* no, skip over */

492 movq PCB_DR6(%rdx),%rax /* yes, do the restore */

493 movq %rax,%dr6

494 movq PCB_DR3(%rdx),%rax

495 movq %rax,%dr3

496 movq PCB_DR2(%rdx),%rax

497 movq %rax,%dr2

498 movq PCB_DR1(%rdx),%rax

499 movq %rax,%dr1

500 movq PCB_DR0(%rdx),%rax

501 movq %rax,%dr0

502 movq %dr7,%rax /* load dr7 so as not to disturb */

503 /* JG correct value? */

504 andq $0x0000fc00,%rax /* reserved bits */

505 /* JG we've got more registers on x86_64 */

506 movq PCB_DR7(%rdx),%rcx

507 /* JG correct value? */

508 andq $~0x0000fc00,%rcx

509 orq %rcx,%rax

510 movq %rax,%dr7

511 1:

512 movq %rbx,%rax

513 movq PCB_RBX(%rdx),%rbx

514

515 CHECKNZ((%rsp), %r9)

516 ret

517 END(cpu_heavy_restore)

518

519 /*

520 * savectx(struct pcb *pcb)

521 *

522 * Update pcb, saving current processor state.

523 */

524 ENTRY(savectx)

525 /* fetch PCB */

526 /* JG use %rdi instead of %rcx everywhere? */

527 movq %rdi,%rcx

528

529 /* caller's return address - child won't execute this routine */

530 movq (%rsp),%rax

531 movq %rax,PCB_RIP(%rcx)

532 movq %rbx,PCB_RBX(%rcx)

533 movq %rsp,PCB_RSP(%rcx)

534 movq %rbp,PCB_RBP(%rcx)

535 movq %r12,PCB_R12(%rcx)

536 movq %r13,PCB_R13(%rcx)

537 movq %r14,PCB_R14(%rcx)

538 movq %r15,PCB_R15(%rcx)

539

540 #if 1

541 /*

542 * If npxthread == NULL, then the npx h/w state is irrelevant and the

543 * state had better already be in the pcb. This is true for forks

544 * but not for dumps (the old book-keeping with FP flags in the pcb

545 * always lost for dumps because the dump pcb has 0 flags).

546 *

547 * If npxthread != NULL, then we have to save the npx h/w state to

548 * npxthread's pcb and copy it to the requested pcb, or save to the

549 * requested pcb and reload. Copying is easier because we would

550 * have to handle h/w bugs for reloading. We used to lose the

551 * parent's npx state for forks by forgetting to reload.

552 */

553 movq PCPU(npxthread),%rax

554 testq %rax,%rax

555 jz 1f

556

557 pushq %rcx /* target pcb */

558 movq TD_SAVEFPU(%rax),%rax /* originating savefpu area */

559 pushq %rax

560

561 movq %rax,%rdi

562 call npxsave

563

564 popq %rax

565 popq %rcx

566

567 movq $PCB_SAVEFPU_SIZE,%rdx

568 leaq PCB_SAVEFPU(%rcx),%rcx

569 movq %rcx,%rsi

570 movq %rax,%rdi

571 call bcopy

572 #endif

573

574 1:

575 CHECKNZ((%rsp), %r9)

576 ret

577 END(savectx)

578

579 /*

580 * cpu_idle_restore() (current thread in %rax on entry) (one-time execution)

581 * (old thread is %rbx on entry)

582 *

583 * Don't bother setting up any regs other than %rbp so backtraces

584 * don't die. This restore function is used to bootstrap into the

585 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for

586 * switching.

587 *

588 * Clear TDF_RUNNING in old thread only after we've cleaned up %cr3.

589 * This only occurs during system boot so no special handling is

590 * required for migration.

591 *

592 * If we are an AP we have to call ap_init() before jumping to

593 * cpu_idle(). ap_init() will synchronize with the BP and finish

594 * setting up various ncpu-dependant globaldata fields. This may

595 * happen on UP as well as SMP if we happen to be simulating multiple

596 * cpus.

597 */

598 ENTRY(cpu_idle_restore)

599 /* cli */

600 /* JG xor? */

601 movl $0,%ebp

602 /* JG push RBP? */

603 pushq $0

604 cmpl $0,PCPU(cpuid)

605 je 1f

606 andl $~TDF_RUNNING,TD_FLAGS(%rbx)

607 orl $TDF_RUNNING,TD_FLAGS(%rax) /* manual, no switch_return */

608 call ap_init

609 /* sti */

610 jmp cpu_idle

611

612 /*

613 * cpu 0's idle thread entry for the first time must use normal

614 * lwkt_switch_return() semantics or a pending cpu migration on

615 * thread0 will deadlock.

616 */

617 1:

618 pushq %rax

619 movq %rbx,%rdi

620 call lwkt_switch_return

621 popq %rax

622 jmp cpu_idle

623 END(cpu_idle_restore)

624

625 /*

626 * cpu_kthread_restore() (current thread is %rax on entry) (one-time execution)

627 * (old thread is %rbx on entry)

628 *

629 * Don't bother setting up any regs other then %rbp so backtraces

630 * don't die. This restore function is used to bootstrap into an

631 * LWKT based kernel thread only. cpu_lwkt_switch() will be used

632 * after this.

633 *

634 * Because this switch target does not 'return' to lwkt_switch()

635 * we have to call lwkt_switch_return(otd) to clean up otd.

636 * otd is in %ebx.

637 *

638 * Since all of our context is on the stack we are reentrant and

639 * we can release our critical section and enable interrupts early.

640 */

641 ENTRY(cpu_kthread_restore)

642 /*sti*/

643 movq TD_PCB(%rax),%r13

644 movq $0,%rbp

645

646 /*

647 * rax and rbx come from the switchout code. Call

648 * lwkt_switch_return(otd).

649 *

650 * NOTE: unlike i386, the %rsi and %rdi are not call-saved regs.

651 */

652 pushq %rax

653 movq %rbx,%rdi

654 call lwkt_switch_return

655 popq %rax

656 decl TD_CRITCOUNT(%rax)

657 movq PCB_R12(%r13),%rdi /* argument to RBX function */

658 movq PCB_RBX(%r13),%rax /* thread function */

659 /* note: top of stack return address inherited by function */

660 CHECKNZ(%rax, %r9)

661 jmp *%rax

662 END(cpu_kthread_restore)

663

664 /*

665 * cpu_lwkt_switch(struct thread *)

666 *

667 * Standard LWKT switching function. Only non-scratch registers are

668 * saved and we don't bother with the MMU state or anything else.

669 *

670 * This function is always called while in a critical section.

671 *

672 * There is a one-instruction window where curthread is the new

673 * thread but %rsp still points to the old thread's stack, but

674 * we are protected by a critical section so it is ok.

675 *

676 * YYY BGL, SPL

677 */

678 ENTRY(cpu_lwkt_switch)

679 pushq %rbp /* JG note: GDB hacked to locate ebp relative to td_sp */

680 /* JG we've got more registers on x86_64 */

681 pushq %rbx

682 movq PCPU(curthread),%rbx

683 pushq %r12

684 pushq %r13

685 pushq %r14

686 pushq %r15

687 pushfq

688

689 #if 1

690 /*

691 * Save the FP state if we have used the FP. Note that calling

692 * npxsave will NULL out PCPU(npxthread).

693 *

694 * We have to deal with the FP state for LWKT threads in case they

695 * happen to get preempted or block while doing an optimized

696 * bzero/bcopy/memcpy.

697 */

698 cmpq %rbx,PCPU(npxthread)

699 jne 1f

700 movq %rdi,%r12 /* save %rdi. %r12 is callee-saved */

701 movq TD_SAVEFPU(%rbx),%rdi

702 call npxsave /* do it in a big C function */

703 movq %r12,%rdi /* restore %rdi */

704 1:

705 #endif

706

707 movq %rdi,%rax /* switch to this thread */

708 pushq $cpu_lwkt_restore

709 movq %rsp,TD_SP(%rbx)

710 movq %rax,PCPU(curthread)

711 movq TD_SP(%rax),%rsp

712

713 /*

714 * %rax contains new thread, %rbx contains old thread.

715 */

716 CHECKNZ((%rsp), %r9)

717 ret

718 END(cpu_lwkt_switch)

719

720 /*

721 * cpu_lwkt_restore() (current thread in %rax on entry)

722 *

723 * Standard LWKT restore function. This function is always called

724 * while in a critical section.

725 *

726 * Warning: due to preemption the restore function can be used to

727 * 'return' to the original thread. Interrupt disablement must be

728 * protected through the switch so we cannot run splz here.

729 */

730 ENTRY(cpu_lwkt_restore)

731 /*

732 * NOTE: %rbx is the previous thread and %eax is the new thread.

733 * %rbx is retained throughout so we can return it.

734 *

735 * lwkt_switch[_return] is responsible for handling TDF_RUNNING.

736 */

737 movq %rbx,%rax

738 popfq

739 popq %r15

740 popq %r14

741 popq %r13

742 popq %r12

743 popq %rbx

744 popq %rbp

745 ret

746 END(cpu_lwkt_restore)

747

748 /*

749 * bootstrap_idle()

750 *

751 * Make AP become the idle loop.

752 */

753 ENTRY(bootstrap_idle)

754 movq PCPU(curthread),%rax

755 movq %rax,%rbx

756 movq TD_SP(%rax),%rsp

757 ret

758 END(bootstrap_idle)