/*- * Copyright (c) 1993 The Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: src/sys/i386/include/ipl.h,v 1.17.2.3 2002/12/17 18:04:02 sam Exp $ * $DragonFly: src/sys/i386/include/Attic/ipl.h,v 1.6 2005/06/16 21:12:46 dillon Exp $ */ #ifndef _MACHINE_IPL_H_ #define _MACHINE_IPL_H_ #ifdef APIC_IO #include #else #include #endif /* * Software interrupt bit numbers in priority order. The priority only * determines which swi will be dispatched next; a higher priority swi * may be dispatched when a nested h/w interrupt handler returns. */ #define SWI_TTY (NHWI + 0) #define SWI_NET (NHWI + 1) #define SWI_CAMNET (NHWI + 2) #define SWI_CRYPTO SWI_CAMNET #define SWI_CAMBIO (NHWI + 3) #define SWI_VM (NHWI + 4) #define SWI_TQ (NHWI + 5) #define SWI_CLOCK (NHWI + 6) #define NSWI 7 /* * Corresponding interrupt-pending bits for ipending. */ #define SWI_TTY_PENDING (1 << SWI_TTY) #define SWI_NET_PENDING (1 << SWI_NET) #define SWI_CAMNET_PENDING (1 << SWI_CAMNET) #define SWI_CRYPTO_PENDING SWI_CAMNET_PENDING #define SWI_CAMBIO_PENDING (1 << SWI_CAMBIO) #define SWI_VM_PENDING (1 << SWI_VM) #define SWI_TQ_PENDING (1 << SWI_TQ) #define SWI_CLOCK_PENDING (1 << SWI_CLOCK) #ifndef LOCORE #endif /* !LOCORE */ #endif /* !_MACHINE_IPL_H_ */