brgphy: Remove debug prints
[dragonfly.git] / sys / dev / netif / mii_layer / brgphy.c
index 1a1bc9b..b42c123 100644 (file)
@@ -54,9 +54,7 @@
 #include "mii.h"
 #include "miivar.h"
 #include "miidevs.h"
-
 #include "brgphyreg.h"
-#include <dev/netif/bge/if_bgereg.h>
 
 #include "miibus_if.h"
 
@@ -69,23 +67,37 @@ static const struct mii_phydesc brgphys[] = {
        MII_PHYDESC(xxBROADCOM, BCM5411),
        MII_PHYDESC(xxBROADCOM, BCM5421),
        MII_PHYDESC(xxBROADCOM, BCM54K2),
+       MII_PHYDESC(xxBROADCOM, BCM5461),
        MII_PHYDESC(xxBROADCOM, BCM5462),
+       MII_PHYDESC(xxBROADCOM, BCM5464),
 
        MII_PHYDESC(xxBROADCOM, BCM5701),
        MII_PHYDESC(xxBROADCOM, BCM5703),
        MII_PHYDESC(xxBROADCOM, BCM5704),
        MII_PHYDESC(xxBROADCOM, BCM5705),
-
        MII_PHYDESC(xxBROADCOM, BCM5714),
-       MII_PHYDESC(xxBROADCOM2,BCM5722),
        MII_PHYDESC(xxBROADCOM, BCM5750),
        MII_PHYDESC(xxBROADCOM, BCM5752),
-       MII_PHYDESC(xxBROADCOM2,BCM5755),
        MII_PHYDESC(xxBROADCOM, BCM5780),
+
+       MII_PHYDESC(xxBROADCOM2,BCM54XX),
+       MII_PHYDESC(xxBROADCOM2,BCM5481),
+       MII_PHYDESC(xxBROADCOM2,BCM5482),
+       MII_PHYDESC(xxBROADCOM2,BCM5722),
+       MII_PHYDESC(xxBROADCOM2,BCM5755),
+       MII_PHYDESC(xxBROADCOM2,BCM5761),
+       MII_PHYDESC(xxBROADCOM2,BCM5784),
        MII_PHYDESC(xxBROADCOM2,BCM5787),
 
        MII_PHYDESC(xxBROADCOM, BCM5706C),
        MII_PHYDESC(xxBROADCOM, BCM5708C),
+       MII_PHYDESC(xxBROADCOM2, BCM5709CAX),
+       MII_PHYDESC(xxBROADCOM2, BCM5709C),
+
+       MII_PHYDESC(xxBROADCOM3, BCM5717C),
+       MII_PHYDESC(xxBROADCOM3, BCM5719C),
+       MII_PHYDESC(xxBROADCOM3, BCM57765),
+       MII_PHYDESC(xxBROADCOM3, BCM57780),
 
        MII_PHYDESC(BROADCOM2, BCM5906),
 
@@ -127,6 +139,7 @@ static void brgphy_5704_a0_bug(struct mii_softc *);
 static void    brgphy_ber_bug(struct mii_softc *);
 static void    brgphy_crc_bug(struct mii_softc *);
 
+static void    brgphy_disable_early_dac(struct mii_softc *);
 static void    brgphy_jumbo_settings(struct mii_softc *, u_long);
 static void    brgphy_eth_wirespeed(struct mii_softc *);
 
@@ -258,8 +271,8 @@ setit:
                        }
 
                        PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
-                       PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
                        PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
+                       PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
 
                        if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
                                break;
@@ -319,10 +332,11 @@ setit:
 
                /*
                 * Check to see if we have link.  If we do, we don't
-                * need to restart the autonegotiation process.
+                * need to restart the autonegotiation process.  Read
+                * the BMSR twice in case it's latched.
                 */
-               reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
-               if (reg & BRGPHY_AUXSTS_LINK) {
+               reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
+               if (reg & BMSR_LINK) {
                        sc->mii_ticks = 0;
                        break;
                }
@@ -332,7 +346,7 @@ setit:
                 */
                if (++sc->mii_ticks <= sc->mii_anegticks)
                        break;
-               
+
                sc->mii_ticks = 0;
                brgphy_mii_phy_auto(sc);
                break;
@@ -369,13 +383,13 @@ static void
 brgphy_status(struct mii_softc *sc)
 {
        struct mii_data *mii = sc->mii_pdata;
-       int bmcr, aux;
+       int bmcr, bmsr;
 
        mii->mii_media_status = IFM_AVALID;
        mii->mii_media_active = IFM_ETHER;
 
-       aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
-       if (aux & BRGPHY_AUXSTS_LINK)
+       bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
+       if (bmsr & BRGPHY_BMSR_LINK)
                mii->mii_media_status |= IFM_ACTIVE;
 
        bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
@@ -383,13 +397,17 @@ brgphy_status(struct mii_softc *sc)
                mii->mii_media_active |= IFM_LOOP;
 
        if (bmcr & BRGPHY_BMCR_AUTOEN) {
-               if ((PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_ACOMP) == 0) {
+               int auxsts;
+
+               if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
                        /* Erg, still trying, I guess... */
                        mii->mii_media_active |= IFM_NONE;
                        return;
                }
 
-               switch (aux & BRGPHY_AUXSTS_AN_RES) {
+               auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS);
+
+               switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
                case BRGPHY_RES_1000FD:
                        mii->mii_media_active |= IFM_1000_T | IFM_FDX;
                        break;
@@ -412,6 +430,13 @@ brgphy_status(struct mii_softc *sc)
                        mii->mii_media_active |= IFM_10_T | IFM_HDX;
                        break;
                default:
+                       if (sc->mii_model == MII_MODEL_BROADCOM2_BCM5906) {
+                               mii->mii_media_active |= (auxsts &
+                                   BRGPHY_RES_100) ? IFM_100_TX : IFM_10_T;
+                               mii->mii_media_active |= (auxsts &
+                                   BRGPHY_RES_FULL) ? IFM_FDX : IFM_HDX;
+                               break;
+                       }
                        mii->mii_media_active |= IFM_NONE;
                        break;
                }
@@ -424,19 +449,21 @@ brgphy_status(struct mii_softc *sc)
 static void
 brgphy_mii_phy_auto(struct mii_softc *sc)
 {
-       int ktcr = 0;
+       int ktcr;
 
-       brgphy_loop(sc);
        brgphy_reset(sc);
+
+       PHY_WRITE(sc, BRGPHY_MII_ANAR,
+           BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
+       DELAY(1000);
+
        ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
        if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
                ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
        PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
        ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
        DELAY(1000);
-       PHY_WRITE(sc, BRGPHY_MII_ANAR,
-           BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
-       DELAY(1000);
+
        PHY_WRITE(sc, BRGPHY_MII_BMCR,
            BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
        PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
@@ -460,8 +487,6 @@ brgphy_loop(struct mii_softc *sc)
 static void
 brgphy_reset(struct mii_softc *sc)
 {
-       struct ifnet *ifp;
-
        mii_phy_reset(sc);
 
        switch (sc->mii_model) {
@@ -483,54 +508,50 @@ brgphy_reset(struct mii_softc *sc)
                break;
        }
 
-       ifp = sc->mii_pdata->mii_ifp;
-       if (strncmp(ifp->if_xname, "bge", 3) == 0) {
-               struct bge_softc *bge_sc = ifp->if_softc;
-
-               if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
-                       brgphy_adc_bug(sc);
-               if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
-                       brgphy_5704_a0_bug(sc);
-               if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) {
-                       brgphy_ber_bug(sc);
-               } else if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) {
-                       PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
-                       PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
-
-                       if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) {
-                               PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
-                               PHY_WRITE(sc, BRGPHY_TEST1,
-                                   BRGPHY_TEST1_TRIM_EN | 0x4);
-                       } else {
-                               PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
-                       }
+       if (sc->mii_privtag != MII_PRIVTAG_BRGPHY)
+               return;
 
-                       PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
+       if (sc->mii_priv & BRGPHY_FLAG_ADC_BUG)
+               brgphy_adc_bug(sc);
+       if (sc->mii_priv & BRGPHY_FLAG_5704_A0)
+               brgphy_5704_a0_bug(sc);
+       if (sc->mii_priv & BRGPHY_FLAG_BER_BUG) {
+               brgphy_ber_bug(sc);
+       } else if (sc->mii_priv & BRGPHY_FLAG_JITTER_BUG) {
+               PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
+               PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
+
+               if (sc->mii_priv & BRGPHY_FLAG_ADJUST_TRIM) {
+                       PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
+                       PHY_WRITE(sc, BRGPHY_TEST1,
+                           BRGPHY_TEST1_TRIM_EN | 0x4);
+               } else {
+                       PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
                }
-               if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
-                       brgphy_crc_bug(sc);
 
-               /* Set Jumbo frame settings in the PHY. */
-               brgphy_jumbo_settings(sc, ifp->if_mtu);
+               PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
+       }
+       if (sc->mii_priv & BRGPHY_FLAG_CRC_BUG)
+               brgphy_crc_bug(sc);
+       if (sc->mii_priv & BRGPHY_FLAG_NO_EARLYDAC)
+               brgphy_disable_early_dac(sc);
 
-               /* Enable Ethernet@Wirespeed */
-               if (bge_sc->bge_flags & BGE_FLAG_ETH_WIRESPEED)
-                       brgphy_eth_wirespeed(sc);
+       /* Set Jumbo frame settings in the PHY. */
+       brgphy_jumbo_settings(sc, sc->mii_pdata->mii_ifp->if_mtu);
 
-               /* Enable Link LED on Dell boxes */
-               if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
-                       PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 
-                       PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
-                               & ~BRGPHY_PHY_EXTCTL_3_LED);
-               }
+       /* Adjust output voltage */
+       if (sc->mii_priv & BRGPHY_FLAG_5906)
+               PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 
-               /* Adjust output voltage (From Linux driver) */
-               if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
-                       PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
-       } else if (strncmp(ifp->if_xname, "bce", 3) == 0) {
-               brgphy_ber_bug(sc);
-               brgphy_jumbo_settings(sc, ifp->if_mtu);
+       /* Enable Ethernet@Wirespeed */
+       if (sc->mii_priv & BRGPHY_FLAG_WIRESPEED)
                brgphy_eth_wirespeed(sc);
+
+       /* Enable Link LED on Dell boxes */
+       if (sc->mii_priv & BRGPHY_FLAG_NO_3LED) {
+               PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
+                   PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
+                   ~BRGPHY_PHY_EXTCTL_3_LED);
        }
 }
 
@@ -739,3 +760,14 @@ brgphy_eth_wirespeed(struct mii_softc *sc)
        val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
        PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
 }
+
+static void
+brgphy_disable_early_dac(struct mii_softc *sc)
+{
+       uint32_t val;
+
+       PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
+       val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
+       val &= ~(1 << 8);
+       PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
+}