ioapic: Fix destination setting.

Since the "destination mode" is physical, the "destination" should be
APIC ID instead of mask (set of processors).  Currently all interrupts
are delivered to CPU0 (BSP).

diff --git a/sys/platform/pc32/apic/apicreg.h b/sys/platform/pc32/apic/apicreg.h
index b2c56f2..df5e57c 100644 (file)
--- a/sys/platform/pc32/apic/apicreg.h
+++ b/sys/platform/pc32/apic/apicreg.h
@@ -808,6 +808,7 @@ typedef struct IOAPIC ioapic_t;
 #define IOART_HI_DEST_MASK     APIC_ID_MASK
 #define IOART_HI_DEST_RESV     ~APIC_ID_MASK
 #define IOART_HI_DEST_BROADCAST        IOART_HI_DEST_MASK      
+#define IOART_HI_DEST_SHIFT    24
 
 /*
  * Low 32 bit word

diff --git a/sys/platform/pc32/apic/mpapic.c b/sys/platform/pc32/apic/mpapic.c
index 598d622..ae5b105 100644 (file)
--- a/sys/platform/pc32/apic/mpapic.c
+++ b/sys/platform/pc32/apic/mpapic.c
@@ -561,7 +561,8 @@ io_apic_setup_intpin(int apic, int pin)
 
        vector = IDT_OFFSET + irq;                      /* IDT vec */
        target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
-       target |= IOART_HI_DEST_BROADCAST;
+       /* Deliver all interrupts to CPU0 (BSP) */
+       target |= (CPU_TO_ID(0) << IOART_HI_DEST_SHIFT) & IOART_HI_DEST_MASK;
        flags |= io_apic_read(apic, select) & IOART_RESV;
        io_apic_write(apic, select, flags | vector);
        io_apic_write(apic, select + 1, target);
@@ -621,7 +622,8 @@ ext_int_setup(int apic, int intr)
        if (apic_int_type(apic, intr) != 3)
                return -1;
 
-       target = IOART_HI_DEST_BROADCAST;
+       /* Deliver interrupts to CPU0 (BSP) */
+       target = (CPU_TO_ID(0) << IOART_HI_DEST_SHIFT) & IOART_HI_DEST_MASK;
        select = IOAPIC_REDTBL0 + (2 * intr);
        vector = IDT_OFFSET + intr;
        flags = DEFAULT_EXTINT_FLAGS;