bnx: Fix transmit hangs for 57766 and 57765 non-Ax chips
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Thu, 21 Mar 2013 08:49:41 +0000 (16:49 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Thu, 21 Mar 2013 08:49:41 +0000 (16:49 +0800)
For the 57766 and 57765 non-Ax chips, the PCIe Fast Training Sequence
(FTS) value needs to setup to prevent transmit hangs.

Obtained-from: tg3

sys/dev/netif/bge/if_bgereg.h
sys/dev/netif/bnx/if_bnx.c

index 8ff0912..cdb2cde 100644 (file)
 #define        BGE_CPMU_MUTEX_REQ              0x365C
 #define        BGE_CPMU_MUTEX_GNT              0x3660
 #define        BGE_CPMU_PHY_STRAP              0x3664
+#define BGE_CPMU_PADRNG_CTL            0x3668
 
 /* Central Power Management Unit (CPMU) register */
 #define        BGE_CPMU_CTRL_LINK_IDLE_MODE    0x00000200
 /* CPMU GPHY Strap register */
 #define        BGE_CPMU_PHY_STRAP_IS_SERDES    0x00000020
 
+/* CPMU Padring Control register */
+#define BGE_CPMU_PADRNG_CTL_RDIV2      0x00040000
+
 /*
  * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
  */
index 1c25ca0..4938791 100644 (file)
@@ -1097,6 +1097,11 @@ bnx_chipinit(struct bnx_softc *sc)
                        CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
                }
                if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
+                       /* Fix transmit hangs */
+                       val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
+                       val |= BGE_CPMU_PADRNG_CTL_RDIV2;
+                       CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
+
                        mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
                        val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;