{ 0, 0, 0, 0, NULL }
};
-
/****************************************************************************/
/* Supported Flash NVRAM device data. */
/****************************************************************************/
.name = "5709/5716 buffered flash (256kB)",
};
-
/****************************************************************************/
/* DragonFly device entry points. */
/****************************************************************************/
static devclass_t bce_devclass;
-
DECLARE_DUMMY_MODULE(if_bce);
MODULE_DEPEND(bce, miibus, 1, 1, 1);
DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
-
/****************************************************************************/
/* Device probe function. */
/* */
return ENXIO;
}
-
/****************************************************************************/
/* PCI Capabilities Probe Function. */
/* */
kprintf("\n");
}
-
/****************************************************************************/
/* PCI Capabilities Probe Function. */
/* */
}
}
-
/****************************************************************************/
/* Device attach function. */
/* */
return(rc);
}
-
/****************************************************************************/
/* Device detach function. */
/* */
return 0;
}
-
/****************************************************************************/
/* Device shutdown function. */
/* */
ifnet_deserialize_all(ifp);
}
-
/****************************************************************************/
/* Indirect register read. */
/* */
return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
}
-
/****************************************************************************/
/* Indirect register write. */
/* */
pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
}
-
/****************************************************************************/
/* Shared memory write. */
/* */
bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
}
-
/****************************************************************************/
/* Shared memory read. */
/* */
return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
}
-
/****************************************************************************/
/* Context memory write. */
/* */
}
}
-
/****************************************************************************/
/* PHY register read. */
/* */
return (val & 0xffff);
}
-
/****************************************************************************/
/* PHY register write. */
/* */
return 0;
}
-
/****************************************************************************/
/* MII bus status change. */
/* */
}
}
-
/****************************************************************************/
/* Acquire NVRAM lock. */
/* */
return 0;
}
-
/****************************************************************************/
/* Release NVRAM lock. */
/* */
return 0;
}
-
/****************************************************************************/
/* Enable NVRAM access. */
/* */
val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
}
-
/****************************************************************************/
/* Disable NVRAM access. */
/* */
val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
}
-
/****************************************************************************/
/* Read a dword (32 bits) from NVRAM. */
/* */
return rc;
}
-
/****************************************************************************/
/* Initialize NVRAM access. */
/* */
return rc;
}
-
/****************************************************************************/
/* Read an arbitrary range of data from NVRAM. */
/* */
return rc;
}
-
/****************************************************************************/
/* Verifies that NVRAM is accessible and contains valid data. */
/* */
return rc;
}
-
/****************************************************************************/
/* Identifies the current media type of the controller and sets the PHY */
/* address. */
}
}
-
static void
bce_destroy_tx_ring(struct bce_tx_ring *txr)
{
kfree(txr->tx_mbuf_ptr, M_DEVBUF);
}
-
static void
bce_destroy_rx_ring(struct bce_rx_ring *rxr)
{
kfree(rxr->rx_mbuf_paddr, M_DEVBUF);
}
-
/****************************************************************************/
/* Free any DMA memory owned by the driver. */
/* */
bus_dma_tag_destroy(sc->parent_tag);
}
-
/****************************************************************************/
/* Get DMA memory from the OS. */
/* */
*busaddr = segs->ds_addr;
}
-
static int
bce_create_tx_ring(struct bce_tx_ring *txr)
{
return 0;
}
-
static int
bce_create_rx_ring(struct bce_rx_ring *rxr)
{
return 0;
}
-
/****************************************************************************/
/* Allocate any DMA memory needed by the driver. */
/* */
return 0;
}
-
/****************************************************************************/
/* Firmware synchronization. */
/* */
return rc;
}
-
/****************************************************************************/
/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
/* */
REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
}
-
/****************************************************************************/
/* Load RISC processor firmware. */
/* */
REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
}
-
/****************************************************************************/
/* Starts the RISC processor. */
/* */
REG_WR_IND(sc, cpu_reg->mode, val);
}
-
/****************************************************************************/
/* Halts the RISC processor. */
/* */
REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
}
-
/****************************************************************************/
/* Start the RX CPU. */
/* */
bce_start_cpu(sc, &cpu_reg);
}
-
/****************************************************************************/
/* Initialize the RX CPU. */
/* */
/* Delay RXP start until initialization is complete. */
}
-
/****************************************************************************/
/* Initialize the TX CPU. */
/* */
bce_start_cpu(sc, &cpu_reg);
}
-
/****************************************************************************/
/* Initialize the TPAT CPU. */
/* */
bce_start_cpu(sc, &cpu_reg);
}
-
/****************************************************************************/
/* Initialize the CP CPU. */
/* */
bce_start_cpu(sc, &cpu_reg);
}
-
/****************************************************************************/
/* Initialize the COM CPU. */
/* */
bce_start_cpu(sc, &cpu_reg);
}
-
/****************************************************************************/
/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
/* */
bce_init_cp_cpu(sc);
}
-
/****************************************************************************/
/* Initialize context memory. */
/* */
return 0;
}
-
/****************************************************************************/
/* Fetch the permanent MAC address of the controller. */
/* */
}
}
-
/****************************************************************************/
/* Program the MAC address. */
/* */
REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
}
-
/****************************************************************************/
/* Stop the controller. */
/* */
sc->bce_coalchg_mask = 0;
}
-
static int
bce_reset(struct bce_softc *sc, uint32_t reset_code)
{
return rc;
}
-
static int
bce_chipinit(struct bce_softc *sc)
{
return 0;
}
-
/****************************************************************************/
/* Initialize the controller in preparation to send/receive traffic. */
/* */
return 0;
}
-
/****************************************************************************/
/* Encapsulate an mbuf cluster into the rx_bd chain. */
/* */
return 0;
}
-
static void
bce_setup_rxdesc_std(struct bce_rx_ring *rxr, uint16_t chain_prod,
uint32_t *prod_bseq)
rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
}
-
/****************************************************************************/
/* Initialize the TX context memory. */
/* */
}
}
-
/****************************************************************************/
/* Allocate memory and initialize the TX data structures. */
/* */
return(rc);
}
-
/****************************************************************************/
/* Free memory and clear the TX data structures. */
/* */
txr->used_tx_bd = 0;
}
-
/****************************************************************************/
/* Initialize the RX context memory. */
/* */
BCE_L2CTX_RX_NX_BDHADDR_LO, val);
}
-
/****************************************************************************/
/* Allocate memory and initialize the RX data structures. */
/* */
return(rc);
}
-
/****************************************************************************/
/* Free memory and clear the RX data structures. */
/* */
bzero(rxr->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
}
-
/****************************************************************************/
/* Set media options. */
/* */
return error;
}
-
/****************************************************************************/
/* Reports current media status. */
/* */
ifmr->ifm_status = mii->mii_media_status;
}
-
/****************************************************************************/
/* Handles PHY generated interrupt events. */
/* */
REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
}
-
/****************************************************************************/
/* Reads the receive consumer value from the status block (skipping over */
/* chain page pointer if necessary). */
return hw_cons;
}
-
/****************************************************************************/
/* Handles received frame interrupt events. */
/* */
rxr->rx_prod_bseq);
}
-
/****************************************************************************/
/* Reads the transmit consumer value from the status block (skipping over */
/* chain page pointer if necessary). */
return hw_cons;
}
-
/****************************************************************************/
/* Handles transmit completion interrupt events. */
/* */
txr->tx_cons = sw_tx_cons;
}
-
/****************************************************************************/
/* Disables interrupt generation. */
/* */
lwkt_serialize_handler_disable(sc->bce_msix[i].msix_serialize);
}
-
/****************************************************************************/
/* Enables interrupt generation. */
/* */
}
}
-
/****************************************************************************/
/* Reenables interrupt generation during interrupt handling. */
/* */
BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | rxr->last_status_idx);
}
-
/****************************************************************************/
/* Handles controller initialization. */
/* */
bce_stop(sc);
}
-
/****************************************************************************/
/* Initialize the controller just enough so that any management firmware */
/* running on the device will continue to operate corectly. */
bce_ifmedia_upd(ifp);
}
-
/****************************************************************************/
/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
/* memory visible to the controller. */
return error;
}
-
static void
bce_xmit(struct bce_tx_ring *txr)
{
txr->tx_prod_bseq);
}
-
/****************************************************************************/
/* Main transmit routine when called from another routine with a lock. */
/* */
bce_xmit(txr);
}
-
/****************************************************************************/
/* Handles any IOCTL calls from the operating system. */
/* */
return error;
}
-
/****************************************************************************/
/* Transmit timeout handler. */
/* */
ifsq_devstart_sched(sc->tx_rings[i].ifsq);
}
-
#ifdef IFPOLL_ENABLE
static void
#endif /* IFPOLL_ENABLE */
-
/*
* Interrupt handler.
*/
bce_reenable_intr(rxr);
}
-
/****************************************************************************/
/* Programs the various packet receive modes (broadcast and multicast). */
/* */
REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
}
-
/****************************************************************************/
/* Called periodically to updates statistics from the controllers */
/* statistics block. */
(u_long)sc->stat_Dot3StatsLateCollisions);
}
-
/****************************************************************************/
/* Periodic function to notify the bootcode that the driver is still */
/* present. */
lwkt_serialize_exit(&sc->main_serialize);
}
-
/****************************************************************************/
/* Periodic function to check whether MSI is lost */
/* */
lwkt_serialize_exit(&sc->main_serialize);
}
-
/****************************************************************************/
/* Periodic function to perform maintenance tasks. */
/* */
}
}
-
static void
bce_tick(void *xsc)
{
lwkt_serialize_exit(&sc->main_serialize);
}
-
/****************************************************************************/
/* Adds any sysctl parameters for tuning or debugging purposes. */
/* */
projects / dragonfly.git / commitdiff