msk(4): Disable ASF on the chips that have it
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Mon, 15 Aug 2011 11:23:14 +0000 (19:23 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Mon, 15 Aug 2011 11:32:16 +0000 (19:32 +0800)
Obtained-from: FreeBSD 222227

sys/dev/netif/msk/if_msk.c
sys/dev/netif/msk/if_mskreg.h

index 88022f8..41bcf7d 100644 (file)
@@ -1120,24 +1120,31 @@ mskc_reset(struct msk_softc *sc)
        int i;
 
        /* Disable ASF. */
-       if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
-               status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
-               /* Clear AHB bridge & microcontroller reset. */
-               status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
-                   Y2_ASF_HCU_CCSR_CPU_RST_MODE);
-               /* Clear ASF microcontroller state. */
-               status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
-               CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
-       } else {
-               CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
+       if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
+           sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
+               if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
+                   sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
+                       CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
+                       status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
+                       /* Clear AHB bridge & microcontroller reset. */
+                       status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
+                           Y2_ASF_HCU_CCSR_CPU_RST_MODE);
+                       /* Clear ASF microcontroller state. */
+                       status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
+                       status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
+                       CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
+                       CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
+               } else {
+                       CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
+               }
+               CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
+               /*
+                * Since we disabled ASF, S/W reset is required for
+                * Power Management.
+                */
+               CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
+               CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
        }
-       CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
-
-       /*
-        * Since we disabled ASF, S/W reset is required for Power Management.
-        */
-       CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
-       CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 
        /* Clear all error bits in the PCI status register. */
        status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
index 46a7f9d..bbafdda 100644 (file)
 /* ASF Subsystem Registers (Yukon-2 only) */
 #define B28_Y2_SMB_CONFIG      0x0e40  /* 32 bit ASF SMBus Config Register */
 #define B28_Y2_SMB_CSD_REG     0x0e44  /* 32 bit ASF SMB Control/Status/Data */
+#define B28_Y2_CPU_WDOG                0x0e48  /* 32 bit Watchdog Register */
 #define B28_Y2_ASF_IRQ_V_BASE  0x0e60  /* 32 bit ASF IRQ Vector Base */
 #define B28_Y2_ASF_STAT_CMD    0x0e68  /* 32 bit ASF Status and Command Reg */
 #define B28_Y2_ASF_HCU_CCSR    0x0e68  /* 32 bit ASF HCU CCSR (Yukon EX) */