.caps = CPUTIMER_INTR_CAP_NONE
};
-/*
- * pointers to pmapped apic hardware.
- */
-
-volatile ioapic_t **ioapic;
-
static int lapic_timer_divisor_idx = -1;
static const uint32_t lapic_timer_divisors[] = {
APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
}
-
-#ifdef SMP /* APIC-IO */
-
-/*
- * IO APIC code,
- */
-
-#define IOAPIC_ISA_INTS 16
-#define REDIRCNT_IOAPIC(A) \
- ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
-
-static int trigger (int apic, int pin, u_int32_t * flags);
-static void polarity (int apic, int pin, u_int32_t * flags, int level);
-
-#define DEFAULT_FLAGS \
- ((u_int32_t) \
- (IOART_INTMSET | \
- IOART_DESTPHY | \
- IOART_DELLOPRI))
-
-#define DEFAULT_ISA_FLAGS \
- ((u_int32_t) \
- (IOART_INTMSET | \
- IOART_TRGREDG | \
- IOART_INTAHI | \
- IOART_DESTPHY | \
- IOART_DELLOPRI))
-
-void
-io_apic_set_id(int apic, int id)
-{
- u_int32_t ux;
-
- ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* get current contents */
- if (((ux & APIC_ID_MASK) >> 24) != id) {
- kprintf("Changing APIC ID for IO APIC #%d"
- " from %d to %d on chip\n",
- apic, ((ux & APIC_ID_MASK) >> 24), id);
- ux &= ~APIC_ID_MASK; /* clear the ID field */
- ux |= (id << 24);
- ioapic_write(ioapic[apic], IOAPIC_ID, ux); /* write new value */
- ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* re-read && test */
- if (((ux & APIC_ID_MASK) >> 24) != id)
- panic("can't control IO APIC #%d ID, reg: 0x%08x",
- apic, ux);
- }
-}
-
-
-int
-io_apic_get_id(int apic)
-{
- return (ioapic_read(ioapic[apic], IOAPIC_ID) & APIC_ID_MASK) >> 24;
-}
-
-
-
-/*
- * Setup the IO APIC.
- */
-void
-io_apic_setup_intpin(int apic, int pin)
-{
- int bus, bustype, irq;
- u_char select; /* the select register is 8 bits */
- u_int32_t flags; /* the window register is 32 bits */
- u_int32_t target; /* the window register is 32 bits */
- u_int32_t vector; /* the window register is 32 bits */
- int level;
- int cpuid;
- char envpath[32];
-
- select = pin * 2 + IOAPIC_REDTBL0; /* register */
-
- /*
- * Always clear an IO APIC pin before [re]programming it. This is
- * particularly important if the pin is set up for a level interrupt
- * as the IOART_REM_IRR bit might be set. When we reprogram the
- * vector any EOI from pending ints on this pin could be lost and
- * IRR might never get reset.
- *
- * To fix this problem, clear the vector and make sure it is
- * programmed as an edge interrupt. This should theoretically
- * clear IRR so we can later, safely program it as a level
- * interrupt.
- */
- imen_lock();
-
- flags = ioapic_read(ioapic[apic], select) & IOART_RESV;
- flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
- flags |= IOART_DESTPHY | IOART_DELFIXED;
-
- target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
- target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
-
- vector = 0;
-
- ioapic_write(ioapic[apic], select, flags | vector);
- ioapic_write(ioapic[apic], select + 1, target);
-
- imen_unlock();
-
- /*
- * We only deal with vectored interrupts here. ? documentation is
- * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
- * vs ExTINT, etc.
- *
- * This test also catches unconfigured pins.
- */
- if (apic_int_type(apic, pin) != 0)
- return;
-
- /*
- * Leave the pin unprogrammed if it does not correspond to
- * an IRQ.
- */
- irq = apic_irq(apic, pin);
- if (irq < 0)
- return;
-
- /* determine the bus type for this pin */
- bus = apic_src_bus_id(apic, pin);
- if (bus < 0)
- return;
- bustype = apic_bus_type(bus);
-
- if ((bustype == ISA) &&
- (pin < IOAPIC_ISA_INTS) &&
- (irq == pin) &&
- (apic_polarity(apic, pin) == 0x1) &&
- (apic_trigger(apic, pin) == 0x3)) {
- /*
- * A broken BIOS might describe some ISA
- * interrupts as active-high level-triggered.
- * Use default ISA flags for those interrupts.
- */
- flags = DEFAULT_ISA_FLAGS;
- } else {
- /*
- * Program polarity and trigger mode according to
- * interrupt entry.
- */
- flags = DEFAULT_FLAGS;
- level = trigger(apic, pin, &flags);
- if (level == 1)
- int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
- polarity(apic, pin, &flags, level);
- }
-
- cpuid = 0;
- ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
- kgetenv_int(envpath, &cpuid);
-
- /* ncpus may not be available yet */
- if (cpuid > mp_naps)
- cpuid = 0;
-
- if (bootverbose) {
- kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
- apic, pin, irq, cpuid);
- }
-
- /*
- * Program the appropriate registers. This routing may be
- * overridden when an interrupt handler for a device is
- * actually added (see register_int(), which calls through
- * the MACHINTR ABI to set up an interrupt handler/vector).
- *
- * The order in which we must program the two registers for
- * safety is unclear! XXX
- */
- imen_lock();
-
- vector = IDT_OFFSET + irq; /* IDT vec */
- target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
- /* Deliver all interrupts to CPU0 (BSP) */
- target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
- IOART_HI_DEST_MASK;
- flags |= ioapic_read(ioapic[apic], select) & IOART_RESV;
- ioapic_write(ioapic[apic], select, flags | vector);
- ioapic_write(ioapic[apic], select + 1, target);
-
- imen_unlock();
-}
-
-int
-io_apic_setup(int apic)
-{
- int maxpin;
- int pin;
-
- maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
- kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
-
- for (pin = 0; pin < maxpin; ++pin) {
- io_apic_setup_intpin(apic, pin);
- }
- while (pin < 32) {
- if (apic_int_type(apic, pin) >= 0) {
- kprintf("Warning: IOAPIC #%d pin %d does not exist,"
- " cannot program!\n", apic, pin);
- }
- ++pin;
- }
-
- /* return GOOD status */
- return 0;
-}
-#undef DEFAULT_ISA_FLAGS
-#undef DEFAULT_FLAGS
-
-
-#define DEFAULT_EXTINT_FLAGS \
- ((u_int32_t) \
- (IOART_INTMSET | \
- IOART_TRGREDG | \
- IOART_INTAHI | \
- IOART_DESTPHY | \
- IOART_DELLOPRI))
-
-/*
- * XXX this function is only used by 8254 setup
- * Setup the source of External INTerrupts.
- */
-int
-ext_int_setup(int apic, int intr)
-{
- u_char select; /* the select register is 8 bits */
- u_int32_t flags; /* the window register is 32 bits */
- u_int32_t target; /* the window register is 32 bits */
- u_int32_t vector; /* the window register is 32 bits */
- int cpuid;
- char envpath[32];
-
- if (apic_int_type(apic, intr) != 3)
- return -1;
-
- cpuid = 0;
- ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
- kgetenv_int(envpath, &cpuid);
-
- /* ncpus may not be available yet */
- if (cpuid > mp_naps)
- cpuid = 0;
-
- /* Deliver interrupts to CPU0 (BSP) */
- target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
- IOART_HI_DEST_MASK;
- select = IOAPIC_REDTBL0 + (2 * intr);
- vector = IDT_OFFSET + intr;
- flags = DEFAULT_EXTINT_FLAGS;
-
- ioapic_write(ioapic[apic], select, flags | vector);
- ioapic_write(ioapic[apic], select + 1, target);
-
- return 0;
-}
-#undef DEFAULT_EXTINT_FLAGS
-
-
-/*
- * Set the trigger level for an IO APIC pin.
- */
-static int
-trigger(int apic, int pin, u_int32_t * flags)
-{
- int id;
- int eirq;
- int level;
- static int intcontrol = -1;
-
- switch (apic_trigger(apic, pin)) {
-
- case 0x00:
- break;
-
- case 0x01:
- *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
- return 0;
-
- case 0x03:
- *flags |= IOART_TRGRLVL;
- return 1;
-
- case -1:
- default:
- goto bad;
- }
-
- if ((id = apic_src_bus_id(apic, pin)) == -1)
- goto bad;
-
- switch (apic_bus_type(id)) {
- case ISA:
- *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
- return 0;
-
- case EISA:
- eirq = apic_src_bus_irq(apic, pin);
-
- if (eirq < 0 || eirq > 15) {
- kprintf("EISA IRQ %d?!?!\n", eirq);
- goto bad;
- }
-
- if (intcontrol == -1) {
- intcontrol = inb(ELCR1) << 8;
- intcontrol |= inb(ELCR0);
- kprintf("EISA INTCONTROL = %08x\n", intcontrol);
- }
-
- /* Use ELCR settings to determine level or edge mode */
- level = (intcontrol >> eirq) & 1;
-
- /*
- * Note that on older Neptune chipset based systems, any
- * pci interrupts often show up here and in the ELCR as well
- * as level sensitive interrupts attributed to the EISA bus.
- */
-
- if (level)
- *flags |= IOART_TRGRLVL;
- else
- *flags &= ~IOART_TRGRLVL;
-
- return level;
-
- case PCI:
- *flags |= IOART_TRGRLVL;
- return 1;
-
- case -1:
- default:
- goto bad;
- }
-
-bad:
- panic("bad APIC IO INT flags");
-}
-
-
-/*
- * Set the polarity value for an IO APIC pin.
- */
-static void
-polarity(int apic, int pin, u_int32_t * flags, int level)
-{
- int id;
-
- switch (apic_polarity(apic, pin)) {
-
- case 0x00:
- break;
-
- case 0x01:
- *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
- return;
-
- case 0x03:
- *flags |= IOART_INTALO;
- return;
-
- case -1:
- default:
- goto bad;
- }
-
- if ((id = apic_src_bus_id(apic, pin)) == -1)
- goto bad;
-
- switch (apic_bus_type(id)) {
- case ISA:
- *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
- return;
-
- case EISA:
- /* polarity converter always gives active high */
- *flags &= ~IOART_INTALO;
- return;
-
- case PCI:
- *flags |= IOART_INTALO;
- return;
-
- case -1:
- default:
- goto bad;
- }
-
-bad:
- panic("bad APIC IO INT flags");
-}
-
-
-/*
- * Print contents of unmasked IRQs.
- */
-void
-imen_dump(void)
-{
- int x;
-
- kprintf("SMP: enabled INTs: ");
- for (x = 0; x < APIC_INTMAPSIZE; ++x) {
- if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
- kprintf("%d ", x);
- }
- kprintf("\n");
-}
-
-
/*
* Inter Processor Interrupt functions.
*/
-#endif /* SMP APIC-IO */
-
/*
* Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
*
*/
#define CPU_TO_ID(CPU) (cpu_num_to_apic_id[CPU])
#define ID_TO_CPU(ID) (apic_id_to_logical[ID])
-#ifdef SMP /* APIC-IO */
-#define IO_TO_ID(IO) (io_num_to_apic_id[IO])
-#define ID_TO_IO(ID) (apic_id_to_logical[ID])
-#endif
#ifdef SMP
extern struct region_descriptor r_gdt, r_idt;
int mp_naps; /* # of Applications processors */
-#ifdef SMP /* APIC-IO */
-static int mp_nbusses; /* # of busses */
-int mp_napics; /* # of IO APICs */
-vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
-u_int32_t *io_apic_versions;
-#endif
extern int nkpt;
u_int32_t cpu_apic_versions[MAXCPU];
* We oversize these to simplify boot-time config.
*/
int cpu_num_to_apic_id[NAPICID];
-#ifdef SMP /* APIC-IO */
-int io_num_to_apic_id[NAPICID];
-#endif
int apic_id_to_logical[NAPICID];
/* AP uses this during bootstrap. Do not staticize. */
static int mptable_ioapic_probe(struct ioapic_enumerator *);
static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
-#ifdef SMP /* APIC-IO */
-static int apic_int_is_bus_type(int intr, int bus_type);
-#endif
static int start_all_aps(u_int boot_addr);
static void install_ap_tramp(u_int boot_addr);
static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
char name[7];
} bus_type_name;
-/* the bus data */
-static bus_datum *bus_data;
-
-/* the IO INT data, one entry per possible APIC INTerrupt */
-static io_int *io_apic_ints;
-static int nintrs;
-
static int processor_entry (const struct PROCENTRY *entry, int cpu);
/*
}
void
-assign_apic_irq(int apic, int intpin, int irq)
-{
- int x;
-
- if (int_to_apicintpin[irq].ioapic != -1)
- panic("assign_apic_irq: inconsistent table");
-
- int_to_apicintpin[irq].ioapic = apic;
- int_to_apicintpin[irq].int_pin = intpin;
- int_to_apicintpin[irq].apic_address = ioapic[apic];
- int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
-
- for (x = 0; x < nintrs; x++) {
- if ((io_apic_ints[x].int_type == 0 ||
- io_apic_ints[x].int_type == 3) &&
- io_apic_ints[x].int_vector == 0xff &&
- io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
- io_apic_ints[x].dst_apic_int == intpin)
- io_apic_ints[x].int_vector = irq;
- }
-}
-
-void
-revoke_apic_irq(int irq)
-{
- int x;
- int oldapic;
- int oldintpin;
-
- if (int_to_apicintpin[irq].ioapic == -1)
- panic("revoke_apic_irq: inconsistent table");
-
- oldapic = int_to_apicintpin[irq].ioapic;
- oldintpin = int_to_apicintpin[irq].int_pin;
-
- int_to_apicintpin[irq].ioapic = -1;
- int_to_apicintpin[irq].int_pin = 0;
- int_to_apicintpin[irq].apic_address = NULL;
- int_to_apicintpin[irq].redirindex = 0;
-
- for (x = 0; x < nintrs; x++) {
- if ((io_apic_ints[x].int_type == 0 ||
- io_apic_ints[x].int_type == 3) &&
- io_apic_ints[x].int_vector != 0xff &&
- io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
- io_apic_ints[x].dst_apic_int == oldintpin)
- io_apic_ints[x].int_vector = 0xff;
- }
-}
-
-void
mp_set_cpuids(int cpu_id, int apic_id)
{
CPU_TO_ID(cpu_id) = apic_id;
return 0;
}
-static int
-apic_int_is_bus_type(int intr, int bus_type)
-{
- int bus;
-
- for (bus = 0; bus < mp_nbusses; ++bus)
- if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
- && ((int) bus_data[bus].bus_type == bus_type))
- return 1;
-
- return 0;
-}
-
-/*
- * Given a traditional ISA INT mask, return an APIC mask.
- */
-u_int
-isa_apic_mask(u_int isa_mask)
-{
- int isa_irq;
- int apic_pin;
-
-#if defined(SKIP_IRQ15_REDIRECT)
- if (isa_mask == (1 << 15)) {
- kprintf("skipping ISA IRQ15 redirect\n");
- return isa_mask;
- }
-#endif /* SKIP_IRQ15_REDIRECT */
-
- isa_irq = ffs(isa_mask); /* find its bit position */
- if (isa_irq == 0) /* doesn't exist */
- return 0;
- --isa_irq; /* make it zero based */
-
- apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
- if (apic_pin == -1)
- return 0;
-
- return (1 << apic_pin); /* convert pin# to a mask */
-}
-
-/*
- * Determine which APIC pin an ISA/EISA INT is attached to.
- */
-#define INTTYPE(I) (io_apic_ints[(I)].int_type)
-#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
-#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
-#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
-
-#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
-int
-isa_apic_irq(int isa_irq)
-{
- int intr;
-
- for (intr = 0; intr < nintrs; ++intr) { /* check each record */
- if (INTTYPE(intr) == 0) { /* standard INT */
- if (SRCBUSIRQ(intr) == isa_irq) {
- if (apic_int_is_bus_type(intr, ISA) ||
- apic_int_is_bus_type(intr, EISA)) {
- if (INTIRQ(intr) == 0xff)
- return -1; /* unassigned */
- return INTIRQ(intr); /* found */
- }
- }
- }
- }
- return -1; /* NOT found */
-}
-
-
-/*
- * Determine which APIC pin a PCI INT is attached to.
- */
-#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
-#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
-#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
-int
-pci_apic_irq(int pciBus, int pciDevice, int pciInt)
-{
- int intr;
-
- --pciInt; /* zero based */
-
- for (intr = 0; intr < nintrs; ++intr) { /* check each record */
- if ((INTTYPE(intr) == 0) /* standard INT */
- && (SRCBUSID(intr) == pciBus)
- && (SRCBUSDEVICE(intr) == pciDevice)
- && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
- if (apic_int_is_bus_type(intr, PCI)) {
- if (INTIRQ(intr) == 0xff) {
- kprintf("IOAPIC: pci_apic_irq() "
- "failed\n");
- return -1; /* unassigned */
- }
- return INTIRQ(intr); /* exact match */
- }
- }
- }
-
- return -1; /* NOT found */
-}
-
-int
-next_apic_irq(int irq)
-{
- int intr, ointr;
- int bus, bustype;
-
- bus = 0;
- bustype = 0;
- for (intr = 0; intr < nintrs; intr++) {
- if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
- continue;
- bus = SRCBUSID(intr);
- bustype = apic_bus_type(bus);
- if (bustype != ISA &&
- bustype != EISA &&
- bustype != PCI)
- continue;
- break;
- }
- if (intr >= nintrs) {
- return -1;
- }
- for (ointr = intr + 1; ointr < nintrs; ointr++) {
- if (INTTYPE(ointr) != 0)
- continue;
- if (bus != SRCBUSID(ointr))
- continue;
- if (bustype == PCI) {
- if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
- continue;
- if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
- continue;
- }
- if (bustype == ISA || bustype == EISA) {
- if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
- continue;
- }
- if (INTPIN(intr) == INTPIN(ointr))
- continue;
- break;
- }
- if (ointr >= nintrs) {
- return -1;
- }
- return INTIRQ(ointr);
-}
-#undef SRCBUSLINE
-#undef SRCBUSDEVICE
-#undef SRCBUSID
-#undef SRCBUSIRQ
-
-#undef INTPIN
-#undef INTIRQ
-#undef INTAPIC
-#undef INTTYPE
-
-/*
- * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
- *
- * XXX FIXME:
- * Exactly what this means is unclear at this point. It is a solution
- * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
- * could route any of the ISA INTs to upper (>15) IRQ values. But most would
- * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
- * option.
- */
-int
-undirect_isa_irq(int rirq)
-{
-#if defined(READY)
- if (bootverbose)
- kprintf("Freeing redirected ISA irq %d.\n", rirq);
- /** FIXME: tickle the MB redirector chip */
- return /* XXX */;
-#else
- if (bootverbose)
- kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
- return 0;
-#endif /* READY */
-}
-
-
-/*
- * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
- */
-int
-undirect_pci_irq(int rirq)
-{
-#if defined(READY)
- if (bootverbose)
- kprintf("Freeing redirected PCI irq %d.\n", rirq);
-
- /** FIXME: tickle the MB redirector chip */
- return /* XXX */;
-#else
- if (bootverbose)
- kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
- rirq);
- return 0;
-#endif /* READY */
-}
-
-
-/*
- * given a bus ID, return:
- * the bus type if found
- * -1 if NOT found
- */
-int
-apic_bus_type(int id)
-{
- int x;
-
- for (x = 0; x < mp_nbusses; ++x)
- if (bus_data[x].bus_id == id)
- return bus_data[x].bus_type;
-
- return -1;
-}
-
-/*
- * given a LOGICAL APIC# and pin#, return:
- * the associated src bus ID if found
- * -1 if NOT found
- */
-int
-apic_src_bus_id(int apic, int pin)
-{
- int x;
-
- /* search each of the possible INTerrupt sources */
- for (x = 0; x < nintrs; ++x)
- if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
- (pin == io_apic_ints[x].dst_apic_int))
- return (io_apic_ints[x].src_bus_id);
-
- return -1; /* NOT found */
-}
-
-/*
- * given a LOGICAL APIC# and pin#, return:
- * the associated src bus IRQ if found
- * -1 if NOT found
- */
-int
-apic_src_bus_irq(int apic, int pin)
-{
- int x;
-
- for (x = 0; x < nintrs; x++)
- if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
- (pin == io_apic_ints[x].dst_apic_int))
- return (io_apic_ints[x].src_bus_irq);
-
- return -1; /* NOT found */
-}
-
-
-/*
- * given a LOGICAL APIC# and pin#, return:
- * the associated INTerrupt type if found
- * -1 if NOT found
- */
-int
-apic_int_type(int apic, int pin)
-{
- int x;
-
- /* search each of the possible INTerrupt sources */
- for (x = 0; x < nintrs; ++x) {
- if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
- (pin == io_apic_ints[x].dst_apic_int))
- return (io_apic_ints[x].int_type);
- }
- return -1; /* NOT found */
-}
-
-/*
- * Return the IRQ associated with an APIC pin
- */
-int
-apic_irq(int apic, int pin)
-{
- int x;
- int res;
-
- for (x = 0; x < nintrs; ++x) {
- if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
- (pin == io_apic_ints[x].dst_apic_int)) {
- res = io_apic_ints[x].int_vector;
- if (res == 0xff)
- return -1;
- if (apic != int_to_apicintpin[res].ioapic)
- panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
- if (pin != int_to_apicintpin[res].int_pin)
- panic("apic_irq inconsistent table (2)");
- return res;
- }
- }
- return -1;
-}
-
-
-/*
- * given a LOGICAL APIC# and pin#, return:
- * the associated trigger mode if found
- * -1 if NOT found
- */
-int
-apic_trigger(int apic, int pin)
-{
- int x;
-
- /* search each of the possible INTerrupt sources */
- for (x = 0; x < nintrs; ++x)
- if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
- (pin == io_apic_ints[x].dst_apic_int))
- return ((io_apic_ints[x].int_flags >> 2) & 0x03);
-
- return -1; /* NOT found */
-}
-
-
-/*
- * given a LOGICAL APIC# and pin#, return:
- * the associated 'active' level if found
- * -1 if NOT found
- */
-int
-apic_polarity(int apic, int pin)
-{
- int x;
-
- /* search each of the possible INTerrupt sources */
- for (x = 0; x < nintrs; ++x)
- if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
- (pin == io_apic_ints[x].dst_apic_int))
- return (io_apic_ints[x].int_flags & 0x03);
-
- return -1; /* NOT found */
-}
-
/*
* Map a physical memory address representing I/O into KVA. The I/O
* block is assumed not to cross a page boundary.
/* global data in mp_machdep.c */
extern int imcr_present;
extern int mp_naps;
-extern int mp_napics;
-extern vm_offset_t io_apic_address[];
extern u_int32_t cpu_apic_versions[];
-extern u_int32_t *io_apic_versions;
extern int cpu_num_to_apic_id[];
-extern int io_num_to_apic_id[];
extern int apic_id_to_logical[];
+
#define APIC_INTMAPSIZE 192
/*
* NOTE:
void mp_start (void);
void mp_announce (void);
void mp_set_cpuids (int, int);
-u_int isa_apic_mask (u_int);
-int isa_apic_irq (int);
-int pci_apic_irq (int, int, int);
-int apic_irq (int, int);
-int next_apic_irq (int);
-int undirect_isa_irq (int);
-int undirect_pci_irq (int);
-int apic_bus_type (int);
-int apic_src_bus_id (int, int);
-int apic_src_bus_irq (int, int);
-int apic_int_type (int, int);
-int apic_trigger (int, int);
-int apic_polarity (int, int);
-void assign_apic_irq (int apic, int intpin, int irq);
-void revoke_apic_irq (int irq);
void init_secondary (void);
int stop_cpus (cpumask_t);
void ap_init (void);
/* global data in mpapic.c */
extern volatile lapic_t lapic;
-extern volatile ioapic_t **ioapic;
extern int lapic_id_max;
#ifndef _SYS_BUS_H_
/* functions in mpapic.c */
void apic_dump (char*);
void lapic_init (boolean_t);
-void imen_dump (void);
int apic_ipi (int, int, int);
void selected_apic_ipi (cpumask_t, int, int);
void single_apic_ipi(int cpu, int vector, int delivery_mode);
int single_apic_ipi_passive(int cpu, int vector, int delivery_mode);
-int io_apic_setup (int);
-void io_apic_setup_intpin (int, int);
-void io_apic_set_id (int, int);
-int io_apic_get_id (int);
-int ext_int_setup (int, int);
void lapic_config(void);
void lapic_enumerator_register(struct lapic_enumerator *);
void ioapic_config(void);
projects / dragonfly.git / commitdiff