lapic: Centralize LAPIC configuration
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Sat, 19 Mar 2011 07:28:54 +0000 (15:28 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Sat, 19 Mar 2011 07:52:09 +0000 (15:52 +0800)
sys/platform/pc32/apic/ioapic_abi.c
sys/platform/pc32/apic/mpapic.c
sys/platform/pc64/apic/ioapic_abi.c
sys/platform/pc64/apic/mpapic.c

index 157fe44..427183a 100644 (file)
@@ -520,7 +520,6 @@ static void
 ioapic_finalize(void)
 {
        u_long ef;
-       uint32_t temp;
 
        KKASSERT(MachIntrABI.type == MACHINTR_ICU);
        KKASSERT(apic_io_enable);
@@ -535,15 +534,6 @@ ioapic_finalize(void)
                outb(0x23, 0x01);       /* disconnect 8259 */
        }
 
-       /*
-        * Setup LINT0 (the 8259 'virtual wire' connection).  We
-        * mask the interrupt, completing the disconnection of the
-        * 8259.
-        */
-       temp = lapic.lvt_lint0;
-       temp |= APIC_LVT_MASKED;
-       lapic.lvt_lint0 = temp;
-
        crit_enter();
 
        ef = read_eflags();
@@ -561,16 +551,6 @@ ioapic_finalize(void)
        MachIntrABI.cleanup();
 
        crit_exit();
-
-       /*
-        * Setup LINT1 to handle NMI
-        */
-       temp = lapic.lvt_lint1;
-       temp &= ~APIC_LVT_MASKED;
-       lapic.lvt_lint1 = temp;
-
-       if (bootverbose)
-               apic_dump("ioapic_finalize()");
 }
 
 /*
index 6c72e35..e88e81f 100644 (file)
@@ -165,26 +165,38 @@ lapic_init(boolean_t bsp)
         *
         * Must be setup edge triggered, active high.
         *
+        * Disable LINT0 on BSP, if I/O APIC is enabled.
+        *
         * Disable LINT0 on the APs.  It doesn't matter what delivery
         * mode we use because we leave it masked.
         */
        temp = lapic.lvt_lint0;
        temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 
                  APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
-       if (bsp)
+       if (bsp) {
                temp |= APIC_LVT_DM_EXTINT;
-       else
+               if (apic_io_enable)
+                       temp |= APIC_LVT_MASKED;
+       } else {
                temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
+       }
        lapic.lvt_lint0 = temp;
 
        /*
-        * Setup LINT1 as NMI, masked till later.
-        * Edge trigger, active high.
+        * Setup LINT1 as NMI.
+        *
+        * Must be setup edge trigger, active high.
+        *
+        * Enable LINT1 on BSP, if I/O APIC is enabled.
+        *
+        * Disable LINT1 on the APs.
         */
        temp = lapic.lvt_lint1;
        temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 
                  APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
        temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
+       if (bsp && apic_io_enable)
+               temp &= ~APIC_LVT_MASKED;
        lapic.lvt_lint1 = temp;
 
        /*
index f0add62..09c1c02 100644 (file)
@@ -520,7 +520,6 @@ static void
 ioapic_finalize(void)
 {
        register_t ef;
-       uint32_t temp;
 
        KKASSERT(MachIntrABI.type == MACHINTR_ICU);
        KKASSERT(apic_io_enable);
@@ -535,15 +534,6 @@ ioapic_finalize(void)
                outb(0x23, 0x01);       /* disconnect 8259 */
        }
 
-       /*
-        * Setup LINT0 (the 8259 'virtual wire' connection).  We
-        * mask the interrupt, completing the disconnection of the
-        * 8259.
-        */
-       temp = lapic->lvt_lint0;
-       temp |= APIC_LVT_MASKED;
-       lapic->lvt_lint0 = temp;
-
        crit_enter();
 
        ef = read_rflags();
@@ -561,16 +551,6 @@ ioapic_finalize(void)
        MachIntrABI.cleanup();
 
        crit_exit();
-
-       /*
-        * Setup LINT1 to handle an NMI 
-        */
-       temp = lapic->lvt_lint1;
-       temp &= ~APIC_LVT_MASKED;
-       lapic->lvt_lint1 = temp;
-
-       if (bootverbose)
-               apic_dump("ioapic_finalize()");
 }
 
 /*
index 5ad9952..0959ebd 100644 (file)
@@ -172,26 +172,38 @@ lapic_init(boolean_t bsp)
         *
         * Must be setup edge triggered, active high.
         *
+        * Disable LINT0 on BSP, if I/O APIC is enabled.
+        *
         * Disable LINT0 on the APs.  It doesn't matter what delivery
         * mode we use because we leave it masked.
         */
        temp = lapic->lvt_lint0;
        temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 
                  APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
-       if (bsp)
+       if (bsp) {
                temp |= APIC_LVT_DM_EXTINT;
-       else
+               if (apic_io_enable)
+                       temp |= APIC_LVT_MASKED;
+       } else {
                temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
+       }
        lapic->lvt_lint0 = temp;
 
        /*
-        * Setup LINT1 as NMI, masked till later.
-        * Edge trigger, active high.
+        * Setup LINT1 as NMI.
+        *
+        * Must be setup edge trigger, active high.
+        *
+        * Enable LINT1 on BSP, if I/O APIC is enabled.
+        *
+        * Disable LINT1 on the APs.
         */
        temp = lapic->lvt_lint1;
        temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | 
                  APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
        temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
+       if (bsp && apic_io_enable)
+               temp &= ~APIC_LVT_MASKED;
        lapic->lvt_lint1 = temp;
 
        /*