ecc: Support the ECC error detection for Xeon E3-1200 family
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Thu, 8 Dec 2011 09:02:36 +0000 (17:02 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Tue, 13 Dec 2011 02:17:27 +0000 (10:17 +0800)
- ecc no longer replaces hostb, instead, it becomes a device under hostb
- Clean up the code a little bit
- Split ecc.c into individual files based on device type

sys/bus/pci/hostb_pci.c
sys/dev/bridge/ecc/Makefile
sys/dev/bridge/ecc/ecc_amd8000.c [moved from sys/dev/bridge/ecc/ecc.c with 56% similarity]
sys/dev/bridge/ecc/ecc_e31200.c [new file with mode: 0644]
sys/dev/bridge/ecc/ecc_e31200_reg.h [new file with mode: 0644]

index 7863bae..e9e7541 100644 (file)
@@ -81,6 +81,7 @@ pci_hostb_attach(device_t dev)
         */
        if (pci_find_extcap(dev, PCIY_AGP, NULL) == 0)
                device_add_child(dev, "agp", -1);
+       device_add_child(dev, "ecc", -1);
        bus_generic_attach(dev);
        return (0);
 }
index da09297..032b28a 100644 (file)
@@ -2,7 +2,7 @@
 #
 
 KMOD = ecc
-SRCS = ecc.c
+SRCS = ecc_amd8000.c ecc_e31200.c
 SRCS += device_if.h bus_if.h pci_if.h pcib_if.h
 SRCS += opt_bus.h opt_pci.h
 MFILES = kern/device_if.m kern/bus_if.m bus/pci/pci_if.m bus/pci/pcib_if.m
similarity index 56%
rename from sys/dev/bridge/ecc/ecc.c
rename to sys/dev/bridge/ecc/ecc_amd8000.c
index 634d008..68f3113 100644 (file)
 
 #include "pcib_if.h"
 
-static int setup_none(device_t dev);
-static int setup_amd64(device_t dev);
-static void poll_amd64(void *dev_arg);
-
-struct pci_memory_controller { 
+struct ecc_amd8000_memctrl {
        uint16_t        vid;
        uint16_t        did;
        const char      *desc;
-       int (*setup)(device_t dev);
 };
 
-struct pci_ecc_softc {
-       struct pci_memory_controller *config;
-       struct callout poll_callout;
-       int poll_enable;
+struct ecc_amd8000_softc {
+       device_t        ecc_device;
+       device_t        ecc_mydev;
+       struct callout  ecc_callout;
+};
+
+#define ecc_printf(sc, fmt, arg...) \
+       device_printf((sc)->ecc_mydev, fmt , ##arg)
+
+static void    ecc_amd8000_callout(void *);
+static int     ecc_amd8000_probe(device_t);
+static int     ecc_amd8000_attach(device_t);
+
+static const struct ecc_amd8000_memctrl ecc_memctrls[] = {
+       { 0x1022, 0x1100, "AMD 8000 memory controller" },
+       { 0x1022, 0x7454, "AMD 8151 memory controller" },
+       { 0, 0, NULL } /* required last entry */
+};
+
+static device_method_t ecc_amd8000_methods[] = {
+        /* Device interface */
+       DEVMETHOD(device_probe,         ecc_amd8000_probe),
+       DEVMETHOD(device_attach,        ecc_amd8000_attach),
+       DEVMETHOD(device_shutdown,      bus_generic_shutdown),
+       DEVMETHOD(device_suspend,       bus_generic_suspend),
+       DEVMETHOD(device_resume,        bus_generic_resume),
+       { 0, 0 }
 };
 
-static struct pci_memory_controller mem_controllers[] = {
-       /* AMD */
-       { 0x1022, 0x7006, "AMD 751", setup_none },
-       { 0x1022, 0x700c, "AMD 762", setup_none },
-       { 0x1022, 0x700e, "AMD 761", setup_none },
-       { 0x1022, 0x1100, "AMD 8000", setup_amd64 },
-       { 0x1022, 0x7454, "AMD 8000", setup_amd64 }
+static driver_t ecc_amd8000_driver = {
+       "ecc",
+       ecc_amd8000_methods,
+       sizeof(struct ecc_amd8000_softc)
 };
+static devclass_t ecc_devclass;
+DRIVER_MODULE(ecc_amd8000, hostb, ecc_amd8000_driver, ecc_devclass, NULL, NULL);
+MODULE_DEPEND(ecc_amd8000, pci, 1, 1, 1);
 
 static int
-pci_ecc_probe(device_t dev)
+ecc_amd8000_probe(device_t dev)
 {
-       struct pci_ecc_softc *sc;
-       uint16_t vid;
-       uint16_t did;
-       int i;
+       const struct ecc_amd8000_memctrl *mc;
+       uint16_t vid, did;
 
        vid = pci_get_vendor(dev);
        did = pci_get_device(dev);
 
-       for (i = 0; i < NELEM(mem_controllers); ++i) {
-               if (mem_controllers[i].vid == vid &&
-                   mem_controllers[i].did == did
-               ) {
-                       sc = device_get_softc(dev);
-                       sc->config = &mem_controllers[i];
-                       return(0);
+       for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
+               if (mc->vid == vid && mc->did == did) {
+                       struct ecc_amd8000_softc *sc = device_get_softc(dev);
+
+                       device_set_desc(dev, mc->desc);
+                       sc->ecc_mydev = dev;
+                       sc->ecc_device = device_get_parent(dev);
+                       return (0);
                }
        }
        return (ENXIO);
 }
 
 static int
-pci_ecc_attach(device_t dev)
+ecc_amd8000_attach(device_t dev)
 {
-       struct pci_ecc_softc *sc = device_get_softc(dev);
+       struct ecc_amd8000_softc *sc = device_get_softc(dev);
+       uint32_t draminfo, eccinfo;
+       int bus, slot, poll = 0;
 
-       return (sc->config->setup(dev));
-}
+       dev = sc->ecc_device; /* XXX */
 
-static device_method_t pci_ecc_methods[] = {
-        /* Device interface */
-        DEVMETHOD(device_probe,         pci_ecc_probe),
-        DEVMETHOD(device_attach,        pci_ecc_attach),
-        DEVMETHOD(device_shutdown,      bus_generic_shutdown),
-        DEVMETHOD(device_suspend,       bus_generic_suspend),
-        DEVMETHOD(device_resume,        bus_generic_resume),
-        { 0, 0 }
-};
-
-static driver_t pci_ecc_driver = {
-       "ecc",
-       pci_ecc_methods,
-       sizeof(struct pci_ecc_softc)
-};
-static devclass_t ecc_devclass;
-DRIVER_MODULE(ecc, pci, pci_ecc_driver, ecc_devclass, NULL, NULL);
-MODULE_DEPEND(ecc, pci, 1, 1, 1);
-
-/*
- * Architecture-specific procedures
- */
-static
-int
-setup_none(device_t dev)
-{
-       return(0);
-}
-
-static
-int
-setup_amd64(device_t dev)
-{
-       struct pci_ecc_softc *sc = device_get_softc(dev);
-       uint32_t draminfo;
-       uint32_t eccinfo;
-       int bus = pci_get_bus(dev);
-       int slot = pci_get_slot(dev);
+       bus = pci_get_bus(dev);
+       slot = pci_get_slot(dev);
 
        /*
         * The memory bridge is recognized as four PCI devices
@@ -151,32 +133,31 @@ setup_amd64(device_t dev)
        draminfo = pcib_read_config(dev, bus, slot, 2, 0x90, 4);
        eccinfo = pcib_read_config(dev, bus, slot, 3, 0x44, 4);
 
-       device_printf(dev, "attached %s memory controller\n", sc->config->desc);
        if ((draminfo >> 17) & 1)
-               device_printf(dev, "memory type: ECC\n");
+               ecc_printf(sc, "memory type: ECC\n");
        else
-               device_printf(dev, "memory type: NON-ECC\n");
+               ecc_printf(sc, "memory type: NON-ECC\n");
        switch((eccinfo >> 22) & 3) {
        case 0:
-               device_printf(dev, "ecc mode: DISABLED\n");
+               ecc_printf(sc, "ecc mode: DISABLED\n");
                break;
        case 1:
-               device_printf(dev, "ecc mode: ENABLED/CORRECT-MODE\n");
-               sc->poll_enable = 1;
+               ecc_printf(sc, "ecc mode: ENABLED/CORRECT-MODE\n");
+               poll = 1;
                break;
        case 2:
-               device_printf(dev, "ecc mode: ENABLED/RESERVED (disabled)\n");
+               ecc_printf(sc, "ecc mode: ENABLED/RESERVED (disabled)\n");
                break;
        case 3:
-               device_printf(dev, "ecc mode: ENABLED/CHIPKILL-MODE\n");
-               sc->poll_enable = 1;
+               ecc_printf(sc, "ecc mode: ENABLED/CHIPKILL-MODE\n");
+               poll = 1;
                break;
        }
 
        /*
         * Enable ECC logging and clear any previous error.
         */
-       if (sc->poll_enable) {
+       if (poll) {
                uint64_t v64;
                uint32_t v32;
 
@@ -186,22 +167,22 @@ setup_amd64(device_t dev)
                v32 &= 0x7F801EFC;
                pcib_write_config(dev, bus, slot, 3, 0x4C, v32, 4);
 
-               callout_init(&sc->poll_callout);
-               callout_reset(&sc->poll_callout, hz, poll_amd64, dev);
+               callout_init_mp(&sc->ecc_callout);
+               callout_reset(&sc->ecc_callout, hz, ecc_amd8000_callout, sc);
        }
-       return(0);
+       return (0);
 }
 
-static
-void
-poll_amd64(void *dev_arg)
+static void
+ecc_amd8000_callout(void *xsc)
 {
-       device_t dev = dev_arg;
-       struct pci_ecc_softc *sc = device_get_softc(dev);
-       int bus = pci_get_bus(dev);
-       int slot = pci_get_slot(dev);
-       uint32_t v32;
-       uint32_t addr;
+       struct ecc_amd8000_softc *sc = xsc;
+       device_t dev = sc->ecc_device;
+       uint32_t v32, addr;
+       int bus, slot;
+
+       bus = pci_get_bus(dev);
+       slot = pci_get_slot(dev);
 
        /*
         * The address calculation is not entirely correct.  We need to
@@ -210,13 +191,12 @@ poll_amd64(void *dev_arg)
        v32 = pcib_read_config(dev, bus, slot, 3, 0x4C, 4);
        if ((v32 & 0x80004000) == 0x80004000) {
                addr = pcib_read_config(dev, bus, slot, 3, 0x50, 4);
-               device_printf(dev, "Correctable ECC error at %08x\n", addr);
+               ecc_printf(sc, "Correctable ECC error at %08x\n", addr);
                pcib_write_config(dev, bus, slot, 3, 0x4C, v32 & 0x7F801EFC, 4);
        } else if ((v32 & 0x80002000) == 0x80002000) {
                addr = pcib_read_config(dev, bus ,slot, 3, 0x50, 4);
-               device_printf(dev, "Uncorrectable ECC error at %08x\n", addr);
+               ecc_printf(sc, "Uncorrectable ECC error at %08x\n", addr);
                pcib_write_config(dev, bus, slot, 3, 0x4C, v32 & 0x7F801EFC, 4);
        }
-       callout_reset(&sc->poll_callout, hz, poll_amd64, dev);
+       callout_reset(&sc->ecc_callout, hz, ecc_amd8000_callout, sc);
 }
-
diff --git a/sys/dev/bridge/ecc/ecc_e31200.c b/sys/dev/bridge/ecc/ecc_e31200.c
new file mode 100644 (file)
index 0000000..d3217dc
--- /dev/null
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2011 The DragonFly Project.  All rights reserved.
+ * 
+ * This code is derived from software contributed to The DragonFly Project
+ * by Sepherosa Ziehau <sepherosa@gmail.com>
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of The DragonFly Project nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific, prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/bitops.h>
+
+#include <bus/pci/pcivar.h>
+#include <bus/pci/pcireg.h>
+#include <bus/pci/pcibus.h>
+#include <bus/pci/pci_cfgreg.h>
+#include <bus/pci/pcib_private.h>
+
+#include <vm/pmap.h>
+
+#include "pcib_if.h"
+
+#include <dev/bridge/ecc/ecc_e31200_reg.h>
+
+struct ecc_e31200_memctrl {
+       uint16_t        vid;
+       uint16_t        did;
+       const char      *desc;
+};
+
+struct ecc_e31200_softc {
+       device_t        ecc_device;
+       device_t        ecc_mydev;
+       struct callout  ecc_callout;
+       volatile uint8_t *ecc_addr;
+};
+
+#define CSR_READ_4(sc, ofs)    (*(volatile uint32_t *)((sc)->ecc_addr + (ofs)))
+
+#define ecc_printf(sc, fmt, arg...) \
+       device_printf((sc)->ecc_mydev, fmt , ##arg)
+
+static int     ecc_e31200_probe(device_t);
+static int     ecc_e31200_attach(device_t);
+
+static void    ecc_e31200_chaninfo(struct ecc_e31200_softc *, uint32_t,
+                   const char *);
+static void    ecc_e31200_status(struct ecc_e31200_softc *);
+static void    ecc_e31200_callout(void *);
+static void    ecc_e31200_errlog(struct ecc_e31200_softc *);
+static void    ecc_e31200_errlog_ch(struct ecc_e31200_softc *, int, int,
+                   const char *);
+
+static const struct ecc_e31200_memctrl ecc_memctrls[] = {
+       { 0x8086, 0x0108, "Intel E3-1200 memory controller" },
+       { 0, 0, NULL } /* required last entry */
+};
+
+static device_method_t ecc_e31200_methods[] = {
+        /* Device interface */
+        DEVMETHOD(device_probe,                ecc_e31200_probe),
+        DEVMETHOD(device_attach,       ecc_e31200_attach),
+        DEVMETHOD(device_shutdown,     bus_generic_shutdown),
+        DEVMETHOD(device_suspend,      bus_generic_suspend),
+        DEVMETHOD(device_resume,       bus_generic_resume),
+        { 0, 0 }
+};
+
+static driver_t ecc_e31200_driver = {
+       "ecc",
+       ecc_e31200_methods,
+       sizeof(struct ecc_e31200_softc)
+};
+static devclass_t ecc_devclass;
+DRIVER_MODULE(ecc_e31200, hostb, ecc_e31200_driver, ecc_devclass, NULL, NULL);
+MODULE_DEPEND(ecc_e31200, pci, 1, 1, 1);
+
+static int
+ecc_e31200_probe(device_t dev)
+{
+       const struct ecc_e31200_memctrl *mc;
+       uint16_t vid, did;
+
+       vid = pci_get_vendor(dev);
+       did = pci_get_device(dev);
+
+       for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
+               if (mc->vid == vid && mc->did == did) {
+                       struct ecc_e31200_softc *sc = device_get_softc(dev);
+
+                       device_set_desc(dev, mc->desc);
+                       sc->ecc_mydev = dev;
+                       sc->ecc_device = device_get_parent(dev);
+                       return (0);
+               }
+       }
+       return (ENXIO);
+}
+
+static int
+ecc_e31200_attach(device_t dev)
+{
+       struct ecc_e31200_softc *sc = device_get_softc(dev);
+       uint32_t capa, dmfc, mch_barlo, mch_barhi;
+       uint64_t mch_bar;
+       int bus, slot;
+
+       dev = sc->ecc_device; /* XXX */
+
+       bus = pci_get_bus(dev);
+       slot = pci_get_slot(dev);
+
+       capa = pcib_read_config(dev, bus, slot, 0, PCI_E31200_CAPID0_A, 4);
+
+       dmfc = __SHIFTOUT(capa, PCI_E31200_CAPID0_A_DMFC);
+       if (dmfc == PCI_E31200_CAPID0_A_DMFC_1333) {
+               ecc_printf(sc, "CAP DDR3 1333 ");
+       } else if (dmfc == PCI_E31200_CAPID0_A_DMFC_1067) {
+               ecc_printf(sc, "CAP DDR3 1067 ");
+       } else if (dmfc == PCI_E31200_CAPID0_A_DMFC_ALL) {
+               ecc_printf(sc, "no CAP ");
+       } else {
+               ecc_printf(sc, "unknown DMFC %#x\n", dmfc);
+               return 0;
+       }
+
+       if (capa & PCI_E31200_CAPID0_A_ECCDIS) {
+               kprintf("NON-ECC\n");
+               return 0;
+       } else {
+               kprintf("ECC\n");
+       }
+
+       mch_barlo = pcib_read_config(dev, bus, slot, 0,
+           PCI_E31200_MCHBAR_LO, 4);
+       mch_barhi = pcib_read_config(dev, bus, slot, 0,
+           PCI_E31200_MCHBAR_HI, 4);
+
+       mch_bar = (uint64_t)mch_barlo | (((uint64_t)mch_barhi) << 32);
+       if (bootverbose)
+               ecc_printf(sc, "MCHBAR %jx\n", (uintmax_t)mch_bar);
+
+       if (mch_bar & PCI_E31200_MCHBAR_LO_EN) {
+               uint64_t map_addr = mch_bar & PCI_E31200_MCHBAR_ADDRMASK;
+               uint32_t dimm_ch0, dimm_ch1;
+
+               sc->ecc_addr = pmap_mapdev_uncacheable(map_addr,
+                   MCH_E31200_SIZE);
+
+               if (bootverbose) {
+                       ecc_printf(sc, "LOG0_C0 %#x\n",
+                           CSR_READ_4(sc, MCH_E31200_ERRLOG0_C0));
+                       ecc_printf(sc, "LOG0_C1 %#x\n",
+                           CSR_READ_4(sc, MCH_E31200_ERRLOG0_C1));
+               }
+
+               dimm_ch0 = CSR_READ_4(sc, MCH_E31200_DIMM_CH0);
+               dimm_ch1 = CSR_READ_4(sc, MCH_E31200_DIMM_CH1);
+
+               if (bootverbose) {
+                       ecc_e31200_chaninfo(sc, dimm_ch0, "channel0");
+                       ecc_e31200_chaninfo(sc, dimm_ch1, "channel1");
+               }
+
+               if (((dimm_ch0 | dimm_ch1) & MCH_E31200_DIMM_ECC) == 0) {
+                       ecc_printf(sc, "No ECC active\n");
+                       pmap_unmapdev((vm_offset_t)sc->ecc_addr,
+                           MCH_E31200_SIZE);
+                       return 0;
+               }
+       }
+
+       ecc_e31200_status(sc);
+       callout_init_mp(&sc->ecc_callout);
+       callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
+
+       return 0;
+}
+
+static void
+ecc_e31200_callout(void *xsc)
+{
+       struct ecc_e31200_softc *sc = xsc;
+
+       ecc_e31200_status(sc);
+       callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
+}
+
+static void
+ecc_e31200_status(struct ecc_e31200_softc *sc)
+{
+       device_t dev = sc->ecc_device;
+       uint16_t errsts;
+       int bus, slot;
+
+       bus = pci_get_bus(dev);
+       slot = pci_get_slot(dev);
+
+       errsts = pcib_read_config(dev, bus, slot, 0, 0xc8, 2);
+       if (errsts & 0x2)
+               ecc_printf(sc, "Uncorrectable ECC error\n");
+       else if (errsts & 0x1)
+               ecc_printf(sc, "Correctable ECC error\n");
+
+       if (errsts & 0x3) {
+               if (sc->ecc_addr != NULL)
+                       ecc_e31200_errlog(sc);
+
+               /* Clear pending errors */
+               pcib_write_config(dev, bus, slot, 0, 0xc8, errsts, 2);
+       }
+}
+
+static void
+ecc_e31200_chaninfo(struct ecc_e31200_softc *sc, uint32_t dimm_ch,
+    const char *desc)
+{
+       int size_a, size_b, ecc;
+
+       size_a = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_A_SIZE);
+       if (size_a != 0) {
+               ecc_printf(sc, "%s, DIMM A %dMB %s %s\n", desc,
+                   size_a * MCH_E31200_DIMM_SIZE_UNIT,
+                   (dimm_ch & MCH_E31200_DIMM_A_X16) ? "X16" : "X8",
+                   (dimm_ch & MCH_E31200_DIMM_A_DUAL_RANK) ?
+                       "DUAL" : "SINGLE");
+       }
+
+       size_b = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_B_SIZE);
+       if (size_b != 0) {
+               ecc_printf(sc, "%s, DIMM B %dMB %s %s\n", desc,
+                   size_b * MCH_E31200_DIMM_SIZE_UNIT,
+                   (dimm_ch & MCH_E31200_DIMM_B_X16) ? "X16" : "X8",
+                   (dimm_ch & MCH_E31200_DIMM_B_DUAL_RANK) ?
+                       "DUAL" : "SINGLE");
+       }
+
+       if (size_a == 0 && size_b == 0)
+               return;
+
+       ecc = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_ECC);
+       if (ecc == MCH_E31200_DIMM_ECC_NONE)
+               ecc_printf(sc, "%s, no ECC active\n", desc);
+       else if (ecc == MCH_E31200_DIMM_ECC_IO)
+               ecc_printf(sc, "%s, ECC active IO\n", desc);
+       else if (ecc == MCH_E31200_DIMM_ECC_LOGIC)
+               ecc_printf(sc, "%s, ECC active logic\n", desc);
+       else
+               ecc_printf(sc, "%s, ECC active IO/logic\n", desc);
+
+       if (dimm_ch & (MCH_E31200_DIMM_ENHI | MCH_E31200_DIMM_RI)) {
+               ecc_printf(sc, "%s", desc);
+               if (dimm_ch & MCH_E31200_DIMM_RI)
+                       kprintf(", rank interleave");
+               if (dimm_ch & MCH_E31200_DIMM_ENHI)
+                       kprintf(", enhanced interleave");
+               kprintf("\n");
+       }
+}
+
+static void
+ecc_e31200_errlog(struct ecc_e31200_softc *sc)
+{
+       ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C0, MCH_E31200_ERRLOG1_C0,
+           "channel0");
+       ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C1, MCH_E31200_ERRLOG1_C1,
+           "channel1");
+}
+
+static void
+ecc_e31200_errlog_ch(struct ecc_e31200_softc *sc,
+    int err0_ofs, int err1_ofs, const char *desc)
+{
+       uint32_t err0, err1;
+
+       err0 = CSR_READ_4(sc, err0_ofs);
+       if ((err0 & (MCH_E31200_ERRLOG0_CERRSTS | MCH_E31200_ERRLOG0_MERRSTS))
+           == 0)
+               return;
+
+       err1 = CSR_READ_4(sc, err1_ofs);
+
+       ecc_printf(sc, "%s error @bank %d, rank %d, chunk %d, syndrome %d, "
+           "row %d, col %d\n", desc,
+           __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRBANK),
+           __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRRANK),
+           __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRCHUNK),
+           __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRSYND),
+           __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRROW),
+           __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRCOL));
+}
diff --git a/sys/dev/bridge/ecc/ecc_e31200_reg.h b/sys/dev/bridge/ecc/ecc_e31200_reg.h
new file mode 100644 (file)
index 0000000..209e0bf
--- /dev/null
@@ -0,0 +1,57 @@
+#ifndef _ECC_E31200_REG_H_
+#define _ECC_E31200_REG_H_
+
+#ifndef _SYS_BITOPS_H_
+#include <sys/bitops.h>
+#endif
+
+#define PCI_E31200_MCHBAR_LO           0x48
+#define PCI_E31200_MCHBAR_LO_EN                0x1
+#define PCI_E31200_MCHBAR_HI           0x4c
+
+#define PCI_E31200_CAPID0_A            0xe4
+#define PCI_E31200_CAPID0_A_DMFC       __BITS(0, 2)
+#define PCI_E31200_CAPID0_A_DMFC_ALL   0
+#define PCI_E31200_CAPID0_A_DMFC_1333  0x6
+#define PCI_E31200_CAPID0_A_DMFC_1067  0x7
+#define PCI_E31200_CAPID0_A_ECCDIS     __BIT(25)
+
+#define PCI_E31200_MCHBAR_ADDRMASK     __BITS64(15, 38)
+
+#define MCH_E31200_SIZE                        (32 * 1024)
+
+#define MCH_E31200_ERRLOG0_C0          0x40c8
+#define MCH_E31200_ERRLOG1_C0          0x40cc
+
+#define MCH_E31200_ERRLOG0_C1          0x44c8
+#define MCH_E31200_ERRLOG1_C1          0x44cc
+
+#define MCH_E31200_ERRLOG0_CERRSTS     __BIT(0)
+#define MCH_E31200_ERRLOG0_MERRSTS     __BIT(1)
+#define MCH_E31200_ERRLOG0_ERRSYND     __BITS(16, 23)
+#define MCH_E31200_ERRLOG0_ERRCHUNK    __BITS(24, 26)
+#define MCH_E31200_ERRLOG0_ERRRANK     __BITS(27, 28)
+#define MCH_E31200_ERRLOG0_ERRBANK     __BITS(29, 31)
+
+#define MCH_E31200_ERRLOG1_ERRROW      __BITS(0, 15)
+#define MCH_E31200_ERRLOG1_ERRCOL      __BITS(16, 31)
+
+#define MCH_E31200_DIMM_CH0            0x5004
+#define MCH_E31200_DIMM_CH1            0x5008
+
+#define MCH_E31200_DIMM_SIZE_UNIT      256             /* MB */
+#define MCH_E31200_DIMM_A_SIZE         __BITS(0, 7)
+#define MCH_E31200_DIMM_B_SIZE         __BITS(8, 15)
+#define MCH_E31200_DIMM_A_DUAL_RANK    __BIT(17)
+#define MCH_E31200_DIMM_B_DUAL_RANK    __BIT(18)
+#define MCH_E31200_DIMM_A_X16          __BIT(19)
+#define MCH_E31200_DIMM_B_X16          __BIT(20)
+#define MCH_E31200_DIMM_RI             __BIT(21)       /* rank interleave */
+#define MCH_E31200_DIMM_ENHI           __BIT(22)       /* enchanced interleave */
+#define MCH_E31200_DIMM_ECC            __BITS(24, 25)
+#define MCH_E31200_DIMM_ECC_NONE       0x0
+#define MCH_E31200_DIMM_ECC_IO         0x1
+#define MCH_E31200_DIMM_ECC_LOGIC      0x2
+#define MCH_E31200_DIMM_ECC_ALL                0x3
+
+#endif /* !_ECC_E31200_REG_H_ */