*/
txr->spare_desc = IGB_TX_SPARE;
txr->intr_nsegs = txr->num_tx_desc / 16;
- txr->wreg_nsegs = 8;
+ txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
txr->oact_hi_desc = txr->num_tx_desc / 2;
txr->oact_lo_desc = txr->num_tx_desc / 8;
if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
/*
* Initialize various watermark
*/
- rxr->wreg_nsegs = 32;
+ rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
return 0;
}
#define IGB_MAX_IVAR_VF 1
/*
+ * Default number of segments received before writing to RX related registers
+ */
+#define IGB_DEF_RXWREG_NSEGS 32
+
+/*
+ * Default number of segments sent before writing to RX related registers
+ */
+#define IGB_DEF_TXWREG_NSEGS 8
+
+/*
* IGB_TXD: Maximum number of Transmit Descriptors
*
* This value is the number of transmit descriptors allocated by the driver.