em(4)/emx(4): Update ig_hal to Intel's 7.1.7
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Mon, 27 Jun 2011 07:54:19 +0000 (15:54 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Mon, 27 Jun 2011 08:17:37 +0000 (16:17 +0800)
Local modification:
- Keep old e1000_read_mac_addr_generic() so that 82574L and 82571EB
  could be probed correctly (instead of bailing out at "Invalid MAC
  address")

Newer device support is not added into em(4) and emx(4) yet.

31 files changed:
sys/conf/files
sys/dev/netif/em/if_em.c
sys/dev/netif/emx/if_emx.c
sys/dev/netif/ig_hal/Makefile
sys/dev/netif/ig_hal/e1000_80003es2lan.c
sys/dev/netif/ig_hal/e1000_80003es2lan.h
sys/dev/netif/ig_hal/e1000_82540.c
sys/dev/netif/ig_hal/e1000_82541.c
sys/dev/netif/ig_hal/e1000_82541.h
sys/dev/netif/ig_hal/e1000_82542.c
sys/dev/netif/ig_hal/e1000_82543.c
sys/dev/netif/ig_hal/e1000_82543.h
sys/dev/netif/ig_hal/e1000_82571.c
sys/dev/netif/ig_hal/e1000_82571.h
sys/dev/netif/ig_hal/e1000_82575.c [deleted file]
sys/dev/netif/ig_hal/e1000_82575.h [deleted file]
sys/dev/netif/ig_hal/e1000_api.c
sys/dev/netif/ig_hal/e1000_api.h
sys/dev/netif/ig_hal/e1000_defines.h
sys/dev/netif/ig_hal/e1000_hw.h
sys/dev/netif/ig_hal/e1000_ich8lan.c
sys/dev/netif/ig_hal/e1000_ich8lan.h
sys/dev/netif/ig_hal/e1000_mac.c
sys/dev/netif/ig_hal/e1000_mac.h
sys/dev/netif/ig_hal/e1000_manage.c
sys/dev/netif/ig_hal/e1000_manage.h
sys/dev/netif/ig_hal/e1000_nvm.c
sys/dev/netif/ig_hal/e1000_nvm.h
sys/dev/netif/ig_hal/e1000_phy.c
sys/dev/netif/ig_hal/e1000_phy.h
sys/dev/netif/ig_hal/e1000_regs.h

index 5d7c259..c02e405 100644 (file)
@@ -324,7 +324,6 @@ dev/netif/ig_hal/e1000_82541.c      optional ig_hal
 dev/netif/ig_hal/e1000_82542.c optional ig_hal
 dev/netif/ig_hal/e1000_82543.c optional ig_hal
 dev/netif/ig_hal/e1000_82571.c optional ig_hal
-dev/netif/ig_hal/e1000_82575.c optional ig_hal
 dev/netif/ig_hal/e1000_api.c   optional ig_hal
 dev/netif/ig_hal/e1000_ich8lan.c       optional ig_hal
 dev/netif/ig_hal/e1000_mac.c   optional ig_hal
index 228a5e8..744306e 100644 (file)
@@ -1856,8 +1856,7 @@ em_set_multi(struct adapter *adapter)
                reg_rctl |= E1000_RCTL_MPE;
                E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
        } else {
-               e1000_update_mc_addr_list(&adapter->hw, mta,
-                   mcnt, 1, adapter->hw.mac.rar_entry_count);
+               e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
        }
 
        if (adapter->hw.mac.type == e1000_82542 && 
index fa83f3f..fbb631f 100644 (file)
@@ -1511,8 +1511,7 @@ emx_set_multi(struct emx_softc *sc)
                reg_rctl |= E1000_RCTL_MPE;
                E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
        } else {
-               e1000_update_mc_addr_list(&sc->hw, mta,
-                   mcnt, 1, sc->hw.mac.rar_entry_count);
+               e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
        }
 }
 
index 0da1d96..4007230 100644 (file)
@@ -3,6 +3,6 @@ SRCS    = device_if.h pci_if.h bus_if.h
 SRCS   += e1000_osdep.c
 SRCS   += e1000_api.c e1000_mac.c e1000_manage.c e1000_nvm.c e1000_phy.c
 SRCS   += e1000_80003es2lan.c e1000_82540.c e1000_82541.c e1000_82542.c \
-          e1000_82543.c e1000_82571.c e1000_82575.c e1000_ich8lan.c
+          e1000_82543.c e1000_82571.c e1000_ich8lan.c
 
 .include <bsd.kmod.mk>
index fa7272e..fd96705 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 /*
  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
@@ -43,9 +43,7 @@ static s32  e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
-static s32  e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw);
 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
-static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
@@ -173,7 +171,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
                break;
        }
 
-       nvm->type               = e1000_nvm_eeprom_spi;
+       nvm->type = e1000_nvm_eeprom_spi;
 
        size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
                          E1000_EECD_SIZE_EX_SHIFT);
@@ -208,17 +206,22 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 {
        struct e1000_mac_info *mac = &hw->mac;
-       s32 ret_val = E1000_SUCCESS;
 
        DEBUGFUNC("e1000_init_mac_params_80003es2lan");
 
-       /* Set media type */
+       /* Set media type and media-dependent function pointers */
        switch (hw->device_id) {
        case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
                hw->phy.media_type = e1000_media_type_internal_serdes;
+               mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
+               mac->ops.setup_physical_interface =
+                       e1000_setup_fiber_serdes_link_generic;
                break;
        default:
                hw->phy.media_type = e1000_media_type_copper;
+               mac->ops.check_for_link = e1000_check_for_copper_link_generic;
+               mac->ops.setup_physical_interface =
+                       e1000_setup_copper_link_80003es2lan;
                break;
        }
 
@@ -228,10 +231,14 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
        mac->rar_entry_count = E1000_RAR_ENTRIES;
        /* Set if part includes ASF firmware */
        mac->asf_firmware_present = TRUE;
-       /* Set if manageability features are enabled. */
+       /* FWSM register */
+       mac->has_fwsm = TRUE;
+       /* ARC supported; valid only if manageability features are enabled. */
        mac->arc_subsystem_valid =
                (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
                        ? TRUE : FALSE;
+       /* Adaptive IFS not supported */
+       mac->adaptive_ifs = FALSE;
 
        /* Function pointers */
 
@@ -243,27 +250,6 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
        mac->ops.init_hw = e1000_init_hw_80003es2lan;
        /* link setup */
        mac->ops.setup_link = e1000_setup_link_generic;
-       /* physical interface link setup */
-       mac->ops.setup_physical_interface =
-               (hw->phy.media_type == e1000_media_type_copper)
-                       ? e1000_setup_copper_link_80003es2lan
-                       : e1000_setup_fiber_serdes_link_generic;
-       /* check for link */
-       switch (hw->phy.media_type) {
-       case e1000_media_type_copper:
-               mac->ops.check_for_link = e1000_check_for_copper_link_generic;
-               break;
-       case e1000_media_type_fiber:
-               mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
-               break;
-       case e1000_media_type_internal_serdes:
-               mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
-               break;
-       default:
-               ret_val = -E1000_ERR_CONFIG;
-               goto out;
-               break;
-       }
        /* check management mode */
        mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
        /* multicast address update */
@@ -272,10 +258,10 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
        mac->ops.write_vfta = e1000_write_vfta_generic;
        /* clearing VFTA */
        mac->ops.clear_vfta = e1000_clear_vfta_generic;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_generic;
        /* read mac address */
        mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;
+       /* ID LED init */
+       mac->ops.id_led_init = e1000_id_led_init_generic;
        /* blink LED */
        mac->ops.blink_led = e1000_blink_led_generic;
        /* setup LED */
@@ -290,8 +276,10 @@ static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
        /* link info */
        mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
 
-out:
-       return ret_val;
+       /* set lan id for port to determine which phy lock to use */
+       hw->mac.ops.set_lan_id(hw);
+
+       return E1000_SUCCESS;
 }
 
 /**
@@ -307,7 +295,6 @@ void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
        hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
        hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
        hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
-       e1000_get_bus_info_pcie_generic(hw);
 }
 
 /**
@@ -342,7 +329,6 @@ static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
        e1000_release_swfw_sync_80003es2lan(hw, mask);
 }
 
-
 /**
  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
  *  @hw: pointer to the HW structure
@@ -532,28 +518,36 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
                goto out;
        }
 
-       /*
-        * The "ready" bit in the MDIC register may be incorrectly set
-        * before the device has completed the "Page Select" MDI
-        * transaction.  So we wait 200us after each MDI command...
-        */
-       usec_delay(200);
+       if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
+               /*
+                * The "ready" bit in the MDIC register may be incorrectly set
+                * before the device has completed the "Page Select" MDI
+                * transaction.  So we wait 200us after each MDI command...
+                */
+               usec_delay(200);
 
-       /* ...and verify the command was successful. */
-       ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
+               /* ...and verify the command was successful. */
+               ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 
-       if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
-               ret_val = -E1000_ERR_PHY;
-               e1000_release_phy_80003es2lan(hw);
-               goto out;
-       }
+               if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
+                       ret_val = -E1000_ERR_PHY;
+                       e1000_release_phy_80003es2lan(hw);
+                       goto out;
+               }
 
-       usec_delay(200);
+               usec_delay(200);
 
-       ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-                                          data);
+               ret_val = e1000_read_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+                                                 data);
+
+               usec_delay(200);
+       } else {
+               ret_val = e1000_read_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+                                                 data);
+       }
 
-       usec_delay(200);
        e1000_release_phy_80003es2lan(hw);
 
 out:
@@ -599,29 +593,36 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
                goto out;
        }
 
+       if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
+               /*
+                * The "ready" bit in the MDIC register may be incorrectly set
+                * before the device has completed the "Page Select" MDI
+                * transaction.  So we wait 200us after each MDI command...
+                */
+               usec_delay(200);
 
-       /*
-        * The "ready" bit in the MDIC register may be incorrectly set
-        * before the device has completed the "Page Select" MDI
-        * transaction.  So we wait 200us after each MDI command...
-        */
-       usec_delay(200);
+               /* ...and verify the command was successful. */
+               ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
 
-       /* ...and verify the command was successful. */
-       ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
+               if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
+                       ret_val = -E1000_ERR_PHY;
+                       e1000_release_phy_80003es2lan(hw);
+                       goto out;
+               }
 
-       if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
-               ret_val = -E1000_ERR_PHY;
-               e1000_release_phy_80003es2lan(hw);
-               goto out;
-       }
+               usec_delay(200);
 
-       usec_delay(200);
+               ret_val = e1000_write_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+                                                 data);
 
-       ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-                                         data);
+               usec_delay(200);
+       } else {
+               ret_val = e1000_write_phy_reg_mdic(hw,
+                                                 MAX_PHY_REG_ADDRESS & offset,
+                                                 data);
+       }
 
-       usec_delay(200);
        e1000_release_phy_80003es2lan(hw);
 
 out:
@@ -802,17 +803,16 @@ static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 
        index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 
-       if (index < GG82563_CABLE_LENGTH_TABLE_SIZE + 5) {
-               phy->min_cable_length = e1000_gg82563_cable_length_table[index];
-               phy->max_cable_length =
-                                e1000_gg82563_cable_length_table[index+5];
-
-               phy->cable_length = (phy->min_cable_length +
-                                    phy->max_cable_length) / 2;
-       } else {
-               ret_val = E1000_ERR_PHY;
+       if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
+               ret_val = -E1000_ERR_PHY;
+               goto out;
        }
 
+       phy->min_cable_length = e1000_gg82563_cable_length_table[index];
+       phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
+
+       phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
+
 out:
        return ret_val;
 }
@@ -892,7 +892,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
        E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
        icr = E1000_READ_REG(hw, E1000_ICR);
 
-       e1000_check_alt_mac_addr_generic(hw);
+       ret_val = e1000_check_alt_mac_addr_generic(hw);
 
 out:
        return ret_val;
@@ -916,11 +916,10 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
        e1000_initialize_hw_bits_80003es2lan(hw);
 
        /* Initialize identification LED */
-       ret_val = e1000_id_led_init_generic(hw);
-       if (ret_val) {
+       ret_val = mac->ops.id_led_init(hw);
+       if (ret_val)
                DEBUGOUT("Error initializing identification LED\n");
                /* This is not fatal and we should not stop init due to this */
-       }
 
        /* Disabling VLAN filtering */
        DEBUGOUT("Initializing the IEEE VLAN\n");
@@ -970,6 +969,19 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
        reg_data &= ~0x00100000;
        E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 
+       /* default to TRUE to enable the MDIC W/A */
+       hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
+
+       ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
+                                     E1000_KMRNCTRLSTA_OFFSET >>
+                                     E1000_KMRNCTRLSTA_OFFSET_SHIFT,
+                                     &i);
+       if (!ret_val) {
+               if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
+                    E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
+                       hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
+       }
+
        /*
         * Clear all of the statistics registers (clear on read).  It is
         * important that we do this after we have tried to establish link
@@ -1036,77 +1048,78 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 
        DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
 
-       if (!phy->reset_disable) {
-               ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-                                            &data);
-               if (ret_val)
-                       goto out;
+       if (phy->reset_disable)
+               goto skip_reset;
 
-               data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
-               /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
-               data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
+       ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                    &data);
+       if (ret_val)
+               goto out;
 
-               ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-                                             data);
-               if (ret_val)
-                       goto out;
+       data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+       /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
+       data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 
-               /*
-                * Options:
-                *   MDI/MDI-X = 0 (default)
-                *   0 - Auto for all speeds
-                *   1 - MDI mode
-                *   2 - MDI-X mode
-                *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
-                */
-               ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
-               if (ret_val)
-                       goto out;
+       ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                     data);
+       if (ret_val)
+               goto out;
 
-               data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
+       /*
+        * Options:
+        *   MDI/MDI-X = 0 (default)
+        *   0 - Auto for all speeds
+        *   1 - MDI mode
+        *   2 - MDI-X mode
+        *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+        */
+       ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
+       if (ret_val)
+               goto out;
 
-               switch (phy->mdix) {
-               case 1:
-                       data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
-                       break;
-               case 2:
-                       data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
-                       break;
-               case 0:
-               default:
-                       data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
-                       break;
-               }
+       data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 
-               /*
-                * Options:
-                *   disable_polarity_correction = 0 (default)
-                *       Automatic Correction for Reversed Cable Polarity
-                *   0 - Disabled
-                *   1 - Enabled
-                */
-               data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
-               if (phy->disable_polarity_correction)
-                       data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+       switch (phy->mdix) {
+       case 1:
+               data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
+               break;
+       case 2:
+               data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
+               break;
+       case 0:
+       default:
+               data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
+               break;
+       }
 
-               ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
-               if (ret_val)
-                       goto out;
+       /*
+        * Options:
+        *   disable_polarity_correction = 0 (default)
+        *       Automatic Correction for Reversed Cable Polarity
+        *   0 - Disabled
+        *   1 - Enabled
+        */
+       data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+       if (phy->disable_polarity_correction)
+               data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 
-               /* SW Reset the PHY so all changes take effect */
-               ret_val = hw->phy.ops.commit(hw);
-               if (ret_val) {
-                       DEBUGOUT("Error Resetting the PHY\n");
-                       goto out;
-               }
+       ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);
+       if (ret_val)
+               goto out;
 
+       /* SW Reset the PHY so all changes take effect */
+       ret_val = hw->phy.ops.commit(hw);
+       if (ret_val) {
+               DEBUGOUT("Error Resetting the PHY\n");
+               goto out;
        }
 
+skip_reset:
        /* Bypass Rx and Tx FIFO's */
        ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-                               E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
-                               E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
-                                       E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
+                                       E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
+                                       E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
+                                       E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
        if (ret_val)
                goto out;
 
@@ -1147,22 +1160,19 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
        if (!(hw->mac.ops.check_mng_mode(hw))) {
                /* Enable Electrical Idle on the PHY */
                data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
-               ret_val = hw->phy.ops.write_reg(hw,
-                                               GG82563_PHY_PWR_MGMT_CTRL,
+               ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
                                                data);
                if (ret_val)
                        goto out;
-               ret_val = hw->phy.ops.read_reg(hw,
-                                              GG82563_PHY_KMRN_MODE_CTRL,
-                                              &data);
-                       if (ret_val)
-                               goto out;
+
+               ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                              &data);
+               if (ret_val)
+                       goto out;
 
                data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
-               ret_val = hw->phy.ops.write_reg(hw,
-                                               GG82563_PHY_KMRN_MODE_CTRL,
+               ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
                                                data);
-
                if (ret_val)
                        goto out;
        }
@@ -1261,7 +1271,6 @@ static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
        DEBUGFUNC("e1000_configure_on_link_up");
 
        if (hw->phy.media_type == e1000_media_type_copper) {
-
                ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
                                                                    &speed,
                                                                    &duplex);
@@ -1308,7 +1317,6 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
        tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
        E1000_WRITE_REG(hw, E1000_TIPG, tipg);
 
-
        do {
                ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
                                               &reg_data);
@@ -1362,7 +1370,6 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
        tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
        E1000_WRITE_REG(hw, E1000_TIPG, tipg);
 
-
        do {
                ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
                                               &reg_data);
@@ -1393,7 +1400,8 @@ out:
  *  using the kumeran interface.  The information retrieved is stored in data.
  *  Release the semaphore before exiting.
  **/
-s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 *data)
+static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+                                           u16 *data)
 {
        u32 kmrnctrlsta;
        s32 ret_val = E1000_SUCCESS;
@@ -1429,7 +1437,8 @@ out:
  *  at the offset using the kumeran interface.  Release semaphore
  *  before exiting.
  **/
-s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, u16 data)
+static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
+                                            u16 data)
 {
        u32 kmrnctrlsta;
        s32 ret_val = E1000_SUCCESS;
@@ -1461,9 +1470,19 @@ static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
        s32 ret_val = E1000_SUCCESS;
 
        DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
-       if (e1000_check_alt_mac_addr_generic(hw))
-               ret_val = e1000_read_mac_addr_generic(hw);
 
+       /*
+        * If there's an alternate MAC address place it in RAR0
+        * so that it will override the Si installed default perm
+        * address.
+        */
+       ret_val = e1000_check_alt_mac_addr_generic(hw);
+       if (ret_val)
+               goto out;
+
+       ret_val = e1000_read_mac_addr_generic(hw);
+
+out:
        return ret_val;
 }
 
index 7bf8d9d..0b33329 100644 (file)
@@ -1,6 +1,6 @@
-/*******************************************************************************
+/******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -29,9 +29,8 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 
-*******************************************************************************/
-/* $FreeBSD$ */
-
+******************************************************************************/
+/*$FreeBSD: $*/
 
 #ifndef _E1000_80003ES2LAN_H_
 #define _E1000_80003ES2LAN_H_
@@ -49,6 +48,9 @@
 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
 
+#define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
+#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
+
 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
 
index 6967261..a3d238f 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 /*
  * 82540EM Gigabit Ethernet Controller
@@ -57,6 +57,7 @@ static s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
 static s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
 static s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
+static s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
 
 /**
  * e1000_init_phy_params_82540 - Init PHY func ptrs.
@@ -227,8 +228,10 @@ static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
        mac->ops.write_vfta = e1000_write_vfta_generic;
        /* clearing VFTA */
        mac->ops.clear_vfta = e1000_clear_vfta_generic;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_generic;
+       /* read mac address */
+       mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
+       /* ID LED init */
+       mac->ops.id_led_init = e1000_id_led_init_generic;
        /* setup LED */
        mac->ops.setup_led = e1000_setup_led_generic;
        /* cleanup LED */
@@ -332,7 +335,7 @@ static s32 e1000_init_hw_82540(struct e1000_hw *hw)
        DEBUGFUNC("e1000_init_hw_82540");
 
        /* Initialize identification LED */
-       ret_val = e1000_id_led_init_generic(hw);
+       ret_val = mac->ops.id_led_init(hw);
        if (ret_val) {
                DEBUGOUT("Error initializing identification LED\n");
                /* This is not fatal and we should not stop init due to this */
@@ -674,3 +677,45 @@ static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
        E1000_READ_REG(hw, E1000_MGTPTC);
 }
 
+/**
+ *  e1000_read_mac_addr_82540 - Read device MAC address
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the device MAC address from the EEPROM and stores the value.
+ *  Since devices with two ports use the same EEPROM, we increment the
+ *  last bit in the MAC address for the second port.
+ *
+ *  This version is being used over generic because of customer issues
+ *  with VmWare and Virtual Box when using generic. It seems in
+ *  the emulated 82545, RAR[0] does NOT have a valid address after a
+ *  reset, this older method works and using this breaks nothing for
+ *  these legacy adapters.
+ **/
+s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
+{
+       s32  ret_val = E1000_SUCCESS;
+       u16 offset, nvm_data, i;
+
+       DEBUGFUNC("e1000_read_mac_addr");
+
+       for (i = 0; i < ETH_ADDR_LEN; i += 2) {
+               offset = i >> 1;
+               ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
+               if (ret_val) {
+                       DEBUGOUT("NVM Read Error\n");
+                       goto out;
+               }
+               hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
+               hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
+       }
+
+       /* Flip last bit of mac address if we're on second port */
+       if (hw->bus.func == E1000_FUNC_1)
+               hw->mac.perm_addr[5] ^= 1;
+
+       for (i = 0; i < ETH_ADDR_LEN; i++)
+               hw->mac.addr[i] = hw->mac.perm_addr[i];
+
+out:
+       return ret_val;
+}
index 03d1103..838e285 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 /*
  * 82541EI Gigabit Ethernet Controller
@@ -259,8 +259,8 @@ static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
        mac->ops.write_vfta = e1000_write_vfta_generic;
        /* clearing VFTA */
        mac->ops.clear_vfta = e1000_clear_vfta_generic;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_generic;
+       /* ID LED init */
+       mac->ops.id_led_init = e1000_id_led_init_generic;
        /* setup LED */
        mac->ops.setup_led = e1000_setup_led_82541;
        /* cleanup LED */
@@ -375,17 +375,25 @@ static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
 {
        struct e1000_mac_info *mac = &hw->mac;
+       struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
        u32 i, txdctl;
        s32 ret_val;
 
        DEBUGFUNC("e1000_init_hw_82541");
 
        /* Initialize identification LED */
-       ret_val = e1000_id_led_init_generic(hw);
+       ret_val = mac->ops.id_led_init(hw);
        if (ret_val) {
                DEBUGOUT("Error initializing identification LED\n");
                /* This is not fatal and we should not stop init due to this */
        }
+        
+       /* Storing the Speed Power Down  value for later use */
+       ret_val = hw->phy.ops.read_reg(hw,
+                                      IGP01E1000_GMII_FIFO,
+                                      &dev_spec->spd_default);
+       if (ret_val)
+               goto out;
 
        /* Disabling VLAN filtering */
        DEBUGOUT("Initializing the IEEE VLAN\n");
@@ -423,6 +431,7 @@ static s32 e1000_init_hw_82541(struct e1000_hw *hw)
         */
        e1000_clear_hw_cntrs_82541(hw);
 
+out:
        return ret_val;
 }
 
index 3b6b961..6db02d2 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 #ifndef _E1000_82541_H_
 #define _E1000_82541_H_
index 3ce3657..2675d8e 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 /*
  * 82542 Gigabit Ethernet Controller
@@ -49,6 +49,7 @@ static s32  e1000_led_on_82542(struct e1000_hw *hw);
 static s32  e1000_led_off_82542(struct e1000_hw *hw);
 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
+static s32  e1000_read_mac_addr_82542(struct e1000_hw *hw);
 
 /**
  *  e1000_init_phy_params_82542 - Init PHY func ptrs.
@@ -132,8 +133,8 @@ static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
        mac->ops.write_vfta = e1000_write_vfta_generic;
        /* clearing VFTA */
        mac->ops.clear_vfta = e1000_clear_vfta_generic;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_generic;
+       /* read mac address */
+       mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
        /* set RAR */
        mac->ops.rar_set = e1000_rar_set_82542;
        /* turn on/off LED */
@@ -554,3 +555,34 @@ static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
        E1000_READ_REG(hw, E1000_PTC1023);
        E1000_READ_REG(hw, E1000_PTC1522);
 }
+
+/**
+ *  e1000_read_mac_addr_82542 - Read device MAC address
+ *  @hw: pointer to the HW structure
+ *
+ *  Reads the device MAC address from the EEPROM and stores the value.
+ **/
+s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
+{
+       s32  ret_val = E1000_SUCCESS;
+       u16 offset, nvm_data, i;
+
+       DEBUGFUNC("e1000_read_mac_addr");
+
+       for (i = 0; i < ETH_ADDR_LEN; i += 2) {
+               offset = i >> 1;
+               ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
+               if (ret_val) {
+                       DEBUGOUT("NVM Read Error\n");
+                       goto out;
+               }
+               hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
+               hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
+       }
+
+       for (i = 0; i < ETH_ADDR_LEN; i++)
+               hw->mac.addr[i] = hw->mac.perm_addr[i];
+
+out:
+       return ret_val;
+}
index 97c7f3b..069f40a 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 /*
  * 82543GC Gigabit Ethernet Controller (Fiber)
@@ -63,7 +63,6 @@ static s32  e1000_led_on_82543(struct e1000_hw *hw);
 static s32  e1000_led_off_82543(struct e1000_hw *hw);
 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
                                    u32 value);
-static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value);
 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
 static s32  e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
@@ -244,8 +243,6 @@ static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
        mac->ops.write_vfta = e1000_write_vfta_82543;
        /* clearing VFTA */
        mac->ops.clear_vfta = e1000_clear_vfta_generic;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_82543;
        /* turn on/off LED */
        mac->ops.led_on = e1000_led_on_82543;
        mac->ops.led_off = e1000_led_off_82543;
@@ -1477,45 +1474,6 @@ static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
 }
 
 /**
- *  e1000_mta_set_82543 - Set multicast filter table address
- *  @hw: pointer to the HW structure
- *  @hash_value: determines the MTA register and bit to set
- *
- *  The multicast table address is a register array of 32-bit registers.
- *  The hash_value is used to determine what register the bit is in, the
- *  current value is read, the new bit is OR'd in and the new value is
- *  written back into the register.
- **/
-static void e1000_mta_set_82543(struct e1000_hw *hw, u32 hash_value)
-{
-       u32 hash_bit, hash_reg, mta, temp;
-
-       DEBUGFUNC("e1000_mta_set_82543");
-
-       hash_reg = (hash_value >> 5);
-
-       /*
-        * If we are on an 82544 and we are trying to write an odd offset
-        * in the MTA, save off the previous entry before writing and
-        * restore the old value after writing.
-        */
-       if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) {
-               hash_reg &= (hw->mac.mta_reg_count - 1);
-               hash_bit = hash_value & 0x1F;
-               mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
-               mta |= (1 << hash_bit);
-               temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1);
-
-               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
-               E1000_WRITE_FLUSH(hw);
-               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp);
-               E1000_WRITE_FLUSH(hw);
-       } else {
-               e1000_mta_set_generic(hw, hash_value);
-       }
-}
-
-/**
  *  e1000_led_on_82543 - Turn on SW controllable LED
  *  @hw: pointer to the HW structure
  *
index 60e5c15..53a22bc 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 #ifndef _E1000_82543_H_
 #define _E1000_82543_H_
index db7852a..2eeef7d 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 /*
  * 82571EB Gigabit Ethernet Controller
@@ -46,6 +46,7 @@
  * 82573E Gigabit Ethernet Controller (Copper)
  * 82573L Gigabit Ethernet Controller
  * 82574L Gigabit Network Connection
+ * 82583V Gigabit Network Connection
  */
 
 #include "e1000_api.h"
@@ -67,11 +68,9 @@ static s32  e1000_init_hw_82571(struct e1000_hw *hw);
 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
 static s32 e1000_led_on_82574(struct e1000_hw *hw);
-static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
-                                           u8 *mc_addr_list, u32 mc_addr_count,
-                                           u32 rar_used_count, u32 rar_count);
 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
+static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
@@ -79,6 +78,10 @@ static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
+static s32  e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
+static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
+static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
+static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
                                        u16 words, u16 *data);
@@ -105,10 +108,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
        phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
        phy->reset_delay_us              = 100;
 
-       phy->ops.acquire                 = e1000_get_hw_semaphore_82571;
-       phy->ops.check_polarity          = e1000_check_polarity_igp;
        phy->ops.check_reset_block       = e1000_check_reset_block_generic;
-       phy->ops.release                 = e1000_put_hw_semaphore_82571;
        phy->ops.reset                   = e1000_phy_hw_reset_generic;
        phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
        phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
@@ -121,10 +121,13 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
                phy->type                   = e1000_phy_igp_2;
                phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
                phy->ops.get_info           = e1000_get_phy_info_igp;
+               phy->ops.check_polarity     = e1000_check_polarity_igp;
                phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
                phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
                phy->ops.read_reg           = e1000_read_phy_reg_igp;
                phy->ops.write_reg          = e1000_write_phy_reg_igp;
+               phy->ops.acquire            = e1000_get_hw_semaphore_82571;
+               phy->ops.release            = e1000_put_hw_semaphore_82571;
 
                /* This uses above function pointers */
                ret_val = e1000_get_phy_id_82571(hw);
@@ -132,6 +135,7 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
                /* Verify PHY ID */
                if (phy->id != IGP01E1000_I_PHY_ID) {
                        ret_val = -E1000_ERR_PHY;
+                       DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
                        goto out;
                }
                break;
@@ -139,11 +143,14 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
                phy->type                   = e1000_phy_m88;
                phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
                phy->ops.get_info           = e1000_get_phy_info_m88;
+               phy->ops.check_polarity     = e1000_check_polarity_m88;
                phy->ops.commit             = e1000_phy_sw_reset_generic;
                phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
                phy->ops.get_cable_length   = e1000_get_cable_length_m88;
                phy->ops.read_reg           = e1000_read_phy_reg_m88;
                phy->ops.write_reg          = e1000_write_phy_reg_m88;
+               phy->ops.acquire            = e1000_get_hw_semaphore_82571;
+               phy->ops.release            = e1000_put_hw_semaphore_82571;
 
                /* This uses above function pointers */
                ret_val = e1000_get_phy_id_82571(hw);
@@ -156,14 +163,18 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
                }
                break;
        case e1000_82574:
+       case e1000_82583:
                phy->type                   = e1000_phy_bm;
                phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
                phy->ops.get_info           = e1000_get_phy_info_m88;
+               phy->ops.check_polarity     = e1000_check_polarity_m88;
                phy->ops.commit             = e1000_phy_sw_reset_generic;
                phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
                phy->ops.get_cable_length   = e1000_get_cable_length_m88;
                phy->ops.read_reg           = e1000_read_phy_reg_bm2;
                phy->ops.write_reg          = e1000_write_phy_reg_bm2;
+               phy->ops.acquire            = e1000_get_hw_semaphore_82574;
+               phy->ops.release            = e1000_put_hw_semaphore_82574;
 
                /* This uses above function pointers */
                ret_val = e1000_get_phy_id_82571(hw);
@@ -216,6 +227,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
        switch (hw->mac.type) {
        case e1000_82573:
        case e1000_82574:
+       case e1000_82583:
                if (((eecd >> 15) & 0x3) == 0x3) {
                        nvm->type = e1000_nvm_flash_hw;
                        nvm->word_size = 2048;
@@ -246,9 +258,18 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
        }
 
        /* Function Pointers */
-       nvm->ops.acquire       = e1000_acquire_nvm_82571;
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+               nvm->ops.acquire = e1000_get_hw_semaphore_82574;
+               nvm->ops.release = e1000_put_hw_semaphore_82574;
+               break;
+       default:
+               nvm->ops.acquire = e1000_acquire_nvm_82571;
+               nvm->ops.release = e1000_release_nvm_82571;
+               break;
+       }
        nvm->ops.read          = e1000_read_nvm_eerd;
-       nvm->ops.release       = e1000_release_nvm_82571;
        nvm->ops.update        = e1000_update_nvm_checksum_82571;
        nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
        nvm->ops.valid_led_default = e1000_valid_led_default_82571;
@@ -264,25 +285,42 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 {
        struct e1000_mac_info *mac = &hw->mac;
-       s32 ret_val = E1000_SUCCESS;
+       u32 swsm = 0;
+       u32 swsm2 = 0;
+       bool force_clear_smbi = FALSE;
 
        DEBUGFUNC("e1000_init_mac_params_82571");
 
-       /* Set media type */
+       /* Set media type and media-dependent function pointers */
        switch (hw->device_id) {
        case E1000_DEV_ID_82571EB_FIBER:
        case E1000_DEV_ID_82572EI_FIBER:
        case E1000_DEV_ID_82571EB_QUAD_FIBER:
                hw->phy.media_type = e1000_media_type_fiber;
+               mac->ops.setup_physical_interface =
+                       e1000_setup_fiber_serdes_link_82571;
+               mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
+               mac->ops.get_link_up_info =
+                       e1000_get_speed_and_duplex_fiber_serdes_generic;
                break;
        case E1000_DEV_ID_82571EB_SERDES:
        case E1000_DEV_ID_82571EB_SERDES_DUAL:
        case E1000_DEV_ID_82571EB_SERDES_QUAD:
        case E1000_DEV_ID_82572EI_SERDES:
                hw->phy.media_type = e1000_media_type_internal_serdes;
+               mac->ops.setup_physical_interface =
+                       e1000_setup_fiber_serdes_link_82571;
+               mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
+               mac->ops.get_link_up_info =
+                       e1000_get_speed_and_duplex_fiber_serdes_generic;
                break;
        default:
                hw->phy.media_type = e1000_media_type_copper;
+               mac->ops.setup_physical_interface =
+                       e1000_setup_copper_link_82571;
+               mac->ops.check_for_link = e1000_check_for_copper_link_generic;
+               mac->ops.get_link_up_info =
+                       e1000_get_speed_and_duplex_copper_generic;
                break;
        }
 
@@ -292,96 +330,117 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
        mac->rar_entry_count = E1000_RAR_ENTRIES;
        /* Set if part includes ASF firmware */
        mac->asf_firmware_present = TRUE;
-       /* Set if manageability features are enabled. */
-       mac->arc_subsystem_valid =
-               (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-                       ? TRUE : FALSE;
+       /* Adaptive IFS supported */
+       mac->adaptive_ifs = TRUE;
 
        /* Function pointers */
 
        /* bus type/speed/width */
        mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
-       /* function id */
-       switch (hw->mac.type) {
-       case e1000_82573:
-       case e1000_82574:
-               mac->ops.set_lan_id = e1000_set_lan_id_single_port;
-               break;
-       default:
-               break;
-       }
        /* reset */
        mac->ops.reset_hw = e1000_reset_hw_82571;
        /* hw initialization */
        mac->ops.init_hw = e1000_init_hw_82571;
        /* link setup */
        mac->ops.setup_link = e1000_setup_link_82571;
-       /* physical interface link setup */
-       mac->ops.setup_physical_interface =
-               (hw->phy.media_type == e1000_media_type_copper)
-                       ? e1000_setup_copper_link_82571
-                       : e1000_setup_fiber_serdes_link_82571;
-       /* check for link */
-       switch (hw->phy.media_type) {
-       case e1000_media_type_copper:
-               mac->ops.check_for_link = e1000_check_for_copper_link_generic;
-               break;
-       case e1000_media_type_fiber:
-               mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
-               break;
-       case e1000_media_type_internal_serdes:
-               mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
-               break;
-       default:
-               ret_val = -E1000_ERR_CONFIG;
-               goto out;
-               break;
-       }
-       /* check management mode */
-       switch (hw->mac.type) {
-       case e1000_82574:
-               mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
-               break;
-       default:
-               mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
-               break;
-       }
        /* multicast address update */
-       mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82571;
+       mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
        /* writing VFTA */
        mac->ops.write_vfta = e1000_write_vfta_generic;
        /* clearing VFTA */
        mac->ops.clear_vfta = e1000_clear_vfta_82571;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_generic;
        /* read mac address */
        mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
+       /* ID LED init */
+       mac->ops.id_led_init = e1000_id_led_init_generic;
        /* blink LED */
        mac->ops.blink_led = e1000_blink_led_generic;
        /* setup LED */
        mac->ops.setup_led = e1000_setup_led_generic;
        /* cleanup LED */
        mac->ops.cleanup_led = e1000_cleanup_led_generic;
-       /* turn on/off LED */
+       /* turn off LED */
+       mac->ops.led_off = e1000_led_off_generic;
+       /* clear hardware counters */
+       mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
+
+       /* MAC-specific function pointers */
        switch (hw->mac.type) {
+       case e1000_82573:
+               mac->ops.set_lan_id = e1000_set_lan_id_single_port;
+               mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
+               mac->ops.led_on = e1000_led_on_generic;
+
+               /* FWSM register */
+               mac->has_fwsm = TRUE;
+               /*
+                * ARC supported; valid only if manageability features are
+                * enabled.
+                */
+               mac->arc_subsystem_valid =
+                       (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
+                       ? TRUE : FALSE;
+               break;
        case e1000_82574:
+       case e1000_82583:
+               mac->ops.set_lan_id = e1000_set_lan_id_single_port;
+               mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
                mac->ops.led_on = e1000_led_on_82574;
                break;
        default:
+               mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
                mac->ops.led_on = e1000_led_on_generic;
+
+               /* FWSM register */
+               mac->has_fwsm = TRUE;
                break;
        }
-       mac->ops.led_off = e1000_led_off_generic;
-       /* clear hardware counters */
-       mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
-       /* link info */
-       mac->ops.get_link_up_info =
-               (hw->phy.media_type == e1000_media_type_copper)
-                       ? e1000_get_speed_and_duplex_copper_generic
-                       : e1000_get_speed_and_duplex_fiber_serdes_generic;
 
-out:
-       return ret_val;
+       /*
+        * Ensure that the inter-port SWSM.SMBI lock bit is clear before
+        * first NVM or PHY acess. This should be done for single-port
+        * devices, and for one port only on dual-port devices so that
+        * for those devices we can still use the SMBI lock to synchronize
+        * inter-port accesses to the PHY & NVM.
+        */
+       switch (hw->mac.type) {
+       case e1000_82571:
+       case e1000_82572:
+               swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
+
+               if (!(swsm2 & E1000_SWSM2_LOCK)) {
+                       /* Only do this for the first interface on this card */
+                       E1000_WRITE_REG(hw, E1000_SWSM2,
+                           swsm2 | E1000_SWSM2_LOCK);
+                       force_clear_smbi = TRUE;
+               } else
+                       force_clear_smbi = FALSE;
+               break;
+       default:
+               force_clear_smbi = TRUE;
+               break;
+       }
+
+       if (force_clear_smbi) {
+               /* Make sure SWSM.SMBI is clear */
+               swsm = E1000_READ_REG(hw, E1000_SWSM);
+               if (swsm & E1000_SWSM_SMBI) {
+                       /* This bit should not be set on a first interface, and
+                        * indicates that the bootagent or EFI code has
+                        * improperly left this bit enabled
+                        */
+                       DEBUGOUT("Please update your 82571 Bootagent\n");
+               }
+               E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
+       }
+
+       /*
+        * Initialze device specific counter of SMBI acquisition
+        * timeouts.
+        */
+        hw->dev_spec._82571.smb_counter = 0;
+
+       return E1000_SUCCESS;
 }
 
 /**
@@ -429,6 +488,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
                ret_val = e1000_get_phy_id(hw);
                break;
        case e1000_82574:
+       case e1000_82583:
                ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
                if (ret_val)
                        goto out;
@@ -446,7 +506,6 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
                ret_val = -E1000_ERR_PHY;
                break;
        }
-
 out:
        return ret_val;
 }
@@ -461,13 +520,39 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 {
        u32 swsm;
        s32 ret_val = E1000_SUCCESS;
-       s32 timeout = hw->nvm.word_size + 1;
+       s32 sw_timeout = hw->nvm.word_size + 1;
+       s32 fw_timeout = hw->nvm.word_size + 1;
        s32 i = 0;
 
        DEBUGFUNC("e1000_get_hw_semaphore_82571");
 
+       /*
+        * If we have timedout 3 times on trying to acquire
+        * the inter-port SMBI semaphore, there is old code
+        * operating on the other port, and it is not
+        * releasing SMBI. Modify the number of times that
+        * we try for the semaphore to interwork with this
+        * older code.
+        */
+       if (hw->dev_spec._82571.smb_counter > 2)
+               sw_timeout = 1;
+
+       /* Get the SW semaphore */
+       while (i < sw_timeout) {
+               swsm = E1000_READ_REG(hw, E1000_SWSM);
+               if (!(swsm & E1000_SWSM_SMBI))
+                       break;
+
+               usec_delay(50);
+               i++;
+       }
+
+       if (i == sw_timeout) {
+               DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
+               hw->dev_spec._82571.smb_counter++;
+       }
        /* Get the FW semaphore. */
-       for (i = 0; i < timeout; i++) {
+       for (i = 0; i < fw_timeout; i++) {
                swsm = E1000_READ_REG(hw, E1000_SWSM);
                E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 
@@ -478,9 +563,9 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
                usec_delay(50);
        }
 
-       if (i == timeout) {
+       if (i == fw_timeout) {
                /* Release semaphores */
-               e1000_put_hw_semaphore_generic(hw);
+               e1000_put_hw_semaphore_82571(hw);
                DEBUGOUT("Driver can't access the NVM\n");
                ret_val = -E1000_ERR_NVM;
                goto out;
@@ -500,16 +585,107 @@ static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 {
        u32 swsm;
 
-       DEBUGFUNC("e1000_put_hw_semaphore_82571");
+       DEBUGFUNC("e1000_put_hw_semaphore_generic");
 
        swsm = E1000_READ_REG(hw, E1000_SWSM);
 
-       swsm &= ~E1000_SWSM_SWESMBI;
+       swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 
        E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 }
 
 /**
+ *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the HW semaphore during reset.
+ *
+ **/
+static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
+{
+       u32 extcnf_ctrl;
+       s32 ret_val = E1000_SUCCESS;
+       s32 i = 0;
+
+       DEBUGFUNC("e1000_get_hw_semaphore_82573");
+
+       extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
+       extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+       do {
+               E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
+               extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
+
+               if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
+                       break;
+
+               extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+               msec_delay(2);
+               i++;
+       } while (i < MDIO_OWNERSHIP_TIMEOUT);
+
+       if (i == MDIO_OWNERSHIP_TIMEOUT) {
+               /* Release semaphores */
+               e1000_put_hw_semaphore_82573(hw);
+               DEBUGOUT("Driver can't access the PHY\n");
+               ret_val = -E1000_ERR_PHY;
+               goto out;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Release hardware semaphore used during reset.
+ *
+ **/
+static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
+{
+       u32 extcnf_ctrl;
+
+       DEBUGFUNC("e1000_put_hw_semaphore_82573");
+
+       extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
+       extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+       E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
+}
+
+/**
+ *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the HW semaphore to access the PHY or NVM.
+ *
+ **/
+static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
+{
+       s32 ret_val;
+
+       DEBUGFUNC("e1000_get_hw_semaphore_82574");
+
+       ret_val = e1000_get_hw_semaphore_82573(hw);
+       return ret_val;
+}
+
+/**
+ *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Release hardware semaphore used to access the PHY or NVM
+ *
+ **/
+static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
+{
+       DEBUGFUNC("e1000_put_hw_semaphore_82574");
+
+       e1000_put_hw_semaphore_82573(hw);
+}
+
+/**
  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
  *  @hw: pointer to the HW structure
  *
@@ -528,8 +704,13 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
        if (ret_val)
                goto out;
 
-       if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
+       switch (hw->mac.type) {
+       case e1000_82573:
+               break;
+       default:
                ret_val = e1000_acquire_nvm_generic(hw);
+               break;
+       }
 
        if (ret_val)
                e1000_put_hw_semaphore_82571(hw);
@@ -574,6 +755,7 @@ static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
        switch (hw->mac.type) {
        case e1000_82573:
        case e1000_82574:
+       case e1000_82583:
                ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
                break;
        case e1000_82571:
@@ -742,7 +924,8 @@ static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
        DEBUGFUNC("e1000_get_cfg_done_82571");
 
        while (timeout) {
-               if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
+               if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
+                   E1000_NVM_CFG_DONE_PORT_0)
                        break;
                msec_delay(1);
                timeout--;
@@ -849,9 +1032,8 @@ out:
  **/
 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 {
-       u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
+       u32 ctrl, ctrl_ext, icr;
        s32 ret_val;
-       u16 i = 0;
 
        DEBUGFUNC("e1000_reset_hw_82571");
 
@@ -876,29 +1058,35 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
         * Must acquire the MDIO ownership before MAC reset.
         * Ownership defaults to firmware after a reset.
         */
-       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
-               extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
-               extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
-               do {
-                       E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
-                       extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
-
-                       if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
-                               break;
-
-                       extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
-                       msec_delay(2);
-                       i++;
-               } while (i < MDIO_OWNERSHIP_TIMEOUT);
+       switch (hw->mac.type) {
+       case e1000_82573:
+               ret_val = e1000_get_hw_semaphore_82573(hw);
+               break;
+       case e1000_82574:
+       case e1000_82583:
+               ret_val = e1000_get_hw_semaphore_82574(hw);
+               break;
+       default:
+               break;
        }
+       if (ret_val)
+               DEBUGOUT("Cannot acquire MDIO ownership\n");
 
        ctrl = E1000_READ_REG(hw, E1000_CTRL);
 
        DEBUGOUT("Issuing a global reset to MAC\n");
        E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 
+       /* Must release MDIO ownership and mutex after MAC reset. */
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
+               e1000_put_hw_semaphore_82574(hw);
+               break;
+       default:
+               break;
+       }
+
        if (hw->nvm.type == e1000_nvm_flash_hw) {
                usec_delay(10);
                ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
@@ -917,15 +1105,33 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
         * Need to wait for Phy configuration completion before accessing
         * NVM and Phy.
         */
-       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
+
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
                msec_delay(25);
+               break;
+       default:
+               break;
+       }
 
        /* Clear any pending interrupt events. */
        E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
        icr = E1000_READ_REG(hw, E1000_ICR);
 
-       if (!(e1000_check_alt_mac_addr_generic(hw)))
+       if (hw->mac.type == e1000_82571) {
+               /* Install any alternate MAC address into RAR0 */
+               ret_val = e1000_check_alt_mac_addr_generic(hw);
+               if (ret_val)
+                       goto out;
+
                e1000_set_laa_state_82571(hw, TRUE);
+       }
+
+       /* Reinitialize the 82571 serdes link state machine */
+       if (hw->phy.media_type == e1000_media_type_internal_serdes)
+               hw->mac.serdes_link_state = e1000_serdes_link_down;
 
 out:
        return ret_val;
@@ -949,11 +1155,10 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
        e1000_initialize_hw_bits_82571(hw);
 
        /* Initialize identification LED */
-       ret_val = e1000_id_led_init_generic(hw);
-       if (ret_val) {
+       ret_val = mac->ops.id_led_init(hw);
+       if (ret_val)
                DEBUGOUT("Error initializing identification LED\n");
                /* This is not fatal and we should not stop init due to this */
-       }
 
        /* Disabling VLAN filtering */
        DEBUGOUT("Initializing the IEEE VLAN\n");
@@ -985,17 +1190,23 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
        E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 
        /* ...for both queues. */
-       if (mac->type != e1000_82573 && mac->type != e1000_82574) {
+       switch (mac->type) {
+       case e1000_82573:
+               e1000_enable_tx_pkt_filtering_generic(hw);
+               /* fall through */
+       case e1000_82574:
+       case e1000_82583:
+               reg_data = E1000_READ_REG(hw, E1000_GCR);
+               reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
+               E1000_WRITE_REG(hw, E1000_GCR, reg_data);
+               break;
+       default:
                reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
                reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
                           E1000_TXDCTL_FULL_TX_DESC_WB |
                           E1000_TXDCTL_COUNT_DESC;
                E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
-       } else {
-               e1000_enable_tx_pkt_filtering_generic(hw);
-               reg_data = E1000_READ_REG(hw, E1000_GCR);
-               reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
-               E1000_WRITE_REG(hw, E1000_GCR, reg_data);
+               break;
        }
 
        /*
@@ -1062,25 +1273,70 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
        }
 
        /* Device Control */
-       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
                reg = E1000_READ_REG(hw, E1000_CTRL);
                reg &= ~(1 << 29);
                E1000_WRITE_REG(hw, E1000_CTRL, reg);
+               break;
+       default:
+               break;
        }
 
        /* Extended Device Control */
-       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
                reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
                reg &= ~(1 << 23);
                reg |= (1 << 22);
                E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
+               break;
+       default:
+               break;
        }
 
-       /* PCI-Ex Control Register */
-       if (hw->mac.type == e1000_82574) {
+       if (hw->mac.type == e1000_82571) {
+               reg = E1000_READ_REG(hw, E1000_PBA_ECC);
+               reg |= E1000_PBA_ECC_CORR_EN;
+               E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
+       }
+
+       /*
+        * Workaround for hardware errata.
+        * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
+        */
+       if ((hw->mac.type == e1000_82571) ||
+          (hw->mac.type == e1000_82572)) {
+               reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
+               reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
+               E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
+       }
+
+       /* PCI-Ex Control Registers */
+       switch (hw->mac.type) {
+       case e1000_82574:
+       case e1000_82583:
                reg = E1000_READ_REG(hw, E1000_GCR);
                reg |= (1 << 22);
                E1000_WRITE_REG(hw, E1000_GCR, reg);
+
+               /*
+                * Workaround for hardware errata.
+                * apply workaround for hardware errata documented in errata
+                * docs Fixes issue where some error prone or unreliable PCIe
+                * completions are occurring, particularly with ASPM enabled.
+                * Without fix, issue can cause tx timeouts.
+                */
+               reg = E1000_READ_REG(hw, E1000_GCR2);
+               reg |= 1;
+               E1000_WRITE_REG(hw, E1000_GCR2, reg);
+               break;
+       default:
+               break;
        }
 
        return;
@@ -1102,7 +1358,10 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
 
        DEBUGFUNC("e1000_clear_vfta_82571");
 
-       if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
                if (hw->mng_cookie.vlan_id != 0) {
                        /*
                         * The VFTA is a 4096b bit-field, each identifying
@@ -1112,11 +1371,13 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
                         * the manageability unit.
                         */
                        vfta_offset = (hw->mng_cookie.vlan_id >>
-                                      E1000_VFTA_ENTRY_SHIFT) &
-                                     E1000_VFTA_ENTRY_MASK;
+                               E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
                        vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
-                                              E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
+                               E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
                }
+               break;
+       default:
+               break;
        }
        for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
                /*
@@ -1177,31 +1438,42 @@ static s32 e1000_led_on_82574(struct e1000_hw *hw)
 }
 
 /**
- *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
+ *  e1000_check_phy_82574 - check 82574 phy hung state
  *  @hw: pointer to the HW structure
- *  @mc_addr_list: array of multicast addresses to program
- *  @mc_addr_count: number of multicast addresses to program
- *  @rar_used_count: the first RAR register free to program
- *  @rar_count: total number of supported Receive Address Registers
  *
- *  Updates the Receive Address Registers and Multicast Table Array.
- *  The caller must have a packed mc_addr_list of multicast addresses.
- *  The parameter rar_count will usually be hw->mac.rar_entry_count
- *  unless there are workarounds that change this.
+ *  Returns whether phy is hung or not
  **/
-static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
-                                           u8 *mc_addr_list, u32 mc_addr_count,
-                                           u32 rar_used_count, u32 rar_count)
+bool e1000_check_phy_82574(struct e1000_hw *hw)
 {
-       DEBUGFUNC("e1000_update_mc_addr_list_82571");
+       u16 status_1kbt = 0;
+       u16 receive_errors = 0;
+       bool phy_hung = FALSE;
+       s32 ret_val = E1000_SUCCESS;
 
-       if (e1000_get_laa_state_82571(hw))
-               rar_count--;
+       DEBUGFUNC("e1000_check_phy_82574");
 
-       e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
-                                         rar_used_count, rar_count);
+       /*
+        * Read PHY Receive Error counter first, if its is max - all F's then
+        * read the Base1000T status register If both are max then PHY is hung.
+        */
+       ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
+                                      &receive_errors);
+       if (ret_val)
+               goto out;
+       if (receive_errors == E1000_RECEIVE_ERROR_MAX)  {
+               ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
+                                              &status_1kbt);
+               if (ret_val)
+                       goto out;
+               if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
+                   E1000_IDLE_ERROR_COUNT_MASK)
+                       phy_hung = TRUE;
+       }
+out:
+       return phy_hung;
 }
 
+
 /**
  *  e1000_setup_link_82571 - Setup flow control and link settings
  *  @hw: pointer to the HW structure
@@ -1221,10 +1493,16 @@ static s32 e1000_setup_link_82571(struct e1000_hw *hw)
         * the default flow control setting, so we explicitly
         * set it to full.
         */
-       if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
-           hw->fc.requested_mode == e1000_fc_default)
-               hw->fc.requested_mode = e1000_fc_full;
-
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
+               if (hw->fc.requested_mode == e1000_fc_default)
+                       hw->fc.requested_mode = e1000_fc_full;
+               break;
+       default:
+               break;
+       }
        return e1000_setup_link_generic(hw);
 }
 
@@ -1238,8 +1516,8 @@ static s32 e1000_setup_link_82571(struct e1000_hw *hw)
  **/
 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
 {
-       u32 ctrl, led_ctrl;
-       s32  ret_val;
+       u32 ctrl;
+       s32 ret_val;
 
        DEBUGFUNC("e1000_setup_copper_link_82571");
 
@@ -1255,11 +1533,6 @@ static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
                break;
        case e1000_phy_igp_2:
                ret_val = e1000_copper_link_setup_igp(hw);
-               /* Setup activity LED */
-               led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL);
-               led_ctrl &= IGP_ACTIVITY_LED_MASK;
-               led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-               E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl);
                break;
        default:
                ret_val = -E1000_ERR_PHY;
@@ -1306,6 +1579,182 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
+ *  @hw: pointer to the HW structure
+ *
+ *  Reports the link state as up or down.
+ *
+ *  If autonegotiation is supported by the link partner, the link state is
+ *  determined by the result of autonegotiation. This is the most likely case.
+ *  If autonegotiation is not supported by the link partner, and the link
+ *  has a valid signal, force the link up.
+ *
+ *  The link state is represented internally here by 4 states:
+ *
+ *  1) down
+ *  2) autoneg_progress
+ *  3) autoneg_complete (the link sucessfully autonegotiated)
+ *  4) forced_up (the link has been forced up, it did not autonegotiate)
+ *
+ **/
+static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       u32 rxcw;
+       u32 ctrl;
+       u32 status;
+       u32 txcw;
+       u32 i;
+       s32 ret_val = E1000_SUCCESS;
+
+       DEBUGFUNC("e1000_check_for_serdes_link_82571");
+
+       ctrl = E1000_READ_REG(hw, E1000_CTRL);
+       status = E1000_READ_REG(hw, E1000_STATUS);
+       rxcw = E1000_READ_REG(hw, E1000_RXCW);
+
+       if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
+
+               /* Receiver is synchronized with no invalid bits.  */
+               switch (mac->serdes_link_state) {
+               case e1000_serdes_link_autoneg_complete:
+                       if (!(status & E1000_STATUS_LU)) {
+                               /*
+                                * We have lost link, retry autoneg before
+                                * reporting link failure
+                                */
+                               mac->serdes_link_state =
+                                   e1000_serdes_link_autoneg_progress;
+                               mac->serdes_has_link = FALSE;
+                               DEBUGOUT("AN_UP     -> AN_PROG\n");
+                       } else {
+                               mac->serdes_has_link = TRUE;
+                       }
+                       break;
+
+               case e1000_serdes_link_forced_up:
+                       /*
+                        * If we are receiving /C/ ordered sets, re-enable
+                        * auto-negotiation in the TXCW register and disable
+                        * forced link in the Device Control register in an
+                        * attempt to auto-negotiate with our link partner.
+                        * If the partner code word is null, stop forcing 
+                        * and restart auto negotiation.
+                        */
+                       if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW))  {
+                               /* Enable autoneg, and unforce link up */
+                               E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
+                               E1000_WRITE_REG(hw, E1000_CTRL,
+                                   (ctrl & ~E1000_CTRL_SLU));
+                               mac->serdes_link_state =
+                                   e1000_serdes_link_autoneg_progress;
+                               mac->serdes_has_link = FALSE;
+                               DEBUGOUT("FORCED_UP -> AN_PROG\n");
+                       } else {
+                               mac->serdes_has_link = TRUE;
+                       }
+                       break;
+
+               case e1000_serdes_link_autoneg_progress:
+                       if (rxcw & E1000_RXCW_C) {
+                               /*
+                                * We received /C/ ordered sets, meaning the
+                                * link partner has autonegotiated, and we can
+                                * trust the Link Up (LU) status bit.
+                                */
+                               if (status & E1000_STATUS_LU) {
+                                       mac->serdes_link_state =
+                                           e1000_serdes_link_autoneg_complete;
+                                       DEBUGOUT("AN_PROG   -> AN_UP\n");
+                                       mac->serdes_has_link = TRUE;
+                               } else {
+                                       /* Autoneg completed, but failed. */
+                                       mac->serdes_link_state =
+                                           e1000_serdes_link_down;
+                                       DEBUGOUT("AN_PROG   -> DOWN\n");
+                               }
+                       } else {
+                               /*
+                                * The link partner did not autoneg.
+                                * Force link up and full duplex, and change
+                                * state to forced.
+                                */
+                               E1000_WRITE_REG(hw, E1000_TXCW,
+                               (mac->txcw & ~E1000_TXCW_ANE));
+                               ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
+                               E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+
+                               /* Configure Flow Control after link up. */
+                               ret_val =
+                                   e1000_config_fc_after_link_up_generic(hw);
+                               if (ret_val) {
+                                       DEBUGOUT("Error config flow control\n");
+                                       break;
+                               }
+                               mac->serdes_link_state =
+                               e1000_serdes_link_forced_up;
+                               mac->serdes_has_link = TRUE;
+                               DEBUGOUT("AN_PROG   -> FORCED_UP\n");
+                       }
+                       break;
+
+               case e1000_serdes_link_down:
+               default:
+                       /*
+                        * The link was down but the receiver has now gained
+                        * valid sync, so lets see if we can bring the link
+                        * up.
+                        */
+                       E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
+                       E1000_WRITE_REG(hw, E1000_CTRL,
+                           (ctrl & ~E1000_CTRL_SLU));
+                       mac->serdes_link_state =
+                           e1000_serdes_link_autoneg_progress;
+                       mac->serdes_has_link = FALSE;
+                       DEBUGOUT("DOWN      -> AN_PROG\n");
+                       break;
+               }
+       } else {
+               if (!(rxcw & E1000_RXCW_SYNCH)) {
+                       mac->serdes_has_link = FALSE;
+                       mac->serdes_link_state = e1000_serdes_link_down;
+                       DEBUGOUT("ANYSTATE  -> DOWN\n");
+               } else {
+                       /*
+                        * Check several times, if Sync and Config
+                        * both are consistently 1 then simply ignore
+                        * the Invalid bit and restart Autoneg
+                        */
+                       for (i = 0; i < AN_RETRY_COUNT; i++) {
+                               usec_delay(10);
+                               rxcw = E1000_READ_REG(hw, E1000_RXCW);
+                               if ((rxcw & E1000_RXCW_IV) &&
+                                   !((rxcw & E1000_RXCW_SYNCH) &&
+                                     (rxcw & E1000_RXCW_C))) {
+                                       mac->serdes_has_link = FALSE;
+                                       mac->serdes_link_state =
+                                           e1000_serdes_link_down;
+                                       DEBUGOUT("ANYSTATE  -> DOWN\n");
+                                       break;
+                               }
+                       }
+
+                       if (i == AN_RETRY_COUNT) {
+                               txcw = E1000_READ_REG(hw, E1000_TXCW);
+                               txcw |= E1000_TXCW_ANE;
+                               E1000_WRITE_REG(hw, E1000_TXCW, txcw);
+                               mac->serdes_link_state =
+                                   e1000_serdes_link_autoneg_progress;
+                               mac->serdes_has_link = FALSE;
+                               DEBUGOUT("ANYSTATE  -> AN_PROG\n");
+                       }
+               }
+       }
+
+       return ret_val;
+}
+
+/**
  *  e1000_valid_led_default_82571 - Verify a valid default LED config
  *  @hw: pointer to the HW structure
  *  @data: pointer to the NVM (EEPROM)
@@ -1325,11 +1774,20 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
                goto out;
        }
 
-       if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
-           *data == ID_LED_RESERVED_F746)
-               *data = ID_LED_DEFAULT_82573;
-       else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
-               *data = ID_LED_DEFAULT;
+       switch (hw->mac.type) {
+       case e1000_82573:
+       case e1000_82574:
+       case e1000_82583:
+               if (*data == ID_LED_RESERVED_F746)
+                       *data = ID_LED_DEFAULT_82573;
+               break;
+       default:
+               if (*data == ID_LED_RESERVED_0000 ||
+                   *data == ID_LED_RESERVED_FFFF)
+                       *data = ID_LED_DEFAULT;
+               break;
+       }
+
 out:
        return ret_val;
 }
@@ -1435,6 +1893,7 @@ out:
        return ret_val;
 }
 
+
 /**
  *  e1000_read_mac_addr_82571 - Read device MAC address
  *  @hw: pointer to the HW structure
@@ -1444,9 +1903,21 @@ static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
        s32 ret_val = E1000_SUCCESS;
 
        DEBUGFUNC("e1000_read_mac_addr_82571");
-       if (e1000_check_alt_mac_addr_generic(hw))
-               ret_val = e1000_read_mac_addr_generic(hw);
 
+       if (hw->mac.type == e1000_82571) {
+               /*
+                * If there's an alternate MAC address place it in RAR0
+                * so that it will override the Si installed default perm
+                * address.
+                */
+               ret_val = e1000_check_alt_mac_addr_generic(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       ret_val = e1000_read_mac_addr_generic(hw);
+
+out:
        return ret_val;
 }
 
index 5e66793..476bfa1 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 #ifndef _E1000_82571_H_
 #define _E1000_82571_H_
@@ -42,6 +42,7 @@
                               (ID_LED_DEF1_DEF2))
 
 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
+#define AN_RETRY_COUNT          5 /* Autoneg Retry Count value */
 
 /* Intr Throttling - RW */
 #define E1000_EITR_82574(_n)    (0x000E8 + (0x4 * (_n)))
 
 #define E1000_RXCFGL    0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
 
+#define E1000_BASE1000T_STATUS 10
+#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
+#define E1000_RECEIVE_ERROR_COUNTER 21
+#define E1000_RECEIVE_ERROR_MAX 0xFFFF
+bool e1000_check_phy_82574(struct e1000_hw *hw);
 bool e1000_get_laa_state_82571(struct e1000_hw *hw);
 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state);
 
diff --git a/sys/dev/netif/ig_hal/e1000_82575.c b/sys/dev/netif/ig_hal/e1000_82575.c
deleted file mode 100644 (file)
index 3d16447..0000000
+++ /dev/null
@@ -1,1669 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2008, Intel Corporation 
-  All rights reserved.
-  
-  Redistribution and use in source and binary forms, with or without 
-  modification, are permitted provided that the following conditions are met:
-  
-   1. Redistributions of source code must retain the above copyright notice, 
-      this list of conditions and the following disclaimer.
-  
-   2. Redistributions in binary form must reproduce the above copyright 
-      notice, this list of conditions and the following disclaimer in the 
-      documentation and/or other materials provided with the distribution.
-  
-   3. Neither the name of the Intel Corporation nor the names of its 
-      contributors may be used to endorse or promote products derived from 
-      this software without specific prior written permission.
-  
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-/*
- * 82575EB Gigabit Network Connection
- * 82575EB Gigabit Backplane Connection
- * 82575GB Gigabit Network Connection
- * 82576 Gigabit Network Connection
- */
-
-#include "e1000_api.h"
-
-static s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
-static s32  e1000_init_nvm_params_82575(struct e1000_hw *hw);
-static s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
-static s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
-static void e1000_release_phy_82575(struct e1000_hw *hw);
-static s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
-static void e1000_release_nvm_82575(struct e1000_hw *hw);
-static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
-static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
-static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
-                                         u16 *duplex);
-static s32  e1000_init_hw_82575(struct e1000_hw *hw);
-static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
-static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                           u16 *data);
-static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
-static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
-                                          bool active);
-static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
-static s32  e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw);
-static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
-static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
-                                            u32 offset, u16 data);
-static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
-static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
-static s32  e1000_configure_pcs_link_82575(struct e1000_hw *hw);
-static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
-                                                 u16 *speed, u16 *duplex);
-static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
-static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
-static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
-static s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
-static s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
-static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
-
-static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count);
-static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw,
-                                           u8 *mc_addr_list, u32 mc_addr_count,
-                                           u32 rar_used_count, u32 rar_count);
-void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
-
-/**
- *  e1000_init_phy_params_82575 - Init PHY func ptrs.
- *  @hw: pointer to the HW structure
- **/
-static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
-{
-       struct e1000_phy_info *phy = &hw->phy;
-       s32 ret_val = E1000_SUCCESS;
-
-       DEBUGFUNC("e1000_init_phy_params_82575");
-
-       if (hw->phy.media_type != e1000_media_type_copper) {
-               phy->type = e1000_phy_none;
-               goto out;
-       } else {
-               phy->ops.power_up   = e1000_power_up_phy_copper;
-               phy->ops.power_down = e1000_power_down_phy_copper_82575;
-       }
-
-       phy->autoneg_mask           = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-       phy->reset_delay_us         = 100;
-
-       phy->ops.acquire            = e1000_acquire_phy_82575;
-       phy->ops.check_reset_block  = e1000_check_reset_block_generic;
-       phy->ops.commit             = e1000_phy_sw_reset_generic;
-       phy->ops.get_cfg_done       = e1000_get_cfg_done_82575;
-       phy->ops.release            = e1000_release_phy_82575;
-
-       if (e1000_sgmii_active_82575(hw)) {
-               phy->ops.reset      = e1000_phy_hw_reset_sgmii_82575;
-               phy->ops.read_reg   = e1000_read_phy_reg_sgmii_82575;
-               phy->ops.write_reg  = e1000_write_phy_reg_sgmii_82575;
-       } else {
-               phy->ops.reset      = e1000_phy_hw_reset_generic;
-               phy->ops.read_reg   = e1000_read_phy_reg_igp;
-               phy->ops.write_reg  = e1000_write_phy_reg_igp;
-       }
-
-       /* Set phy->phy_addr and phy->id. */
-       ret_val = e1000_get_phy_id_82575(hw);
-
-       /* Verify phy id and set remaining function pointers */
-       switch (phy->id) {
-       case M88E1111_I_PHY_ID:
-               phy->type                   = e1000_phy_m88;
-               phy->ops.check_polarity     = e1000_check_polarity_m88;
-               phy->ops.get_info           = e1000_get_phy_info_m88;
-               phy->ops.get_cable_length   = e1000_get_cable_length_m88;
-               phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
-               break;
-       case IGP03E1000_E_PHY_ID:
-       case IGP04E1000_E_PHY_ID:
-               phy->type                   = e1000_phy_igp_3;
-               phy->ops.check_polarity     = e1000_check_polarity_igp;
-               phy->ops.get_info           = e1000_get_phy_info_igp;
-               phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
-               phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
-               phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82575;
-               phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
-               break;
-       default:
-               ret_val = -E1000_ERR_PHY;
-               goto out;
-       }
-
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
- *  @hw: pointer to the HW structure
- **/
-static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
-{
-       struct e1000_nvm_info *nvm = &hw->nvm;
-       u32 eecd = E1000_READ_REG(hw, E1000_EECD);
-       u16 size;
-
-       DEBUGFUNC("e1000_init_nvm_params_82575");
-
-       nvm->opcode_bits        = 8;
-       nvm->delay_usec         = 1;
-       switch (nvm->override) {
-       case e1000_nvm_override_spi_large:
-               nvm->page_size    = 32;
-               nvm->address_bits = 16;
-               break;
-       case e1000_nvm_override_spi_small:
-               nvm->page_size    = 8;
-               nvm->address_bits = 8;
-               break;
-       default:
-               nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
-               nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
-               break;
-       }
-
-       nvm->type              = e1000_nvm_eeprom_spi;
-
-       size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-                         E1000_EECD_SIZE_EX_SHIFT);
-
-       /*
-        * Added to a constant, "size" becomes the left-shift value
-        * for setting word_size.
-        */
-       size += NVM_WORD_SIZE_BASE_SHIFT;
-
-       /* EEPROM access above 16k is unsupported */
-       if (size > 14)
-               size = 14;
-       nvm->word_size  = 1 << size;
-
-       /* Function Pointers */
-       nvm->ops.acquire       = e1000_acquire_nvm_82575;
-       nvm->ops.read          = e1000_read_nvm_eerd;
-       nvm->ops.release       = e1000_release_nvm_82575;
-       nvm->ops.update        = e1000_update_nvm_checksum_generic;
-       nvm->ops.valid_led_default = e1000_valid_led_default_82575;
-       nvm->ops.validate      = e1000_validate_nvm_checksum_generic;
-       nvm->ops.write         = e1000_write_nvm_spi;
-
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_init_mac_params_82575 - Init MAC func ptrs.
- *  @hw: pointer to the HW structure
- **/
-static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
-{
-       struct e1000_mac_info *mac = &hw->mac;
-       struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
-       u32 ctrl_ext = 0;
-
-       DEBUGFUNC("e1000_init_mac_params_82575");
-
-       /* Set media type */
-        /*
-        * The 82575 uses bits 22:23 for link mode. The mode can be changed
-         * based on the EEPROM. We cannot rely upon device ID. There
-         * is no distinguishable difference between fiber and internal
-         * SerDes mode on the 82575. There can be an external PHY attached
-         * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
-         */
-       hw->phy.media_type = e1000_media_type_copper;
-       dev_spec->sgmii_active = FALSE;
-
-       ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
-       if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
-           E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
-               hw->phy.media_type = e1000_media_type_internal_serdes;
-               ctrl_ext |= E1000_CTRL_I2C_ENA;
-       } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
-               dev_spec->sgmii_active = TRUE;
-               ctrl_ext |= E1000_CTRL_I2C_ENA;
-       } else {
-               ctrl_ext &= ~E1000_CTRL_I2C_ENA;
-       }
-       E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
-
-       /* Set mta register count */
-       mac->mta_reg_count = 128;
-       /* Set rar entry count */
-       mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
-       if (mac->type == e1000_82576)
-               mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
-       /* Set if part includes ASF firmware */
-       mac->asf_firmware_present = TRUE;
-       /* Set if manageability features are enabled. */
-       mac->arc_subsystem_valid =
-               (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-                       ? TRUE : FALSE;
-
-       /* Function pointers */
-
-       /* bus type/speed/width */
-       mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
-       /* reset */
-       mac->ops.reset_hw = e1000_reset_hw_82575;
-       /* hw initialization */
-       mac->ops.init_hw = e1000_init_hw_82575;
-       /* link setup */
-       mac->ops.setup_link = e1000_setup_link_generic;
-       /* physical interface link setup */
-       mac->ops.setup_physical_interface =
-               (hw->phy.media_type == e1000_media_type_copper)
-                       ? e1000_setup_copper_link_82575
-                       : e1000_setup_fiber_serdes_link_82575;
-       /* physical interface shutdown */
-       mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575;
-       /* check for link */
-       mac->ops.check_for_link = e1000_check_for_link_82575;
-       /* receive address register setting */
-       mac->ops.rar_set = e1000_rar_set_generic;
-       /* read mac address */
-       mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
-       /* multicast address update */
-       mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82575;
-       /* writing VFTA */
-       mac->ops.write_vfta = e1000_write_vfta_generic;
-       /* clearing VFTA */
-       mac->ops.clear_vfta = e1000_clear_vfta_generic;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_generic;
-       /* blink LED */
-       mac->ops.blink_led = e1000_blink_led_generic;
-       /* setup LED */
-       mac->ops.setup_led = e1000_setup_led_generic;
-       /* cleanup LED */
-       mac->ops.cleanup_led = e1000_cleanup_led_generic;
-       /* turn on/off LED */
-       mac->ops.led_on = e1000_led_on_generic;
-       mac->ops.led_off = e1000_led_off_generic;
-       /* clear hardware counters */
-       mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
-       /* link info */
-       mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
-
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_init_function_pointers_82575 - Init func ptrs.
- *  @hw: pointer to the HW structure
- *
- *  Called to initialize all function pointers and parameters.
- **/
-void e1000_init_function_pointers_82575(struct e1000_hw *hw)
-{
-       DEBUGFUNC("e1000_init_function_pointers_82575");
-
-       hw->mac.ops.init_params = e1000_init_mac_params_82575;
-       hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
-       hw->phy.ops.init_params = e1000_init_phy_params_82575;
-}
-
-/**
- *  e1000_acquire_phy_82575 - Acquire rights to access PHY
- *  @hw: pointer to the HW structure
- *
- *  Acquire access rights to the correct PHY.
- **/
-static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
-{
-       u16 mask;
-
-       DEBUGFUNC("e1000_acquire_phy_82575");
-
-       mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
-
-       return e1000_acquire_swfw_sync_82575(hw, mask);
-}
-
-/**
- *  e1000_release_phy_82575 - Release rights to access PHY
- *  @hw: pointer to the HW structure
- *
- *  A wrapper to release access rights to the correct PHY.
- **/
-static void e1000_release_phy_82575(struct e1000_hw *hw)
-{
-       u16 mask;
-
-       DEBUGFUNC("e1000_release_phy_82575");
-
-       mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
-       e1000_release_swfw_sync_82575(hw, mask);
-}
-
-/**
- *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
- *  @hw: pointer to the HW structure
- *  @offset: register offset to be read
- *  @data: pointer to the read data
- *
- *  Reads the PHY register at offset using the serial gigabit media independent
- *  interface and stores the retrieved information in data.
- **/
-static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                          u16 *data)
-{
-       struct e1000_phy_info *phy = &hw->phy;
-       u32 i, i2ccmd = 0;
-
-       DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
-
-       if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
-               DEBUGOUT1("PHY Address %u is out of range\n", offset);
-               return -E1000_ERR_PARAM;
-       }
-
-       /*
-        * Set up Op-code, Phy Address, and register address in the I2CCMD
-        * register.  The MAC will take care of interfacing with the
-        * PHY to retrieve the desired data.
-        */
-       i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
-                 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
-                 (E1000_I2CCMD_OPCODE_READ));
-
-       E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
-
-       /* Poll the ready bit to see if the I2C read completed */
-       for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
-               usec_delay(50);
-               i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
-               if (i2ccmd & E1000_I2CCMD_READY)
-                       break;
-       }
-       if (!(i2ccmd & E1000_I2CCMD_READY)) {
-               DEBUGOUT("I2CCMD Read did not complete\n");
-               return -E1000_ERR_PHY;
-       }
-       if (i2ccmd & E1000_I2CCMD_ERROR) {
-               DEBUGOUT("I2CCMD Error bit set\n");
-               return -E1000_ERR_PHY;
-       }
-
-       /* Need to byte-swap the 16-bit value. */
-       *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
-
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
- *  @hw: pointer to the HW structure
- *  @offset: register offset to write to
- *  @data: data to write at register offset
- *
- *  Writes the data to PHY register at the offset using the serial gigabit
- *  media independent interface.
- **/
-static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                           u16 data)
-{
-       struct e1000_phy_info *phy = &hw->phy;
-       u32 i, i2ccmd = 0;
-       u16 phy_data_swapped;
-
-       DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
-
-       if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
-               DEBUGOUT1("PHY Address %d is out of range\n", offset);
-               return -E1000_ERR_PARAM;
-       }
-
-       /* Swap the data bytes for the I2C interface */
-       phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
-
-       /*
-        * Set up Op-code, Phy Address, and register address in the I2CCMD
-        * register.  The MAC will take care of interfacing with the
-        * PHY to retrieve the desired data.
-        */
-       i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
-                 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
-                 E1000_I2CCMD_OPCODE_WRITE |
-                 phy_data_swapped);
-
-       E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
-
-       /* Poll the ready bit to see if the I2C read completed */
-       for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
-               usec_delay(50);
-               i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
-               if (i2ccmd & E1000_I2CCMD_READY)
-                       break;
-       }
-       if (!(i2ccmd & E1000_I2CCMD_READY)) {
-               DEBUGOUT("I2CCMD Write did not complete\n");
-               return -E1000_ERR_PHY;
-       }
-       if (i2ccmd & E1000_I2CCMD_ERROR) {
-               DEBUGOUT("I2CCMD Error bit set\n");
-               return -E1000_ERR_PHY;
-       }
-
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
- *  @hw: pointer to the HW structure
- *
- *  Retrieves the PHY address and ID for both PHY's which do and do not use
- *  sgmi interface.
- **/
-static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
-{
-       struct e1000_phy_info *phy = &hw->phy;
-       s32  ret_val = E1000_SUCCESS;
-       u16 phy_id;
-
-       DEBUGFUNC("e1000_get_phy_id_82575");
-
-       /*
-        * For SGMII PHYs, we try the list of possible addresses until
-        * we find one that works.  For non-SGMII PHYs
-        * (e.g. integrated copper PHYs), an address of 1 should
-        * work.  The result of this function should mean phy->phy_addr
-        * and phy->id are set correctly.
-        */
-       if (!(e1000_sgmii_active_82575(hw))) {
-               phy->addr = 1;
-               ret_val = e1000_get_phy_id(hw);
-               goto out;
-       }
-
-       /*
-        * The address field in the I2CCMD register is 3 bits and 0 is invalid.
-        * Therefore, we need to test 1-7
-        */
-       for (phy->addr = 1; phy->addr < 8; phy->addr++) {
-               ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
-               if (ret_val == E1000_SUCCESS) {
-                       DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
-                                 phy_id,
-                                 phy->addr);
-                       /*
-                        * At the time of this writing, The M88 part is
-                        * the only supported SGMII PHY product.
-                        */
-                       if (phy_id == M88_VENDOR)
-                               break;
-               } else {
-                       DEBUGOUT1("PHY address %u was unreadable\n",
-                                 phy->addr);
-               }
-       }
-
-       /* A valid PHY type couldn't be found. */
-       if (phy->addr == 8) {
-               phy->addr = 0;
-               ret_val = -E1000_ERR_PHY;
-               goto out;
-       }
-
-       ret_val = e1000_get_phy_id(hw);
-
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
- *  @hw: pointer to the HW structure
- *
- *  Resets the PHY using the serial gigabit media independent interface.
- **/
-static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
-{
-       s32 ret_val = E1000_SUCCESS;
-
-       DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
-
-       /*
-        * This isn't a TRUE "hard" reset, but is the only reset
-        * available to us at this time.
-        */
-
-       DEBUGOUT("Soft resetting SGMII attached PHY...\n");
-
-       if (!(hw->phy.ops.write_reg))
-               goto out;
-
-       /*
-        * SFP documentation requires the following to configure the SPF module
-        * to work on SGMII.  No further documentation is given.
-        */
-       ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
-       if (ret_val)
-               goto out;
-
-       ret_val = hw->phy.ops.commit(hw);
-
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
- *  @hw: pointer to the HW structure
- *  @active: TRUE to enable LPLU, FALSE to disable
- *
- *  Sets the LPLU D0 state according to the active flag.  When
- *  activating LPLU this function also disables smart speed
- *  and vice versa.  LPLU will not be activated unless the
- *  device autonegotiation advertisement meets standards of
- *  either 10 or 10/100 or 10/100/1000 at all duplexes.
- *  This is a function pointer entry point only called by
- *  PHY setup routines.
- **/
-static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
-{
-       struct e1000_phy_info *phy = &hw->phy;
-       s32 ret_val = E1000_SUCCESS;
-       u16 data;
-
-       DEBUGFUNC("e1000_set_d0_lplu_state_82575");
-
-       if (!(hw->phy.ops.read_reg))
-               goto out;
-
-       ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
-       if (ret_val)
-               goto out;
-
-       if (active) {
-               data |= IGP02E1000_PM_D0_LPLU;
-               ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                            data);
-               if (ret_val)
-                       goto out;
-
-               /* When LPLU is enabled, we should disable SmartSpeed */
-               ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                           &data);
-               data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-               ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                            data);
-               if (ret_val)
-                       goto out;
-       } else {
-               data &= ~IGP02E1000_PM_D0_LPLU;
-               ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                            data);
-               /*
-                * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
-                * during Dx states where the power conservation is most
-                * important.  During driver activity we should enable
-                * SmartSpeed, so performance is maintained.
-                */
-               if (phy->smart_speed == e1000_smart_speed_on) {
-                       ret_val = phy->ops.read_reg(hw,
-                                                   IGP01E1000_PHY_PORT_CONFIG,
-                                                   &data);
-                       if (ret_val)
-                               goto out;
-
-                       data |= IGP01E1000_PSCFR_SMART_SPEED;
-                       ret_val = phy->ops.write_reg(hw,
-                                                    IGP01E1000_PHY_PORT_CONFIG,
-                                                    data);
-                       if (ret_val)
-                               goto out;
-               } else if (phy->smart_speed == e1000_smart_speed_off) {
-                       ret_val = phy->ops.read_reg(hw,
-                                                   IGP01E1000_PHY_PORT_CONFIG,
-                                                   &data);
-                       if (ret_val)
-                               goto out;
-
-                       data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-                       ret_val = phy->ops.write_reg(hw,
-                                                    IGP01E1000_PHY_PORT_CONFIG,
-                                                    data);
-                       if (ret_val)
-                               goto out;
-               }
-       }
-
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_acquire_nvm_82575 - Request for access to EEPROM
- *  @hw: pointer to the HW structure
- *
- *  Acquire the necessary semaphores for exclusive access to the EEPROM.
- *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
- *  Return successful if access grant bit set, else clear the request for
- *  EEPROM access and return -E1000_ERR_NVM (-1).
- **/
-static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
-{
-       s32 ret_val;
-
-       DEBUGFUNC("e1000_acquire_nvm_82575");
-
-       ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
-       if (ret_val)
-               goto out;
-
-       ret_val = e1000_acquire_nvm_generic(hw);
-
-       if (ret_val)
-               e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
-
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
- *  @hw: pointer to the HW structure
- *
- *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
- *  then release the semaphores acquired.
- **/
-static void e1000_release_nvm_82575(struct e1000_hw *hw)
-{
-       DEBUGFUNC("e1000_release_nvm_82575");
-
-       e1000_release_nvm_generic(hw);
-       e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
-}
-
-/**
- *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
- *  @hw: pointer to the HW structure
- *  @mask: specifies which semaphore to acquire
- *
- *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
- *  will also specify which port we're acquiring the lock for.
- **/
-static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
-{
-       u32 swfw_sync;
-       u32 swmask = mask;
-       u32 fwmask = mask << 16;
-       s32 ret_val = E1000_SUCCESS;
-       s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
-
-       DEBUGFUNC("e1000_acquire_swfw_sync_82575");
-
-       while (i < timeout) {
-               if (e1000_get_hw_semaphore_generic(hw)) {
-                       ret_val = -E1000_ERR_SWFW_SYNC;
-                       goto out;
-               }
-
-               swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
-               if (!(swfw_sync & (fwmask | swmask)))
-                       break;
-
-               /*
-                * Firmware currently using resource (fwmask)
-                * or other software thread using resource (swmask)
-                */
-               e1000_put_hw_semaphore_generic(hw);
-               msec_delay_irq(5);
-               i++;
-       }
-
-       if (i == timeout) {
-               DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
-               ret_val = -E1000_ERR_SWFW_SYNC;
-               goto out;
-       }
-
-       swfw_sync |= swmask;
-       E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
-
-       e1000_put_hw_semaphore_generic(hw);
-
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
- *  @hw: pointer to the HW structure
- *  @mask: specifies which semaphore to acquire
- *
- *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
- *  will also specify which port we're releasing the lock for.
- **/
-static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
-{
-       u32 swfw_sync;
-
-       DEBUGFUNC("e1000_release_swfw_sync_82575");
-
-       while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
-       /* Empty */
-
-       swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
-       swfw_sync &= ~mask;
-       E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
-
-       e1000_put_hw_semaphore_generic(hw);
-}
-
-/**
- *  e1000_get_cfg_done_82575 - Read config done bit
- *  @hw: pointer to the HW structure
- *
- *  Read the management control register for the config done bit for
- *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
- *  to read the config done bit, so an error is *ONLY* logged and returns
- *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
- *  would not be able to be reset or change link.
- **/
-static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
-{
-       s32 timeout = PHY_CFG_TIMEOUT;
-       s32 ret_val = E1000_SUCCESS;
-       u32 mask = E1000_NVM_CFG_DONE_PORT_0;
-
-       DEBUGFUNC("e1000_get_cfg_done_82575");
-
-       if (hw->bus.func == 1)
-               mask = E1000_NVM_CFG_DONE_PORT_1;
-
-       while (timeout) {
-               if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
-                       break;
-               msec_delay(1);
-               timeout--;
-       }
-       if (!timeout) {
-               DEBUGOUT("MNG configuration cycle has not completed.\n");
-       }
-
-       /* If EEPROM is not marked present, init the PHY manually */
-       if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
-           (hw->phy.type == e1000_phy_igp_3)) {
-               e1000_phy_init_script_igp3(hw);
-       }
-
-       return ret_val;
-}
-
-/**
- *  e1000_get_link_up_info_82575 - Get link speed/duplex info
- *  @hw: pointer to the HW structure
- *  @speed: stores the current speed
- *  @duplex: stores the current duplex
- *
- *  This is a wrapper function, if using the serial gigabit media independent
- *  interface, use PCS to retrieve the link speed and duplex information.
- *  Otherwise, use the generic function to get the link speed and duplex info.
- **/
-static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
-                                        u16 *duplex)
-{
-       s32 ret_val;
-
-       DEBUGFUNC("e1000_get_link_up_info_82575");
-
-       if (hw->phy.media_type != e1000_media_type_copper ||
-           e1000_sgmii_active_82575(hw)) {
-               ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
-                                                              duplex);
-       } else {
-               ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
-                                                                   duplex);
-       }
-
-       return ret_val;
-}
-
-/**
- *  e1000_check_for_link_82575 - Check for link
- *  @hw: pointer to the HW structure
- *
- *  If sgmii is enabled, then use the pcs register to determine link, otherwise
- *  use the generic interface for determining link.
- **/
-static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
-{
-       s32 ret_val;
-       u16 speed, duplex;
-
-       DEBUGFUNC("e1000_check_for_link_82575");
-
-       /* SGMII link check is done through the PCS register. */
-       if ((hw->phy.media_type != e1000_media_type_copper) ||
-           (e1000_sgmii_active_82575(hw)))
-               ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
-                                                              &duplex);
-       else
-               ret_val = e1000_check_for_copper_link_generic(hw);
-
-       return ret_val;
-}
-
-/**
- *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
- *  @hw: pointer to the HW structure
- *  @speed: stores the current speed
- *  @duplex: stores the current duplex
- *
- *  Using the physical coding sub-layer (PCS), retrieve the current speed and
- *  duplex, then store the values in the pointers provided.
- **/
-static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
-                                                u16 *speed, u16 *duplex)
-{
-       struct e1000_mac_info *mac = &hw->mac;
-       u32 pcs;
-
-       DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
-
-       /* Set up defaults for the return values of this function */
-       mac->serdes_has_link = FALSE;
-       *speed = 0;
-       *duplex = 0;
-
-       /*
-        * Read the PCS Status register for link state. For non-copper mode,
-        * the status register is not accurate. The PCS status register is
-        * used instead.
-        */
-       pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
-
-       /*
-        * The link up bit determines when link is up on autoneg. The sync ok
-        * gets set once both sides sync up and agree upon link. Stable link
-        * can be determined by checking for both link up and link sync ok
-        */
-       if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
-               mac->serdes_has_link = TRUE;
-
-               /* Detect and store PCS speed */
-               if (pcs & E1000_PCS_LSTS_SPEED_1000) {
-                       *speed = SPEED_1000;
-               } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
-                       *speed = SPEED_100;
-               } else {
-                       *speed = SPEED_10;
-               }
-
-               /* Detect and store PCS duplex */
-               if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
-                       *duplex = FULL_DUPLEX;
-               } else {
-                       *duplex = HALF_DUPLEX;
-               }
-       }
-
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_init_rx_addrs_82575 - Initialize receive address's
- *  @hw: pointer to the HW structure
- *  @rar_count: receive address registers
- *
- *  Setups the receive address registers by setting the base receive address
- *  register to the devices MAC address and clearing all the other receive
- *  address registers to 0.
- **/
-static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
-{
-       u32 i;
-       u8 addr[6] = {0,0,0,0,0,0};
-       /*
-        * This function is essentially the same as that of
-        * e1000_init_rx_addrs_generic. However it also takes care
-        * of the special case where the register offset of the
-        * second set of RARs begins elsewhere. This is implicitly taken care by
-        * function e1000_rar_set_generic.
-        */
-
-       DEBUGFUNC("e1000_init_rx_addrs_82575");
-
-       /* Setup the receive address */
-       DEBUGOUT("Programming MAC Address into RAR[0]\n");
-       hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
-
-       /* Zero out the other (rar_entry_count - 1) receive addresses */
-       DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
-       for (i = 1; i < rar_count; i++) {
-           hw->mac.ops.rar_set(hw, addr, i);
-       }
-}
-
-/**
- *  e1000_update_mc_addr_list_82575 - Update Multicast addresses
- *  @hw: pointer to the HW structure
- *  @mc_addr_list: array of multicast addresses to program
- *  @mc_addr_count: number of multicast addresses to program
- *  @rar_used_count: the first RAR register free to program
- *  @rar_count: total number of supported Receive Address Registers
- *
- *  Updates the Receive Address Registers and Multicast Table Array.
- *  The caller must have a packed mc_addr_list of multicast addresses.
- *  The parameter rar_count will usually be hw->mac.rar_entry_count
- *  unless there are workarounds that change this.
- **/
-static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw,
-                                     u8 *mc_addr_list, u32 mc_addr_count,
-                                     u32 rar_used_count, u32 rar_count)
-{
-       u32 hash_value;
-       u32 i;
-       u8 addr[6] = {0,0,0,0,0,0};
-       /*
-        * This function is essentially the same as that of 
-        * e1000_update_mc_addr_list_generic. However it also takes care 
-        * of the special case where the register offset of the 
-        * second set of RARs begins elsewhere. This is implicitly taken care by 
-        * function e1000_rar_set_generic.
-        */
-
-       DEBUGFUNC("e1000_update_mc_addr_list_82575");
-
-       /*
-        * Load the first set of multicast addresses into the exact
-        * filters (RAR).  If there are not enough to fill the RAR
-        * array, clear the filters.
-        */
-       for (i = rar_used_count; i < rar_count; i++) {
-               if (mc_addr_count) {
-                       e1000_rar_set_generic(hw, mc_addr_list, i);
-                       mc_addr_count--;
-                       mc_addr_list += ETH_ADDR_LEN;
-               } else {
-                       e1000_rar_set_generic(hw, addr, i);
-               }
-       }
-
-       /* Clear the old settings from the MTA */
-       DEBUGOUT("Clearing MTA\n");
-       for (i = 0; i < hw->mac.mta_reg_count; i++) {
-               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
-               E1000_WRITE_FLUSH(hw);
-       }
-
-       /* Load any remaining multicast addresses into the hash table. */
-       for (; mc_addr_count > 0; mc_addr_count--) {
-               hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
-               DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
-               hw->mac.ops.mta_set(hw, hash_value);
-               mc_addr_list += ETH_ADDR_LEN;
-       }
-}
-
-/**
- *  e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down
- *  @hw: pointer to the HW structure
- *
- *  In the case of fiber serdes shut down optics and PCS on driver unload
- *  when management pass thru is not enabled.
- **/
-void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
-{
-       u32 reg;
-       u16 eeprom_data = 0;
-
-       if (hw->mac.type != e1000_82576 ||
-          (hw->phy.media_type != e1000_media_type_fiber &&
-           hw->phy.media_type != e1000_media_type_internal_serdes))
-               return;
-
-       if (hw->bus.func == 0)
-               hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
-
-       /*
-        * If APM is not enabled in the EEPROM and management interface is
-        * not enabled, then power down.
-        */
-       if (!(eeprom_data & E1000_NVM_APME_82575) &&
-           !e1000_enable_mng_pass_thru(hw)) {
-               /* Disable PCS to turn off link */
-               reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
-               reg &= ~E1000_PCS_CFG_PCS_EN;
-               E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
-
-               /* shutdown the laser */
-               reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
-               reg |= E1000_CTRL_EXT_SDP7_DATA;
-               E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
-
-               /* flush the write to verfiy completion */
-               E1000_WRITE_FLUSH(hw);
-               msec_delay(1);
-       }
-
-       return;
-}
-
-/**
- *  e1000_reset_hw_82575 - Reset hardware
- *  @hw: pointer to the HW structure
- *
- *  This resets the hardware into a known state.
- **/
-static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
-{
-       u32 ctrl, icr;
-       s32 ret_val;
-
-       DEBUGFUNC("e1000_reset_hw_82575");
-
-       /*
-        * Prevent the PCI-E bus from sticking if there is no TLP connection
-        * on the last TLP read/write transaction when MAC is reset.
-        */
-       ret_val = e1000_disable_pcie_master_generic(hw);
-       if (ret_val) {
-               DEBUGOUT("PCI-E Master disable polling has failed.\n");
-       }
-
-       DEBUGOUT("Masking off all interrupts\n");
-       E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
-
-       E1000_WRITE_REG(hw, E1000_RCTL, 0);
-       E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
-       E1000_WRITE_FLUSH(hw);
-
-       msec_delay(10);
-
-       ctrl = E1000_READ_REG(hw, E1000_CTRL);
-
-       DEBUGOUT("Issuing a global reset to MAC\n");
-       E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
-
-       ret_val = e1000_get_auto_rd_done_generic(hw);
-       if (ret_val) {
-               /*
-                * When auto config read does not complete, do not
-                * return with an error. This can happen in situations
-                * where there is no eeprom and prevents getting link.
-                */
-               DEBUGOUT("Auto Read Done did not complete\n");
-       }
-
-       /* If EEPROM is not present, run manual init scripts */
-       if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
-               e1000_reset_init_script_82575(hw);
-
-       /* Clear any pending interrupt events. */
-       E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
-       icr = E1000_READ_REG(hw, E1000_ICR);
-
-       e1000_check_alt_mac_addr_generic(hw);
-
-       return ret_val;
-}
-
-/**
- *  e1000_init_hw_82575 - Initialize hardware
- *  @hw: pointer to the HW structure
- *
- *  This inits the hardware readying it for operation.
- **/
-static s32 e1000_init_hw_82575(struct e1000_hw *hw)
-{
-       struct e1000_mac_info *mac = &hw->mac;
-       s32 ret_val;
-       u16 i, rar_count = mac->rar_entry_count;
-
-       DEBUGFUNC("e1000_init_hw_82575");
-
-       /* Initialize identification LED */
-       ret_val = e1000_id_led_init_generic(hw);
-       if (ret_val) {
-               DEBUGOUT("Error initializing identification LED\n");
-               /* This is not fatal and we should not stop init due to this */
-       }
-
-       /* Disabling VLAN filtering */
-       DEBUGOUT("Initializing the IEEE VLAN\n");
-       mac->ops.clear_vfta(hw);
-
-       /* Setup the receive address */
-       e1000_init_rx_addrs_82575(hw, rar_count);
-       /* Zero out the Multicast HASH table */
-       DEBUGOUT("Zeroing the MTA\n");
-       for (i = 0; i < mac->mta_reg_count; i++)
-               E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
-
-       /* Setup link and flow control */
-       ret_val = mac->ops.setup_link(hw);
-
-       /*
-        * Clear all of the statistics registers (clear on read).  It is
-        * important that we do this after we have tried to establish link
-        * because the symbol error count will increment wildly if there
-        * is no link.
-        */
-       e1000_clear_hw_cntrs_82575(hw);
-
-       return ret_val;
-}
-
-/**
- *  e1000_setup_copper_link_82575 - Configure copper link settings
- *  @hw: pointer to the HW structure
- *
- *  Configures the link for auto-neg or forced speed and duplex.  Then we check
- *  for link, once link is established calls to configure collision distance
- *  and flow control are called.
- **/
-static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
-{
-       u32 ctrl, led_ctrl;
-       s32  ret_val;
-       bool link;
-
-       DEBUGFUNC("e1000_setup_copper_link_82575");
-
-       ctrl = E1000_READ_REG(hw, E1000_CTRL);
-       ctrl |= E1000_CTRL_SLU;
-       ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-       E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
-
-       switch (hw->phy.type) {
-       case e1000_phy_m88:
-               ret_val = e1000_copper_link_setup_m88(hw);
-               break;
-       case e1000_phy_igp_3:
-               ret_val = e1000_copper_link_setup_igp(hw);
-               /* Setup activity LED */
-               led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL);
-               led_ctrl &= IGP_ACTIVITY_LED_MASK;
-               led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-               E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl);
-               break;
-       default:
-               ret_val = -E1000_ERR_PHY;
-               break;
-       }
-
-       if (ret_val)
-               goto out;
-
-       if (hw->mac.autoneg) {
-               /*
-                * Setup autoneg and flow control advertisement
-                * and perform autonegotiation.
-                */
-               ret_val = e1000_copper_link_autoneg(hw);
-               if (ret_val)
-                       goto out;
-       } else {
-               /*
-                * PHY will be set to 10H, 10F, 100H or 100F
-                * depending on user settings.
-                */
-               DEBUGOUT("Forcing Speed and Duplex\n");
-               ret_val = hw->phy.ops.force_speed_duplex(hw);
-               if (ret_val) {
-                       DEBUGOUT("Error Forcing Speed and Duplex\n");
-                       goto out;
-               }
-       }
-
-       ret_val = e1000_configure_pcs_link_82575(hw);
-       if (ret_val)
-               goto out;
-
-       /*
-        * Check link status. Wait up to 100 microseconds for link to become
-        * valid.
-        */
-       ret_val = e1000_phy_has_link_generic(hw,
-                                            COPPER_LINK_UP_LIMIT,
-                                            10,
-                                            &link);
-       if (ret_val)
-               goto out;
-
-       if (link) {
-               DEBUGOUT("Valid link established!!!\n");
-               /* Config the MAC and PHY after link is up */
-               e1000_config_collision_dist_generic(hw);
-               ret_val = e1000_config_fc_after_link_up_generic(hw);
-       } else {
-               DEBUGOUT("Unable to establish link!!!\n");
-       }
-
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
- *  @hw: pointer to the HW structure
- *
- *  Configures speed and duplex for fiber and serdes links.
- **/
-static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
-{
-       u32 reg;
-
-       DEBUGFUNC("e1000_setup_fiber_serdes_link_82575");
-
-       /*
-        * On the 82575, SerDes loopback mode persists until it is
-        * explicitly turned off or a power cycle is performed.  A read to
-        * the register does not indicate its status.  Therefore, we ensure
-        * loopback mode is disabled during initialization.
-        */
-       E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
-
-       /* Force link up, set 1gb, set both sw defined pins */
-       reg = E1000_READ_REG(hw, E1000_CTRL);
-       reg |= E1000_CTRL_SLU |
-              E1000_CTRL_SPD_1000 |
-              E1000_CTRL_FRCSPD |
-              E1000_CTRL_SWDPIN0 |
-              E1000_CTRL_SWDPIN1;
-       E1000_WRITE_REG(hw, E1000_CTRL, reg);
-
-       /* Power on phy for 82576 fiber adapters */
-       if (hw->mac.type == e1000_82576) {
-               reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
-               reg &= ~E1000_CTRL_EXT_SDP7_DATA;
-               E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
-       }
-
-       /* Set switch control to serdes energy detect */
-       reg = E1000_READ_REG(hw, E1000_CONNSW);
-       reg |= E1000_CONNSW_ENRGSRC;
-       E1000_WRITE_REG(hw, E1000_CONNSW, reg);
-
-       /*
-        * New SerDes mode allows for forcing speed or autonegotiating speed
-        * at 1gb. Autoneg should be default set by most drivers. This is the
-        * mode that will be compatible with older link partners and switches.
-        * However, both are supported by the hardware and some drivers/tools.
-        */
-       reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
-
-       reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
-               E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
-
-       if (hw->mac.autoneg) {
-               /* Set PCS register for autoneg */
-               reg |= E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
-                      E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
-                      E1000_PCS_LCTL_AN_ENABLE |     /* Enable Autoneg */
-                      E1000_PCS_LCTL_AN_RESTART;     /* Restart autoneg */
-               DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
-       } else {
-               /* Set PCS register for forced speed */
-               reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
-                      E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
-                      E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
-                      E1000_PCS_LCTL_FSD |           /* Force Speed */
-                      E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
-               DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
-       }
-
-       if (hw->mac.type == e1000_82576) {
-               reg |= E1000_PCS_LCTL_FORCE_FCTRL;
-               e1000_force_mac_fc_generic(hw);
-       }
-
-       E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
-
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_valid_led_default_82575 - Verify a valid default LED config
- *  @hw: pointer to the HW structure
- *  @data: pointer to the NVM (EEPROM)
- *
- *  Read the EEPROM for the current default LED configuration.  If the
- *  LED configuration is not valid, set to a valid LED configuration.
- **/
-static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
-{
-       s32 ret_val;
-
-       DEBUGFUNC("e1000_valid_led_default_82575");
-
-       ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
-       if (ret_val) {
-               DEBUGOUT("NVM Read Error\n");
-               goto out;
-       }
-
-       if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
-               switch(hw->phy.media_type) {
-               case e1000_media_type_fiber:
-               case e1000_media_type_internal_serdes:
-                       *data = ID_LED_DEFAULT_82575_SERDES;
-                       break;
-               case e1000_media_type_copper:
-               default:
-                       *data = ID_LED_DEFAULT;
-                       break;
-               }
-       }
-out:
-       return ret_val;
-}
-
-/**
- *  e1000_configure_pcs_link_82575 - Configure PCS link
- *  @hw: pointer to the HW structure
- *
- *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
- *  only used on copper connections where the serialized gigabit media
- *  independent interface (sgmii) is being used.  Configures the link
- *  for auto-negotiation or forces speed/duplex.
- **/
-static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw)
-{
-       struct e1000_mac_info *mac = &hw->mac;
-       u32 reg = 0;
-
-       DEBUGFUNC("e1000_configure_pcs_link_82575");
-
-       if (hw->phy.media_type != e1000_media_type_copper ||
-           !(e1000_sgmii_active_82575(hw)))
-               goto out;
-
-       /* For SGMII, we need to issue a PCS autoneg restart */
-       reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
-
-       /* AN time out should be disabled for SGMII mode */
-       reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
-
-       if (mac->autoneg) {
-               /* Make sure forced speed and force link are not set */
-               reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
-
-               /*
-                * The PHY should be setup prior to calling this function.
-                * All we need to do is restart autoneg and enable autoneg.
-                */
-               reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
-       } else {
-               /* Set PCS register for forced speed */
-
-               /* Turn off bits for full duplex, speed, and autoneg */
-               reg &= ~(E1000_PCS_LCTL_FSV_1000 |
-                        E1000_PCS_LCTL_FSV_100 |
-                        E1000_PCS_LCTL_FDV_FULL |
-                        E1000_PCS_LCTL_AN_ENABLE);
-
-               /* Check for duplex first */
-               if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
-                       reg |= E1000_PCS_LCTL_FDV_FULL;
-
-               /* Now set speed */
-               if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
-                       reg |= E1000_PCS_LCTL_FSV_100;
-
-               /* Force speed and force link */
-               reg |= E1000_PCS_LCTL_FSD |
-                      E1000_PCS_LCTL_FORCE_LINK |
-                      E1000_PCS_LCTL_FLV_LINK_UP;
-
-               DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
-                         reg);
-       }
-       E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
-
-out:
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_sgmii_active_82575 - Return sgmii state
- *  @hw: pointer to the HW structure
- *
- *  82575 silicon has a serialized gigabit media independent interface (sgmii)
- *  which can be enabled for use in the embedded applications.  Simply
- *  return the current state of the sgmii interface.
- **/
-static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
-{
-       struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
-
-       DEBUGFUNC("e1000_sgmii_active_82575");
-
-       if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576)
-               return FALSE;
-
-       return dev_spec->sgmii_active;
-}
-
-/**
- *  e1000_reset_init_script_82575 - Inits HW defaults after reset
- *  @hw: pointer to the HW structure
- *
- *  Inits recommended HW defaults after a reset when there is no EEPROM
- *  detected. This is only for the 82575.
- **/
-static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
-{
-       DEBUGFUNC("e1000_reset_init_script_82575");
-
-       if (hw->mac.type == e1000_82575) {
-               DEBUGOUT("Running reset init script for 82575\n");
-               /* SerDes configuration via SERDESCTRL */
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
-
-               /* CCM configuration via CCMCTL register */
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
-
-               /* PCIe lanes configuration */
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
-
-               /* PCIe PLL Configuration */
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
-               e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
-       }
-
-       return E1000_SUCCESS;
-}
-
-/**
- *  e1000_read_mac_addr_82575 - Read device MAC address
- *  @hw: pointer to the HW structure
- **/
-static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
-{
-       s32 ret_val = E1000_SUCCESS;
-
-       DEBUGFUNC("e1000_read_mac_addr_82575");
-       if (e1000_check_alt_mac_addr_generic(hw))
-               ret_val = e1000_read_mac_addr_generic(hw);
-
-       return ret_val;
-}
-
-/**
- * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
- * @hw: pointer to the HW structure
- *
- * In the case of a PHY power down to save power, or to turn off link during a
- * driver unload, or wake on lan is not enabled, remove the link.
- **/
-static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
-{
-       struct e1000_phy_info *phy = &hw->phy;
-       struct e1000_mac_info *mac = &hw->mac;
-
-       if (!(phy->ops.check_reset_block))
-               return;
-
-       /* If the management interface is not enabled, then power down */
-       if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
-               e1000_power_down_phy_copper(hw);
-
-       return;
-}
-
-/**
- *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
- *  @hw: pointer to the HW structure
- *
- *  Clears the hardware counters by reading the counter registers.
- **/
-static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
-{
-       DEBUGFUNC("e1000_clear_hw_cntrs_82575");
-
-       e1000_clear_hw_cntrs_base_generic(hw);
-
-       E1000_READ_REG(hw, E1000_PRC64);
-       E1000_READ_REG(hw, E1000_PRC127);
-       E1000_READ_REG(hw, E1000_PRC255);
-       E1000_READ_REG(hw, E1000_PRC511);
-       E1000_READ_REG(hw, E1000_PRC1023);
-       E1000_READ_REG(hw, E1000_PRC1522);
-       E1000_READ_REG(hw, E1000_PTC64);
-       E1000_READ_REG(hw, E1000_PTC127);
-       E1000_READ_REG(hw, E1000_PTC255);
-       E1000_READ_REG(hw, E1000_PTC511);
-       E1000_READ_REG(hw, E1000_PTC1023);
-       E1000_READ_REG(hw, E1000_PTC1522);
-
-       E1000_READ_REG(hw, E1000_ALGNERRC);
-       E1000_READ_REG(hw, E1000_RXERRC);
-       E1000_READ_REG(hw, E1000_TNCRS);
-       E1000_READ_REG(hw, E1000_CEXTERR);
-       E1000_READ_REG(hw, E1000_TSCTC);
-       E1000_READ_REG(hw, E1000_TSCTFC);
-
-       E1000_READ_REG(hw, E1000_MGTPRC);
-       E1000_READ_REG(hw, E1000_MGTPDC);
-       E1000_READ_REG(hw, E1000_MGTPTC);
-
-       E1000_READ_REG(hw, E1000_IAC);
-       E1000_READ_REG(hw, E1000_ICRXOC);
-
-       E1000_READ_REG(hw, E1000_ICRXPTC);
-       E1000_READ_REG(hw, E1000_ICRXATC);
-       E1000_READ_REG(hw, E1000_ICTXPTC);
-       E1000_READ_REG(hw, E1000_ICTXATC);
-       E1000_READ_REG(hw, E1000_ICTXQEC);
-       E1000_READ_REG(hw, E1000_ICTXQMTC);
-       E1000_READ_REG(hw, E1000_ICRXDMTC);
-
-       E1000_READ_REG(hw, E1000_CBTMPC);
-       E1000_READ_REG(hw, E1000_HTDPMC);
-       E1000_READ_REG(hw, E1000_CBRMPC);
-       E1000_READ_REG(hw, E1000_RPTHC);
-       E1000_READ_REG(hw, E1000_HGPTC);
-       E1000_READ_REG(hw, E1000_HTCBDPC);
-       E1000_READ_REG(hw, E1000_HGORCL);
-       E1000_READ_REG(hw, E1000_HGORCH);
-       E1000_READ_REG(hw, E1000_HGOTCL);
-       E1000_READ_REG(hw, E1000_HGOTCH);
-       E1000_READ_REG(hw, E1000_LENERRS);
-
-       /* This register should not be read in copper configurations */
-       if (hw->phy.media_type == e1000_media_type_internal_serdes)
-               E1000_READ_REG(hw, E1000_SCVPC);
-}
-/**
- *  e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
- *  @hw: pointer to the HW structure
- *
- *  After rx enable if managability is enabled then there is likely some
- *  bad data at the start of the fifo and possibly in the DMA fifo.  This
- *  function clears the fifos and flushes any packets that came in as rx was
- *  being enabled.
- **/
-void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
-{
-       u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
-       int i, ms_wait;
-
-       DEBUGFUNC("e1000_rx_fifo_workaround_82575");
-       if (hw->mac.type != e1000_82575 ||
-           !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
-               return;
-
-       /* Disable all RX queues */
-       for (i = 0; i < 4; i++) {
-               rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
-               E1000_WRITE_REG(hw, E1000_RXDCTL(i),
-                               rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
-       }
-       /* Poll all queues to verify they have shut down */
-       for (ms_wait = 0; ms_wait < 10; ms_wait++) {
-               msec_delay(1);
-               rx_enabled = 0;
-               for (i = 0; i < 4; i++)
-                       rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
-               if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
-                       break;
-       }
-
-       if (ms_wait == 10)
-               DEBUGOUT("Queue disable timed out after 10ms\n");
-
-       /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
-        * incoming packets are rejected.  Set enable and wait 2ms so that
-        * any packet that was coming in as RCTL.EN was set is flushed
-        */
-       rfctl = E1000_READ_REG(hw, E1000_RFCTL);
-       E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
-
-       rlpml = E1000_READ_REG(hw, E1000_RLPML);
-       E1000_WRITE_REG(hw, E1000_RLPML, 0);
-
-       rctl = E1000_READ_REG(hw, E1000_RCTL);
-       temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
-       temp_rctl |= E1000_RCTL_LPE;
-
-       E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
-       E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
-       E1000_WRITE_FLUSH(hw);
-       msec_delay(2);
-
-       /* Enable RX queues that were previously enabled and restore our
-        * previous state
-        */
-       for (i = 0; i < 4; i++)
-               E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
-       E1000_WRITE_REG(hw, E1000_RCTL, rctl);
-       E1000_WRITE_FLUSH(hw);
-
-       E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
-       E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
-
-       /* Flush receive errors generated by workaround */
-       E1000_READ_REG(hw, E1000_ROC);
-       E1000_READ_REG(hw, E1000_RNBC);
-       E1000_READ_REG(hw, E1000_MPC);
-}
-
diff --git a/sys/dev/netif/ig_hal/e1000_82575.h b/sys/dev/netif/ig_hal/e1000_82575.h
deleted file mode 100644 (file)
index 56321e4..0000000
+++ /dev/null
@@ -1,474 +0,0 @@
-/******************************************************************************
-
-  Copyright (c) 2001-2008, Intel Corporation 
-  All rights reserved.
-  
-  Redistribution and use in source and binary forms, with or without 
-  modification, are permitted provided that the following conditions are met:
-  
-   1. Redistributions of source code must retain the above copyright notice, 
-      this list of conditions and the following disclaimer.
-  
-   2. Redistributions in binary form must reproduce the above copyright 
-      notice, this list of conditions and the following disclaimer in the 
-      documentation and/or other materials provided with the distribution.
-  
-   3. Neither the name of the Intel Corporation nor the names of its 
-      contributors may be used to endorse or promote products derived from 
-      this software without specific prior written permission.
-  
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE.
-
-******************************************************************************/
-/*$FreeBSD$*/
-
-#ifndef _E1000_82575_H_
-#define _E1000_82575_H_
-
-#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
-                                     (ID_LED_DEF1_DEF2 <<  8) | \
-                                     (ID_LED_DEF1_DEF2 <<  4) | \
-                                     (ID_LED_OFF1_ON2))
-/*
- * Receive Address Register Count
- * Number of high/low register pairs in the RAR.  The RAR (Receive Address
- * Registers) holds the directed and multicast addresses that we monitor.
- * These entries are also used for MAC-based filtering.
- */
-/*
- * For 82576, there are an additional set of RARs that begin at an offset
- * separate from the first set of RARs.
- */
-#define E1000_RAR_ENTRIES_82575   16
-#define E1000_RAR_ENTRIES_82576   24
-
-#ifdef E1000_BIT_FIELDS
-struct e1000_adv_data_desc {
-       u64 buffer_addr;    /* Address of the descriptor's data buffer */
-       union {
-               u32 data;
-               struct {
-                       u32 datalen :16; /* Data buffer length */
-                       u32 rsvd    :4;
-                       u32 dtyp    :4;  /* Descriptor type */
-                       u32 dcmd    :8;  /* Descriptor command */
-               } config;
-       } lower;
-       union {
-               u32 data;
-               struct {
-                       u32 status  :4;  /* Descriptor status */
-                       u32 idx     :4;
-                       u32 popts   :6;  /* Packet Options */
-                       u32 paylen  :18; /* Payload length */
-               } options;
-       } upper;
-};
-
-#define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
-#define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
-#define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
-#define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
-#define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
-#define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
-#define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
-#define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
-#define E1000_ADV_DCMD_RS       0x8  /* Report Status */
-#define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
-#define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
-/* Extended Device Control */
-#define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
-
-struct e1000_adv_context_desc {
-       union {
-               u32 ip_config;
-               struct {
-                       u32 iplen    :9;
-                       u32 maclen   :7;
-                       u32 vlan_tag :16;
-               } fields;
-       } ip_setup;
-       u32 seq_num;
-       union {
-               u64 l4_config;
-               struct {
-                       u32 mkrloc :9;
-                       u32 tucmd  :11;
-                       u32 dtyp   :4;
-                       u32 adv    :8;
-                       u32 rsvd   :4;
-                       u32 idx    :4;
-                       u32 l4len  :8;
-                       u32 mss    :16;
-               } fields;
-       } l4_setup;
-};
-#endif
-
-/* SRRCTL bit definitions */
-#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
-#define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
-#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
-#define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
-#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
-#define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
-
-#define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
-#define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
-
-#define E1000_TX_HEAD_WB_ENABLE   0x1
-#define E1000_TX_SEQNUM_WB_ENABLE 0x2
-
-#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
-#define E1000_MRQC_ENABLE_VMDQ              0x00000003
-#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
-
-#define E1000_VMRCTL_MIRROR_PORT_SHIFT      8
-#define E1000_VMRCTL_MIRROR_DSTPORT_MASK    (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
-#define E1000_VMRCTL_POOL_MIRROR_ENABLE     (1 << 0)
-#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE   (1 << 1)
-#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
-
-#define E1000_EICR_TX_QUEUE ( \
-    E1000_EICR_TX_QUEUE0 |    \
-    E1000_EICR_TX_QUEUE1 |    \
-    E1000_EICR_TX_QUEUE2 |    \
-    E1000_EICR_TX_QUEUE3)
-
-#define E1000_EICR_RX_QUEUE ( \
-    E1000_EICR_RX_QUEUE0 |    \
-    E1000_EICR_RX_QUEUE1 |    \
-    E1000_EICR_RX_QUEUE2 |    \
-    E1000_EICR_RX_QUEUE3)
-
-#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
-#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
-
-#define EIMS_ENABLE_MASK ( \
-    E1000_EIMS_RX_QUEUE  | \
-    E1000_EIMS_TX_QUEUE  | \
-    E1000_EIMS_TCP_TIMER | \
-    E1000_EIMS_OTHER)
-
-/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
-#define E1000_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
-#define E1000_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
-#define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
-#define E1000_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
-#define E1000_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
-#define E1000_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
-#define E1000_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
-#define E1000_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
-#define E1000_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
-#define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
-
-/* Receive Descriptor - Advanced */
-union e1000_adv_rx_desc {
-       struct {
-               u64 pkt_addr;             /* Packet buffer address */
-               u64 hdr_addr;             /* Header buffer address */
-       } read;
-       struct {
-               struct {
-                       union {
-                               u32 data;
-                               struct {
-                                       u16 pkt_info; /* RSS type, Packet type */
-                                       u16 hdr_info; /* Split Header,
-                                                      * header buffer length */
-                               } hs_rss;
-                       } lo_dword;
-                       union {
-                               u32 rss;          /* RSS Hash */
-                               struct {
-                                       u16 ip_id;    /* IP id */
-                                       u16 csum;     /* Packet Checksum */
-                               } csum_ip;
-                       } hi_dword;
-               } lower;
-               struct {
-                       u32 status_error;     /* ext status/error */
-                       u16 length;           /* Packet length */
-                       u16 vlan;             /* VLAN tag */
-               } upper;
-       } wb;  /* writeback */
-};
-
-#define E1000_RXDADV_RSSTYPE_MASK        0x0000F000
-#define E1000_RXDADV_RSSTYPE_SHIFT       12
-#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
-#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
-#define E1000_RXDADV_SPLITHEADER_EN      0x00001000
-#define E1000_RXDADV_SPH                 0x8000
-#define E1000_RXDADV_ERR_HBO             0x00800000
-
-/* RSS Hash results */
-#define E1000_RXDADV_RSSTYPE_NONE        0x00000000
-#define E1000_RXDADV_RSSTYPE_IPV4_TCP    0x00000001
-#define E1000_RXDADV_RSSTYPE_IPV4        0x00000002
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP    0x00000003
-#define E1000_RXDADV_RSSTYPE_IPV6_EX     0x00000004
-#define E1000_RXDADV_RSSTYPE_IPV6        0x00000005
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
-#define E1000_RXDADV_RSSTYPE_IPV4_UDP    0x00000007
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP    0x00000008
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
-
-/* RSS Packet Types as indicated in the receive descriptor */
-#define E1000_RXDADV_PKTTYPE_NONE        0x00000000
-#define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV4_EX     0x00000020 /* IPV4 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_IPV6        0x00000040 /* IPV6 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV6_EX     0x00000080 /* IPV6 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
-#define E1000_RXDADV_PKTTYPE_UDP         0x00000200 /* UDP hdr present */
-#define E1000_RXDADV_PKTTYPE_SCTP        0x00000400 /* SCTP hdr present */
-#define E1000_RXDADV_PKTTYPE_NFS         0x00000800 /* NFS hdr present */
-
-#define E1000_RXDADV_PKTTYPE_IPSEC_ESP   0x00001000 /* IPSec ESP */
-#define E1000_RXDADV_PKTTYPE_IPSEC_AH    0x00002000 /* IPSec AH */
-#define E1000_RXDADV_PKTTYPE_LINKSEC     0x00004000 /* LinkSec Encap */
-#define E1000_RXDADV_PKTTYPE_ETQF        0x00008000 /* PKTTYPE is ETQF index */
-#define E1000_RXDADV_PKTTYPE_ETQF_MASK   0x00000070 /* ETQF has 8 indices */
-#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT  4          /* Right-shift 4 bits */
-
-/* LinkSec results */
-/* Security Processing bit Indication */
-#define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
-#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
-#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
-#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
-#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
-
-#define E1000_RXDADV_IPSEC_STATUS_SECP          0x00020000
-#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
-#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
-
-/* Transmit Descriptor - Advanced */
-union e1000_adv_tx_desc {
-       struct {
-               u64 buffer_addr;    /* Address of descriptor's data buf */
-               u32 cmd_type_len;
-               u32 olinfo_status;
-       } read;
-       struct {
-               u64 rsvd;       /* Reserved */
-               u32 nxtseq_seed;
-               u32 status;
-       } wb;
-};
-
-/* Adv Transmit Descriptor Config Masks */
-#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
-#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
-#define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
-#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
-#define E1000_ADVTXD_DCMD_DDTYP_ISCSI  0x10000000 /* DDP hdr type or iSCSI */
-#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
-#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
-#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
-#define E1000_ADVTXD_MAC_LINKSEC  0x00040000 /* Apply LinkSec on packet */
-#define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
-#define E1000_ADVTXD_STAT_SN_CRC  0x00000002 /* NXTSEQ/SEED present in WB */
-#define E1000_ADVTXD_IDX_SHIFT    4  /* Adv desc Index shift */
-#define E1000_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
-#define E1000_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
-#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
-
-/* Context descriptors */
-struct e1000_adv_tx_context_desc {
-       u32 vlan_macip_lens;
-       u32 seqnum_seed;
-       u32 type_tucmd_mlhl;
-       u32 mss_l4len_idx;
-};
-
-#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
-#define E1000_ADVTXD_VLAN_SHIFT     16  /* Adv ctxt vlan tag shift */
-#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
-#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
-#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP    0x00002000 /* IPSec Type ESP */
-/* IPSec Encrypt Enable for ESP */
-#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN  0x00004000
-#define E1000_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
-#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
-#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
-/* Adv ctxt IPSec SA IDX mask */
-#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK     0x000000FF
-/* Adv ctxt IPSec ESP len mask */
-#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK      0x000000FF
-
-/* Additional Transmit Descriptor Control definitions */
-#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
-#define E1000_TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
-/* Tx Queue Arbitration Priority 0=low, 1=high */
-#define E1000_TXDCTL_PRIORITY      0x08000000
-
-/* Additional Receive Descriptor Control definitions */
-#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
-#define E1000_RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
-
-/* Direct Cache Access (DCA) definitions */
-#define E1000_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
-#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
-
-#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
-#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
-
-#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
-#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
-#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
-#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
-
-#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
-#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
-#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
-
-#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
-#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
-#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
-#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
-
-/* Additional interrupt register bit definitions */
-#define E1000_ICR_LSECPNS       0x00000020          /* PN threshold - server */
-#define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
-#define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
-
-/* ETQF register bit definitions */
-#define E1000_ETQF_FILTER_ENABLE   (1 << 26)
-#define E1000_ETQF_IMM_INT         (1 << 29)
-#define E1000_ETQF_1588            (1 << 30)
-#define E1000_ETQF_QUEUE_ENABLE    (1 << 31)
-/*
- * ETQF filter list: one static filter per filter consumer. This is
- *                   to avoid filter collisions later. Add new filters
- *                   here!!
- *
- * Current filters:
- *    EAPOL 802.1x (0x888e): Filter 0
- */
-#define E1000_ETQF_FILTER_EAPOL          0
-
-#define E1000_NVM_APME_82575          0x0400
-#define MAX_NUM_VFS                   8
-
-#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
-#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
-#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
-#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
-
-/* Easy defines for setting default pool, would normally be left a zero */
-#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
-#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
-
-/* Other useful VMD_CTL register defines */
-#define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
-#define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
-#define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
-
-/* Per VM Offload register setup */
-#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
-#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
-#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
-#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
-#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
-
-#define E1000_V2PMAILBOX_REQ   0x00000001 /* Request for PF Ready bit */
-#define E1000_V2PMAILBOX_ACK   0x00000002 /* Ack PF message received */
-#define E1000_V2PMAILBOX_VFU   0x00000004 /* VF owns the mailbox buffer */
-#define E1000_V2PMAILBOX_PFU   0x00000008 /* PF owns the mailbox buffer */
-#define E1000_V2PMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */
-#define E1000_V2PMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */
-#define E1000_V2PMAILBOX_RSTI  0x00000040 /* PF has reset indication */
-
-#define E1000_P2VMAILBOX_STS   0x00000001 /* Initiate message send to VF */
-#define E1000_P2VMAILBOX_ACK   0x00000002 /* Ack message recv'd from VF */
-#define E1000_P2VMAILBOX_VFU   0x00000004 /* VF owns the mailbox buffer */
-#define E1000_P2VMAILBOX_PFU   0x00000008 /* PF owns the mailbox buffer */
-#define E1000_P2VMAILBOX_RVFU  0x00000010 /* Reset VFU - used when VF stuck */
-
-#define E1000_VFMAILBOX_SIZE   16 /* 16 32 bit words - 64 bytes */
-
-/* If it's a E1000_VF_* msg then it originates in the VF and is sent to the
- * PF.  The reverse is TRUE if it is E1000_PF_*.
- * Message ACK's are the value or'd with 0xF0000000
- */
-#define E1000_VT_MSGTYPE_ACK      0xF0000000  /* Messages below or'd with
-                                               * this are the ACK */
-#define E1000_VT_MSGTYPE_NACK     0xFF000000  /* Messages below or'd with
-                                               * this are the NACK */
-#define E1000_VT_MSGINFO_SHIFT    16
-/* bits 23:16 are used for exra info for certain messages */
-#define E1000_VT_MSGINFO_MASK     (0xFF << E1000_VT_MSGINFO_SHIFT)
-
-#define E1000_VF_MSGTYPE_REQ_MAC  1 /* VF needs to know its MAC */
-#define E1000_VF_MSGTYPE_VFLR     2 /* VF notifies VFLR to PF */
-#define E1000_VF_SET_MULTICAST    3 /* VF requests PF to set MC addr */
-#define E1000_VF_SET_VLAN         4 /* VF requests PF to set VLAN */
-
-/* Add 100h to all PF msgs, leaves room for up to 255 discrete message types
- * from VF to PF - way more than we'll ever need */
-#define E1000_PF_MSGTYPE_RESET    (1 + 0x100) /* PF notifies global reset
-                                               * imminent to VF */
-#define E1000_PF_MSGTYPE_LSC      (2 + 0x100) /* PF notifies VF of LSC... VF
-                                               * will see extra msg info for
-                                               * status */
-
-#define E1000_PF_MSG_LSCDOWN      (1 << E1000_VT_MSGINFO_SHIFT)
-#define E1000_PF_MSG_LSCUP        (2 << E1000_VT_MSGINFO_SHIFT)
-
-#define ALL_QUEUES   0xFFFF
-
-s32  e1000_send_mail_to_pf_vf(struct e1000_hw *hw, u32 *msg,
-                              s16 size);
-s32  e1000_receive_mail_from_pf_vf(struct e1000_hw *hw,
-                                   u32 *msg, s16 size);
-s32  e1000_send_mail_to_vf(struct e1000_hw *hw, u32 *msg,
-                           u32 vf_number, s16 size);
-s32  e1000_receive_mail_from_vf(struct e1000_hw *hw, u32 *msg,
-                                u32 vf_number, s16 size);
-void e1000_vmdq_loopback_enable_vf(struct e1000_hw *hw);
-void e1000_vmdq_loopback_disable_vf(struct e1000_hw *hw);
-void e1000_vmdq_replication_enable_vf(struct e1000_hw *hw, u32 enables);
-void e1000_vmdq_replication_disable_vf(struct e1000_hw *hw);
-void e1000_vmdq_enable_replication_mode_vf(struct e1000_hw *hw);
-void e1000_vmdq_broadcast_replication_enable_vf(struct e1000_hw *hw,
-                                               u32 enables);
-void e1000_vmdq_multicast_replication_enable_vf(struct e1000_hw *hw,
-                                               u32 enables);
-void e1000_vmdq_broadcast_replication_disable_vf(struct e1000_hw *hw,
-                                               u32 disables);
-void e1000_vmdq_multicast_replication_disable_vf(struct e1000_hw *hw,
-                                               u32 disables);
-bool e1000_check_for_pf_ack_vf(struct e1000_hw *hw);
-
-bool e1000_check_for_pf_mail_vf(struct e1000_hw *hw, u32*);
-
-
-#endif
index d1e85c8..9334901 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 #include "e1000_api.h"
 
@@ -112,6 +112,7 @@ out:
        return ret_val;
 }
 
+
 /**
  *  e1000_set_mac_type - Sets MAC type
  *  @hw: pointer to the HW structure
@@ -129,9 +130,11 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
        DEBUGFUNC("e1000_set_mac_type");
 
        switch (hw->device_id) {
+#ifndef NO_82542_SUPPORT
        case E1000_DEV_ID_82542:
                mac->type = e1000_82542;
                break;
+#endif
        case E1000_DEV_ID_82543GC_FIBER:
        case E1000_DEV_ID_82543GC_COPPER:
                mac->type = e1000_82543;
@@ -198,7 +201,6 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
        case E1000_DEV_ID_82571PT_QUAD_COPPER:
        case E1000_DEV_ID_82571EB_QUAD_FIBER:
        case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
-       case E1000_DEV_ID_82571EB_QUAD_COPPER_BP:
                mac->type = e1000_82571;
                break;
        case E1000_DEV_ID_82572EI:
@@ -213,8 +215,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
                mac->type = e1000_82573;
                break;
        case E1000_DEV_ID_82574L:
+       case E1000_DEV_ID_82574LA:
                mac->type = e1000_82574;
                break;
+       case E1000_DEV_ID_82583V:
+               mac->type = e1000_82583;
+               break;
        case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
        case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
        case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
@@ -228,6 +234,7 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
        case E1000_DEV_ID_ICH8_IGP_M_AMT:
        case E1000_DEV_ID_ICH8_IGP_AMT:
        case E1000_DEV_ID_ICH8_IGP_C:
+       case E1000_DEV_ID_ICH8_82567V_3:
                mac->type = e1000_ich8lan;
                break;
        case E1000_DEV_ID_ICH9_IFE:
@@ -246,18 +253,19 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
                break;
        case E1000_DEV_ID_ICH10_D_BM_LM:
        case E1000_DEV_ID_ICH10_D_BM_LF:
+       case E1000_DEV_ID_ICH10_D_BM_V:
+       case E1000_DEV_ID_ICH10_HANKSVILLE:
                mac->type = e1000_ich10lan;
                break;
-       case E1000_DEV_ID_82575EB_COPPER:
-       case E1000_DEV_ID_82575EB_FIBER_SERDES:
-       case E1000_DEV_ID_82575GB_QUAD_COPPER:
-               mac->type = e1000_82575;
+       case E1000_DEV_ID_PCH_D_HV_DM:
+       case E1000_DEV_ID_PCH_D_HV_DC:
+       case E1000_DEV_ID_PCH_M_HV_LM:
+       case E1000_DEV_ID_PCH_M_HV_LC:
+               mac->type = e1000_pchlan;
                break;
-       case E1000_DEV_ID_82576:
-       case E1000_DEV_ID_82576_FIBER:
-       case E1000_DEV_ID_82576_SERDES:
-       case E1000_DEV_ID_82576_QUAD_COPPER:
-               mac->type = e1000_82576;
+       case E1000_DEV_ID_PCH2_LV_LM:
+       case E1000_DEV_ID_PCH2_LV_V:
+               mac->type = e1000_pch2lan;
                break;
        default:
                /* Should never have loaded on this device */
@@ -311,9 +319,11 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
         * the functions in that family.
         */
        switch (hw->mac.type) {
+#ifndef NO_82542_SUPPORT
        case e1000_82542:
                e1000_init_function_pointers_82542(hw);
                break;
+#endif
        case e1000_82543:
        case e1000_82544:
                e1000_init_function_pointers_82543(hw);
@@ -335,6 +345,7 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
        case e1000_82572:
        case e1000_82573:
        case e1000_82574:
+       case e1000_82583:
                e1000_init_function_pointers_82571(hw);
                break;
        case e1000_80003es2lan:
@@ -343,12 +354,10 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
        case e1000_ich8lan:
        case e1000_ich9lan:
        case e1000_ich10lan:
+       case e1000_pchlan:
+       case e1000_pch2lan:
                e1000_init_function_pointers_ich8lan(hw);
                break;
-       case e1000_82575:
-       case e1000_82576:
-               e1000_init_function_pointers_82575(hw);
-               break;
        default:
                DEBUGOUT("Hardware not supported\n");
                ret_val = -E1000_ERR_CONFIG;
@@ -371,7 +380,6 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
                ret_val = e1000_init_phy_params(hw);
                if (ret_val)
                        goto out;
-
        }
 
 out:
@@ -427,26 +435,16 @@ void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
  *  @hw: pointer to the HW structure
  *  @mc_addr_list: array of multicast addresses to program
  *  @mc_addr_count: number of multicast addresses to program
- *  @rar_used_count: the first RAR register free to program
- *  @rar_count: total number of supported Receive Address Registers
  *
- *  Updates the Receive Address Registers and Multicast Table Array.
+ *  Updates the Multicast Table Array.
  *  The caller must have a packed mc_addr_list of multicast addresses.
- *  The parameter rar_count will usually be hw->mac.rar_entry_count
- *  unless there are workarounds that change this.  Currently no func pointer
- *  exists and all implementations are handled in the generic version of this
- *  function.
  **/
 void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
-                               u32 mc_addr_count, u32 rar_used_count,
-                               u32 rar_count)
+                               u32 mc_addr_count)
 {
        if (hw->mac.ops.update_mc_addr_list)
-               hw->mac.ops.update_mc_addr_list(hw,
-                                               mc_addr_list,
-                                               mc_addr_count,
-                                               rar_used_count,
-                                               rar_count);
+               hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
+                                               mc_addr_count);
 }
 
 /**
@@ -618,6 +616,21 @@ s32 e1000_blink_led(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_id_led_init - store LED configurations in SW
+ *  @hw: pointer to the HW structure
+ *
+ *  Initializes the LED config in SW. This is a function pointer entry point
+ *  called by drivers.
+ **/
+s32 e1000_id_led_init(struct e1000_hw *hw)
+{
+       if (hw->mac.ops.id_led_init)
+               return hw->mac.ops.id_led_init(hw);
+
+       return E1000_SUCCESS;
+}
+
+/**
  *  e1000_led_on - Turn on SW controllable LED
  *  @hw: pointer to the HW structure
  *
@@ -726,20 +739,6 @@ s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
 }
 
 /**
- *  e1000_mta_set - Sets multicast table bit
- *  @hw: pointer to the HW structure
- *  @hash_value: Multicast hash value.
- *
- *  This sets the bit in the multicast table corresponding to the
- *  hash value.  This is a function pointer entry point called by drivers.
- **/
-void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
-{
-       if (hw->mac.ops.mta_set)
-               hw->mac.ops.mta_set(hw, hash_value);
-}
-
-/**
  *  e1000_hash_mc_addr - Determines address location in multicast table
  *  @hw: pointer to the HW structure
  *  @mc_addr: Multicast address to hash.
@@ -1080,6 +1079,37 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_read_pba_string - Read device part number string
+ *  @hw: pointer to the HW structure
+ *  @pba_num: pointer to device part number
+ *  @pba_num_size: size of part number buffer
+ *
+ *  Reads the product board assembly (PBA) number from the EEPROM and stores
+ *  the value in pba_num.
+ *  Currently no func pointer exists and all implementations are handled in the
+ *  generic version of this function.
+ **/
+s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size)
+{
+       return e1000_read_pba_string_generic(hw, pba_num, pba_num_size);
+}
+
+/**
+ *  e1000_read_pba_length - Read device part number string length
+ *  @hw: pointer to the HW structure
+ *  @pba_num_size: size of part number buffer
+ *
+ *  Reads the product board assembly (PBA) number length from the EEPROM and
+ *  stores the value in pba_num.
+ *  Currently no func pointer exists and all implementations are handled in the
+ *  generic version of this function.
+ **/
+s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size)
+{
+       return e1000_read_pba_length_generic(hw, pba_num_size);
+}
+
+/**
  *  e1000_read_pba_num - Read device part number
  *  @hw: pointer to the HW structure
  *  @pba_num: pointer to device part number
@@ -1174,22 +1204,6 @@ s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 }
 
 /**
- *  e1000_write_8bit_ctrl_reg - Writes 8bit Control register
- *  @hw: pointer to the HW structure
- *  @reg: 32bit register offset
- *  @offset: the register to write
- *  @data: the value to write.
- *
- *  Writes the PHY register at offset with the value in data.
- *  This is a function pointer entry point called by drivers.
- **/
-s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
-                              u8 data)
-{
-       return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);
-}
-
-/**
  * e1000_power_up_phy - Restores link in case of PHY power down
  * @hw: pointer to the HW structure
  *
@@ -1217,15 +1231,3 @@ void e1000_power_down_phy(struct e1000_hw *hw)
                hw->phy.ops.power_down(hw);
 }
 
-/**
- *  e1000_shutdown_fiber_serdes_link - Remove link during power down
- *  @hw: pointer to the HW structure
- *
- *  Shutdown the optics and PCS on driver unload.
- **/
-void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw)
-{
-       if (hw->mac.ops.shutdown_serdes)
-               hw->mac.ops.shutdown_serdes(hw);
-}
-
index 4629ff0..94cbde9 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 #ifndef _E1000_API_H_
 #define _E1000_API_H_
 
 #include "e1000_hw.h"
 
+#ifndef NO_82542_SUPPORT
 extern void    e1000_init_function_pointers_82542(struct e1000_hw *hw);
+#endif
 extern void    e1000_init_function_pointers_82543(struct e1000_hw *hw);
 extern void    e1000_init_function_pointers_82540(struct e1000_hw *hw);
 extern void    e1000_init_function_pointers_82571(struct e1000_hw *hw);
 extern void    e1000_init_function_pointers_82541(struct e1000_hw *hw);
 extern void    e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);
 extern void    e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82575(struct e1000_hw *hw);
-extern void    e1000_rx_fifo_flush_82575(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_vf(struct e1000_hw *hw);
-extern void    e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
 
 s32  e1000_set_mac_type(struct e1000_hw *hw);
 s32  e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
@@ -67,25 +65,22 @@ s32  e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
 s32  e1000_disable_pcie_master(struct e1000_hw *hw);
 void e1000_config_collision_dist(struct e1000_hw *hw);
 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
-void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
 u32  e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
 void e1000_update_mc_addr_list(struct e1000_hw *hw,
-                               u8 *mc_addr_list, u32 mc_addr_count,
-                               u32 rar_used_count, u32 rar_count);
+                               u8 *mc_addr_list, u32 mc_addr_count);
 s32  e1000_setup_led(struct e1000_hw *hw);
 s32  e1000_cleanup_led(struct e1000_hw *hw);
 s32  e1000_check_reset_block(struct e1000_hw *hw);
 s32  e1000_blink_led(struct e1000_hw *hw);
 s32  e1000_led_on(struct e1000_hw *hw);
 s32  e1000_led_off(struct e1000_hw *hw);
+s32 e1000_id_led_init(struct e1000_hw *hw);
 void e1000_reset_adaptive(struct e1000_hw *hw);
 void e1000_update_adaptive(struct e1000_hw *hw);
 s32  e1000_get_cable_length(struct e1000_hw *hw);
 s32  e1000_validate_mdi_setting(struct e1000_hw *hw);
 s32  e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
-s32  e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
-                               u32 offset, u8 data);
 s32  e1000_get_phy_info(struct e1000_hw *hw);
 void e1000_release_phy(struct e1000_hw *hw);
 s32  e1000_acquire_phy(struct e1000_hw *hw);
@@ -96,6 +91,9 @@ void e1000_power_up_phy(struct e1000_hw *hw);
 void e1000_power_down_phy(struct e1000_hw *hw);
 s32  e1000_read_mac_addr(struct e1000_hw *hw);
 s32  e1000_read_pba_num(struct e1000_hw *hw, u32 *part_num);
+s32  e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, 
+                           u32 pba_num_size);
+s32  e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);
 void e1000_reload_nvm(struct e1000_hw *hw);
 s32  e1000_update_nvm_checksum(struct e1000_hw *hw);
 s32  e1000_validate_nvm_checksum(struct e1000_hw *hw);
@@ -116,7 +114,9 @@ s32  e1000_mng_write_cmd_header(struct e1000_hw *hw,
                                 struct e1000_host_mng_command_header *hdr);
 s32  e1000_mng_write_dhcp_info(struct e1000_hw * hw,
                                     u8 *buffer, u16 length);
+#ifndef NO_82542_SUPPORT
 u32  e1000_translate_register_82542(u32 reg);
+#endif
 
 /*
  * TBI_ACCEPT macro definition:
index b454a69..24fe608 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 #ifndef _E1000_DEFINES_H_
 #define _E1000_DEFINES_H_
@@ -49,6 +49,8 @@
 #define E1000_WUC_LSCWO      0x00000020 /* Link Status wake up override */
 #define E1000_WUC_SPM        0x80000000 /* Enable SPM */
 #define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
+#define E1000_WUC_FLX6_PHY  0x4000 /* Flexible Filter 6 Enable */
+#define E1000_WUC_FLX7_PHY  0x8000 /* Flexible Filter 7 Enable */
 
 /* Wake Up Filter Control */
 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
@@ -64,6 +66,8 @@
 #define E1000_WUFC_FLX1_PHY      0x00002000 /* Flexible Filter 1 Enable */
 #define E1000_WUFC_FLX2_PHY      0x00004000 /* Flexible Filter 2 Enable */
 #define E1000_WUFC_FLX3_PHY      0x00008000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_FLX4_PHY      0x00000200 /* Flexible Filter 4 Enable */
+#define E1000_WUFC_FLX5_PHY      0x00000400 /* Flexible Filter 5 Enable */
 #define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 #define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 #define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
+#define E1000_WUFC_FLX6  0x00400000 /* Flexible Filter 6 Enable */
+#define E1000_WUFC_FLX7  0x00800000 /* Flexible Filter 7 Enable */
 #define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/
 #define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
 #define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/
+#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */
+#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/
 #define E1000_WUFC_ALL_FILTERS  0x000F00FF /* Mask for all wakeup filters */
+#define E1000_WUFC_ALL_FILTERS_6  0x003F00FF /* Mask for all 6 wakeup filters*/
+#define E1000_WUFC_ALL_FILTERS_8  0x00FF00FF /* Mask for all 8 wakeup filters*/
 #define E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
 #define E1000_WUFC_FLX_FILTERS  0x000F0000 /*Mask for the 4 flexible filters */
-/*
- * For 82576 to utilize Extended filter masks in addition to
- * existing (filter) masks
- */
-#define E1000_WUFC_EXT_FLX_FILTERS      0x00300000 /* Ext. FLX filter mask */
+#define E1000_WUFC_FLX_FILTERS_6  0x003F0000 /* Mask for 6 flexible filters */
+#define E1000_WUFC_FLX_FILTERS_8  0x00FF0000 /* Mask for 8 flexible filters */
 
 /* Wake Up Status */
 #define E1000_WUS_LNKC         E1000_WUFC_LNKC
 #define E1000_WUS_FLX1         E1000_WUFC_FLX1
 #define E1000_WUS_FLX2         E1000_WUFC_FLX2
 #define E1000_WUS_FLX3         E1000_WUFC_FLX3
+#define E1000_WUS_FLX4         E1000_WUFC_FLX4
+#define E1000_WUS_FLX5         E1000_WUFC_FLX5
+#define E1000_WUS_FLX6         E1000_WUFC_FLX6
+#define E1000_WUS_FLX7         E1000_WUFC_FLX7
+#define E1000_WUS_FLX4_PHY         E1000_WUFC_FLX4_PHY
+#define E1000_WUS_FLX5_PHY         E1000_WUFC_FLX5_PHY
+#define E1000_WUS_FLX6_PHY         0x0400
+#define E1000_WUS_FLX7_PHY         0x0800
 #define E1000_WUS_FLX_FILTERS  E1000_WUFC_FLX_FILTERS
+#define E1000_WUS_FLX_FILTERS_6  E1000_WUFC_FLX_FILTERS_6
+#define E1000_WUS_FLX_FILTERS_8  E1000_WUFC_FLX_FILTERS_8
+#define E1000_WUS_FLX_FILTERS_PHY_6  E1000_WUFC_FLX_FILTERS_PHY_6
 
 /* Wake Up Packet Length */
 #define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
 
 /* Four Flexible Filters are supported */
 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
-/* Two Extended Flexible Filters are supported (82576) */
-#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
-#define E1000_FHFT_LENGTH_OFFSET        0xFC /* Length byte in FHFT */
-#define E1000_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
+/* Six Flexible Filters are supported */
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6   6
+/* Eight Flexible Filters are supported */
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8   8
 
 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 #define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
 
 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
+#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
+#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8
 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 
 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
 #define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
+#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
 #define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
 #define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SDP7_DIR  0x00000800 /* Direction of SDP7 0=in 1=out */
+#define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* Direction of SDP3 0=in 1=out */
 #define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
 #define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
 #define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
-/* Physical Func Reset Done Indication */
-#define E1000_CTRL_EXT_PFRSTD    0x00004000
 #define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
 #define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
+#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/
+#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX  0x00400000
 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
 #define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
 #define E1000_CTRL_EXT_LINK_MODE_KMRN    0x00000000
 #define E1000_CTRL_EXT_CANC           0x04000000 /* Int delay cancellation */
 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
 /* IAME enable bit (27) was removed in >= 82575 */
-#define E1000_CTRL_EXT_IAME           0x08000000 /* Int acknowledge Auto-mask */
-#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000 /* Clear Interrupt timers
-                                                  * after IMS clear */
+#define E1000_CTRL_EXT_IAME          0x08000000 /* Int acknowledge Auto-mask */
 #define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error
                                                   * detection enabled */
 #define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity
 #define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
 #define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
 #define E1000_CTRL_EXT_LSECCK         0x00001000
+#define E1000_CTRL_EXT_PHYPDEN        0x00100000
 #define E1000_I2CCMD_REG_ADDR_SHIFT   16
 #define E1000_I2CCMD_REG_ADDR         0x00FF0000
 #define E1000_I2CCMD_PHY_ADDR_SHIFT   24
 #define E1000_I2CCMD_ERROR            0x80000000
 #define E1000_MAX_SGMII_PHY_REG_ADDR  255
 #define E1000_I2CCMD_PHY_TIMEOUT      200
-#define E1000_IVAR_VALID        0x80
-#define E1000_GPIE_NSICR        0x00000001
-#define E1000_GPIE_MSIX_MODE    0x00000010
-#define E1000_GPIE_EIAME        0x40000000
-#define E1000_GPIE_PBA          0x80000000
 
 /* Receive Descriptor bit definitions */
 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 #define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
 #define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
 
+#define E1000_MANC2H_PORT_623    0x00000020 /* Port 0x26f */
+#define E1000_MANC2H_PORT_664    0x00000040 /* Port 0x298 */
+#define E1000_MDEF_PORT_623      0x00000800 /* Port 0x26f */
+#define E1000_MDEF_PORT_664      0x00000400 /* Port 0x298 */
+
 /* Receive Control */
 #define E1000_RCTL_RST            0x00000001    /* Software reset */
 #define E1000_RCTL_EN             0x00000002    /* enable */
 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
-#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
-#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
+#define E1000_RCTL_UPE            0x00000008    /* unicast promisc enable */
+#define E1000_RCTL_MPE            0x00000010    /* multicast promisc enable */
 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
 #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
 #define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
 #define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
-#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min thresh size */
+#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min thresh size */
+#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min thresh size */
 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
 #define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
 #define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
 
 /* SWFW_SYNC Definitions */
-#define E1000_SWFW_EEP_SM   0x1
-#define E1000_SWFW_PHY0_SM  0x2
-#define E1000_SWFW_PHY1_SM  0x4
-#define E1000_SWFW_CSR_SM   0x8
+#define E1000_SWFW_EEP_SM   0x01
+#define E1000_SWFW_PHY0_SM  0x02
+#define E1000_SWFW_PHY1_SM  0x04
+#define E1000_SWFW_CSR_SM   0x08
+#define E1000_SWFW_PHY2_SM  0x20
+#define E1000_SWFW_PHY3_SM  0x40
 
 /* FACTPS Definitions */
 #define E1000_FACTPS_LFS    0x40000000  /* LAN Function Select */
 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 #define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
 #define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
-#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
+#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 #define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
 #define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
                                                * PHYRST_N pin */
 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
                                            * LINK_0 and LINK_1 pins */
+#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
+#define E1000_CTRL_LANPHYPC_VALUE    0x00020000 /* SW value of LANPHYPC */
 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 #define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
 #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
-#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion by NVM */
+#define E1000_STATUS_LAN_INIT_DONE 0x00000200  /* Lan Init Completion by NVM */
 #define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
+#define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
 #define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state.
                                                  * Clear on write '0'. */
 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
 #define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
 
 /* Constants used to interpret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
-#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
-#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
+#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed 50-66 MHz */
+#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
+#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
 
 #define SPEED_10    10
 #define SPEED_100   100
 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
 
 /* LED Control */
+#define E1000_PHY_LED0_MODE_MASK          0x00000007
+#define E1000_PHY_LED0_IVRT               0x00000008
+#define E1000_PHY_LED0_BLINK              0x00000010
+#define E1000_PHY_LED0_MASK               0x0000001F
+
 #define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
 #define E1000_LEDCTL_LED0_MODE_SHIFT      0
 #define E1000_LEDCTL_LED0_BLINK_RATE      0x00000020
 #define E1000_COLD_SHIFT                12
 
 /* Default values for the transmit IPG register */
+#ifndef NO_82542_SUPPORT
 #define DEFAULT_82542_TIPG_IPGT        10
+#endif
 #define DEFAULT_82543_TIPG_IPGT_FIBER  9
 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
 
 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
 
+#ifndef NO_82542_SUPPORT
 #define DEFAULT_82542_TIPG_IPGR1 2
+#endif
 #define DEFAULT_82543_TIPG_IPGR1 8
 #define E1000_TIPG_IPGR1_SHIFT  10
 
+#ifndef NO_82542_SUPPORT
 #define DEFAULT_82542_TIPG_IPGR2 10
+#endif
 #define DEFAULT_82543_TIPG_IPGR2 6
 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
 #define E1000_TIPG_IPGR2_SHIFT  20
 /* Extended Configuration Control and Size */
 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
+#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
 #define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
+#define E1000_EXTCNF_CTRL_GATE_PHY_CFG           0x00000080
 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
 #define E1000_KABGTXD_BGSQLBIAS           0x00050000
 
 /* PBA constants */
-#define E1000_PBA_6K  0x0006   /* 6KB */
+#define E1000_PBA_6K  0x0006    /* 6KB */
 #define E1000_PBA_8K  0x0008    /* 8KB */
+#define E1000_PBA_10K 0x000A    /* 10KB */
 #define E1000_PBA_12K 0x000C    /* 12KB */
+#define E1000_PBA_14K 0x000E    /* 14KB */
 #define E1000_PBA_16K 0x0010    /* 16KB */
+#define E1000_PBA_18K 0x0012
 #define E1000_PBA_20K 0x0014
 #define E1000_PBA_22K 0x0016
 #define E1000_PBA_24K 0x0018
+#define E1000_PBA_26K 0x001A
 #define E1000_PBA_30K 0x001E
 #define E1000_PBA_32K 0x0020
 #define E1000_PBA_34K 0x0022
+#define E1000_PBA_35K 0x0023
 #define E1000_PBA_38K 0x0026
 #define E1000_PBA_40K 0x0028
 #define E1000_PBA_48K 0x0030    /* 48KB */
 #define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
 #define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
 
+#define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */
+
 /* Interrupt Cause Read */
 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
 #define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
 #define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
 #define E1000_ICR_MNG           0x00040000 /* Manageability event */
 #define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
+#define E1000_ICR_DRSTA         0x40000000 /* Device Reset Asserted */
 #define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver
                                             * should claim the interrupt */
 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
-#define E1000_ICR_HOST_ARB_PAR  0x00400000 /* host arb read buffer parity err */
+#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
 #define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
 #define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
 #define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
 #define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
+#define E1000_ICR_FER           0x00400000 /* Fatal Error */
 
-/* Extended Interrupt Cause Read */
-#define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
-#define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
-#define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
-#define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
-#define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
-#define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
-#define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
-#define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
-#define E1000_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
-#define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
-/* TCP Timer */
-#define E1000_TCPTIMER_KS       0x00000100 /* KickStart */
-#define E1000_TCPTIMER_COUNT_ENABLE       0x00000200 /* Count Enable */
-#define E1000_TCPTIMER_COUNT_FINISH       0x00000400 /* Count finish */
-#define E1000_TCPTIMER_LOOP     0x00000800 /* Loop */
+/* PBA ECC Register */
+#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
+#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
+#define E1000_PBA_ECC_CORR_EN      0x00000001 /* Enable ECC error correction */
+#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
+#define E1000_PBA_ECC_INT_EN     0x00000004 /* Enable ICR bit 5 on ECC error */
 
 /*
  * This defines the bits that are set in the Interrupt Mask
     E1000_IMS_LSC)
 
 /* Interrupt Mask Set */
-#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
+#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
 #define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
 #define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
 #define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
 #define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
 #define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_IMS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Asserted */
 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
                                                          * parity error */
 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
 #define E1000_IMS_TXQ0          E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
 #define E1000_IMS_TXQ1          E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
 #define E1000_IMS_OTHER         E1000_ICR_OTHER /* Other Interrupts */
-
-/* Extended Interrupt Mask Set */
-#define E1000_EIMS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EIMS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EIMS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EIMS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EIMS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EIMS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EIMS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EIMS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
+#define E1000_IMS_FER           E1000_ICR_FER /* Fatal Error */
 
 /* Interrupt Mask Clear */
-#define E1000_IMC_RXSEQ                E1000_ICR_RXSEQ /* rx sequence error */
+#define E1000_IMC_RXSEQ                E1000_ICR_RXSEQ /* rx sequence error */
 
 /* Interrupt Cause Set */
-#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
+#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
 #define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 #define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 #define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
 #define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
 #define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_ICS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Aserted */
 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
                                                          * parity error */
 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
 #define E1000_ICS_PHYINT    E1000_ICR_PHYINT
 #define E1000_ICS_EPRST     E1000_ICR_EPRST
 
-/* Extended Interrupt Cause Set */
-#define E1000_EICS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EICS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EICS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EICS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EICS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EICS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EICS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EICS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EICS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EICS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
-
 /* Transmit Descriptor Control */
 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
  */
 #define E1000_RAR_ENTRIES     15
 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
+#define E1000_RAL_MAC_ADDR_LEN 4
+#define E1000_RAH_MAC_ADDR_LEN 2
+#define E1000_RAH_POOL_MASK 0x03FC0000
+#define E1000_RAH_POOL_1 0x00040000
 
 /* Error Codes */
 #define E1000_SUCCESS      0
 #define E1000_BLK_PHY_RESET   12
 #define E1000_ERR_SWFW_SYNC 13
 #define E1000_NOT_IMPLEMENTED 14
+#define E1000_ERR_MBX      15
+#define E1000_ERR_INVALID_ARGUMENT  16
+#define E1000_ERR_NO_SPACE          17
+#define E1000_ERR_NVM_PBA_SECTION   18
 
 /* Loop limit on how long we wait for auto-negotiation to complete */
 #define FIBER_LINK_UP_LIMIT               50
 #define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
 #define E1000_RXCW_ANC        0x80000000        /* Auto-neg complete */
 
+#define E1000_TSYNCTXCTL_VALID    0x00000001 /* tx timestamp valid */
+#define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable tx timestampping */
+
+#define E1000_TSYNCRXCTL_VALID      0x00000001 /* rx timestamp valid */
+#define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* rx type mask */
+#define E1000_TSYNCRXCTL_TYPE_L2_V2       0x00
+#define E1000_TSYNCRXCTL_TYPE_L4_V1       0x02
+#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2    0x04
+#define E1000_TSYNCRXCTL_TYPE_ALL         0x08
+#define E1000_TSYNCRXCTL_TYPE_EVENT_V2    0x0A
+#define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable rx timestampping */
+
+#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF
+#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE       0x00
+#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE  0x01
+#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02
+#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
+#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
+
+#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK               0x00000F00
+#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE                 0x0000
+#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE            0x0100
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE       0x0200
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE      0x0300
+#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE             0x0800
+#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE           0x0900
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE  0x0A00
+#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE             0x0B00
+#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE           0x0C00
+#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE           0x0D00
+
+#define E1000_TIMINCA_16NS_SHIFT 24
+/* TUPLE Filtering Configuration */
+#define E1000_TTQF_DISABLE_MASK   0xF0008000     /* TTQF Disable Mask */
+#define E1000_TTQF_QUEUE_ENABLE   0x100          /* TTQF Queue Enable Bit */
+#define E1000_TTQF_PROTOCOL_MASK  0xFF           /* TTQF Protocol Mask */
+/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
+#define E1000_TTQF_PROTOCOL_TCP   0x0
+/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
+#define E1000_TTQF_PROTOCOL_UDP   0x1
+/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
+#define E1000_TTQF_PROTOCOL_SCTP  0x2
+#define E1000_TTQF_PROTOCOL_SHIFT 5              /* TTQF Protocol Shift */
+#define E1000_TTQF_QUEUE_SHIFT    16             /* TTQF Queue Shfit */
+#define E1000_TTQF_RX_QUEUE_MASK  0x70000        /* TTQF Queue Mask */
+#define E1000_TTQF_MASK_ENABLE    0x10000000     /* TTQF Mask Enable Bit */
+#define E1000_IMIR_CLEAR_MASK     0xF001FFFF     /* IMIR Reg Clear Mask */
+#define E1000_IMIR_PORT_BYPASS    0x20000        /* IMIR Port Bypass Bit */
+#define E1000_IMIR_PRIORITY_SHIFT 29             /* IMIR Priority Shift */
+#define E1000_IMIREXT_CLEAR_MASK  0x7FFFF        /* IMIREXT Reg Clear Mask */
+
+#define E1000_MDICNFG_EXT_MDIO    0x80000000      /* MDI ext/int destination */
+#define E1000_MDICNFG_COM_MDIO    0x40000000      /* MDI shared w/ lan 0 */
+#define E1000_MDICNFG_PHY_MASK    0x03E00000
+#define E1000_MDICNFG_PHY_SHIFT   21
+
 /* PCI Express Control */
 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
+#define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
+#define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
+#define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
+#define E1000_GCR_CAP_VER2              0x00040000
 
 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
                            E1000_GCR_RXDSCW_NO_SNOOP      | \
                                         /* 0=DTE device */
 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
                                         /* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
+#define CR_1000T_MS_ENABLE      0x1000 /* 1=Master/Slave manual config value */
                                         /* 0=Automatic Master/Slave config */
 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
 #define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
 
 /* 1000BASE-T Status Register */
 #define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
+#define SR_1000T_ASYM_PAUSE_DIR  0x0100 /* LP asymmetric pause direction bit */
 #define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
 #define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
 #define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
 
+#define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
+
 /* NVM Control */
 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
 #define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
 #define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
 #define E1000_EECD_SECVAL_SHIFT      22
+#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
 
 #define E1000_NVM_SWDPIN0   0x0001   /* SWDPIN 0 NVM Value */
 #define E1000_NVM_LED_LOGIC 0x0020   /* Led Logic Word */
-#define E1000_NVM_RW_REG_DATA   16   /* Offset to data in NVM read/write regs */
+#define E1000_NVM_RW_REG_DATA   16  /* Offset to data in NVM read/write regs */
 #define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
 #define E1000_NVM_RW_REG_START  1    /* Start operation */
 #define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
 #define NVM_ALT_MAC_ADDR_PTR       0x0037
 #define NVM_CHECKSUM_REG           0x003F
 
-#define E1000_NVM_CFG_DONE_PORT_0  0x40000 /* MNG config cycle done */
-#define E1000_NVM_CFG_DONE_PORT_1  0x80000 /* ...for second port */
+#define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
+#define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
+#define E1000_NVM_CFG_DONE_PORT_2  0x100000 /* ...for third port */
+#define E1000_NVM_CFG_DONE_PORT_3  0x200000 /* ...for fourth port */
+
+#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
+
+/* Mask bits for fields in Word 0x24 of the NVM */
+#define NVM_WORD24_COM_MDIO         0x0008 /* MDIO interface shared */
+#define NVM_WORD24_EXT_MDIO         0x0004 /* MDIO accesses routed external */
 
 /* Mask bits for fields in Word 0x0f of the NVM */
 #define NVM_WORD0F_PAUSE_MASK       0x3000
 /* Mask bits for fields in Word 0x1a of the NVM */
 #define NVM_WORD1A_ASPM_MASK  0x000C
 
+/* Mask bits for fields in Word 0x03 of the EEPROM */
+#define NVM_COMPAT_LOM    0x0800
+
+/* length of string needed to store PBA number */
+#define E1000_PBANUM_LENGTH             11
+
 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 #define NVM_SUM                    0xBABA
 
 #define NVM_MAC_ADDR_OFFSET        0
 #define NVM_PBA_OFFSET_0           8
 #define NVM_PBA_OFFSET_1           9
+#define NVM_PBA_PTR_GUARD          0xFAFA
 #define NVM_RESERVED_WORD          0xFFFF
 #define NVM_PHY_CLASS_A            0x8000
 #define NVM_SERDES_AMPLITUDE_MASK  0x000F
 #define PCIX_STATUS_REGISTER_HI      0xEA
 #define PCI_HEADER_TYPE_REGISTER     0x0E
 #define PCIE_LINK_STATUS             0x12
+#define PCIE_DEVICE_CONTROL2         0x28
 
 #define PCIX_COMMAND_MMRBC_MASK      0x000C
 #define PCIX_COMMAND_MMRBC_SHIFT     0x2
 #define PCI_HEADER_TYPE_MULTIFUNC    0x80
 #define PCIE_LINK_WIDTH_MASK         0x3F0
 #define PCIE_LINK_WIDTH_SHIFT        4
+#define PCIE_LINK_SPEED_MASK         0x0F
+#define PCIE_LINK_SPEED_2500         0x01
+#define PCIE_LINK_SPEED_5000         0x02
+#define PCIE_DEVICE_CONTROL2_16ms    0x0005
 
 #ifndef ETH_ADDR_LEN
 #define ETH_ADDR_LEN                 6
 #define IFE_C_E_PHY_ID       0x02A80310
 #define BME1000_E_PHY_ID     0x01410CB0
 #define BME1000_E_PHY_ID_R2  0x01410CB1
-#define IGP04E1000_E_PHY_ID  0x02A80391
+#define I82577_E_PHY_ID 0x01540050
+#define I82578_E_PHY_ID 0x004DD040
+#define I82579_E_PHY_ID    0x01540090
+#define I82580_I_PHY_ID      0x015403A0
 #define M88_VENDOR           0x0141
 
 /* M88E1000 Specific Registers */
 
 /* M88E1000 PHY Specific Control Register */
 #define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
+#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
 #define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
 /* 1=CLK125 low, 0=CLK125 toggling */
 #define M88E1000_PSCR_CLK125_DISABLE    0x0010
-#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
+#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000 /* MDI Crossover Mode bits 6:5 */
                                                /* Manual MDI configuration */
 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
 #define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
 #define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
 #define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Tx */
 
 /* M88E1000 PHY Specific Status Register */
 #define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
 #define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
 
+
 /* M88EC018 Rev 2 specific DownShift settings */
 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X    0x0000
 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X    0x0C00
 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X    0x0E00
 
+#define I82578_EPSCR_DOWNSHIFT_ENABLE          0x0020
+#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK    0x001C
+
 /* BME1000 PHY Specific Control Register */
 #define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
 
 #define E1000_MDIC_READY     0x10000000
 #define E1000_MDIC_INT_EN    0x20000000
 #define E1000_MDIC_ERROR     0x40000000
+#define E1000_MDIC_DEST      0x80000000
 
 /* SerDes Control */
 #define E1000_GEN_CTL_READY             0x80000000
 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
 #define E1000_GEN_POLL_TIMEOUT          640
 
-/* LinkSec register fields */
-#define E1000_LSECTXCAP_SUM_MASK        0x00FF0000
-#define E1000_LSECTXCAP_SUM_SHIFT       16
-#define E1000_LSECRXCAP_SUM_MASK        0x00FF0000
-#define E1000_LSECRXCAP_SUM_SHIFT       16
-
-#define E1000_LSECTXCTRL_EN_MASK        0x00000003
-#define E1000_LSECTXCTRL_DISABLE        0x0
-#define E1000_LSECTXCTRL_AUTH           0x1
-#define E1000_LSECTXCTRL_AUTH_ENCRYPT   0x2
-#define E1000_LSECTXCTRL_AISCI          0x00000020
-#define E1000_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
-#define E1000_LSECTXCTRL_RSV_MASK       0x000000D8
-
-#define E1000_LSECRXCTRL_EN_MASK        0x0000000C
-#define E1000_LSECRXCTRL_EN_SHIFT       2
-#define E1000_LSECRXCTRL_DISABLE        0x0
-#define E1000_LSECRXCTRL_CHECK          0x1
-#define E1000_LSECRXCTRL_STRICT         0x2
-#define E1000_LSECRXCTRL_DROP           0x3
-#define E1000_LSECRXCTRL_PLSH           0x00000040
-#define E1000_LSECRXCTRL_RP             0x00000080
-#define E1000_LSECRXCTRL_RSV_MASK       0xFFFFFF33
+
+/* DMA Coalescing register fields */
+#define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coalescing
+                                                    * Watchdog Timer */
+#define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coalescing Receive
+                                                    * Threshold */
+#define E1000_DMACR_DMACTHR_SHIFT       16
+#define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe
+                                                    * transactions */
+#define E1000_DMACR_DMAC_LX_SHIFT       28
+#define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */
+
+#define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coalescing Transmit
+                                                    * Threshold */
+
+#define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */
+
+#define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Receive Traffic Rate
+                                                    * Threshold */
+#define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rcv packet rate in
+                                                    * current window */
+
+#define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rcv Traffic
+                                                    * Current Cnt */
+
+#define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* Flow ctrl Rcv Threshold
+                                                    * High val */
+#define E1000_FCRTC_RTH_COAL_SHIFT      4
+#define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision based
+                                                      on DMA coal */
+
 
 #endif /* _E1000_DEFINES_H_ */
index decb99a..14daf0a 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 #ifndef _E1000_HW_H_
 #define _E1000_HW_H_
@@ -41,7 +41,9 @@
 
 struct e1000_hw;
 
+#ifndef NO_82542_SUPPORT
 #define E1000_DEV_ID_82542                    0x1000
+#endif
 #define E1000_DEV_ID_82543GC_FIBER            0x1001
 #define E1000_DEV_ID_82543GC_COPPER           0x1004
 #define E1000_DEV_ID_82544EI_COPPER           0x1008
@@ -95,10 +97,13 @@ struct e1000_hw;
 #define E1000_DEV_ID_82573E_IAMT              0x108C
 #define E1000_DEV_ID_82573L                   0x109A
 #define E1000_DEV_ID_82574L                   0x10D3
+#define E1000_DEV_ID_82574LA                  0x10F6
+#define E1000_DEV_ID_82583V                   0x150C
 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
+#define E1000_DEV_ID_ICH8_82567V_3            0x1501
 #define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
 #define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
 #define E1000_DEV_ID_ICH8_IGP_C               0x104B
@@ -118,16 +123,23 @@ struct e1000_hw;
 #define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
 #define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
 #define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
+#define E1000_DEV_ID_ICH10_HANKSVILLE         0xF0FE
 #define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
 #define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
-#define E1000_DEV_ID_82576                    0x10C9
-#define E1000_DEV_ID_82576_FIBER              0x10E6
-#define E1000_DEV_ID_82576_SERDES             0x10E7
-#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
-#define E1000_DEV_ID_82576_VF                 0x10CA
-#define E1000_DEV_ID_82575EB_COPPER           0x10A7
-#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
-#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
+#define E1000_DEV_ID_ICH10_D_BM_V             0x1525
+
+#define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
+#define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
+#define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
+#define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
+#define E1000_DEV_ID_PCH2_LV_LM               0x1502
+#define E1000_DEV_ID_PCH2_LV_V                0x1503
+#define E1000_DEV_ID_82580_COPPER             0x150E
+#define E1000_DEV_ID_82580_FIBER              0x150F
+#define E1000_DEV_ID_82580_SERDES             0x1510
+#define E1000_DEV_ID_82580_SGMII              0x1511
+#define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
+#define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
 #define E1000_REVISION_0 0
 #define E1000_REVISION_1 1
 #define E1000_REVISION_2 2
@@ -136,10 +148,19 @@ struct e1000_hw;
 
 #define E1000_FUNC_0     0
 #define E1000_FUNC_1     1
+#define E1000_FUNC_2     2
+#define E1000_FUNC_3     3
+
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
 
 enum e1000_mac_type {
        e1000_undefined = 0,
+#ifndef NO_82542_SUPPORT
        e1000_82542,
+#endif
        e1000_82543,
        e1000_82544,
        e1000_82540,
@@ -155,13 +176,13 @@ enum e1000_mac_type {
        e1000_82572,
        e1000_82573,
        e1000_82574,
+       e1000_82583,
        e1000_80003es2lan,
        e1000_ich8lan,
        e1000_ich9lan,
        e1000_ich10lan,
-       e1000_82575,
-       e1000_82576,
-       e1000_vfadapt,
+       e1000_pchlan,
+       e1000_pch2lan,
        e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 };
 
@@ -200,7 +221,10 @@ enum e1000_phy_type {
        e1000_phy_igp_3,
        e1000_phy_ife,
        e1000_phy_bm,
-       e1000_phy_vf,
+       e1000_phy_82578,
+       e1000_phy_82577,
+       e1000_phy_82579,
+       e1000_phy_82580,
 };
 
 enum e1000_bus_type {
@@ -280,6 +304,16 @@ enum e1000_smart_speed {
        e1000_smart_speed_off
 };
 
+enum e1000_serdes_link_state {
+       e1000_serdes_link_down = 0,
+       e1000_serdes_link_autoneg_progress,
+       e1000_serdes_link_autoneg_complete,
+       e1000_serdes_link_forced_up
+};
+
+#define __le16 u16
+#define __le32 u32
+#define __le64 u64
 /* Receive Descriptor */
 struct e1000_rx_desc {
        __le64 buffer_addr; /* Address of the descriptor's data buffer */
@@ -497,37 +531,6 @@ struct e1000_hw_stats {
        u64 doosync;
 };
 
-struct e1000_vf_stats {
-       u64 base_gprc;
-       u64 base_gptc;
-       u64 base_gorc;
-       u64 base_gotc;
-       u64 base_mprc;
-       u64 base_gotlbc;
-       u64 base_gptlbc;
-       u64 base_gorlbc;
-       u64 base_gprlbc;
-
-       u32 last_gprc;
-       u32 last_gptc;
-       u32 last_gorc;
-       u32 last_gotc;
-       u32 last_mprc;
-       u32 last_gotlbc;
-       u32 last_gptlbc;
-       u32 last_gorlbc;
-       u32 last_gprlbc;
-
-       u64 gprc;
-       u64 gptc;
-       u64 gorc;
-       u64 gotc;
-       u64 mprc;
-       u64 gotlbc;
-       u64 gptlbc;
-       u64 gorlbc;
-       u64 gprlbc;
-};
 
 struct e1000_phy_stats {
        u32 idle_errors;
@@ -582,6 +585,7 @@ struct e1000_host_mng_command_info {
 struct e1000_mac_operations {
        /* Function pointers for the MAC. */
        s32  (*init_params)(struct e1000_hw *);
+       s32  (*id_led_init)(struct e1000_hw *);
        s32  (*blink_led)(struct e1000_hw *);
        s32  (*check_for_link)(struct e1000_hw *);
        bool (*check_mng_mode)(struct e1000_hw *hw);
@@ -593,15 +597,13 @@ struct e1000_mac_operations {
        s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
        s32  (*led_on)(struct e1000_hw *);
        s32  (*led_off)(struct e1000_hw *);
-       void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
+       void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
        s32  (*reset_hw)(struct e1000_hw *);
        s32  (*init_hw)(struct e1000_hw *);
-       void (*shutdown_serdes)(struct e1000_hw *);
        s32  (*setup_link)(struct e1000_hw *);
        s32  (*setup_physical_interface)(struct e1000_hw *);
        s32  (*setup_led)(struct e1000_hw *);
        void (*write_vfta)(struct e1000_hw *, u32, u32);
-       void (*mta_set)(struct e1000_hw *, u32);
        void (*config_collision_dist)(struct e1000_hw *);
        void (*rar_set)(struct e1000_hw *, u8*, u32);
        s32  (*read_mac_addr)(struct e1000_hw *);
@@ -625,11 +627,13 @@ struct e1000_phy_operations {
        s32  (*get_cable_length)(struct e1000_hw *);
        s32  (*get_info)(struct e1000_hw *);
        s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
+       s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
        void (*release)(struct e1000_hw *);
        s32  (*reset)(struct e1000_hw *);
        s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
        s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
        s32  (*write_reg)(struct e1000_hw *, u32, u16);
+       s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
        void (*power_up)(struct e1000_hw *);
        void (*power_down)(struct e1000_hw *);
 };
@@ -667,18 +671,26 @@ struct e1000_mac_info {
        u16 ifs_ratio;
        u16 ifs_step_size;
        u16 mta_reg_count;
+
+       /* Maximum size of the MTA register table in all supported adapters */
+       #define MAX_MTA_REG 128
+       u32 mta_shadow[MAX_MTA_REG];
        u16 rar_entry_count;
 
        u8  forced_speed_duplex;
 
        bool adaptive_ifs;
+       bool has_fwsm;
        bool arc_subsystem_valid;
        bool asf_firmware_present;
        bool autoneg;
        bool autoneg_failed;
        bool get_link_status;
        bool in_ifs_mode;
+#ifndef NO_82542_SUPPORT
        bool report_tx_early;
+#endif
+       enum e1000_serdes_link_state serdes_link_state;
        bool serdes_has_link;
        bool tx_pkt_filtering;
 };
@@ -745,6 +757,7 @@ struct e1000_fc_info {
        u32 high_water;          /* Flow control high-water mark */
        u32 low_water;           /* Flow control low-water mark */
        u16 pause_time;          /* Flow control pause timer */
+       u16 refresh_time;        /* Flow control refresh timer */
        bool send_xon;           /* Flow control send XON */
        bool strict_ieee;        /* Strict IEEE mode */
        enum e1000_fc_mode current_mode; /* FC mode in effect */
@@ -758,10 +771,12 @@ struct e1000_dev_spec_82541 {
        bool phy_init_script;
 };
 
+#ifndef NO_82542_SUPPORT
 struct e1000_dev_spec_82542 {
        bool dma_fairness;
 };
 
+#endif /* NO_82542_SUPPORT */
 struct e1000_dev_spec_82543 {
        u32  tbi_compatibility;
        bool dma_fairness;
@@ -770,6 +785,11 @@ struct e1000_dev_spec_82543 {
 
 struct e1000_dev_spec_82571 {
        bool laa_is_present;
+       u32 smb_counter;
+};
+
+struct e1000_dev_spec_80003es2lan {
+       bool  mdic_wa_enable;
 };
 
 struct e1000_shadow_ram {
@@ -782,14 +802,8 @@ struct e1000_shadow_ram {
 struct e1000_dev_spec_ich8lan {
        bool kmrn_lock_loss_workaround_enabled;
        struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
-};
-
-struct e1000_dev_spec_82575 {
-       bool sgmii_active;
-};
-
-struct e1000_dev_spec_vf {
-       u32     vf_number;
+       bool nvm_k1_enabled;
+       bool eee_disable;
 };
 
 struct e1000_hw {
@@ -808,12 +822,13 @@ struct e1000_hw {
 
        union {
                struct e1000_dev_spec_82541     _82541;
+#ifndef NO_82542_SUPPORT
                struct e1000_dev_spec_82542     _82542;
+#endif
                struct e1000_dev_spec_82543     _82543;
                struct e1000_dev_spec_82571     _82571;
+               struct e1000_dev_spec_80003es2lan _80003es2lan;
                struct e1000_dev_spec_ich8lan   ich8lan;
-               struct e1000_dev_spec_82575     _82575;
-               struct e1000_dev_spec_vf        vf;
        } dev_spec;
 
        u16 device_id;
@@ -829,11 +844,12 @@ struct e1000_hw {
 #include "e1000_82571.h"
 #include "e1000_80003es2lan.h"
 #include "e1000_ich8lan.h"
-#include "e1000_82575.h"
 
 /* These functions must be implemented by drivers */
+#ifndef NO_82542_SUPPORT
 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 void e1000_pci_set_mwi(struct e1000_hw *hw);
+#endif
 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
index f368998..bf10e0d 100644 (file)
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2008, Intel Corporation 
+  Copyright (c) 2001-2009, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD$*/
 
 /*
  * 82562G 10/100 Network Connection
  * 82567LF-3 Gigabit Network Connection
  * 82567LM-3 Gigabit Network Connection
  * 82567LM-4 Gigabit Network Connection
+ * 82577LM Gigabit Network Connection
+ * 82577LC Gigabit Network Connection
+ * 82578DM Gigabit Network Connection
+ * 82578DC Gigabit Network Connection
+ * 82579LM Gigabit Network Connection
+ * 82579V Gigabit Network Connection
  */
 
 #include "e1000_api.h"
 
 static s32  e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
+static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
 static s32  e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
 static s32  e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
 static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
+static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
+static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
-static s32  e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
+static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
+static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
-static s32  e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
-static s32  e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
+static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
                                             bool active);
 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
@@ -81,6 +90,7 @@ static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
                                             u16 *data);
+static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
@@ -91,11 +101,15 @@ static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
+static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
+static s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
+static s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
+static s32  e1000_led_on_pchlan(struct e1000_hw *hw);
+static s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 static s32  e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
 static s32  e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
-static s32  e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
@@ -112,6 +126,12 @@ static s32  e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
                                            u8 size, u16 data);
 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
+static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
+static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
+static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
+static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
+static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
+static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 
 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 /* Offset 04h HSFSTS */
@@ -155,6 +175,130 @@ union ich8_hws_flash_regacc {
 };
 
 /**
+ *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Initialize family-specific PHY parameters and function pointers.
+ **/
+static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 ctrl, fwsm;
+       s32 ret_val = E1000_SUCCESS;
+
+       DEBUGFUNC("e1000_init_phy_params_pchlan");
+
+       phy->addr                     = 1;
+       phy->reset_delay_us           = 100;
+
+       phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
+       phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
+       phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
+       phy->ops.read_reg             = e1000_read_phy_reg_hv;
+       phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
+       phy->ops.release              = e1000_release_swflag_ich8lan;
+       phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
+       phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
+       phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
+       phy->ops.write_reg            = e1000_write_phy_reg_hv;
+       phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
+       phy->ops.power_up             = e1000_power_up_phy_copper;
+       phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
+       phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+       /*
+        * The MAC-PHY interconnect may still be in SMBus mode
+        * after Sx->S0.  If the manageability engine (ME) is
+        * disabled, then toggle the LANPHYPC Value bit to force
+        * the interconnect to PCIe mode.
+        */
+       fwsm = E1000_READ_REG(hw, E1000_FWSM);
+       if (!(fwsm & E1000_ICH_FWSM_FW_VALID) &&
+           !(hw->phy.ops.check_reset_block(hw))) {
+               ctrl = E1000_READ_REG(hw, E1000_CTRL);
+               ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
+               ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
+               E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+               usec_delay(10);
+               ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
+               E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+               msec_delay(50);
+
+               /*
+                * Gate automatic PHY configuration by hardware on
+                * non-managed 82579
+                */
+               if (hw->mac.type == e1000_pch2lan)
+                       e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
+       }
+
+       /*
+        * Reset the PHY before any acccess to it.  Doing so, ensures that
+        * the PHY is in a known good state before we read/write PHY registers.
+        * The generic reset is sufficient here, because we haven't determined
+        * the PHY type yet.
+        */
+       ret_val = e1000_phy_hw_reset_generic(hw);
+       if (ret_val)
+               goto out;
+
+       /* Ungate automatic PHY configuration on non-managed 82579 */
+       if ((hw->mac.type == e1000_pch2lan)  &&
+           !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
+               msec_delay(10);
+               e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
+       }
+
+       phy->id = e1000_phy_unknown;
+       switch (hw->mac.type) {
+       default:
+               ret_val = e1000_get_phy_id(hw);
+               if (ret_val)
+                       goto out;
+               if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
+                       break;
+               /* fall-through */
+       case e1000_pch2lan:
+               /*
+                * In case the PHY needs to be in mdio slow mode,
+                * set slow mode and try to get the PHY id again.
+                */
+               ret_val = e1000_set_mdio_slow_mode_hv(hw);
+               if (ret_val)
+                       goto out;
+               ret_val = e1000_get_phy_id(hw);
+               if (ret_val)
+                       goto out;
+               break;
+       }
+       phy->type = e1000_get_phy_type_from_id(phy->id);
+
+       switch (phy->type) {
+       case e1000_phy_82577:
+       case e1000_phy_82579:
+               phy->ops.check_polarity = e1000_check_polarity_82577;
+               phy->ops.force_speed_duplex =
+                       e1000_phy_force_speed_duplex_82577;
+               phy->ops.get_cable_length = e1000_get_cable_length_82577;
+               phy->ops.get_info = e1000_get_phy_info_82577;
+               phy->ops.commit = e1000_phy_sw_reset_generic;
+               break;
+       case e1000_phy_82578:
+               phy->ops.check_polarity = e1000_check_polarity_m88;
+               phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
+               phy->ops.get_cable_length = e1000_get_cable_length_m88;
+               phy->ops.get_info = e1000_get_phy_info_m88;
+               break;
+       default:
+               ret_val = -E1000_ERR_PHY;
+               break;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
  *  @hw: pointer to the HW structure
  *
@@ -172,12 +316,9 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
        phy->reset_delay_us           = 100;
 
        phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
-       phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
        phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
-       phy->ops.force_speed_duplex   = e1000_phy_force_speed_duplex_ich8lan;
        phy->ops.get_cable_length     = e1000_get_cable_length_igp_2;
        phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
-       phy->ops.get_info             = e1000_get_phy_info_ich8lan;
        phy->ops.read_reg             = e1000_read_phy_reg_igp;
        phy->ops.release              = e1000_release_swflag_ich8lan;
        phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
@@ -197,7 +338,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
                phy->ops.read_reg  = e1000_read_phy_reg_bm;
                ret_val = e1000_determine_phy_address(hw);
                if (ret_val) {
-                       DEBUGOUT("Cannot determine PHY address. Erroring out\n");
+                       DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
                        goto out;
                }
        }
@@ -216,12 +357,20 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
        case IGP03E1000_E_PHY_ID:
                phy->type = e1000_phy_igp_3;
                phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+               phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
+               phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
+               phy->ops.get_info = e1000_get_phy_info_igp;
+               phy->ops.check_polarity = e1000_check_polarity_igp;
+               phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
                break;
        case IFE_E_PHY_ID:
        case IFE_PLUS_E_PHY_ID:
        case IFE_C_E_PHY_ID:
                phy->type = e1000_phy_ife;
                phy->autoneg_mask = E1000_ALL_NOT_GIG;
+               phy->ops.get_info = e1000_get_phy_info_ife;
+               phy->ops.check_polarity = e1000_check_polarity_ife;
+               phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
                break;
        case BME1000_E_PHY_ID:
                phy->type = e1000_phy_bm;
@@ -229,6 +378,9 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
                phy->ops.read_reg = e1000_read_phy_reg_bm;
                phy->ops.write_reg = e1000_write_phy_reg_bm;
                phy->ops.commit = e1000_phy_sw_reset_generic;
+               phy->ops.get_info = e1000_get_phy_info_m88;
+               phy->ops.check_polarity = e1000_check_polarity_m88;
+               phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
                break;
        default:
                ret_val = -E1000_ERR_PHY;
@@ -297,9 +449,9 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
        }
 
        /* Function Pointers */
-       nvm->ops.acquire       = e1000_acquire_swflag_ich8lan;
+       nvm->ops.acquire       = e1000_acquire_nvm_ich8lan;
+       nvm->ops.release       = e1000_release_nvm_ich8lan;
        nvm->ops.read          = e1000_read_nvm_ich8lan;
-       nvm->ops.release       = e1000_release_swflag_ich8lan;
        nvm->ops.update        = e1000_update_nvm_checksum_ich8lan;
        nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
        nvm->ops.validate      = e1000_validate_nvm_checksum_ich8lan;
@@ -319,6 +471,7 @@ out:
 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 {
        struct e1000_mac_info *mac = &hw->mac;
+       u16 pci_cfg;
 
        DEBUGFUNC("e1000_init_mac_params_ich8lan");
 
@@ -333,8 +486,12 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
                mac->rar_entry_count--;
        /* Set if part includes ASF firmware */
        mac->asf_firmware_present = TRUE;
-       /* Set if manageability features are enabled. */
-       mac->arc_subsystem_valid = TRUE;
+       /* FWSM register */
+       mac->has_fwsm = TRUE;
+       /* ARC subsystem not supported */
+       mac->arc_subsystem_valid = FALSE;
+       /* Adaptive IFS supported */
+       mac->adaptive_ifs = TRUE;
 
        /* Function pointers */
 
@@ -351,36 +508,201 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
        /* physical interface setup */
        mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
        /* check for link */
-       mac->ops.check_for_link = e1000_check_for_copper_link_generic;
-       /* check management mode */
-       mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
+       mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
        /* link info */
        mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
        /* multicast address update */
        mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
-       /* setting MTA */
-       mac->ops.mta_set = e1000_mta_set_generic;
-       /* blink LED */
-       mac->ops.blink_led = e1000_blink_led_generic;
-       /* setup LED */
-       mac->ops.setup_led = e1000_setup_led_generic;
-       /* cleanup LED */
-       mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
-       /* turn on/off LED */
-       mac->ops.led_on = e1000_led_on_ich8lan;
-       mac->ops.led_off = e1000_led_off_ich8lan;
        /* clear hardware counters */
        mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 
+       /* LED operations */
+       switch (mac->type) {
+       case e1000_ich8lan:
+       case e1000_ich9lan:
+       case e1000_ich10lan:
+               /* check management mode */
+               mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
+               /* ID LED init */
+               mac->ops.id_led_init = e1000_id_led_init_generic;
+               /* blink LED */
+               mac->ops.blink_led = e1000_blink_led_generic;
+               /* setup LED */
+               mac->ops.setup_led = e1000_setup_led_generic;
+               /* cleanup LED */
+               mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
+               /* turn on/off LED */
+               mac->ops.led_on = e1000_led_on_ich8lan;
+               mac->ops.led_off = e1000_led_off_ich8lan;
+               break;
+       case e1000_pch2lan:
+               mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
+               mac->ops.rar_set = e1000_rar_set_pch2lan;
+               /* fall-through */
+       case e1000_pchlan:
+               /* save PCH revision_id */
+               e1000_read_pci_cfg(hw, 0x2, &pci_cfg);
+               hw->revision_id = (u8)(pci_cfg &= 0x000F);
+               /* check management mode */
+               mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
+               /* ID LED init */
+               mac->ops.id_led_init = e1000_id_led_init_pchlan;
+               /* setup LED */
+               mac->ops.setup_led = e1000_setup_led_pchlan;
+               /* cleanup LED */
+               mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
+               /* turn on/off LED */
+               mac->ops.led_on = e1000_led_on_pchlan;
+               mac->ops.led_off = e1000_led_off_pchlan;
+               break;
+       default:
+               break;
+       }
+
        /* Enable PCS Lock-loss workaround for ICH8 */
        if (mac->type == e1000_ich8lan)
                e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
 
+       /* Gate automatic PHY configuration by hardware on managed 82579 */
+       if ((mac->type == e1000_pch2lan) &&
+           (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
+               e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
 
        return E1000_SUCCESS;
 }
 
 /**
+ *  e1000_set_eee_pchlan - Enable/disable EEE support
+ *  @hw: pointer to the HW structure
+ *
+ *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
+ *  the LPI Control register will remain set only if/when link is up.
+ **/
+static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 phy_reg;
+
+       DEBUGFUNC("e1000_set_eee_pchlan");
+
+       if (hw->phy.type != e1000_phy_82579)
+               goto out;
+
+       ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
+       if (ret_val)
+               goto out;
+
+       if (hw->dev_spec.ich8lan.eee_disable)
+               phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
+       else
+               phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
+
+       ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
+ *  @hw: pointer to the HW structure
+ *
+ *  Checks to see of the link status of the hardware has changed.  If a
+ *  change in link status has been detected, then we read the PHY registers
+ *  to get the current speed/duplex if link exists.
+ **/
+static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_mac_info *mac = &hw->mac;
+       s32 ret_val;
+       bool link;
+
+       DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
+
+       /*
+        * We only want to go out to the PHY registers to see if Auto-Neg
+        * has completed and/or if our link status has changed.  The
+        * get_link_status flag is set upon receiving a Link Status
+        * Change or Rx Sequence Error interrupt.
+        */
+       if (!mac->get_link_status) {
+               ret_val = E1000_SUCCESS;
+               goto out;
+       }
+
+       /*
+        * First we want to see if the MII Status Register reports
+        * link.  If so, then we want to get the current speed/duplex
+        * of the PHY.
+        */
+       ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
+       if (ret_val)
+               goto out;
+
+       if (hw->mac.type == e1000_pchlan) {
+               ret_val = e1000_k1_gig_workaround_hv(hw, link);
+               if (ret_val)
+                       goto out;
+       }
+
+       if (!link)
+               goto out; /* No link detected */
+
+       mac->get_link_status = FALSE;
+
+       if (hw->phy.type == e1000_phy_82578) {
+               ret_val = e1000_link_stall_workaround_hv(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       if (hw->mac.type == e1000_pch2lan) {
+               ret_val = e1000_k1_workaround_lv(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       /*
+        * Check if there was DownShift, must be checked
+        * immediately after link-up
+        */
+       e1000_check_downshift_generic(hw);
+
+       /* Enable/Disable EEE after link up */
+       ret_val = e1000_set_eee_pchlan(hw);
+       if (ret_val)
+               goto out;
+
+       /*
+        * If we are forcing speed/duplex, then we simply return since
+        * we have already determined whether we have link or not.
+        */
+       if (!mac->autoneg) {
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+       }
+
+       /*
+        * Auto-Neg is enabled.  Auto Speed Detection takes care
+        * of MAC speed/duplex configuration.  So we only need to
+        * configure Collision Distance in the MAC.
+        */
+       e1000_config_collision_dist_generic(hw);
+
+       /*
+        * Configure Flow Control now that Auto-Neg has completed.
+        * First, we need to restore the desired flow control
+        * settings because we may have had to re-autoneg with a
+        * different link partner.
+        */
+       ret_val = e1000_config_fc_after_link_up_generic(hw);
+       if (ret_val)
+               DEBUGOUT("Error configuring flow control\n");
+
+out:
+       return ret_val;
+}
+
+/**
  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
  *  @hw: pointer to the HW structure
  *
@@ -392,16 +714,51 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
 
        hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
        hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
-       hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
+       switch (hw->mac.type) {
+       case e1000_ich8lan:
+       case e1000_ich9lan:
+       case e1000_ich10lan:
+               hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
+               break;
+       case e1000_pchlan:
+       case e1000_pch2lan:
+               hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
+               break;
+       default:
+               break;
+       }
+}
+
+/**
+ *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquires the mutex for performing NVM operations.
+ **/
+static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
+{
+       DEBUGFUNC("e1000_acquire_nvm_ich8lan");
+       return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_release_nvm_ich8lan - Release NVM mutex
+ *  @hw: pointer to the HW structure
+ *
+ *  Releases the mutex used while performing NVM operations.
+ **/
+static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
+{
+       DEBUGFUNC("e1000_release_nvm_ich8lan");
+       return;
 }
 
 /**
  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
  *  @hw: pointer to the HW structure
  *
- *  Acquires the software control flag for performing NVM and PHY
- *  operations.  This is a function pointer entry point only called by
- *  read/write routines for the PHY and NVM parts.
+ *  Acquires the software control flag for performing PHY and select
+ *  MAC CSR accesses.
  **/
 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 {
@@ -412,18 +769,35 @@ static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 
        while (timeout) {
                extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
-               extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
-               E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
+               if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
+                       break;
+
+               msec_delay_irq(1);
+               timeout--;
+       }
+
+       if (!timeout) {
+               DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
+               ret_val = -E1000_ERR_CONFIG;
+               goto out;
+       }
+
+       timeout = SW_FLAG_TIMEOUT;
 
+       extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
+       E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
+
+       while (timeout) {
                extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
                if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
                        break;
+
                msec_delay_irq(1);
                timeout--;
        }
 
        if (!timeout) {
-               DEBUGOUT("FW or HW has locked the resource for too long.\n");
+               DEBUGOUT("Failed to acquire the semaphore.\n");
                extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
                E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
                ret_val = -E1000_ERR_CONFIG;
@@ -438,9 +812,8 @@ out:
  *  e1000_release_swflag_ich8lan - Release software control flag
  *  @hw: pointer to the HW structure
  *
- *  Releases the software control flag for performing NVM and PHY operations.
- *  This is a function pointer entry point only called by read/write
- *  routines for the PHY and NVM parts.
+ *  Releases the software control flag for performing PHY and select
+ *  MAC CSR accesses.
  **/
 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 {
@@ -459,7 +832,7 @@ static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
  *  e1000_check_mng_mode_ich8lan - Checks management mode
  *  @hw: pointer to the HW structure
  *
- *  This checks if the adapter has manageability enabled.
+ *  This checks if the adapter has any manageability enabled.
  *  This is a function pointer entry point only called by read/write
  *  routines for the PHY and NVM parts.
  **/
@@ -471,336 +844,1129 @@ static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 
        fwsm = E1000_READ_REG(hw, E1000_FWSM);
 
-       return (fwsm & E1000_FWSM_MODE_MASK) ==
-               (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
+       return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
+              ((fwsm & E1000_FWSM_MODE_MASK) ==
+               (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 }
 
 /**
- *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
+ *  e1000_check_mng_mode_pchlan - Checks management mode
  *  @hw: pointer to the HW structure
  *
- *  Checks if firmware is blocking the reset of the PHY.
- *  This is a function pointer entry point only called by
- *  reset routines.
+ *  This checks if the adapter has iAMT enabled.
+ *  This is a function pointer entry point only called by read/write
+ *  routines for the PHY and NVM parts.
  **/
-static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
+static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 {
        u32 fwsm;
 
-       DEBUGFUNC("e1000_check_reset_block_ich8lan");
+       DEBUGFUNC("e1000_check_mng_mode_pchlan");
 
        fwsm = E1000_READ_REG(hw, E1000_FWSM);
 
-       return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
-                                               : E1000_BLK_PHY_RESET;
+       return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
+              (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 }
 
 /**
- *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
+ *  e1000_rar_set_pch2lan - Set receive address register
  *  @hw: pointer to the HW structure
+ *  @addr: pointer to the receive address
+ *  @index: receive address array register
  *
- *  Forces the speed and duplex settings of the PHY.
- *  This is a function pointer entry point only called by
- *  PHY setup routines.
+ *  Sets the receive address array register at index to the address passed
+ *  in by addr.  For 82579, RAR[0] is the base address register that is to
+ *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
+ *  Use SHRA[0-3] in place of those reserved for ME.
  **/
-static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
+static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
 {
-       struct e1000_phy_info *phy = &hw->phy;
-       s32 ret_val;
-       u16 data;
-       bool link;
+       u32 rar_low, rar_high;
 
-       DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
-
-       if (phy->type != e1000_phy_ife) {
-               ret_val = e1000_phy_force_speed_duplex_igp(hw);
-               goto out;
-       }
+       DEBUGFUNC("e1000_rar_set_pch2lan");
 
-       ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
-       if (ret_val)
-               goto out;
+       /*
+        * HW expects these in little endian so we reverse the byte order
+        * from network order (big endian) to little endian
+        */
+       rar_low = ((u32) addr[0] |
+                  ((u32) addr[1] << 8) |
+                  ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 
-       e1000_phy_force_speed_duplex_setup(hw, &data);
+       rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 
-       ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
-       if (ret_val)
-               goto out;
+       /* If MAC address zero, no need to set the AV bit */
+       if (rar_low || rar_high)
+               rar_high |= E1000_RAH_AV;
 
-       /* Disable MDI-X support for 10/100 */
-       ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
-       if (ret_val)
-               goto out;
+       if (index == 0) {
+               E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
+               E1000_WRITE_FLUSH(hw);
+               E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
+               E1000_WRITE_FLUSH(hw);
+               return;
+       }
 
-       data &= ~IFE_PMC_AUTO_MDIX;
-       data &= ~IFE_PMC_FORCE_MDIX;
+       if (index < hw->mac.rar_entry_count) {
+               E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
+               E1000_WRITE_FLUSH(hw);
+               E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
+               E1000_WRITE_FLUSH(hw);
 
-       ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
-       if (ret_val)
-               goto out;
+               /* verify the register updates */
+               if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
+                   (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
+                       return;
 
-       DEBUGOUT1("IFE PMC: %X\n", data);
+               DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
+                        (index - 1), E1000_READ_REG(hw, E1000_FWSM));
+       }
 
-       usec_delay(1);
+       DEBUGOUT1("Failed to write receive address at index %d\n", index);
+}
 
-       if (phy->autoneg_wait_to_complete) {
-               DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
+/**
+ *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
+ *  @hw: pointer to the HW structure
+ *
+ *  Checks if firmware is blocking the reset of the PHY.
+ *  This is a function pointer entry point only called by
+ *  reset routines.
+ **/
+static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
+{
+       u32 fwsm;
 
-               ret_val = e1000_phy_has_link_generic(hw,
-                                                    PHY_FORCE_LIMIT,
-                                                    100000,
-                                                    &link);
-               if (ret_val)
-                       goto out;
+       DEBUGFUNC("e1000_check_reset_block_ich8lan");
 
-               if (!link)
-                       DEBUGOUT("Link taking longer than expected.\n");
+       if (hw->phy.reset_disable)
+               return E1000_BLK_PHY_RESET;
 
-               /* Try once more */
-               ret_val = e1000_phy_has_link_generic(hw,
-                                                    PHY_FORCE_LIMIT,
-                                                    100000,
-                                                    &link);
-               if (ret_val)
-                       goto out;
-       }
+       fwsm = E1000_READ_REG(hw, E1000_FWSM);
 
-out:
-       return ret_val;
+       return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
+                                               : E1000_BLK_PHY_RESET;
 }
 
 /**
- *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
+ *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
  *  @hw: pointer to the HW structure
  *
- *  Resets the PHY
- *  This is a function pointer entry point called by drivers
- *  or other shared routines.
+ *  Assumes semaphore already acquired.
+ *
  **/
-static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
+static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 {
-       struct e1000_phy_info *phy = &hw->phy;
-       u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
-       s32 ret_val;
-       u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
-       u16 word_addr, reg_data, reg_addr, phy_page = 0;
+       u16 phy_data;
+       u32 strap = E1000_READ_REG(hw, E1000_STRAP);
+       s32 ret_val = E1000_SUCCESS;
 
-       DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
+       strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 
-       ret_val = e1000_phy_hw_reset_generic(hw);
+       ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
        if (ret_val)
                goto out;
 
-       /*
-        * Initialize the PHY from the NVM on ICH platforms.  This
+       phy_data &= ~HV_SMB_ADDR_MASK;
+       phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
+       phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
+       ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
+ *  @hw:   pointer to the HW structure
+ *
+ *  SW should configure the LCD from the NVM extended configuration region
+ *  as a workaround for certain parts.
+ **/
+static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
+{
+       struct e1000_phy_info *phy = &hw->phy;
+       u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
+       s32 ret_val = E1000_SUCCESS;
+       u16 word_addr, reg_data, reg_addr, phy_page = 0;
+
+       DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
+
+       /*
+        * Initialize the PHY from the NVM on ICH platforms.  This
         * is needed due to an issue where the NVM configuration is
         * not properly autoloaded after power transitions.
         * Therefore, after each PHY reset, we will load the
         * configuration data out of the NVM manually.
         */
-       if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
-               /* Check if SW needs configure the PHY */
-               if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
-                   (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
-                       sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
-               else
+       switch (hw->mac.type) {
+       case e1000_ich8lan:
+               if (phy->type != e1000_phy_igp_3)
+                       return ret_val;
+
+               if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
+                   (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
                        sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
+                       break;
+               }
+               /* Fall-thru */
+       case e1000_pchlan:
+       case e1000_pch2lan:
+               sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
+               break;
+       default:
+               return ret_val;
+       }
 
-               data = E1000_READ_REG(hw, E1000_FEXTNVM);
-               if (!(data & sw_cfg_mask))
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               return ret_val;
+
+       data = E1000_READ_REG(hw, E1000_FEXTNVM);
+       if (!(data & sw_cfg_mask))
+               goto out;
+
+       /*
+        * Make sure HW does not configure LCD from PHY
+        * extended configuration before SW configuration
+        */
+       data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
+       if (!(hw->mac.type == e1000_pch2lan)) {
+               if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
                        goto out;
+       }
 
-               /* Wait for basic configuration completes before proceeding*/
-               do {
-                       data = E1000_READ_REG(hw, E1000_STATUS);
-                       data &= E1000_STATUS_LAN_INIT_DONE;
-                       usec_delay(100);
-               } while ((!data) && --loop);
+       cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
+       cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
+       cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
+       if (!cnf_size)
+               goto out;
 
+       cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
+       cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
+
+       if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
+           (hw->mac.type == e1000_pchlan)) ||
+            (hw->mac.type == e1000_pch2lan)) {
                /*
-                * If basic configuration is incomplete before the above loop
-                * count reaches 0, loading the configuration from NVM will
-                * leave the PHY in a bad state possibly resulting in no link.
+                * HW configures the SMBus address and LEDs when the
+                * OEM and LCD Write Enable bits are set in the NVM.
+                * When both NVM bits are cleared, SW will configure
+                * them instead.
                 */
-               if (loop == 0)
-                       DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
+               ret_val = e1000_write_smbus_addr(hw);
+               if (ret_val)
+                       goto out;
 
-               /* Clear the Init Done bit for the next init event */
-               data = E1000_READ_REG(hw, E1000_STATUS);
-               data &= ~E1000_STATUS_LAN_INIT_DONE;
-               E1000_WRITE_REG(hw, E1000_STATUS, data);
+               data = E1000_READ_REG(hw, E1000_LEDCTL);
+               ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
+                                                       (u16)data);
+               if (ret_val)
+                       goto out;
+       }
 
-               /*
-                * Make sure HW does not configure LCD from PHY
-                * extended configuration before SW configuration
-                */
-               data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
-               if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
+       /* Configure LCD from extended configuration region. */
+
+       /* cnf_base_addr is in DWORD */
+       word_addr = (u16)(cnf_base_addr << 1);
+
+       for (i = 0; i < cnf_size; i++) {
+               ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
+                                          &reg_data);
+               if (ret_val)
                        goto out;
 
-               cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
-               cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
-               cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
-               if (!cnf_size)
+               ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
+                                          1, &reg_addr);
+               if (ret_val)
+                       goto out;
+
+               /* Save off the PHY page for future writes. */
+               if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
+                       phy_page = reg_data;
+                       continue;
+               }
+
+               reg_addr &= PHY_REG_MASK;
+               reg_addr |= phy_page;
+
+               ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
+                                                   reg_data);
+               if (ret_val)
                        goto out;
+       }
 
-               cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
-               cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
+out:
+       hw->phy.ops.release(hw);
+       return ret_val;
+}
 
-               /* Configure LCD from extended configuration region. */
+/**
+ *  e1000_k1_gig_workaround_hv - K1 Si workaround
+ *  @hw:   pointer to the HW structure
+ *  @link: link up bool flag
+ *
+ *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
+ *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
+ *  If link is down, the function will restore the default K1 setting located
+ *  in the NVM.
+ **/
+static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 status_reg = 0;
+       bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
 
-               /* cnf_base_addr is in DWORD */
-               word_addr = (u16)(cnf_base_addr << 1);
+       DEBUGFUNC("e1000_k1_gig_workaround_hv");
 
-               for (i = 0; i < cnf_size; i++) {
-                       ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
-                                                  &reg_data);
-                       if (ret_val)
-                               goto out;
+       if (hw->mac.type != e1000_pchlan)
+               goto out;
 
-                       ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
-                                                  1, &reg_addr);
+       /* Wrap the whole flow with the sw flag */
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               goto out;
+
+       /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
+       if (link) {
+               if (hw->phy.type == e1000_phy_82578) {
+                       ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
+                                                             &status_reg);
                        if (ret_val)
-                               goto out;
+                               goto release;
 
-                       /* Save off the PHY page for future writes. */
-                       if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
-                               phy_page = reg_data;
-                               continue;
-                       }
+                       status_reg &= BM_CS_STATUS_LINK_UP |
+                                     BM_CS_STATUS_RESOLVED |
+                                     BM_CS_STATUS_SPEED_MASK;
 
-                       reg_addr |= phy_page;
+                       if (status_reg == (BM_CS_STATUS_LINK_UP |
+                                          BM_CS_STATUS_RESOLVED |
+                                          BM_CS_STATUS_SPEED_1000))
+                               k1_enable = FALSE;
+               }
 
-                       ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data);
+               if (hw->phy.type == e1000_phy_82577) {
+                       ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
+                                                             &status_reg);
                        if (ret_val)
-                               goto out;
+                               goto release;
+
+                       status_reg &= HV_M_STATUS_LINK_UP |
+                                     HV_M_STATUS_AUTONEG_COMPLETE |
+                                     HV_M_STATUS_SPEED_MASK;
+
+                       if (status_reg == (HV_M_STATUS_LINK_UP |
+                                          HV_M_STATUS_AUTONEG_COMPLETE |
+                                          HV_M_STATUS_SPEED_1000))
+                               k1_enable = FALSE;
                }
+
+               /* Link stall fix for link up */
+               ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
+                                                      0x0100);
+               if (ret_val)
+                       goto release;
+
+       } else {
+               /* Link stall fix for link down */
+               ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
+                                                      0x4100);
+               if (ret_val)
+                       goto release;
        }
 
+       ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
+
+release:
+       hw->phy.ops.release(hw);
 out:
        return ret_val;
 }
 
 /**
- *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
+ *  e1000_configure_k1_ich8lan - Configure K1 power state
  *  @hw: pointer to the HW structure
+ *  @enable: K1 state to configure
+ *
+ *  Configure the K1 power state based on the provided parameter.
+ *  Assumes semaphore already acquired.
  *
- *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
+ *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
  **/
-static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
+s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
 {
-       s32 ret_val = -E1000_ERR_PHY_TYPE;
+       s32 ret_val = E1000_SUCCESS;
+       u32 ctrl_reg = 0;
+       u32 ctrl_ext = 0;
+       u32 reg = 0;
+       u16 kmrn_reg = 0;
 
-       DEBUGFUNC("e1000_get_phy_info_ich8lan");
+       DEBUGFUNC("e1000_configure_k1_ich8lan");
 
-       switch (hw->phy.type) {
-       case e1000_phy_ife:
-               ret_val = e1000_get_phy_info_ife_ich8lan(hw);
-               break;
-       case e1000_phy_igp_3:
-       case e1000_phy_bm:
-               ret_val = e1000_get_phy_info_igp(hw);
-               break;
-       default:
-               break;
+       ret_val = e1000_read_kmrn_reg_locked(hw,
+                                            E1000_KMRNCTRLSTA_K1_CONFIG,
+                                            &kmrn_reg);
+       if (ret_val)
+               goto out;
+
+       if (k1_enable)
+               kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
+       else
+               kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
+
+       ret_val = e1000_write_kmrn_reg_locked(hw,
+                                             E1000_KMRNCTRLSTA_K1_CONFIG,
+                                             kmrn_reg);
+       if (ret_val)
+               goto out;
+
+       usec_delay(20);
+       ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+       ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
+
+       reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+       reg |= E1000_CTRL_FRCSPD;
+       E1000_WRITE_REG(hw, E1000_CTRL, reg);
+
+       E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
+       usec_delay(20);
+       E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
+       E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+       usec_delay(20);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
+ *  @hw:       pointer to the HW structure
+ *  @d0_state: boolean if entering d0 or d3 device state
+ *
+ *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
+ *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
+ *  in NVM determines whether HW should configure LPLU and Gbe Disable.
+ **/
+s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
+{
+       s32 ret_val = 0;
+       u32 mac_reg;
+       u16 oem_reg;
+
+       DEBUGFUNC("e1000_oem_bits_config_ich8lan");
+
+       if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
+               return ret_val;
+
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               return ret_val;
+
+       if (!(hw->mac.type == e1000_pch2lan)) {
+               mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
+               if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
+                       goto out;
        }
 
+       mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
+       if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
+               goto out;
+
+       mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
+
+       ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
+       if (ret_val)
+               goto out;
+
+       oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
+
+       if (d0_state) {
+               if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
+                       oem_reg |= HV_OEM_BITS_GBE_DIS;
+
+               if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
+                       oem_reg |= HV_OEM_BITS_LPLU;
+       } else {
+               if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
+                       oem_reg |= HV_OEM_BITS_GBE_DIS;
+
+               if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
+                       oem_reg |= HV_OEM_BITS_LPLU;
+       }
+       /* Restart auto-neg to activate the bits */
+       if (!hw->phy.ops.check_reset_block(hw))
+               oem_reg |= HV_OEM_BITS_RESTART_AN;
+       ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
+
+out:
+       hw->phy.ops.release(hw);
+
        return ret_val;
 }
 
+
 /**
- *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
+ *  e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
  *  @hw: pointer to the HW structure
- *
- *  Populates "phy" structure with various feature states.
- *  This function is only called by other family-specific
- *  routines.
  **/
-static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
+s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
+{
+       DEBUGFUNC("e1000_hv_phy_powerdown_workaround_ich8lan");
+
+       if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
+               return E1000_SUCCESS;
+
+       return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444);
+}
+
+/**
+ *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
+ *  @hw:   pointer to the HW structure
+ **/
+static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
 {
-       struct e1000_phy_info *phy = &hw->phy;
        s32 ret_val;
        u16 data;
-       bool link;
 
-       DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
+       DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
 
-       ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
+       ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
        if (ret_val)
+               return ret_val;
+
+       data |= HV_KMRN_MDIO_SLOW;
+
+       ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
+
+       return ret_val;
+}
+
+/**
+ *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
+ *  done after every PHY reset.
+ **/
+static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
+
+       if (hw->mac.type != e1000_pchlan)
                goto out;
 
-       if (!link) {
-               DEBUGOUT("Phy info is only valid if link is up\n");
-               ret_val = -E1000_ERR_CONFIG;
+       /* Set MDIO slow mode before any other MDIO access */
+       if (hw->phy.type == e1000_phy_82577) {
+               ret_val = e1000_set_mdio_slow_mode_hv(hw);
+               if (ret_val)
+                       goto out;
+       }
+
+       /* Hanksville M Phy init for IEEE. */
+       if ((hw->revision_id == 2) &&
+           (hw->phy.type == e1000_phy_82577) &&
+           ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
+               hw->phy.ops.write_reg(hw, 0x10, 0x8823);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0018);
+               hw->phy.ops.write_reg(hw, 0x10, 0x8824);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0016);
+               hw->phy.ops.write_reg(hw, 0x10, 0x8825);
+               hw->phy.ops.write_reg(hw, 0x11, 0x001A);
+               hw->phy.ops.write_reg(hw, 0x10, 0x888C);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0007);
+               hw->phy.ops.write_reg(hw, 0x10, 0x888D);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0007);
+               hw->phy.ops.write_reg(hw, 0x10, 0x888E);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0007);
+               hw->phy.ops.write_reg(hw, 0x10, 0x8827);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0001);
+               hw->phy.ops.write_reg(hw, 0x10, 0x8835);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0001);
+               hw->phy.ops.write_reg(hw, 0x10, 0x8834);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0001);
+               hw->phy.ops.write_reg(hw, 0x10, 0x8833);
+               hw->phy.ops.write_reg(hw, 0x11, 0x0002);
+       }
+
+       if (((hw->phy.type == e1000_phy_82577) &&
+            ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
+           ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
+               /* Disable generation of early preamble */
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
+               if (ret_val)
+                       goto out;
+
+               /* Preamble tuning for SSC */
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
+               if (ret_val)
+                       goto out;
+       }
+
+       if (hw->phy.type == e1000_phy_82578) {
+               if (hw->revision_id < 3) {
+                       /* PHY config */
+                       ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
+                                                       0x66C0);
+                       if (ret_val)
+                               goto out;
+
+                       /* PHY config */
+                       ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
+                                                       0xFFFF);
+                       if (ret_val)
+                               goto out;
+               }
+
+               /*
+                * Return registers to default by doing a soft reset then
+                * writing 0x3140 to the control register.
+                */
+               if (hw->phy.revision < 2) {
+                       e1000_phy_sw_reset_generic(hw);
+                       ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
+                                                       0x3140);
+               }
+       }
+
+       if ((hw->revision_id == 2) &&
+           (hw->phy.type == e1000_phy_82577) &&
+           ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
+               /*
+                * Workaround for OEM (GbE) not operating after reset -
+                * restart AN (twice)
+                */
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
+               if (ret_val)
+                       goto out;
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
+               if (ret_val)
+                       goto out;
+       }
+
+       /* Select page 0 */
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
+               goto out;
+
+       hw->phy.addr = 1;
+       ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
+       hw->phy.ops.release(hw);
+       if (ret_val)
+               goto out;
+
+       /*
+        * Configure the K1 Si workaround during phy reset assuming there is
+        * link so that it disables K1 if link is in 1Gbps.
+        */
+       ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
+       if (ret_val)
+               goto out;
+
+       /* Workaround for link disconnects on a busy hub in half duplex */
+       ret_val = hw->phy.ops.acquire(hw);
+       if (ret_val)
                goto out;
+       ret_val = hw->phy.ops.read_reg_locked(hw,
+                                             PHY_REG(BM_PORT_CTRL_PAGE, 17),
+                                             &phy_data);
+       if (ret_val)
+               goto release;
+       ret_val = hw->phy.ops.write_reg_locked(hw,
+                                              PHY_REG(BM_PORT_CTRL_PAGE, 17),
+                                              phy_data & 0x00FF);
+release:
+       hw->phy.ops.release(hw);
+out:
+       return ret_val;
+}
+
+/**
+ *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
+ *  @hw:   pointer to the HW structure
+ **/
+void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
+{
+       u32 mac_reg;
+       u16 i;
+
+       DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
+
+       /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
+       for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
+               mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
+               hw->phy.ops.write_reg(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
+               hw->phy.ops.write_reg(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
+               mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
+               hw->phy.ops.write_reg(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
+               hw->phy.ops.write_reg(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
+       }
+}
+
+static u32 e1000_calc_rx_da_crc(u8 mac[])
+{
+       u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
+       u32 i, j, mask, crc;
+
+       DEBUGFUNC("e1000_calc_rx_da_crc");
+
+       crc = 0xffffffff;
+       for (i = 0; i < 6; i++) {
+               crc = crc ^ mac[i];
+               for (j = 8; j > 0; j--) {
+                       mask = (crc & 1) * (-1);
+                       crc = (crc >> 1) ^ (poly & mask);
+               }
        }
+       return ~crc;
+}
 
-       ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
+/**
+ *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
+ *  with 82579 PHY
+ *  @hw: pointer to the HW structure
+ *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
+ **/
+s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
+{
+       s32 ret_val = E1000_SUCCESS;
+       u16 phy_reg, data;
+       u32 mac_reg;
+       u16 i;
+
+       DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
+
+       if (hw->mac.type != e1000_pch2lan)
+               goto out;
+
+       /* disable Rx path while enabling/disabling workaround */
+       hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
+       ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
        if (ret_val)
                goto out;
-       phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
-                                  ? FALSE : TRUE;
 
-       if (phy->polarity_correction) {
-               ret_val = e1000_check_polarity_ife_ich8lan(hw);
+       if (enable) {
+               /*
+                * Write Rx addresses (rar_entry_count for RAL/H, +4 for
+                * SHRAL/H) and initial CRC values to the MAC
+                */
+               for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
+                       u8 mac_addr[ETH_ADDR_LEN] = {0};
+                       u32 addr_high, addr_low;
+
+                       addr_high = E1000_READ_REG(hw, E1000_RAH(i));
+                       if (!(addr_high & E1000_RAH_AV))
+                               continue;
+                       addr_low = E1000_READ_REG(hw, E1000_RAL(i));
+                       mac_addr[0] = (addr_low & 0xFF);
+                       mac_addr[1] = ((addr_low >> 8) & 0xFF);
+                       mac_addr[2] = ((addr_low >> 16) & 0xFF);
+                       mac_addr[3] = ((addr_low >> 24) & 0xFF);
+                       mac_addr[4] = (addr_high & 0xFF);
+                       mac_addr[5] = ((addr_high >> 8) & 0xFF);
+
+                       E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
+                                       e1000_calc_rx_da_crc(mac_addr));
+               }
+
+               /* Write Rx addresses to the PHY */
+               e1000_copy_rx_addrs_to_phy_ich8lan(hw);
+
+               /* Enable jumbo frame workaround in the MAC */
+               mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
+               mac_reg &= ~(1 << 14);
+               mac_reg |= (7 << 15);
+               E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
+
+               mac_reg = E1000_READ_REG(hw, E1000_RCTL);
+               mac_reg |= E1000_RCTL_SECRC;
+               E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
+
+               ret_val = e1000_read_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_CTRL_OFFSET,
+                                               &data);
+               if (ret_val)
+                       goto out;
+               ret_val = e1000_write_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_CTRL_OFFSET,
+                                               data | (1 << 0));
+               if (ret_val)
+                       goto out;
+               ret_val = e1000_read_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_HD_CTRL,
+                                               &data);
+               if (ret_val)
+                       goto out;
+               data &= ~(0xF << 8);
+               data |= (0xB << 8);
+               ret_val = e1000_write_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_HD_CTRL,
+                                               data);
+               if (ret_val)
+                       goto out;
+
+               /* Enable jumbo frame workaround in the PHY */
+               hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
+               data &= ~(0x7F << 5);
+               data |= (0x37 << 5);
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
+               if (ret_val)
+                       goto out;
+               hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
+               data &= ~(1 << 13);
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
+               if (ret_val)
+                       goto out;
+               hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
+               data &= ~(0x3FF << 2);
+               data |= (0x1A << 2);
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
+               if (ret_val)
+                       goto out;
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xFE00);
+               if (ret_val)
+                       goto out;
+               hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
+               ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10));
                if (ret_val)
                        goto out;
        } else {
-               /* Polarity is forced */
-               phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
-                                     ? e1000_rev_polarity_reversed
-                                     : e1000_rev_polarity_normal;
+               /* Write MAC register values back to h/w defaults */
+               mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
+               mac_reg &= ~(0xF << 14);
+               E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
+
+               mac_reg = E1000_READ_REG(hw, E1000_RCTL);
+               mac_reg &= ~E1000_RCTL_SECRC;
+               E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
+
+               ret_val = e1000_read_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_CTRL_OFFSET,
+                                               &data);
+               if (ret_val)
+                       goto out;
+               ret_val = e1000_write_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_CTRL_OFFSET,
+                                               data & ~(1 << 0));
+               if (ret_val)
+                       goto out;
+               ret_val = e1000_read_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_HD_CTRL,
+                                               &data);
+               if (ret_val)
+                       goto out;
+               data &= ~(0xF << 8);
+               data |= (0xB << 8);
+               ret_val = e1000_write_kmrn_reg_generic(hw,
+                                               E1000_KMRNCTRLSTA_HD_CTRL,
+                                               data);
+               if (ret_val)
+                       goto out;
+
+               /* Write PHY register values back to h/w defaults */
+               hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
+               data &= ~(0x7F << 5);
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
+               if (ret_val)
+                       goto out;
+               hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
+               data |= (1 << 13);
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
+               if (ret_val)
+                       goto out;
+               hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
+               data &= ~(0x3FF << 2);
+               data |= (0x8 << 2);
+               ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
+               if (ret_val)
+                       goto&nbs