ioapic/i386: Rearrange pin information for ioapic low level intrhandler
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Mon, 29 Aug 2011 11:54:51 +0000 (19:54 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Mon, 29 Aug 2011 12:12:30 +0000 (20:12 +0800)
- Remove unused field, thus reduce the information size from 32 bytes
  to 16bytes.
- Struct, field and macro renaming

sys/platform/pc32/apic/apic_vector.s
sys/platform/pc32/apic/ioapic_abi.c
sys/platform/pc32/apic/ioapic_abi.h
sys/platform/pc32/apic/ioapic_ipl.s
sys/platform/pc32/i386/genassym.c

index 1f4f297..a9be21e 100644 (file)
        addl    $3*4,%esp ;     /* dummy xflags, trap & error codes */  \
 
 #define IOAPICADDR(irq_num) \
-       CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ADDR
+       CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_ADDR
 #define REDIRIDX(irq_num) \
-       CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ENTIDX
+       CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_IDX
 #define IOAPICFLAGS(irq_num) \
-       CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_FLAGS
+       CNAME(ioapic_irqs) + IOAPIC_IRQI_SIZE * (irq_num) + IOAPIC_IRQI_FLAGS
 
 #define MASK_IRQ(irq_num)                                              \
        IOAPIC_IMASK_LOCK ;                     /* into critical reg */ \
-       testl   $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
+       testl   $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ;        \
        jne     7f ;                    /* masked, don't mask */        \
-       orl     $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
+       orl     $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ;        \
                                                /* set the mask bit */  \
        movl    IOAPICADDR(irq_num), %ecx ;     /* ioapic addr */       \
        movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
@@ -91,7 +91,7 @@
  *  and the EOI cycle would cause redundant INTs to occur.
  */
 #define MASK_LEVEL_IRQ(irq_num)                                                \
-       testl   $IOAPIC_IM_FLAG_LEVEL, IOAPICFLAGS(irq_num) ;           \
+       testl   $IOAPIC_IRQI_FLAG_LEVEL, IOAPICFLAGS(irq_num) ;         \
        jz      9f ;                            /* edge, don't mask */  \
        MASK_IRQ(irq_num) ;                                             \
 9: ;                                                                   \
        cmpl    $0,%eax ;                                               \
        jnz     8f ;                                                    \
        IOAPIC_IMASK_LOCK ;                     /* into critical reg */ \
-       testl   $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
+       testl   $IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ;        \
        je      7f ;                    /* bit clear, not masked */     \
-       andl    $~IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;         \
+       andl    $~IOAPIC_IRQI_FLAG_MASKED, IOAPICFLAGS(irq_num) ;       \
                                                /* clear mask bit */    \
        movl    IOAPICADDR(irq_num),%ecx ;      /* ioapic addr */       \
        movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
index b21d8f9..a8f5745 100644 (file)
@@ -505,7 +505,7 @@ struct machintr_abi MachIntrABI_IOAPIC = {
 
 static int     ioapic_abi_extint_irq = -1;
 
-struct apic_intmapinfo int_to_apicintpin[IOAPIC_HWI_VECTORS];
+struct ioapic_irqinfo  ioapic_irqs[IOAPIC_HWI_VECTORS];
 
 static void
 ioapic_abi_intren(int irq)
@@ -586,6 +586,9 @@ ioapic_vectorctl(int op, int intr, int flags)
            intr == IOAPIC_HWI_SYSCALL)
                return EINVAL;
 
+       if (ioapic_irqs[intr].io_addr == NULL)
+               return EINVAL;
+
        ef = read_eflags();
        cpu_disable_intr();
        error = 0;
@@ -603,21 +606,18 @@ ioapic_vectorctl(int op, int intr, int flags)
                 * first, then reprogrammed with the new vector.  This should
                 * clear the IRR bit.
                 */
-               if (int_to_apicintpin[intr].ioapic >= 0) {
-                       imen_lock();
+               imen_lock();
 
-                       select = int_to_apicintpin[intr].redirindex;
-                       value = ioapic_read(int_to_apicintpin[intr].apic_address,
-                                           select);
-                       value |= IOART_INTMSET;
+               select = ioapic_irqs[intr].io_idx;
+               value = ioapic_read(ioapic_irqs[intr].io_addr, select);
+               value |= IOART_INTMSET;
 
-                       ioapic_write(int_to_apicintpin[intr].apic_address,
-                                    select, (value & ~APIC_TRIGMOD_MASK));
-                       ioapic_write(int_to_apicintpin[intr].apic_address,
-                                    select, (value & ~IOART_INTVEC) | vector);
+               ioapic_write(ioapic_irqs[intr].io_addr, select,
+                   (value & ~APIC_TRIGMOD_MASK));
+               ioapic_write(ioapic_irqs[intr].io_addr, select,
+                   (value & ~IOART_INTVEC) | vector);
 
-                       imen_unlock();
-               }
+               imen_unlock();
 
                machintr_intren(intr);
                break;
@@ -639,20 +639,17 @@ ioapic_vectorctl(int op, int intr, int flags)
                 * edge-triggering first, then reprogrammed with the new vector.
                 * This should clear the IRR bit.
                 */
-               if (int_to_apicintpin[intr].ioapic >= 0) {
-                       imen_lock();
+               imen_lock();
 
-                       select = int_to_apicintpin[intr].redirindex;
-                       value = ioapic_read(int_to_apicintpin[intr].apic_address,
-                                           select);
+               select = ioapic_irqs[intr].io_idx;
+               value = ioapic_read(ioapic_irqs[intr].io_addr, select);
 
-                       ioapic_write(int_to_apicintpin[intr].apic_address,
-                                    select, (value & ~APIC_TRIGMOD_MASK));
-                       ioapic_write(int_to_apicintpin[intr].apic_address,
-                                    select, (value & ~IOART_INTVEC) | vector);
+               ioapic_write(ioapic_irqs[intr].io_addr, select,
+                   (value & ~APIC_TRIGMOD_MASK));
+               ioapic_write(ioapic_irqs[intr].io_addr, select,
+                   (value & ~IOART_INTVEC) | vector);
 
-                       imen_unlock();
-               }
+               imen_unlock();
                break;
 
        default:
@@ -691,7 +688,7 @@ void
 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
     enum intr_polarity pola)
 {
-       struct apic_intmapinfo *info;
+       struct ioapic_irqinfo *info;
        struct ioapic_irqmap *map;
        void *ioaddr;
        int pin;
@@ -719,17 +716,15 @@ ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
        pin = ioapic_gsi_pin(map->im_gsi);
        ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 
-       info = &int_to_apicintpin[irq];
+       info = &ioapic_irqs[irq];
 
        imen_lock();
 
-       info->ioapic = 0; /* XXX unused */
-       info->int_pin = pin;
-       info->apic_address = ioaddr;
-       info->redirindex = IOAPIC_REDTBL + (2 * pin);
-       info->flags = IOAPIC_IM_FLAG_MASKED;
+       info->io_addr = ioaddr;
+       info->io_idx = IOAPIC_REDTBL + (2 * pin);
+       info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
        if (map->im_trig == INTR_TRIGGER_LEVEL)
-               info->flags |= IOAPIC_IM_FLAG_LEVEL;
+               info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 
        ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
            map->im_trig, map->im_pola);
@@ -803,7 +798,7 @@ ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
 static void
 ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
 {
-       struct apic_intmapinfo *info;
+       struct ioapic_irqinfo *info;
        struct ioapic_irqmap *map;
        void *ioaddr;
        int pin;
@@ -850,13 +845,13 @@ ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
        pin = ioapic_gsi_pin(map->im_gsi);
        ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 
-       info = &int_to_apicintpin[irq];
+       info = &ioapic_irqs[irq];
 
        imen_lock();
 
-       info->flags &= ~IOAPIC_IM_FLAG_LEVEL;
+       info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
        if (map->im_trig == INTR_TRIGGER_LEVEL)
-               info->flags |= IOAPIC_IM_FLAG_LEVEL;
+               info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
 
        ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
            map->im_trig, map->im_pola);
@@ -867,7 +862,7 @@ ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
 int
 ioapic_abi_extint_irqmap(int irq)
 {
-       struct apic_intmapinfo *info;
+       struct ioapic_irqinfo *info;
        struct ioapic_irqmap *map;
        void *ioaddr;
        int pin, error, vec;
@@ -911,15 +906,13 @@ ioapic_abi_extint_irqmap(int irq)
        pin = ioapic_gsi_pin(map->im_gsi);
        ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 
-       info = &int_to_apicintpin[irq];
+       info = &ioapic_irqs[irq];
 
        imen_lock();
 
-       info->ioapic = 0; /* XXX unused */
-       info->int_pin = pin;
-       info->apic_address = ioaddr;
-       info->redirindex = IOAPIC_REDTBL + (2 * pin);
-       info->flags = IOAPIC_IM_FLAG_MASKED;
+       info->io_addr = ioaddr;
+       info->io_idx = IOAPIC_REDTBL + (2 * pin);
+       info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
 
        ioapic_extpin_setup(ioaddr, pin, vec);
 
index 9312845..d77c611 100644 (file)
 
 /*
  * NOTE:
- * - Keep size of apic_intmapinfo power of 2
- * - Update IOAPIC_IM_SZSHIFT after changing apic_intmapinfo size
+ * - Keep size of ioapic_irqinfo power of 2
+ * - Update IOAPIC_IRQI_SZSHIFT after changing ioapic_irqinfo size
  */
-struct apic_intmapinfo {
-       int ioapic;
-       int int_pin;
-       volatile void *apic_address;
-       int redirindex;
-       uint32_t flags;         /* IOAPIC_IM_FLAG_ */
-       uint32_t pad[3];
+struct ioapic_irqinfo {
+       uint32_t        io_flags;       /* IOAPIC_IRQI_FLAG_ */
+       volatile void   *io_addr;
+       int             io_idx;
+       uint32_t        io_pad;
 };
-#define IOAPIC_IM_SZSHIFT      5
+#define IOAPIC_IRQI_SZSHIFT    4
 
-#define IOAPIC_IM_FLAG_LEVEL   0x1     /* default to edge trigger */
-#define IOAPIC_IM_FLAG_MASKED  0x2
+#define IOAPIC_IRQI_FLAG_LEVEL 0x1     /* default to edge trigger */
+#define IOAPIC_IRQI_FLAG_MASKED        0x2
 
-extern struct apic_intmapinfo  int_to_apicintpin[];
+extern struct ioapic_irqinfo   ioapic_irqs[];
 
 extern struct machintr_abi MachIntrABI_IOAPIC;
 
index 86f06fb..0639264 100644 (file)
@@ -77,10 +77,10 @@ ENTRY(IOAPIC_INTRDIS)
        IOAPIC_IMASK_LOCK               /* enter critical reg */
        movl    4(%esp),%eax
 1:
-       shll    $IOAPIC_IM_SZSHIFT, %eax
-       orl     $IOAPIC_IM_FLAG_MASKED, CNAME(int_to_apicintpin) + IOAPIC_IM_FLAGS(%eax)
-       movl    CNAME(int_to_apicintpin) + IOAPIC_IM_ADDR(%eax), %edx
-       movl    CNAME(int_to_apicintpin) + IOAPIC_IM_ENTIDX(%eax), %ecx
+       shll    $IOAPIC_IRQI_SZSHIFT, %eax
+       orl     $IOAPIC_IRQI_FLAG_MASKED, CNAME(ioapic_irqs) + IOAPIC_IRQI_FLAGS(%eax)
+       movl    CNAME(ioapic_irqs) + IOAPIC_IRQI_ADDR(%eax), %edx
+       movl    CNAME(ioapic_irqs) + IOAPIC_IRQI_IDX(%eax), %ecx
        testl   %edx, %edx
        jz      2f
        movl    %ecx, (%edx)            /* target register index */
@@ -94,10 +94,10 @@ ENTRY(IOAPIC_INTREN)
        IOAPIC_IMASK_LOCK               /* enter critical reg */
        movl    4(%esp), %eax           /* mask into %eax */
 1:
-       shll    $IOAPIC_IM_SZSHIFT, %eax
-       andl    $~IOAPIC_IM_FLAG_MASKED, CNAME(int_to_apicintpin) + IOAPIC_IM_FLAGS(%eax)
-       movl    CNAME(int_to_apicintpin) + IOAPIC_IM_ADDR(%eax), %edx
-       movl    CNAME(int_to_apicintpin) + IOAPIC_IM_ENTIDX(%eax), %ecx
+       shll    $IOAPIC_IRQI_SZSHIFT, %eax
+       andl    $~IOAPIC_IRQI_FLAG_MASKED, CNAME(ioapic_irqs) + IOAPIC_IRQI_FLAGS(%eax)
+       movl    CNAME(ioapic_irqs) + IOAPIC_IRQI_ADDR(%eax), %edx
+       movl    CNAME(ioapic_irqs) + IOAPIC_IRQI_IDX(%eax), %ecx
        testl   %edx, %edx
        jz      2f
        movl    %ecx, (%edx)            /* write the target register index */
index 9a6c2ed..d62acc8 100644 (file)
@@ -234,10 +234,10 @@ ASSYM(VM86_FRAMESIZE, sizeof(struct vm86frame));
 
 ASSYM(LA_EOI, offsetof(struct LAPIC, eoi));
 
-ASSYM(IOAPIC_IM_ADDR, offsetof(struct apic_intmapinfo, apic_address));
-ASSYM(IOAPIC_IM_ENTIDX, offsetof(struct apic_intmapinfo, redirindex));
-ASSYM(IOAPIC_IM_FLAGS, offsetof(struct apic_intmapinfo, flags));
-ASSYM(IOAPIC_IM_SIZE, sizeof(struct apic_intmapinfo));
-ASSYM(IOAPIC_IM_SZSHIFT, IOAPIC_IM_SZSHIFT);
-ASSYM(IOAPIC_IM_FLAG_LEVEL, IOAPIC_IM_FLAG_LEVEL);
-ASSYM(IOAPIC_IM_FLAG_MASKED, IOAPIC_IM_FLAG_MASKED);
+ASSYM(IOAPIC_IRQI_ADDR, offsetof(struct ioapic_irqinfo, io_addr));
+ASSYM(IOAPIC_IRQI_IDX, offsetof(struct ioapic_irqinfo, io_idx));
+ASSYM(IOAPIC_IRQI_FLAGS, offsetof(struct ioapic_irqinfo, io_flags));
+ASSYM(IOAPIC_IRQI_SIZE, sizeof(struct ioapic_irqinfo));
+ASSYM(IOAPIC_IRQI_SZSHIFT, IOAPIC_IRQI_SZSHIFT);
+ASSYM(IOAPIC_IRQI_FLAG_LEVEL, IOAPIC_IRQI_FLAG_LEVEL);
+ASSYM(IOAPIC_IRQI_FLAG_MASKED, IOAPIC_IRQI_FLAG_MASKED);