ioapic: Function/variable renaming (apic -> ioapic)
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Wed, 2 Feb 2011 12:46:18 +0000 (20:46 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Wed, 2 Feb 2011 13:13:54 +0000 (21:13 +0800)
20 files changed:
sys/platform/pc32/apic/apic_abi.c
sys/platform/pc32/apic/apic_ipl.h
sys/platform/pc32/apic/apic_ipl.s
sys/platform/pc32/apic/apic_vector.s
sys/platform/pc32/apic/ioapic_abi.h [copied from sys/sys/machintr.h with 51% similarity]
sys/platform/pc32/apic/mpapic.c
sys/platform/pc32/i386/mp_machdep.c
sys/platform/pc32/icu/icu_abi.c
sys/platform/pc32/include/smp.h
sys/platform/pc64/apic/apic_abi.c
sys/platform/pc64/apic/apic_ipl.h
sys/platform/pc64/apic/apic_ipl.s
sys/platform/pc64/apic/apic_vector.s
sys/platform/pc64/apic/ioapic_abi.h [copied from sys/sys/machintr.h with 51% similarity]
sys/platform/pc64/apic/mpapic.c
sys/platform/pc64/icu/icu_abi.c
sys/platform/pc64/include/smp.h
sys/platform/pc64/x86_64/machdep.c
sys/platform/pc64/x86_64/mp_machdep.c
sys/sys/machintr.h

index 68d79d0..b7cafa6 100644 (file)
 #ifdef SMP /* APIC-IO */
 
 extern inthand_t
-       IDTVEC(apic_intr0),
-       IDTVEC(apic_intr1),
-       IDTVEC(apic_intr2),
-       IDTVEC(apic_intr3),
-       IDTVEC(apic_intr4),
-       IDTVEC(apic_intr5),
-       IDTVEC(apic_intr6),
-       IDTVEC(apic_intr7),
-       IDTVEC(apic_intr8),
-       IDTVEC(apic_intr9),
-       IDTVEC(apic_intr10),
-       IDTVEC(apic_intr11),
-       IDTVEC(apic_intr12),
-       IDTVEC(apic_intr13),
-       IDTVEC(apic_intr14),
-       IDTVEC(apic_intr15),
-       IDTVEC(apic_intr16),
-       IDTVEC(apic_intr17),
-       IDTVEC(apic_intr18),
-       IDTVEC(apic_intr19),
-       IDTVEC(apic_intr20),
-       IDTVEC(apic_intr21),
-       IDTVEC(apic_intr22),
-       IDTVEC(apic_intr23),
-       IDTVEC(apic_intr24),
-       IDTVEC(apic_intr25),
-       IDTVEC(apic_intr26),
-       IDTVEC(apic_intr27),
-       IDTVEC(apic_intr28),
-       IDTVEC(apic_intr29),
-       IDTVEC(apic_intr30),
-       IDTVEC(apic_intr31),
-       IDTVEC(apic_intr32),
-       IDTVEC(apic_intr33),
-       IDTVEC(apic_intr34),
-       IDTVEC(apic_intr35),
-       IDTVEC(apic_intr36),
-       IDTVEC(apic_intr37),
-       IDTVEC(apic_intr38),
-       IDTVEC(apic_intr39),
-       IDTVEC(apic_intr40),
-       IDTVEC(apic_intr41),
-       IDTVEC(apic_intr42),
-       IDTVEC(apic_intr43),
-       IDTVEC(apic_intr44),
-       IDTVEC(apic_intr45),
-       IDTVEC(apic_intr46),
-       IDTVEC(apic_intr47),
-       IDTVEC(apic_intr48),
-       IDTVEC(apic_intr49),
-       IDTVEC(apic_intr50),
-       IDTVEC(apic_intr51),
-       IDTVEC(apic_intr52),
-       IDTVEC(apic_intr53),
-       IDTVEC(apic_intr54),
-       IDTVEC(apic_intr55),
-       IDTVEC(apic_intr56),
-       IDTVEC(apic_intr57),
-       IDTVEC(apic_intr58),
-       IDTVEC(apic_intr59),
-       IDTVEC(apic_intr60),
-       IDTVEC(apic_intr61),
-       IDTVEC(apic_intr62),
-       IDTVEC(apic_intr63),
-       IDTVEC(apic_intr64),
-       IDTVEC(apic_intr65),
-       IDTVEC(apic_intr66),
-       IDTVEC(apic_intr67),
-       IDTVEC(apic_intr68),
-       IDTVEC(apic_intr69),
-       IDTVEC(apic_intr70),
-       IDTVEC(apic_intr71),
-       IDTVEC(apic_intr72),
-       IDTVEC(apic_intr73),
-       IDTVEC(apic_intr74),
-       IDTVEC(apic_intr75),
-       IDTVEC(apic_intr76),
-       IDTVEC(apic_intr77),
-       IDTVEC(apic_intr78),
-       IDTVEC(apic_intr79),
-       IDTVEC(apic_intr80),
-       IDTVEC(apic_intr81),
-       IDTVEC(apic_intr82),
-       IDTVEC(apic_intr83),
-       IDTVEC(apic_intr84),
-       IDTVEC(apic_intr85),
-       IDTVEC(apic_intr86),
-       IDTVEC(apic_intr87),
-       IDTVEC(apic_intr88),
-       IDTVEC(apic_intr89),
-       IDTVEC(apic_intr90),
-       IDTVEC(apic_intr91),
-       IDTVEC(apic_intr92),
-       IDTVEC(apic_intr93),
-       IDTVEC(apic_intr94),
-       IDTVEC(apic_intr95),
-       IDTVEC(apic_intr96),
-       IDTVEC(apic_intr97),
-       IDTVEC(apic_intr98),
-       IDTVEC(apic_intr99),
-       IDTVEC(apic_intr100),
-       IDTVEC(apic_intr101),
-       IDTVEC(apic_intr102),
-       IDTVEC(apic_intr103),
-       IDTVEC(apic_intr104),
-       IDTVEC(apic_intr105),
-       IDTVEC(apic_intr106),
-       IDTVEC(apic_intr107),
-       IDTVEC(apic_intr108),
-       IDTVEC(apic_intr109),
-       IDTVEC(apic_intr110),
-       IDTVEC(apic_intr111),
-       IDTVEC(apic_intr112),
-       IDTVEC(apic_intr113),
-       IDTVEC(apic_intr114),
-       IDTVEC(apic_intr115),
-       IDTVEC(apic_intr116),
-       IDTVEC(apic_intr117),
-       IDTVEC(apic_intr118),
-       IDTVEC(apic_intr119),
-       IDTVEC(apic_intr120),
-       IDTVEC(apic_intr121),
-       IDTVEC(apic_intr122),
-       IDTVEC(apic_intr123),
-       IDTVEC(apic_intr124),
-       IDTVEC(apic_intr125),
-       IDTVEC(apic_intr126),
-       IDTVEC(apic_intr127),
-       IDTVEC(apic_intr128),
-       IDTVEC(apic_intr129),
-       IDTVEC(apic_intr130),
-       IDTVEC(apic_intr131),
-       IDTVEC(apic_intr132),
-       IDTVEC(apic_intr133),
-       IDTVEC(apic_intr134),
-       IDTVEC(apic_intr135),
-       IDTVEC(apic_intr136),
-       IDTVEC(apic_intr137),
-       IDTVEC(apic_intr138),
-       IDTVEC(apic_intr139),
-       IDTVEC(apic_intr140),
-       IDTVEC(apic_intr141),
-       IDTVEC(apic_intr142),
-       IDTVEC(apic_intr143),
-       IDTVEC(apic_intr144),
-       IDTVEC(apic_intr145),
-       IDTVEC(apic_intr146),
-       IDTVEC(apic_intr147),
-       IDTVEC(apic_intr148),
-       IDTVEC(apic_intr149),
-       IDTVEC(apic_intr150),
-       IDTVEC(apic_intr151),
-       IDTVEC(apic_intr152),
-       IDTVEC(apic_intr153),
-       IDTVEC(apic_intr154),
-       IDTVEC(apic_intr155),
-       IDTVEC(apic_intr156),
-       IDTVEC(apic_intr157),
-       IDTVEC(apic_intr158),
-       IDTVEC(apic_intr159),
-       IDTVEC(apic_intr160),
-       IDTVEC(apic_intr161),
-       IDTVEC(apic_intr162),
-       IDTVEC(apic_intr163),
-       IDTVEC(apic_intr164),
-       IDTVEC(apic_intr165),
-       IDTVEC(apic_intr166),
-       IDTVEC(apic_intr167),
-       IDTVEC(apic_intr168),
-       IDTVEC(apic_intr169),
-       IDTVEC(apic_intr170),
-       IDTVEC(apic_intr171),
-       IDTVEC(apic_intr172),
-       IDTVEC(apic_intr173),
-       IDTVEC(apic_intr174),
-       IDTVEC(apic_intr175),
-       IDTVEC(apic_intr176),
-       IDTVEC(apic_intr177),
-       IDTVEC(apic_intr178),
-       IDTVEC(apic_intr179),
-       IDTVEC(apic_intr180),
-       IDTVEC(apic_intr181),
-       IDTVEC(apic_intr182),
-       IDTVEC(apic_intr183),
-       IDTVEC(apic_intr184),
-       IDTVEC(apic_intr185),
-       IDTVEC(apic_intr186),
-       IDTVEC(apic_intr187),
-       IDTVEC(apic_intr188),
-       IDTVEC(apic_intr189),
-       IDTVEC(apic_intr190),
-       IDTVEC(apic_intr191);
-
-static inthand_t *apic_intr[APIC_HWI_VECTORS] = {
-       &IDTVEC(apic_intr0),
-       &IDTVEC(apic_intr1),
-       &IDTVEC(apic_intr2),
-       &IDTVEC(apic_intr3),
-       &IDTVEC(apic_intr4),
-       &IDTVEC(apic_intr5),
-       &IDTVEC(apic_intr6),
-       &IDTVEC(apic_intr7),
-       &IDTVEC(apic_intr8),
-       &IDTVEC(apic_intr9),
-       &IDTVEC(apic_intr10),
-       &IDTVEC(apic_intr11),
-       &IDTVEC(apic_intr12),
-       &IDTVEC(apic_intr13),
-       &IDTVEC(apic_intr14),
-       &IDTVEC(apic_intr15),
-       &IDTVEC(apic_intr16),
-       &IDTVEC(apic_intr17),
-       &IDTVEC(apic_intr18),
-       &IDTVEC(apic_intr19),
-       &IDTVEC(apic_intr20),
-       &IDTVEC(apic_intr21),
-       &IDTVEC(apic_intr22),
-       &IDTVEC(apic_intr23),
-       &IDTVEC(apic_intr24),
-       &IDTVEC(apic_intr25),
-       &IDTVEC(apic_intr26),
-       &IDTVEC(apic_intr27),
-       &IDTVEC(apic_intr28),
-       &IDTVEC(apic_intr29),
-       &IDTVEC(apic_intr30),
-       &IDTVEC(apic_intr31),
-       &IDTVEC(apic_intr32),
-       &IDTVEC(apic_intr33),
-       &IDTVEC(apic_intr34),
-       &IDTVEC(apic_intr35),
-       &IDTVEC(apic_intr36),
-       &IDTVEC(apic_intr37),
-       &IDTVEC(apic_intr38),
-       &IDTVEC(apic_intr39),
-       &IDTVEC(apic_intr40),
-       &IDTVEC(apic_intr41),
-       &IDTVEC(apic_intr42),
-       &IDTVEC(apic_intr43),
-       &IDTVEC(apic_intr44),
-       &IDTVEC(apic_intr45),
-       &IDTVEC(apic_intr46),
-       &IDTVEC(apic_intr47),
-       &IDTVEC(apic_intr48),
-       &IDTVEC(apic_intr49),
-       &IDTVEC(apic_intr50),
-       &IDTVEC(apic_intr51),
-       &IDTVEC(apic_intr52),
-       &IDTVEC(apic_intr53),
-       &IDTVEC(apic_intr54),
-       &IDTVEC(apic_intr55),
-       &IDTVEC(apic_intr56),
-       &IDTVEC(apic_intr57),
-       &IDTVEC(apic_intr58),
-       &IDTVEC(apic_intr59),
-       &IDTVEC(apic_intr60),
-       &IDTVEC(apic_intr61),
-       &IDTVEC(apic_intr62),
-       &IDTVEC(apic_intr63),
-       &IDTVEC(apic_intr64),
-       &IDTVEC(apic_intr65),
-       &IDTVEC(apic_intr66),
-       &IDTVEC(apic_intr67),
-       &IDTVEC(apic_intr68),
-       &IDTVEC(apic_intr69),
-       &IDTVEC(apic_intr70),
-       &IDTVEC(apic_intr71),
-       &IDTVEC(apic_intr72),
-       &IDTVEC(apic_intr73),
-       &IDTVEC(apic_intr74),
-       &IDTVEC(apic_intr75),
-       &IDTVEC(apic_intr76),
-       &IDTVEC(apic_intr77),
-       &IDTVEC(apic_intr78),
-       &IDTVEC(apic_intr79),
-       &IDTVEC(apic_intr80),
-       &IDTVEC(apic_intr81),
-       &IDTVEC(apic_intr82),
-       &IDTVEC(apic_intr83),
-       &IDTVEC(apic_intr84),
-       &IDTVEC(apic_intr85),
-       &IDTVEC(apic_intr86),
-       &IDTVEC(apic_intr87),
-       &IDTVEC(apic_intr88),
-       &IDTVEC(apic_intr89),
-       &IDTVEC(apic_intr90),
-       &IDTVEC(apic_intr91),
-       &IDTVEC(apic_intr92),
-       &IDTVEC(apic_intr93),
-       &IDTVEC(apic_intr94),
-       &IDTVEC(apic_intr95),
-       &IDTVEC(apic_intr96),
-       &IDTVEC(apic_intr97),
-       &IDTVEC(apic_intr98),
-       &IDTVEC(apic_intr99),
-       &IDTVEC(apic_intr100),
-       &IDTVEC(apic_intr101),
-       &IDTVEC(apic_intr102),
-       &IDTVEC(apic_intr103),
-       &IDTVEC(apic_intr104),
-       &IDTVEC(apic_intr105),
-       &IDTVEC(apic_intr106),
-       &IDTVEC(apic_intr107),
-       &IDTVEC(apic_intr108),
-       &IDTVEC(apic_intr109),
-       &IDTVEC(apic_intr110),
-       &IDTVEC(apic_intr111),
-       &IDTVEC(apic_intr112),
-       &IDTVEC(apic_intr113),
-       &IDTVEC(apic_intr114),
-       &IDTVEC(apic_intr115),
-       &IDTVEC(apic_intr116),
-       &IDTVEC(apic_intr117),
-       &IDTVEC(apic_intr118),
-       &IDTVEC(apic_intr119),
-       &IDTVEC(apic_intr120),
-       &IDTVEC(apic_intr121),
-       &IDTVEC(apic_intr122),
-       &IDTVEC(apic_intr123),
-       &IDTVEC(apic_intr124),
-       &IDTVEC(apic_intr125),
-       &IDTVEC(apic_intr126),
-       &IDTVEC(apic_intr127),
-       &IDTVEC(apic_intr128),
-       &IDTVEC(apic_intr129),
-       &IDTVEC(apic_intr130),
-       &IDTVEC(apic_intr131),
-       &IDTVEC(apic_intr132),
-       &IDTVEC(apic_intr133),
-       &IDTVEC(apic_intr134),
-       &IDTVEC(apic_intr135),
-       &IDTVEC(apic_intr136),
-       &IDTVEC(apic_intr137),
-       &IDTVEC(apic_intr138),
-       &IDTVEC(apic_intr139),
-       &IDTVEC(apic_intr140),
-       &IDTVEC(apic_intr141),
-       &IDTVEC(apic_intr142),
-       &IDTVEC(apic_intr143),
-       &IDTVEC(apic_intr144),
-       &IDTVEC(apic_intr145),
-       &IDTVEC(apic_intr146),
-       &IDTVEC(apic_intr147),
-       &IDTVEC(apic_intr148),
-       &IDTVEC(apic_intr149),
-       &IDTVEC(apic_intr150),
-       &IDTVEC(apic_intr151),
-       &IDTVEC(apic_intr152),
-       &IDTVEC(apic_intr153),
-       &IDTVEC(apic_intr154),
-       &IDTVEC(apic_intr155),
-       &IDTVEC(apic_intr156),
-       &IDTVEC(apic_intr157),
-       &IDTVEC(apic_intr158),
-       &IDTVEC(apic_intr159),
-       &IDTVEC(apic_intr160),
-       &IDTVEC(apic_intr161),
-       &IDTVEC(apic_intr162),
-       &IDTVEC(apic_intr163),
-       &IDTVEC(apic_intr164),
-       &IDTVEC(apic_intr165),
-       &IDTVEC(apic_intr166),
-       &IDTVEC(apic_intr167),
-       &IDTVEC(apic_intr168),
-       &IDTVEC(apic_intr169),
-       &IDTVEC(apic_intr170),
-       &IDTVEC(apic_intr171),
-       &IDTVEC(apic_intr172),
-       &IDTVEC(apic_intr173),
-       &IDTVEC(apic_intr174),
-       &IDTVEC(apic_intr175),
-       &IDTVEC(apic_intr176),
-       &IDTVEC(apic_intr177),
-       &IDTVEC(apic_intr178),
-       &IDTVEC(apic_intr179),
-       &IDTVEC(apic_intr180),
-       &IDTVEC(apic_intr181),
-       &IDTVEC(apic_intr182),
-       &IDTVEC(apic_intr183),
-       &IDTVEC(apic_intr184),
-       &IDTVEC(apic_intr185),
-       &IDTVEC(apic_intr186),
-       &IDTVEC(apic_intr187),
-       &IDTVEC(apic_intr188),
-       &IDTVEC(apic_intr189),
-       &IDTVEC(apic_intr190),
-       &IDTVEC(apic_intr191)
+       IDTVEC(ioapic_intr0),
+       IDTVEC(ioapic_intr1),
+       IDTVEC(ioapic_intr2),
+       IDTVEC(ioapic_intr3),
+       IDTVEC(ioapic_intr4),
+       IDTVEC(ioapic_intr5),
+       IDTVEC(ioapic_intr6),
+       IDTVEC(ioapic_intr7),
+       IDTVEC(ioapic_intr8),
+       IDTVEC(ioapic_intr9),
+       IDTVEC(ioapic_intr10),
+       IDTVEC(ioapic_intr11),
+       IDTVEC(ioapic_intr12),
+       IDTVEC(ioapic_intr13),
+       IDTVEC(ioapic_intr14),
+       IDTVEC(ioapic_intr15),
+       IDTVEC(ioapic_intr16),
+       IDTVEC(ioapic_intr17),
+       IDTVEC(ioapic_intr18),
+       IDTVEC(ioapic_intr19),
+       IDTVEC(ioapic_intr20),
+       IDTVEC(ioapic_intr21),
+       IDTVEC(ioapic_intr22),
+       IDTVEC(ioapic_intr23),
+       IDTVEC(ioapic_intr24),
+       IDTVEC(ioapic_intr25),
+       IDTVEC(ioapic_intr26),
+       IDTVEC(ioapic_intr27),
+       IDTVEC(ioapic_intr28),
+       IDTVEC(ioapic_intr29),
+       IDTVEC(ioapic_intr30),
+       IDTVEC(ioapic_intr31),
+       IDTVEC(ioapic_intr32),
+       IDTVEC(ioapic_intr33),
+       IDTVEC(ioapic_intr34),
+       IDTVEC(ioapic_intr35),
+       IDTVEC(ioapic_intr36),
+       IDTVEC(ioapic_intr37),
+       IDTVEC(ioapic_intr38),
+       IDTVEC(ioapic_intr39),
+       IDTVEC(ioapic_intr40),
+       IDTVEC(ioapic_intr41),
+       IDTVEC(ioapic_intr42),
+       IDTVEC(ioapic_intr43),
+       IDTVEC(ioapic_intr44),
+       IDTVEC(ioapic_intr45),
+       IDTVEC(ioapic_intr46),
+       IDTVEC(ioapic_intr47),
+       IDTVEC(ioapic_intr48),
+       IDTVEC(ioapic_intr49),
+       IDTVEC(ioapic_intr50),
+       IDTVEC(ioapic_intr51),
+       IDTVEC(ioapic_intr52),
+       IDTVEC(ioapic_intr53),
+       IDTVEC(ioapic_intr54),
+       IDTVEC(ioapic_intr55),
+       IDTVEC(ioapic_intr56),
+       IDTVEC(ioapic_intr57),
+       IDTVEC(ioapic_intr58),
+       IDTVEC(ioapic_intr59),
+       IDTVEC(ioapic_intr60),
+       IDTVEC(ioapic_intr61),
+       IDTVEC(ioapic_intr62),
+       IDTVEC(ioapic_intr63),
+       IDTVEC(ioapic_intr64),
+       IDTVEC(ioapic_intr65),
+       IDTVEC(ioapic_intr66),
+       IDTVEC(ioapic_intr67),
+       IDTVEC(ioapic_intr68),
+       IDTVEC(ioapic_intr69),
+       IDTVEC(ioapic_intr70),
+       IDTVEC(ioapic_intr71),
+       IDTVEC(ioapic_intr72),
+       IDTVEC(ioapic_intr73),
+       IDTVEC(ioapic_intr74),
+       IDTVEC(ioapic_intr75),
+       IDTVEC(ioapic_intr76),
+       IDTVEC(ioapic_intr77),
+       IDTVEC(ioapic_intr78),
+       IDTVEC(ioapic_intr79),
+       IDTVEC(ioapic_intr80),
+       IDTVEC(ioapic_intr81),
+       IDTVEC(ioapic_intr82),
+       IDTVEC(ioapic_intr83),
+       IDTVEC(ioapic_intr84),
+       IDTVEC(ioapic_intr85),
+       IDTVEC(ioapic_intr86),
+       IDTVEC(ioapic_intr87),
+       IDTVEC(ioapic_intr88),
+       IDTVEC(ioapic_intr89),
+       IDTVEC(ioapic_intr90),
+       IDTVEC(ioapic_intr91),
+       IDTVEC(ioapic_intr92),
+       IDTVEC(ioapic_intr93),
+       IDTVEC(ioapic_intr94),
+       IDTVEC(ioapic_intr95),
+       IDTVEC(ioapic_intr96),
+       IDTVEC(ioapic_intr97),
+       IDTVEC(ioapic_intr98),
+       IDTVEC(ioapic_intr99),
+       IDTVEC(ioapic_intr100),
+       IDTVEC(ioapic_intr101),
+       IDTVEC(ioapic_intr102),
+       IDTVEC(ioapic_intr103),
+       IDTVEC(ioapic_intr104),
+       IDTVEC(ioapic_intr105),
+       IDTVEC(ioapic_intr106),
+       IDTVEC(ioapic_intr107),
+       IDTVEC(ioapic_intr108),
+       IDTVEC(ioapic_intr109),
+       IDTVEC(ioapic_intr110),
+       IDTVEC(ioapic_intr111),
+       IDTVEC(ioapic_intr112),
+       IDTVEC(ioapic_intr113),
+       IDTVEC(ioapic_intr114),
+       IDTVEC(ioapic_intr115),
+       IDTVEC(ioapic_intr116),
+       IDTVEC(ioapic_intr117),
+       IDTVEC(ioapic_intr118),
+       IDTVEC(ioapic_intr119),
+       IDTVEC(ioapic_intr120),
+       IDTVEC(ioapic_intr121),
+       IDTVEC(ioapic_intr122),
+       IDTVEC(ioapic_intr123),
+       IDTVEC(ioapic_intr124),
+       IDTVEC(ioapic_intr125),
+       IDTVEC(ioapic_intr126),
+       IDTVEC(ioapic_intr127),
+       IDTVEC(ioapic_intr128),
+       IDTVEC(ioapic_intr129),
+       IDTVEC(ioapic_intr130),
+       IDTVEC(ioapic_intr131),
+       IDTVEC(ioapic_intr132),
+       IDTVEC(ioapic_intr133),
+       IDTVEC(ioapic_intr134),
+       IDTVEC(ioapic_intr135),
+       IDTVEC(ioapic_intr136),
+       IDTVEC(ioapic_intr137),
+       IDTVEC(ioapic_intr138),
+       IDTVEC(ioapic_intr139),
+       IDTVEC(ioapic_intr140),
+       IDTVEC(ioapic_intr141),
+       IDTVEC(ioapic_intr142),
+       IDTVEC(ioapic_intr143),
+       IDTVEC(ioapic_intr144),
+       IDTVEC(ioapic_intr145),
+       IDTVEC(ioapic_intr146),
+       IDTVEC(ioapic_intr147),
+       IDTVEC(ioapic_intr148),
+       IDTVEC(ioapic_intr149),
+       IDTVEC(ioapic_intr150),
+       IDTVEC(ioapic_intr151),
+       IDTVEC(ioapic_intr152),
+       IDTVEC(ioapic_intr153),
+       IDTVEC(ioapic_intr154),
+       IDTVEC(ioapic_intr155),
+       IDTVEC(ioapic_intr156),
+       IDTVEC(ioapic_intr157),
+       IDTVEC(ioapic_intr158),
+       IDTVEC(ioapic_intr159),
+       IDTVEC(ioapic_intr160),
+       IDTVEC(ioapic_intr161),
+       IDTVEC(ioapic_intr162),
+       IDTVEC(ioapic_intr163),
+       IDTVEC(ioapic_intr164),
+       IDTVEC(ioapic_intr165),
+       IDTVEC(ioapic_intr166),
+       IDTVEC(ioapic_intr167),
+       IDTVEC(ioapic_intr168),
+       IDTVEC(ioapic_intr169),
+       IDTVEC(ioapic_intr170),
+       IDTVEC(ioapic_intr171),
+       IDTVEC(ioapic_intr172),
+       IDTVEC(ioapic_intr173),
+       IDTVEC(ioapic_intr174),
+       IDTVEC(ioapic_intr175),
+       IDTVEC(ioapic_intr176),
+       IDTVEC(ioapic_intr177),
+       IDTVEC(ioapic_intr178),
+       IDTVEC(ioapic_intr179),
+       IDTVEC(ioapic_intr180),
+       IDTVEC(ioapic_intr181),
+       IDTVEC(ioapic_intr182),
+       IDTVEC(ioapic_intr183),
+       IDTVEC(ioapic_intr184),
+       IDTVEC(ioapic_intr185),
+       IDTVEC(ioapic_intr186),
+       IDTVEC(ioapic_intr187),
+       IDTVEC(ioapic_intr188),
+       IDTVEC(ioapic_intr189),
+       IDTVEC(ioapic_intr190),
+       IDTVEC(ioapic_intr191);
+
+static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
+       &IDTVEC(ioapic_intr0),
+       &IDTVEC(ioapic_intr1),
+       &IDTVEC(ioapic_intr2),
+       &IDTVEC(ioapic_intr3),
+       &IDTVEC(ioapic_intr4),
+       &IDTVEC(ioapic_intr5),
+       &IDTVEC(ioapic_intr6),
+       &IDTVEC(ioapic_intr7),
+       &IDTVEC(ioapic_intr8),
+       &IDTVEC(ioapic_intr9),
+       &IDTVEC(ioapic_intr10),
+       &IDTVEC(ioapic_intr11),
+       &IDTVEC(ioapic_intr12),
+       &IDTVEC(ioapic_intr13),
+       &IDTVEC(ioapic_intr14),
+       &IDTVEC(ioapic_intr15),
+       &IDTVEC(ioapic_intr16),
+       &IDTVEC(ioapic_intr17),
+       &IDTVEC(ioapic_intr18),
+       &IDTVEC(ioapic_intr19),
+       &IDTVEC(ioapic_intr20),
+       &IDTVEC(ioapic_intr21),
+       &IDTVEC(ioapic_intr22),
+       &IDTVEC(ioapic_intr23),
+       &IDTVEC(ioapic_intr24),
+       &IDTVEC(ioapic_intr25),
+       &IDTVEC(ioapic_intr26),
+       &IDTVEC(ioapic_intr27),
+       &IDTVEC(ioapic_intr28),
+       &IDTVEC(ioapic_intr29),
+       &IDTVEC(ioapic_intr30),
+       &IDTVEC(ioapic_intr31),
+       &IDTVEC(ioapic_intr32),
+       &IDTVEC(ioapic_intr33),
+       &IDTVEC(ioapic_intr34),
+       &IDTVEC(ioapic_intr35),
+       &IDTVEC(ioapic_intr36),
+       &IDTVEC(ioapic_intr37),
+       &IDTVEC(ioapic_intr38),
+       &IDTVEC(ioapic_intr39),
+       &IDTVEC(ioapic_intr40),
+       &IDTVEC(ioapic_intr41),
+       &IDTVEC(ioapic_intr42),
+       &IDTVEC(ioapic_intr43),
+       &IDTVEC(ioapic_intr44),
+       &IDTVEC(ioapic_intr45),
+       &IDTVEC(ioapic_intr46),
+       &IDTVEC(ioapic_intr47),
+       &IDTVEC(ioapic_intr48),
+       &IDTVEC(ioapic_intr49),
+       &IDTVEC(ioapic_intr50),
+       &IDTVEC(ioapic_intr51),
+       &IDTVEC(ioapic_intr52),
+       &IDTVEC(ioapic_intr53),
+       &IDTVEC(ioapic_intr54),
+       &IDTVEC(ioapic_intr55),
+       &IDTVEC(ioapic_intr56),
+       &IDTVEC(ioapic_intr57),
+       &IDTVEC(ioapic_intr58),
+       &IDTVEC(ioapic_intr59),
+       &IDTVEC(ioapic_intr60),
+       &IDTVEC(ioapic_intr61),
+       &IDTVEC(ioapic_intr62),
+       &IDTVEC(ioapic_intr63),
+       &IDTVEC(ioapic_intr64),
+       &IDTVEC(ioapic_intr65),
+       &IDTVEC(ioapic_intr66),
+       &IDTVEC(ioapic_intr67),
+       &IDTVEC(ioapic_intr68),
+       &IDTVEC(ioapic_intr69),
+       &IDTVEC(ioapic_intr70),
+       &IDTVEC(ioapic_intr71),
+       &IDTVEC(ioapic_intr72),
+       &IDTVEC(ioapic_intr73),
+       &IDTVEC(ioapic_intr74),
+       &IDTVEC(ioapic_intr75),
+       &IDTVEC(ioapic_intr76),
+       &IDTVEC(ioapic_intr77),
+       &IDTVEC(ioapic_intr78),
+       &IDTVEC(ioapic_intr79),
+       &IDTVEC(ioapic_intr80),
+       &IDTVEC(ioapic_intr81),
+       &IDTVEC(ioapic_intr82),
+       &IDTVEC(ioapic_intr83),
+       &IDTVEC(ioapic_intr84),
+       &IDTVEC(ioapic_intr85),
+       &IDTVEC(ioapic_intr86),
+       &IDTVEC(ioapic_intr87),
+       &IDTVEC(ioapic_intr88),
+       &IDTVEC(ioapic_intr89),
+       &IDTVEC(ioapic_intr90),
+       &IDTVEC(ioapic_intr91),
+       &IDTVEC(ioapic_intr92),
+       &IDTVEC(ioapic_intr93),
+       &IDTVEC(ioapic_intr94),
+       &IDTVEC(ioapic_intr95),
+       &IDTVEC(ioapic_intr96),
+       &IDTVEC(ioapic_intr97),
+       &IDTVEC(ioapic_intr98),
+       &IDTVEC(ioapic_intr99),
+       &IDTVEC(ioapic_intr100),
+       &IDTVEC(ioapic_intr101),
+       &IDTVEC(ioapic_intr102),
+       &IDTVEC(ioapic_intr103),
+       &IDTVEC(ioapic_intr104),
+       &IDTVEC(ioapic_intr105),
+       &IDTVEC(ioapic_intr106),
+       &IDTVEC(ioapic_intr107),
+       &IDTVEC(ioapic_intr108),
+       &IDTVEC(ioapic_intr109),
+       &IDTVEC(ioapic_intr110),
+       &IDTVEC(ioapic_intr111),
+       &IDTVEC(ioapic_intr112),
+       &IDTVEC(ioapic_intr113),
+       &IDTVEC(ioapic_intr114),
+       &IDTVEC(ioapic_intr115),
+       &IDTVEC(ioapic_intr116),
+       &IDTVEC(ioapic_intr117),
+       &IDTVEC(ioapic_intr118),
+       &IDTVEC(ioapic_intr119),
+       &IDTVEC(ioapic_intr120),
+       &IDTVEC(ioapic_intr121),
+       &IDTVEC(ioapic_intr122),
+       &IDTVEC(ioapic_intr123),
+       &IDTVEC(ioapic_intr124),
+       &IDTVEC(ioapic_intr125),
+       &IDTVEC(ioapic_intr126),
+       &IDTVEC(ioapic_intr127),
+       &IDTVEC(ioapic_intr128),
+       &IDTVEC(ioapic_intr129),
+       &IDTVEC(ioapic_intr130),
+       &IDTVEC(ioapic_intr131),
+       &IDTVEC(ioapic_intr132),
+       &IDTVEC(ioapic_intr133),
+       &IDTVEC(ioapic_intr134),
+       &IDTVEC(ioapic_intr135),
+       &IDTVEC(ioapic_intr136),
+       &IDTVEC(ioapic_intr137),
+       &IDTVEC(ioapic_intr138),
+       &IDTVEC(ioapic_intr139),
+       &IDTVEC(ioapic_intr140),
+       &IDTVEC(ioapic_intr141),
+       &IDTVEC(ioapic_intr142),
+       &IDTVEC(ioapic_intr143),
+       &IDTVEC(ioapic_intr144),
+       &IDTVEC(ioapic_intr145),
+       &IDTVEC(ioapic_intr146),
+       &IDTVEC(ioapic_intr147),
+       &IDTVEC(ioapic_intr148),
+       &IDTVEC(ioapic_intr149),
+       &IDTVEC(ioapic_intr150),
+       &IDTVEC(ioapic_intr151),
+       &IDTVEC(ioapic_intr152),
+       &IDTVEC(ioapic_intr153),
+       &IDTVEC(ioapic_intr154),
+       &IDTVEC(ioapic_intr155),
+       &IDTVEC(ioapic_intr156),
+       &IDTVEC(ioapic_intr157),
+       &IDTVEC(ioapic_intr158),
+       &IDTVEC(ioapic_intr159),
+       &IDTVEC(ioapic_intr160),
+       &IDTVEC(ioapic_intr161),
+       &IDTVEC(ioapic_intr162),
+       &IDTVEC(ioapic_intr163),
+       &IDTVEC(ioapic_intr164),
+       &IDTVEC(ioapic_intr165),
+       &IDTVEC(ioapic_intr166),
+       &IDTVEC(ioapic_intr167),
+       &IDTVEC(ioapic_intr168),
+       &IDTVEC(ioapic_intr169),
+       &IDTVEC(ioapic_intr170),
+       &IDTVEC(ioapic_intr171),
+       &IDTVEC(ioapic_intr172),
+       &IDTVEC(ioapic_intr173),
+       &IDTVEC(ioapic_intr174),
+       &IDTVEC(ioapic_intr175),
+       &IDTVEC(ioapic_intr176),
+       &IDTVEC(ioapic_intr177),
+       &IDTVEC(ioapic_intr178),
+       &IDTVEC(ioapic_intr179),
+       &IDTVEC(ioapic_intr180),
+       &IDTVEC(ioapic_intr181),
+       &IDTVEC(ioapic_intr182),
+       &IDTVEC(ioapic_intr183),
+       &IDTVEC(ioapic_intr184),
+       &IDTVEC(ioapic_intr185),
+       &IDTVEC(ioapic_intr186),
+       &IDTVEC(ioapic_intr187),
+       &IDTVEC(ioapic_intr188),
+       &IDTVEC(ioapic_intr189),
+       &IDTVEC(ioapic_intr190),
+       &IDTVEC(ioapic_intr191)
 };
 
-extern void    APIC_INTREN(int);
-extern void    APIC_INTRDIS(int);
-
-static int     apic_setvar(int, const void *);
-static int     apic_getvar(int, void *);
-static int     apic_vectorctl(int, int, int);
-static void    apic_finalize(void);
-static void    apic_cleanup(void);
-static void    apic_setdefault(void);
-
-static int     apic_imcr_present;
-
-struct machintr_abi MachIntrABI_APIC = {
-       MACHINTR_APIC,
-       .intrdis        = APIC_INTRDIS,
-       .intren         = APIC_INTREN,
-       .vectorctl      = apic_vectorctl,
-       .setvar         = apic_setvar,
-       .getvar         = apic_getvar,
-       .finalize       = apic_finalize,
-       .cleanup        = apic_cleanup,
-       .setdefault     = apic_setdefault
+extern void    IOAPIC_INTREN(int);
+extern void    IOAPIC_INTRDIS(int);
+
+static int     ioapic_setvar(int, const void *);
+static int     ioapic_getvar(int, void *);
+static int     ioapic_vectorctl(int, int, int);
+static void    ioapic_finalize(void);
+static void    ioapic_cleanup(void);
+static void    ioapic_setdefault(void);
+
+static int     ioapic_imcr_present;
+
+struct machintr_abi MachIntrABI_IOAPIC = {
+       MACHINTR_IOAPIC,
+       .intrdis        = IOAPIC_INTRDIS,
+       .intren         = IOAPIC_INTREN,
+       .vectorctl      = ioapic_vectorctl,
+       .setvar         = ioapic_setvar,
+       .getvar         = ioapic_getvar,
+       .finalize       = ioapic_finalize,
+       .cleanup        = ioapic_cleanup,
+       .setdefault     = ioapic_setdefault
 };
 
 static int
-apic_setvar(int varid, const void *buf)
+ioapic_setvar(int varid, const void *buf)
 {
        int error = 0;
 
        switch (varid) {
        case MACHINTR_VAR_IMCR_PRESENT:
-               apic_imcr_present = *(const int *)buf;
+               ioapic_imcr_present = *(const int *)buf;
                break;
 
        default:
@@ -491,13 +491,13 @@ apic_setvar(int varid, const void *buf)
 }
 
 static int
-apic_getvar(int varid, void *buf)
+ioapic_getvar(int varid, void *buf)
 {
        int error = 0;
 
        switch (varid) {
        case MACHINTR_VAR_IMCR_PRESENT:
-               *(int *)buf = apic_imcr_present;
+               *(int *)buf = ioapic_imcr_present;
                break;
 
        default:
@@ -516,7 +516,7 @@ apic_getvar(int varid, void *buf)
  *  - enable NMI.
  */
 static void
-apic_finalize(void)
+ioapic_finalize(void)
 {
        uint32_t temp;
 
@@ -528,7 +528,7 @@ apic_finalize(void)
         * from the BSP.  The 8259 may still be connected to LINT0 on
         * the BSP's LAPIC.
         */
-       if (apic_imcr_present) {
+       if (ioapic_imcr_present) {
                outb(0x22, 0x70);       /* select IMCR */
                outb(0x23, 0x01);       /* disconnect 8259 */
        }
@@ -546,7 +546,7 @@ apic_finalize(void)
         * 8259 is completely disconnected; switch to IOAPIC MachIntrABI
         * and reconfigure the default IDT entries.
         */
-       MachIntrABI = MachIntrABI_APIC;
+       MachIntrABI = MachIntrABI_IOAPIC;
        MachIntrABI.setdefault();
 
        /*
@@ -566,13 +566,13 @@ apic_finalize(void)
  * that had already been posted to the cpu.
  */
 static void
-apic_cleanup(void)
+ioapic_cleanup(void)
 {
        bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
 }
 
 static int
-apic_vectorctl(int op, int intr, int flags)
+ioapic_vectorctl(int op, int intr, int flags)
 {
        int error;
        int vector;
@@ -580,7 +580,7 @@ apic_vectorctl(int op, int intr, int flags)
        uint32_t value;
        u_long ef;
 
-       if (intr < 0 || intr >= APIC_HWI_VECTORS ||
+       if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
            intr == IDT_OFFSET_SYSCALL - IDT_OFFSET)
                return EINVAL;
 
@@ -591,7 +591,7 @@ apic_vectorctl(int op, int intr, int flags)
        switch(op) {
        case MACHINTR_VECTOR_SETUP:
                vector = IDT_OFFSET + intr;
-               setidt(vector, apic_intr[intr], SDT_SYS386IGT,
+               setidt(vector, ioapic_intr[intr], SDT_SYS386IGT,
                       SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 
                /*
@@ -610,14 +610,14 @@ apic_vectorctl(int op, int intr, int flags)
                        imen_lock();
 
                        select = int_to_apicintpin[intr].redirindex;
-                       value = io_apic_read(int_to_apicintpin[intr].ioapic,
-                                            select);
+                       value = ioapic_read(int_to_apicintpin[intr].ioapic,
+                                           select);
                        value |= IOART_INTMSET;
 
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~APIC_TRIGMOD_MASK));
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~IOART_INTVEC) | vector);
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~APIC_TRIGMOD_MASK));
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~IOART_INTVEC) | vector);
 
                        imen_unlock();
                }
@@ -633,7 +633,7 @@ apic_vectorctl(int op, int intr, int flags)
                machintr_intrdis(intr);
 
                vector = IDT_OFFSET + intr;
-               setidt(vector, apic_intr[intr], SDT_SYS386IGT, SEL_KPL,
+               setidt(vector, ioapic_intr[intr], SDT_SYS386IGT, SEL_KPL,
                       GSEL(GCODE_SEL, SEL_KPL));
 
                /*
@@ -646,13 +646,13 @@ apic_vectorctl(int op, int intr, int flags)
                        imen_lock();
 
                        select = int_to_apicintpin[intr].redirindex;
-                       value = io_apic_read(int_to_apicintpin[intr].ioapic,
-                                            select);
+                       value = ioapic_read(int_to_apicintpin[intr].ioapic,
+                                           select);
 
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~APIC_TRIGMOD_MASK));
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~IOART_INTVEC) | vector);
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~APIC_TRIGMOD_MASK));
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~IOART_INTVEC) | vector);
 
                        imen_unlock();
                }
@@ -668,14 +668,14 @@ apic_vectorctl(int op, int intr, int flags)
 }
 
 static void
-apic_setdefault(void)
+ioapic_setdefault(void)
 {
        int intr;
 
-       for (intr = 0; intr < APIC_HWI_VECTORS; ++intr) {
+       for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
                if (intr == IDT_OFFSET_SYSCALL - IDT_OFFSET)
                        continue;
-               setidt(IDT_OFFSET + intr, apic_intr[intr], SDT_SYS386IGT,
+               setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
                       SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
        }
 }
index 5fad179..7a18ff7 100644 (file)
@@ -31,7 +31,7 @@
 
 #ifdef SMP /* APIC-IO */
 
-#define APIC_HWI_VECTORS 192
+#define IOAPIC_HWI_VECTORS 192
 
 #endif
 
 /*
  * Interrupts may or may not be disabled when using these functions.
  */
-#define APIC_IMASK_LOCK                                                        \
+#define IOAPIC_IMASK_LOCK                                              \
         SPIN_LOCK(imen_spinlock) ;                                     \
 
-#define APIC_IMASK_UNLOCK                                              \
+#define IOAPIC_IMASK_UNLOCK                                            \
         SPIN_UNLOCK(imen_spinlock) ;                                   \
 
 #endif
index b61a954..8d95b67 100644 (file)
@@ -75,8 +75,8 @@
         * Functions to enable and disable a hardware interrupt.  The
         * IRQ number is passed as an argument.
         */
-ENTRY(APIC_INTRDIS)
-       APIC_IMASK_LOCK                 /* enter critical reg */
+ENTRY(IOAPIC_INTRDIS)
+       IOAPIC_IMASK_LOCK               /* enter critical reg */
        movl    4(%esp),%eax
 1:
        shll    $IOAPIC_IM_SZSHIFT, %eax
@@ -89,11 +89,11 @@ ENTRY(APIC_INTRDIS)
        orl     $IOART_INTMASK, IOAPIC_WINDOW(%edx)
                                        /* set intmask in target apic reg */
 2:
-       APIC_IMASK_UNLOCK               /* exit critical reg */
+       IOAPIC_IMASK_UNLOCK             /* exit critical reg */
        ret
 
-ENTRY(APIC_INTREN)
-       APIC_IMASK_LOCK                 /* enter critical reg */
+ENTRY(IOAPIC_INTREN)
+       IOAPIC_IMASK_LOCK               /* enter critical reg */
        movl    4(%esp), %eax           /* mask into %eax */
 1:
        shll    $IOAPIC_IM_SZSHIFT, %eax
@@ -106,7 +106,7 @@ ENTRY(APIC_INTREN)
        andl    $~IOART_INTMASK, IOAPIC_WINDOW(%edx)
                                        /* clear mask bit */
 2:     
-       APIC_IMASK_UNLOCK               /* exit critical reg */
+       IOAPIC_IMASK_UNLOCK             /* exit critical reg */
        ret
 
 /******************************************************************************
@@ -114,28 +114,28 @@ ENTRY(APIC_INTREN)
  */
 
 /*
- * u_int io_apic_write(int apic, int select);
+ * u_int ioapic_write(int apic, int select);
  */
-ENTRY(io_apic_read)
-       movl    4(%esp), %ecx           /* APIC # */
+ENTRY(ioapic_read)
+       movl    4(%esp), %ecx           /* IOAPIC # */
        movl    ioapic, %eax
-       movl    (%eax,%ecx,4), %edx     /* APIC base register address */
+       movl    (%eax,%ecx,4), %edx     /* IOAPIC base register address */
        movl    8(%esp), %eax           /* target register index */
        movl    %eax, (%edx)            /* write the target register index */
-       movl    IOAPIC_WINDOW(%edx), %eax /* read the APIC register data */
+       movl    IOAPIC_WINDOW(%edx), %eax /* read the IOAPIC register data */
        ret                             /* %eax = register value */
 
 /*
- * void io_apic_write(int apic, int select, int value);
+ * void ioapic_write(int apic, int select, int value);
  */
-ENTRY(io_apic_write)
-       movl    4(%esp), %ecx           /* APIC # */
+ENTRY(ioapic_write)
+       movl    4(%esp), %ecx           /* IOAPIC # */
        movl    ioapic, %eax
-       movl    (%eax,%ecx,4), %edx     /* APIC base register address */
+       movl    (%eax,%ecx,4), %edx     /* IOAPIC base register address */
        movl    8(%esp), %eax           /* target register index */
        movl    %eax, (%edx)            /* write the target register index */
        movl    12(%esp), %eax          /* target register value */
-       movl    %eax, IOAPIC_WINDOW(%edx) /* write the APIC register data */
+       movl    %eax, IOAPIC_WINDOW(%edx) /* write the IOAPIC register data */
        ret                             /* %eax = void */
 
 #endif
index c571d30..ef18fb9 100644 (file)
@@ -74,7 +74,7 @@
        CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_FLAGS
 
 #define MASK_IRQ(irq_num)                                              \
-       APIC_IMASK_LOCK ;                       /* into critical reg */ \
+       IOAPIC_IMASK_LOCK ;                     /* into critical reg */ \
        testl   $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
        jne     7f ;                    /* masked, don't mask */        \
        orl     $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
@@ -84,7 +84,7 @@
        movl    %eax, (%ecx) ;                  /* write the index */   \
        orl     $IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* set the mask */  \
 7: ;                                           /* already masked */    \
-       APIC_IMASK_UNLOCK ;                                             \
+       IOAPIC_IMASK_UNLOCK ;                                           \
 
 /*
  * Test to see whether we are handling an edge or level triggered INT.
 #define UNMASK_IRQ(irq_num)                                            \
        cmpl    $0,%eax ;                                               \
        jnz     8f ;                                                    \
-       APIC_IMASK_LOCK ;                       /* into critical reg */ \
+       IOAPIC_IMASK_LOCK ;                     /* into critical reg */ \
        testl   $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
        je      7f ;                    /* bit clear, not masked */     \
        andl    $~IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;         \
        movl    %eax,(%ecx) ;                   /* write the index */   \
        andl    $~IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* clear the mask */ \
 7: ;                                                                   \
-       APIC_IMASK_UNLOCK ;                                             \
+       IOAPIC_IMASK_UNLOCK ;                                           \
 8: ;                                                                   \
 
 #ifdef SMP /* APIC-IO */
 #define        INTR_HANDLER(irq_num)                                           \
        .text ;                                                         \
        SUPERALIGN_TEXT ;                                               \
-IDTVEC(apic_intr##irq_num) ;                                           \
+IDTVEC(ioapic_intr##irq_num) ;                                         \
        PUSH_FRAME ;                                                    \
        FAKE_MCOUNT(15*4(%esp)) ;                                       \
        MASK_LEVEL_IRQ(irq_num) ;                                       \
similarity index 51%
copy from sys/sys/machintr.h
copy to sys/platform/pc32/apic/ioapic_abi.h
index 4254666..0e6f843 100644 (file)
@@ -1,8 +1,14 @@
 /*
- * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
+ * Copyright (c) 1991 The Regents of the University of California.
+ * Copyright (c) 1996, by Steve Passe.  All rights reserved.
+ * Copyright (c) 2005,2008 The DragonFly Project.  All rights reserved.
+ * All rights reserved.
  * 
  * This code is derived from software contributed to The DragonFly Project
  * by Matthew Dillon <dillon@backplane.com>
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
  * 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- * 
- * $DragonFly: src/sys/sys/machintr.h,v 1.7 2007/04/30 16:46:01 dillon Exp $
- */
-/*
- * This module defines the ABI for the machine-independant cpu interrupt
- * vector and masking layer.
- */
-
-#ifndef _SYS_QUEUE_H_
-#include <sys/queue.h>
-#endif
-
-enum machintr_type { MACHINTR_GENERIC, MACHINTR_ICU, MACHINTR_APIC };
-
-#define MACHINTR_VAR_SIZEMASK  0xFFFF
-
-#define MACHINTR_VAR_IMCR_PRESENT      (0x00010000|sizeof(int))
-
-#define MACHINTR_VECTOR_SETUP          1
-#define MACHINTR_VECTOR_TEARDOWN       2
-
-/*
- * Machine interrupt ABIs - registered at boot-time
  */
-struct machintr_abi {
-    enum machintr_type type;
-    void       (*intrdis)(int);                /* hardware disable irq */
-    void       (*intren)(int);                 /* hardware enable irq */
-    int                (*vectorctl)(int, int, int);    /* hardware intr vector ctl */
-    int                (*setvar)(int, const void *);   /* set miscellanious info */
-    int                (*getvar)(int, void *);         /* get miscellanious info */
-    void       (*finalize)(void);              /* final before ints enabled */
-    void       (*cleanup)(void);               /* cleanup */
-    void       (*setdefault)(void);            /* set default vectors */
-};
-
-#define machintr_intren(intr)  MachIntrABI.intren(intr)
-#define machintr_intrdis(intr) MachIntrABI.intrdis(intr)
-#define machintr_vector_setup(intr, flags)     \
-           MachIntrABI.vectorctl(MACHINTR_VECTOR_SETUP, intr, flags)
-#define machintr_vector_teardown(intr)         \
-           MachIntrABI.vectorctl(MACHINTR_VECTOR_TEARDOWN, intr, 0)
 
-#ifdef _KERNEL
+#ifndef _ARCH_APIC_IOAPIC_ABI_H_
+#define _ARCH_APIC_IOAPIC_ABI_H_
 
-extern struct machintr_abi MachIntrABI;
-extern int machintr_setvar_simple(int, int);
+extern struct machintr_abi MachIntrABI_IOAPIC;
 
-#endif
+#endif /* !_ARCH_APIC_IOAPIC_ABI_H_ */
index e1f6297..d32fb30 100644 (file)
@@ -435,15 +435,15 @@ io_apic_set_id(int apic, int id)
 {
        u_int32_t ux;
        
-       ux = io_apic_read(apic, IOAPIC_ID);     /* get current contents */
+       ux = ioapic_read(apic, IOAPIC_ID);      /* get current contents */
        if (((ux & APIC_ID_MASK) >> 24) != id) {
                kprintf("Changing APIC ID for IO APIC #%d"
                       " from %d to %d on chip\n",
                       apic, ((ux & APIC_ID_MASK) >> 24), id);
                ux &= ~APIC_ID_MASK;    /* clear the ID field */
                ux |= (id << 24);
-               io_apic_write(apic, IOAPIC_ID, ux);     /* write new value */
-               ux = io_apic_read(apic, IOAPIC_ID);     /* re-read && test */
+               ioapic_write(apic, IOAPIC_ID, ux);      /* write new value */
+               ux = ioapic_read(apic, IOAPIC_ID);      /* re-read && test */
                if (((ux & APIC_ID_MASK) >> 24) != id)
                        panic("can't control IO APIC #%d ID, reg: 0x%08x",
                              apic, ux);
@@ -454,7 +454,7 @@ io_apic_set_id(int apic, int id)
 int
 io_apic_get_id(int apic)
 {
-  return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
+  return (ioapic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
 }
   
 
@@ -490,17 +490,17 @@ io_apic_setup_intpin(int apic, int pin)
         */
        imen_lock();
 
-       flags = io_apic_read(apic, select) & IOART_RESV;
+       flags = ioapic_read(apic, select) & IOART_RESV;
        flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
        flags |= IOART_DESTPHY | IOART_DELFIXED;
 
-       target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
+       target = ioapic_read(apic, select + 1) & IOART_HI_DEST_RESV;
        target |= 0;    /* fixed mode cpu mask of 0 - don't deliver anywhere */
 
        vector = 0;
 
-       io_apic_write(apic, select, flags | vector);
-       io_apic_write(apic, select + 1, target);
+       ioapic_write(apic, select, flags | vector);
+       ioapic_write(apic, select + 1, target);
 
        imen_unlock();
 
@@ -576,13 +576,13 @@ io_apic_setup_intpin(int apic, int pin)
        imen_lock();
 
        vector = IDT_OFFSET + irq;                      /* IDT vec */
-       target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
+       target = ioapic_read(apic, select + 1) & IOART_HI_DEST_RESV;
        /* Deliver all interrupts to CPU0 (BSP) */
        target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
                  IOART_HI_DEST_MASK;
-       flags |= io_apic_read(apic, select) & IOART_RESV;
-       io_apic_write(apic, select, flags | vector);
-       io_apic_write(apic, select + 1, target);
+       flags |= ioapic_read(apic, select) & IOART_RESV;
+       ioapic_write(apic, select, flags | vector);
+       ioapic_write(apic, select + 1, target);
 
        imen_unlock();
 }
@@ -654,8 +654,8 @@ ext_int_setup(int apic, int intr)
        vector = IDT_OFFSET + intr;
        flags = DEFAULT_EXTINT_FLAGS;
 
-       io_apic_write(apic, select, flags | vector);
-       io_apic_write(apic, select + 1, target);
+       ioapic_write(apic, select, flags | vector);
+       ioapic_write(apic, select + 1, target);
 
        return 0;
 }
index a4f85ad..a875566 100644 (file)
@@ -686,7 +686,7 @@ if (apic_io_enable) {
 
        /* fill the LOGICAL io_apic_versions table */
        for (apic = 0; apic < mp_napics; ++apic) {
-               ux = io_apic_read(apic, IOAPIC_VER);
+               ux = ioapic_read(apic, IOAPIC_VER);
                io_apic_versions[apic] = ux;
                io_apic_set_id(apic, IO_TO_ID(apic));
        }
@@ -1637,7 +1637,7 @@ int_entry(const struct INTENTRY *entry, int intr)
                /* This signal goes to all IO APICS.  Select an IO APIC
                   with sufficient number of interrupt pins */
                for (apic = 0; apic < mp_napics; apic++)
-                       if (((io_apic_read(apic, IOAPIC_VER) & 
+                       if (((ioapic_read(apic, IOAPIC_VER) & 
                              IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 
                            entry->dst_apic_int)
                                break;
@@ -2039,7 +2039,7 @@ mptable_default(int type)
 #endif /* 0 */
 
        /* one and only IO APIC */
-       io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
+       io_apic_id = (ioapic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
 
        /*
         * sanity check, refer to MP spec section 3.6.6, last paragraph
index 3953c5c..9c99530 100644 (file)
 
 #include <sys/thread2.h>
 
+#include <machine_base/apic/ioapic_abi.h>
+
 #include "icu.h"
 #include "icu_ipl.h"
 
-extern struct machintr_abi MachIntrABI_APIC;
-
 extern inthand_t
        IDTVEC(icu_intr0),      IDTVEC(icu_intr1),
        IDTVEC(icu_intr2),      IDTVEC(icu_intr3),
@@ -152,9 +152,9 @@ icu_finalize(void)
 #ifdef SMP
        if (apic_io_enable) {
                KKASSERT(MachIntrABI.type == MACHINTR_ICU);
-               MachIntrABI_APIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
-                                       &icu_imcr_present);
-               MachIntrABI_APIC.finalize();
+               MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
+                                         &icu_imcr_present);
+               MachIntrABI_IOAPIC.finalize();
                return;
        }
 #endif
index 4f29c92..8e9836e 100644 (file)
@@ -52,8 +52,8 @@ extern volatile u_int         checkstate_probed_cpus;
 extern void (*cpustop_restartfunc) (void);
 
 /* functions in apic_ipl.s */
-u_int  io_apic_read            (int, int);
-void   io_apic_write           (int, int, u_int);
+u_int  ioapic_read             (int, int);
+void   ioapic_write            (int, int, u_int);
 
 /* global data in mp_machdep.c */
 extern int                     mp_naps;
index 5731547..5f6e874 100644 (file)
 #ifdef SMP /* APIC-IO */
 
 extern inthand_t
-       IDTVEC(apic_intr0),
-       IDTVEC(apic_intr1),
-       IDTVEC(apic_intr2),
-       IDTVEC(apic_intr3),
-       IDTVEC(apic_intr4),
-       IDTVEC(apic_intr5),
-       IDTVEC(apic_intr6),
-       IDTVEC(apic_intr7),
-       IDTVEC(apic_intr8),
-       IDTVEC(apic_intr9),
-       IDTVEC(apic_intr10),
-       IDTVEC(apic_intr11),
-       IDTVEC(apic_intr12),
-       IDTVEC(apic_intr13),
-       IDTVEC(apic_intr14),
-       IDTVEC(apic_intr15),
-       IDTVEC(apic_intr16),
-       IDTVEC(apic_intr17),
-       IDTVEC(apic_intr18),
-       IDTVEC(apic_intr19),
-       IDTVEC(apic_intr20),
-       IDTVEC(apic_intr21),
-       IDTVEC(apic_intr22),
-       IDTVEC(apic_intr23),
-       IDTVEC(apic_intr24),
-       IDTVEC(apic_intr25),
-       IDTVEC(apic_intr26),
-       IDTVEC(apic_intr27),
-       IDTVEC(apic_intr28),
-       IDTVEC(apic_intr29),
-       IDTVEC(apic_intr30),
-       IDTVEC(apic_intr31),
-       IDTVEC(apic_intr32),
-       IDTVEC(apic_intr33),
-       IDTVEC(apic_intr34),
-       IDTVEC(apic_intr35),
-       IDTVEC(apic_intr36),
-       IDTVEC(apic_intr37),
-       IDTVEC(apic_intr38),
-       IDTVEC(apic_intr39),
-       IDTVEC(apic_intr40),
-       IDTVEC(apic_intr41),
-       IDTVEC(apic_intr42),
-       IDTVEC(apic_intr43),
-       IDTVEC(apic_intr44),
-       IDTVEC(apic_intr45),
-       IDTVEC(apic_intr46),
-       IDTVEC(apic_intr47),
-       IDTVEC(apic_intr48),
-       IDTVEC(apic_intr49),
-       IDTVEC(apic_intr50),
-       IDTVEC(apic_intr51),
-       IDTVEC(apic_intr52),
-       IDTVEC(apic_intr53),
-       IDTVEC(apic_intr54),
-       IDTVEC(apic_intr55),
-       IDTVEC(apic_intr56),
-       IDTVEC(apic_intr57),
-       IDTVEC(apic_intr58),
-       IDTVEC(apic_intr59),
-       IDTVEC(apic_intr60),
-       IDTVEC(apic_intr61),
-       IDTVEC(apic_intr62),
-       IDTVEC(apic_intr63),
-       IDTVEC(apic_intr64),
-       IDTVEC(apic_intr65),
-       IDTVEC(apic_intr66),
-       IDTVEC(apic_intr67),
-       IDTVEC(apic_intr68),
-       IDTVEC(apic_intr69),
-       IDTVEC(apic_intr70),
-       IDTVEC(apic_intr71),
-       IDTVEC(apic_intr72),
-       IDTVEC(apic_intr73),
-       IDTVEC(apic_intr74),
-       IDTVEC(apic_intr75),
-       IDTVEC(apic_intr76),
-       IDTVEC(apic_intr77),
-       IDTVEC(apic_intr78),
-       IDTVEC(apic_intr79),
-       IDTVEC(apic_intr80),
-       IDTVEC(apic_intr81),
-       IDTVEC(apic_intr82),
-       IDTVEC(apic_intr83),
-       IDTVEC(apic_intr84),
-       IDTVEC(apic_intr85),
-       IDTVEC(apic_intr86),
-       IDTVEC(apic_intr87),
-       IDTVEC(apic_intr88),
-       IDTVEC(apic_intr89),
-       IDTVEC(apic_intr90),
-       IDTVEC(apic_intr91),
-       IDTVEC(apic_intr92),
-       IDTVEC(apic_intr93),
-       IDTVEC(apic_intr94),
-       IDTVEC(apic_intr95),
-       IDTVEC(apic_intr96),
-       IDTVEC(apic_intr97),
-       IDTVEC(apic_intr98),
-       IDTVEC(apic_intr99),
-       IDTVEC(apic_intr100),
-       IDTVEC(apic_intr101),
-       IDTVEC(apic_intr102),
-       IDTVEC(apic_intr103),
-       IDTVEC(apic_intr104),
-       IDTVEC(apic_intr105),
-       IDTVEC(apic_intr106),
-       IDTVEC(apic_intr107),
-       IDTVEC(apic_intr108),
-       IDTVEC(apic_intr109),
-       IDTVEC(apic_intr110),
-       IDTVEC(apic_intr111),
-       IDTVEC(apic_intr112),
-       IDTVEC(apic_intr113),
-       IDTVEC(apic_intr114),
-       IDTVEC(apic_intr115),
-       IDTVEC(apic_intr116),
-       IDTVEC(apic_intr117),
-       IDTVEC(apic_intr118),
-       IDTVEC(apic_intr119),
-       IDTVEC(apic_intr120),
-       IDTVEC(apic_intr121),
-       IDTVEC(apic_intr122),
-       IDTVEC(apic_intr123),
-       IDTVEC(apic_intr124),
-       IDTVEC(apic_intr125),
-       IDTVEC(apic_intr126),
-       IDTVEC(apic_intr127),
-       IDTVEC(apic_intr128),
-       IDTVEC(apic_intr129),
-       IDTVEC(apic_intr130),
-       IDTVEC(apic_intr131),
-       IDTVEC(apic_intr132),
-       IDTVEC(apic_intr133),
-       IDTVEC(apic_intr134),
-       IDTVEC(apic_intr135),
-       IDTVEC(apic_intr136),
-       IDTVEC(apic_intr137),
-       IDTVEC(apic_intr138),
-       IDTVEC(apic_intr139),
-       IDTVEC(apic_intr140),
-       IDTVEC(apic_intr141),
-       IDTVEC(apic_intr142),
-       IDTVEC(apic_intr143),
-       IDTVEC(apic_intr144),
-       IDTVEC(apic_intr145),
-       IDTVEC(apic_intr146),
-       IDTVEC(apic_intr147),
-       IDTVEC(apic_intr148),
-       IDTVEC(apic_intr149),
-       IDTVEC(apic_intr150),
-       IDTVEC(apic_intr151),
-       IDTVEC(apic_intr152),
-       IDTVEC(apic_intr153),
-       IDTVEC(apic_intr154),
-       IDTVEC(apic_intr155),
-       IDTVEC(apic_intr156),
-       IDTVEC(apic_intr157),
-       IDTVEC(apic_intr158),
-       IDTVEC(apic_intr159),
-       IDTVEC(apic_intr160),
-       IDTVEC(apic_intr161),
-       IDTVEC(apic_intr162),
-       IDTVEC(apic_intr163),
-       IDTVEC(apic_intr164),
-       IDTVEC(apic_intr165),
-       IDTVEC(apic_intr166),
-       IDTVEC(apic_intr167),
-       IDTVEC(apic_intr168),
-       IDTVEC(apic_intr169),
-       IDTVEC(apic_intr170),
-       IDTVEC(apic_intr171),
-       IDTVEC(apic_intr172),
-       IDTVEC(apic_intr173),
-       IDTVEC(apic_intr174),
-       IDTVEC(apic_intr175),
-       IDTVEC(apic_intr176),
-       IDTVEC(apic_intr177),
-       IDTVEC(apic_intr178),
-       IDTVEC(apic_intr179),
-       IDTVEC(apic_intr180),
-       IDTVEC(apic_intr181),
-       IDTVEC(apic_intr182),
-       IDTVEC(apic_intr183),
-       IDTVEC(apic_intr184),
-       IDTVEC(apic_intr185),
-       IDTVEC(apic_intr186),
-       IDTVEC(apic_intr187),
-       IDTVEC(apic_intr188),
-       IDTVEC(apic_intr189),
-       IDTVEC(apic_intr190),
-       IDTVEC(apic_intr191);
-
-static inthand_t *apic_intr[APIC_HWI_VECTORS] = {
-       &IDTVEC(apic_intr0),
-       &IDTVEC(apic_intr1),
-       &IDTVEC(apic_intr2),
-       &IDTVEC(apic_intr3),
-       &IDTVEC(apic_intr4),
-       &IDTVEC(apic_intr5),
-       &IDTVEC(apic_intr6),
-       &IDTVEC(apic_intr7),
-       &IDTVEC(apic_intr8),
-       &IDTVEC(apic_intr9),
-       &IDTVEC(apic_intr10),
-       &IDTVEC(apic_intr11),
-       &IDTVEC(apic_intr12),
-       &IDTVEC(apic_intr13),
-       &IDTVEC(apic_intr14),
-       &IDTVEC(apic_intr15),
-       &IDTVEC(apic_intr16),
-       &IDTVEC(apic_intr17),
-       &IDTVEC(apic_intr18),
-       &IDTVEC(apic_intr19),
-       &IDTVEC(apic_intr20),
-       &IDTVEC(apic_intr21),
-       &IDTVEC(apic_intr22),
-       &IDTVEC(apic_intr23),
-       &IDTVEC(apic_intr24),
-       &IDTVEC(apic_intr25),
-       &IDTVEC(apic_intr26),
-       &IDTVEC(apic_intr27),
-       &IDTVEC(apic_intr28),
-       &IDTVEC(apic_intr29),
-       &IDTVEC(apic_intr30),
-       &IDTVEC(apic_intr31),
-       &IDTVEC(apic_intr32),
-       &IDTVEC(apic_intr33),
-       &IDTVEC(apic_intr34),
-       &IDTVEC(apic_intr35),
-       &IDTVEC(apic_intr36),
-       &IDTVEC(apic_intr37),
-       &IDTVEC(apic_intr38),
-       &IDTVEC(apic_intr39),
-       &IDTVEC(apic_intr40),
-       &IDTVEC(apic_intr41),
-       &IDTVEC(apic_intr42),
-       &IDTVEC(apic_intr43),
-       &IDTVEC(apic_intr44),
-       &IDTVEC(apic_intr45),
-       &IDTVEC(apic_intr46),
-       &IDTVEC(apic_intr47),
-       &IDTVEC(apic_intr48),
-       &IDTVEC(apic_intr49),
-       &IDTVEC(apic_intr50),
-       &IDTVEC(apic_intr51),
-       &IDTVEC(apic_intr52),
-       &IDTVEC(apic_intr53),
-       &IDTVEC(apic_intr54),
-       &IDTVEC(apic_intr55),
-       &IDTVEC(apic_intr56),
-       &IDTVEC(apic_intr57),
-       &IDTVEC(apic_intr58),
-       &IDTVEC(apic_intr59),
-       &IDTVEC(apic_intr60),
-       &IDTVEC(apic_intr61),
-       &IDTVEC(apic_intr62),
-       &IDTVEC(apic_intr63),
-       &IDTVEC(apic_intr64),
-       &IDTVEC(apic_intr65),
-       &IDTVEC(apic_intr66),
-       &IDTVEC(apic_intr67),
-       &IDTVEC(apic_intr68),
-       &IDTVEC(apic_intr69),
-       &IDTVEC(apic_intr70),
-       &IDTVEC(apic_intr71),
-       &IDTVEC(apic_intr72),
-       &IDTVEC(apic_intr73),
-       &IDTVEC(apic_intr74),
-       &IDTVEC(apic_intr75),
-       &IDTVEC(apic_intr76),
-       &IDTVEC(apic_intr77),
-       &IDTVEC(apic_intr78),
-       &IDTVEC(apic_intr79),
-       &IDTVEC(apic_intr80),
-       &IDTVEC(apic_intr81),
-       &IDTVEC(apic_intr82),
-       &IDTVEC(apic_intr83),
-       &IDTVEC(apic_intr84),
-       &IDTVEC(apic_intr85),
-       &IDTVEC(apic_intr86),
-       &IDTVEC(apic_intr87),
-       &IDTVEC(apic_intr88),
-       &IDTVEC(apic_intr89),
-       &IDTVEC(apic_intr90),
-       &IDTVEC(apic_intr91),
-       &IDTVEC(apic_intr92),
-       &IDTVEC(apic_intr93),
-       &IDTVEC(apic_intr94),
-       &IDTVEC(apic_intr95),
-       &IDTVEC(apic_intr96),
-       &IDTVEC(apic_intr97),
-       &IDTVEC(apic_intr98),
-       &IDTVEC(apic_intr99),
-       &IDTVEC(apic_intr100),
-       &IDTVEC(apic_intr101),
-       &IDTVEC(apic_intr102),
-       &IDTVEC(apic_intr103),
-       &IDTVEC(apic_intr104),
-       &IDTVEC(apic_intr105),
-       &IDTVEC(apic_intr106),
-       &IDTVEC(apic_intr107),
-       &IDTVEC(apic_intr108),
-       &IDTVEC(apic_intr109),
-       &IDTVEC(apic_intr110),
-       &IDTVEC(apic_intr111),
-       &IDTVEC(apic_intr112),
-       &IDTVEC(apic_intr113),
-       &IDTVEC(apic_intr114),
-       &IDTVEC(apic_intr115),
-       &IDTVEC(apic_intr116),
-       &IDTVEC(apic_intr117),
-       &IDTVEC(apic_intr118),
-       &IDTVEC(apic_intr119),
-       &IDTVEC(apic_intr120),
-       &IDTVEC(apic_intr121),
-       &IDTVEC(apic_intr122),
-       &IDTVEC(apic_intr123),
-       &IDTVEC(apic_intr124),
-       &IDTVEC(apic_intr125),
-       &IDTVEC(apic_intr126),
-       &IDTVEC(apic_intr127),
-       &IDTVEC(apic_intr128),
-       &IDTVEC(apic_intr129),
-       &IDTVEC(apic_intr130),
-       &IDTVEC(apic_intr131),
-       &IDTVEC(apic_intr132),
-       &IDTVEC(apic_intr133),
-       &IDTVEC(apic_intr134),
-       &IDTVEC(apic_intr135),
-       &IDTVEC(apic_intr136),
-       &IDTVEC(apic_intr137),
-       &IDTVEC(apic_intr138),
-       &IDTVEC(apic_intr139),
-       &IDTVEC(apic_intr140),
-       &IDTVEC(apic_intr141),
-       &IDTVEC(apic_intr142),
-       &IDTVEC(apic_intr143),
-       &IDTVEC(apic_intr144),
-       &IDTVEC(apic_intr145),
-       &IDTVEC(apic_intr146),
-       &IDTVEC(apic_intr147),
-       &IDTVEC(apic_intr148),
-       &IDTVEC(apic_intr149),
-       &IDTVEC(apic_intr150),
-       &IDTVEC(apic_intr151),
-       &IDTVEC(apic_intr152),
-       &IDTVEC(apic_intr153),
-       &IDTVEC(apic_intr154),
-       &IDTVEC(apic_intr155),
-       &IDTVEC(apic_intr156),
-       &IDTVEC(apic_intr157),
-       &IDTVEC(apic_intr158),
-       &IDTVEC(apic_intr159),
-       &IDTVEC(apic_intr160),
-       &IDTVEC(apic_intr161),
-       &IDTVEC(apic_intr162),
-       &IDTVEC(apic_intr163),
-       &IDTVEC(apic_intr164),
-       &IDTVEC(apic_intr165),
-       &IDTVEC(apic_intr166),
-       &IDTVEC(apic_intr167),
-       &IDTVEC(apic_intr168),
-       &IDTVEC(apic_intr169),
-       &IDTVEC(apic_intr170),
-       &IDTVEC(apic_intr171),
-       &IDTVEC(apic_intr172),
-       &IDTVEC(apic_intr173),
-       &IDTVEC(apic_intr174),
-       &IDTVEC(apic_intr175),
-       &IDTVEC(apic_intr176),
-       &IDTVEC(apic_intr177),
-       &IDTVEC(apic_intr178),
-       &IDTVEC(apic_intr179),
-       &IDTVEC(apic_intr180),
-       &IDTVEC(apic_intr181),
-       &IDTVEC(apic_intr182),
-       &IDTVEC(apic_intr183),
-       &IDTVEC(apic_intr184),
-       &IDTVEC(apic_intr185),
-       &IDTVEC(apic_intr186),
-       &IDTVEC(apic_intr187),
-       &IDTVEC(apic_intr188),
-       &IDTVEC(apic_intr189),
-       &IDTVEC(apic_intr190),
-       &IDTVEC(apic_intr191)
+       IDTVEC(ioapic_intr0),
+       IDTVEC(ioapic_intr1),
+       IDTVEC(ioapic_intr2),
+       IDTVEC(ioapic_intr3),
+       IDTVEC(ioapic_intr4),
+       IDTVEC(ioapic_intr5),
+       IDTVEC(ioapic_intr6),
+       IDTVEC(ioapic_intr7),
+       IDTVEC(ioapic_intr8),
+       IDTVEC(ioapic_intr9),
+       IDTVEC(ioapic_intr10),
+       IDTVEC(ioapic_intr11),
+       IDTVEC(ioapic_intr12),
+       IDTVEC(ioapic_intr13),
+       IDTVEC(ioapic_intr14),
+       IDTVEC(ioapic_intr15),
+       IDTVEC(ioapic_intr16),
+       IDTVEC(ioapic_intr17),
+       IDTVEC(ioapic_intr18),
+       IDTVEC(ioapic_intr19),
+       IDTVEC(ioapic_intr20),
+       IDTVEC(ioapic_intr21),
+       IDTVEC(ioapic_intr22),
+       IDTVEC(ioapic_intr23),
+       IDTVEC(ioapic_intr24),
+       IDTVEC(ioapic_intr25),
+       IDTVEC(ioapic_intr26),
+       IDTVEC(ioapic_intr27),
+       IDTVEC(ioapic_intr28),
+       IDTVEC(ioapic_intr29),
+       IDTVEC(ioapic_intr30),
+       IDTVEC(ioapic_intr31),
+       IDTVEC(ioapic_intr32),
+       IDTVEC(ioapic_intr33),
+       IDTVEC(ioapic_intr34),
+       IDTVEC(ioapic_intr35),
+       IDTVEC(ioapic_intr36),
+       IDTVEC(ioapic_intr37),
+       IDTVEC(ioapic_intr38),
+       IDTVEC(ioapic_intr39),
+       IDTVEC(ioapic_intr40),
+       IDTVEC(ioapic_intr41),
+       IDTVEC(ioapic_intr42),
+       IDTVEC(ioapic_intr43),
+       IDTVEC(ioapic_intr44),
+       IDTVEC(ioapic_intr45),
+       IDTVEC(ioapic_intr46),
+       IDTVEC(ioapic_intr47),
+       IDTVEC(ioapic_intr48),
+       IDTVEC(ioapic_intr49),
+       IDTVEC(ioapic_intr50),
+       IDTVEC(ioapic_intr51),
+       IDTVEC(ioapic_intr52),
+       IDTVEC(ioapic_intr53),
+       IDTVEC(ioapic_intr54),
+       IDTVEC(ioapic_intr55),
+       IDTVEC(ioapic_intr56),
+       IDTVEC(ioapic_intr57),
+       IDTVEC(ioapic_intr58),
+       IDTVEC(ioapic_intr59),
+       IDTVEC(ioapic_intr60),
+       IDTVEC(ioapic_intr61),
+       IDTVEC(ioapic_intr62),
+       IDTVEC(ioapic_intr63),
+       IDTVEC(ioapic_intr64),
+       IDTVEC(ioapic_intr65),
+       IDTVEC(ioapic_intr66),
+       IDTVEC(ioapic_intr67),
+       IDTVEC(ioapic_intr68),
+       IDTVEC(ioapic_intr69),
+       IDTVEC(ioapic_intr70),
+       IDTVEC(ioapic_intr71),
+       IDTVEC(ioapic_intr72),
+       IDTVEC(ioapic_intr73),
+       IDTVEC(ioapic_intr74),
+       IDTVEC(ioapic_intr75),
+       IDTVEC(ioapic_intr76),
+       IDTVEC(ioapic_intr77),
+       IDTVEC(ioapic_intr78),
+       IDTVEC(ioapic_intr79),
+       IDTVEC(ioapic_intr80),
+       IDTVEC(ioapic_intr81),
+       IDTVEC(ioapic_intr82),
+       IDTVEC(ioapic_intr83),
+       IDTVEC(ioapic_intr84),
+       IDTVEC(ioapic_intr85),
+       IDTVEC(ioapic_intr86),
+       IDTVEC(ioapic_intr87),
+       IDTVEC(ioapic_intr88),
+       IDTVEC(ioapic_intr89),
+       IDTVEC(ioapic_intr90),
+       IDTVEC(ioapic_intr91),
+       IDTVEC(ioapic_intr92),
+       IDTVEC(ioapic_intr93),
+       IDTVEC(ioapic_intr94),
+       IDTVEC(ioapic_intr95),
+       IDTVEC(ioapic_intr96),
+       IDTVEC(ioapic_intr97),
+       IDTVEC(ioapic_intr98),
+       IDTVEC(ioapic_intr99),
+       IDTVEC(ioapic_intr100),
+       IDTVEC(ioapic_intr101),
+       IDTVEC(ioapic_intr102),
+       IDTVEC(ioapic_intr103),
+       IDTVEC(ioapic_intr104),
+       IDTVEC(ioapic_intr105),
+       IDTVEC(ioapic_intr106),
+       IDTVEC(ioapic_intr107),
+       IDTVEC(ioapic_intr108),
+       IDTVEC(ioapic_intr109),
+       IDTVEC(ioapic_intr110),
+       IDTVEC(ioapic_intr111),
+       IDTVEC(ioapic_intr112),
+       IDTVEC(ioapic_intr113),
+       IDTVEC(ioapic_intr114),
+       IDTVEC(ioapic_intr115),
+       IDTVEC(ioapic_intr116),
+       IDTVEC(ioapic_intr117),
+       IDTVEC(ioapic_intr118),
+       IDTVEC(ioapic_intr119),
+       IDTVEC(ioapic_intr120),
+       IDTVEC(ioapic_intr121),
+       IDTVEC(ioapic_intr122),
+       IDTVEC(ioapic_intr123),
+       IDTVEC(ioapic_intr124),
+       IDTVEC(ioapic_intr125),
+       IDTVEC(ioapic_intr126),
+       IDTVEC(ioapic_intr127),
+       IDTVEC(ioapic_intr128),
+       IDTVEC(ioapic_intr129),
+       IDTVEC(ioapic_intr130),
+       IDTVEC(ioapic_intr131),
+       IDTVEC(ioapic_intr132),
+       IDTVEC(ioapic_intr133),
+       IDTVEC(ioapic_intr134),
+       IDTVEC(ioapic_intr135),
+       IDTVEC(ioapic_intr136),
+       IDTVEC(ioapic_intr137),
+       IDTVEC(ioapic_intr138),
+       IDTVEC(ioapic_intr139),
+       IDTVEC(ioapic_intr140),
+       IDTVEC(ioapic_intr141),
+       IDTVEC(ioapic_intr142),
+       IDTVEC(ioapic_intr143),
+       IDTVEC(ioapic_intr144),
+       IDTVEC(ioapic_intr145),
+       IDTVEC(ioapic_intr146),
+       IDTVEC(ioapic_intr147),
+       IDTVEC(ioapic_intr148),
+       IDTVEC(ioapic_intr149),
+       IDTVEC(ioapic_intr150),
+       IDTVEC(ioapic_intr151),
+       IDTVEC(ioapic_intr152),
+       IDTVEC(ioapic_intr153),
+       IDTVEC(ioapic_intr154),
+       IDTVEC(ioapic_intr155),
+       IDTVEC(ioapic_intr156),
+       IDTVEC(ioapic_intr157),
+       IDTVEC(ioapic_intr158),
+       IDTVEC(ioapic_intr159),
+       IDTVEC(ioapic_intr160),
+       IDTVEC(ioapic_intr161),
+       IDTVEC(ioapic_intr162),
+       IDTVEC(ioapic_intr163),
+       IDTVEC(ioapic_intr164),
+       IDTVEC(ioapic_intr165),
+       IDTVEC(ioapic_intr166),
+       IDTVEC(ioapic_intr167),
+       IDTVEC(ioapic_intr168),
+       IDTVEC(ioapic_intr169),
+       IDTVEC(ioapic_intr170),
+       IDTVEC(ioapic_intr171),
+       IDTVEC(ioapic_intr172),
+       IDTVEC(ioapic_intr173),
+       IDTVEC(ioapic_intr174),
+       IDTVEC(ioapic_intr175),
+       IDTVEC(ioapic_intr176),
+       IDTVEC(ioapic_intr177),
+       IDTVEC(ioapic_intr178),
+       IDTVEC(ioapic_intr179),
+       IDTVEC(ioapic_intr180),
+       IDTVEC(ioapic_intr181),
+       IDTVEC(ioapic_intr182),
+       IDTVEC(ioapic_intr183),
+       IDTVEC(ioapic_intr184),
+       IDTVEC(ioapic_intr185),
+       IDTVEC(ioapic_intr186),
+       IDTVEC(ioapic_intr187),
+       IDTVEC(ioapic_intr188),
+       IDTVEC(ioapic_intr189),
+       IDTVEC(ioapic_intr190),
+       IDTVEC(ioapic_intr191);
+
+static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
+       &IDTVEC(ioapic_intr0),
+       &IDTVEC(ioapic_intr1),
+       &IDTVEC(ioapic_intr2),
+       &IDTVEC(ioapic_intr3),
+       &IDTVEC(ioapic_intr4),
+       &IDTVEC(ioapic_intr5),
+       &IDTVEC(ioapic_intr6),
+       &IDTVEC(ioapic_intr7),
+       &IDTVEC(ioapic_intr8),
+       &IDTVEC(ioapic_intr9),
+       &IDTVEC(ioapic_intr10),
+       &IDTVEC(ioapic_intr11),
+       &IDTVEC(ioapic_intr12),
+       &IDTVEC(ioapic_intr13),
+       &IDTVEC(ioapic_intr14),
+       &IDTVEC(ioapic_intr15),
+       &IDTVEC(ioapic_intr16),
+       &IDTVEC(ioapic_intr17),
+       &IDTVEC(ioapic_intr18),
+       &IDTVEC(ioapic_intr19),
+       &IDTVEC(ioapic_intr20),
+       &IDTVEC(ioapic_intr21),
+       &IDTVEC(ioapic_intr22),
+       &IDTVEC(ioapic_intr23),
+       &IDTVEC(ioapic_intr24),
+       &IDTVEC(ioapic_intr25),
+       &IDTVEC(ioapic_intr26),
+       &IDTVEC(ioapic_intr27),
+       &IDTVEC(ioapic_intr28),
+       &IDTVEC(ioapic_intr29),
+       &IDTVEC(ioapic_intr30),
+       &IDTVEC(ioapic_intr31),
+       &IDTVEC(ioapic_intr32),
+       &IDTVEC(ioapic_intr33),
+       &IDTVEC(ioapic_intr34),
+       &IDTVEC(ioapic_intr35),
+       &IDTVEC(ioapic_intr36),
+       &IDTVEC(ioapic_intr37),
+       &IDTVEC(ioapic_intr38),
+       &IDTVEC(ioapic_intr39),
+       &IDTVEC(ioapic_intr40),
+       &IDTVEC(ioapic_intr41),
+       &IDTVEC(ioapic_intr42),
+       &IDTVEC(ioapic_intr43),
+       &IDTVEC(ioapic_intr44),
+       &IDTVEC(ioapic_intr45),
+       &IDTVEC(ioapic_intr46),
+       &IDTVEC(ioapic_intr47),
+       &IDTVEC(ioapic_intr48),
+       &IDTVEC(ioapic_intr49),
+       &IDTVEC(ioapic_intr50),
+       &IDTVEC(ioapic_intr51),
+       &IDTVEC(ioapic_intr52),
+       &IDTVEC(ioapic_intr53),
+       &IDTVEC(ioapic_intr54),
+       &IDTVEC(ioapic_intr55),
+       &IDTVEC(ioapic_intr56),
+       &IDTVEC(ioapic_intr57),
+       &IDTVEC(ioapic_intr58),
+       &IDTVEC(ioapic_intr59),
+       &IDTVEC(ioapic_intr60),
+       &IDTVEC(ioapic_intr61),
+       &IDTVEC(ioapic_intr62),
+       &IDTVEC(ioapic_intr63),
+       &IDTVEC(ioapic_intr64),
+       &IDTVEC(ioapic_intr65),
+       &IDTVEC(ioapic_intr66),
+       &IDTVEC(ioapic_intr67),
+       &IDTVEC(ioapic_intr68),
+       &IDTVEC(ioapic_intr69),
+       &IDTVEC(ioapic_intr70),
+       &IDTVEC(ioapic_intr71),
+       &IDTVEC(ioapic_intr72),
+       &IDTVEC(ioapic_intr73),
+       &IDTVEC(ioapic_intr74),
+       &IDTVEC(ioapic_intr75),
+       &IDTVEC(ioapic_intr76),
+       &IDTVEC(ioapic_intr77),
+       &IDTVEC(ioapic_intr78),
+       &IDTVEC(ioapic_intr79),
+       &IDTVEC(ioapic_intr80),
+       &IDTVEC(ioapic_intr81),
+       &IDTVEC(ioapic_intr82),
+       &IDTVEC(ioapic_intr83),
+       &IDTVEC(ioapic_intr84),
+       &IDTVEC(ioapic_intr85),
+       &IDTVEC(ioapic_intr86),
+       &IDTVEC(ioapic_intr87),
+       &IDTVEC(ioapic_intr88),
+       &IDTVEC(ioapic_intr89),
+       &IDTVEC(ioapic_intr90),
+       &IDTVEC(ioapic_intr91),
+       &IDTVEC(ioapic_intr92),
+       &IDTVEC(ioapic_intr93),
+       &IDTVEC(ioapic_intr94),
+       &IDTVEC(ioapic_intr95),
+       &IDTVEC(ioapic_intr96),
+       &IDTVEC(ioapic_intr97),
+       &IDTVEC(ioapic_intr98),
+       &IDTVEC(ioapic_intr99),
+       &IDTVEC(ioapic_intr100),
+       &IDTVEC(ioapic_intr101),
+       &IDTVEC(ioapic_intr102),
+       &IDTVEC(ioapic_intr103),
+       &IDTVEC(ioapic_intr104),
+       &IDTVEC(ioapic_intr105),
+       &IDTVEC(ioapic_intr106),
+       &IDTVEC(ioapic_intr107),
+       &IDTVEC(ioapic_intr108),
+       &IDTVEC(ioapic_intr109),
+       &IDTVEC(ioapic_intr110),
+       &IDTVEC(ioapic_intr111),
+       &IDTVEC(ioapic_intr112),
+       &IDTVEC(ioapic_intr113),
+       &IDTVEC(ioapic_intr114),
+       &IDTVEC(ioapic_intr115),
+       &IDTVEC(ioapic_intr116),
+       &IDTVEC(ioapic_intr117),
+       &IDTVEC(ioapic_intr118),
+       &IDTVEC(ioapic_intr119),
+       &IDTVEC(ioapic_intr120),
+       &IDTVEC(ioapic_intr121),
+       &IDTVEC(ioapic_intr122),
+       &IDTVEC(ioapic_intr123),
+       &IDTVEC(ioapic_intr124),
+       &IDTVEC(ioapic_intr125),
+       &IDTVEC(ioapic_intr126),
+       &IDTVEC(ioapic_intr127),
+       &IDTVEC(ioapic_intr128),
+       &IDTVEC(ioapic_intr129),
+       &IDTVEC(ioapic_intr130),
+       &IDTVEC(ioapic_intr131),
+       &IDTVEC(ioapic_intr132),
+       &IDTVEC(ioapic_intr133),
+       &IDTVEC(ioapic_intr134),
+       &IDTVEC(ioapic_intr135),
+       &IDTVEC(ioapic_intr136),
+       &IDTVEC(ioapic_intr137),
+       &IDTVEC(ioapic_intr138),
+       &IDTVEC(ioapic_intr139),
+       &IDTVEC(ioapic_intr140),
+       &IDTVEC(ioapic_intr141),
+       &IDTVEC(ioapic_intr142),
+       &IDTVEC(ioapic_intr143),
+       &IDTVEC(ioapic_intr144),
+       &IDTVEC(ioapic_intr145),
+       &IDTVEC(ioapic_intr146),
+       &IDTVEC(ioapic_intr147),
+       &IDTVEC(ioapic_intr148),
+       &IDTVEC(ioapic_intr149),
+       &IDTVEC(ioapic_intr150),
+       &IDTVEC(ioapic_intr151),
+       &IDTVEC(ioapic_intr152),
+       &IDTVEC(ioapic_intr153),
+       &IDTVEC(ioapic_intr154),
+       &IDTVEC(ioapic_intr155),
+       &IDTVEC(ioapic_intr156),
+       &IDTVEC(ioapic_intr157),
+       &IDTVEC(ioapic_intr158),
+       &IDTVEC(ioapic_intr159),
+       &IDTVEC(ioapic_intr160),
+       &IDTVEC(ioapic_intr161),
+       &IDTVEC(ioapic_intr162),
+       &IDTVEC(ioapic_intr163),
+       &IDTVEC(ioapic_intr164),
+       &IDTVEC(ioapic_intr165),
+       &IDTVEC(ioapic_intr166),
+       &IDTVEC(ioapic_intr167),
+       &IDTVEC(ioapic_intr168),
+       &IDTVEC(ioapic_intr169),
+       &IDTVEC(ioapic_intr170),
+       &IDTVEC(ioapic_intr171),
+       &IDTVEC(ioapic_intr172),
+       &IDTVEC(ioapic_intr173),
+       &IDTVEC(ioapic_intr174),
+       &IDTVEC(ioapic_intr175),
+       &IDTVEC(ioapic_intr176),
+       &IDTVEC(ioapic_intr177),
+       &IDTVEC(ioapic_intr178),
+       &IDTVEC(ioapic_intr179),
+       &IDTVEC(ioapic_intr180),
+       &IDTVEC(ioapic_intr181),
+       &IDTVEC(ioapic_intr182),
+       &IDTVEC(ioapic_intr183),
+       &IDTVEC(ioapic_intr184),
+       &IDTVEC(ioapic_intr185),
+       &IDTVEC(ioapic_intr186),
+       &IDTVEC(ioapic_intr187),
+       &IDTVEC(ioapic_intr188),
+       &IDTVEC(ioapic_intr189),
+       &IDTVEC(ioapic_intr190),
+       &IDTVEC(ioapic_intr191)
 };
 
-extern void    APIC_INTREN(int);
-extern void    APIC_INTRDIS(int);
-
-static int     apic_setvar(int, const void *);
-static int     apic_getvar(int, void *);
-static int     apic_vectorctl(int, int, int);
-static void    apic_finalize(void);
-static void    apic_cleanup(void);
-static void    apic_setdefault(void);
-
-static int     apic_imcr_present;
-
-struct machintr_abi MachIntrABI_APIC = {
-       MACHINTR_APIC,
-       .intrdis        = APIC_INTRDIS,
-       .intren         = APIC_INTREN,
-       .vectorctl      = apic_vectorctl,
-       .setvar         = apic_setvar,
-       .getvar         = apic_getvar,
-       .finalize       = apic_finalize,
-       .cleanup        = apic_cleanup,
-       .setdefault     = apic_setdefault
+extern void    IOAPIC_INTREN(int);
+extern void    IOAPIC_INTRDIS(int);
+
+static int     ioapic_setvar(int, const void *);
+static int     ioapic_getvar(int, void *);
+static int     ioapic_vectorctl(int, int, int);
+static void    ioapic_finalize(void);
+static void    ioapic_cleanup(void);
+static void    ioapic_setdefault(void);
+
+static int     ioapic_imcr_present;
+
+struct machintr_abi MachIntrABI_IOAPIC = {
+       MACHINTR_IOAPIC,
+       .intrdis        = IOAPIC_INTRDIS,
+       .intren         = IOAPIC_INTREN,
+       .vectorctl      = ioapic_vectorctl,
+       .setvar         = ioapic_setvar,
+       .getvar         = ioapic_getvar,
+       .finalize       = ioapic_finalize,
+       .cleanup        = ioapic_cleanup,
+       .setdefault     = ioapic_setdefault
 };
 
 static int
-apic_setvar(int varid, const void *buf)
+ioapic_setvar(int varid, const void *buf)
 {
        int error = 0;
 
        switch(varid) {
        case MACHINTR_VAR_IMCR_PRESENT:
-               apic_imcr_present = *(const int *)buf;
+               ioapic_imcr_present = *(const int *)buf;
                break;
 
        default:
@@ -491,13 +491,13 @@ apic_setvar(int varid, const void *buf)
 }
 
 static int
-apic_getvar(int varid, void *buf)
+ioapic_getvar(int varid, void *buf)
 {
        int error = 0;
 
        switch(varid) {
        case MACHINTR_VAR_IMCR_PRESENT:
-               *(int *)buf = apic_imcr_present;
+               *(int *)buf = ioapic_imcr_present;
                break;
 
        default:
@@ -516,7 +516,7 @@ apic_getvar(int varid, void *buf)
  *  - enable NMI.
  */
 static void
-apic_finalize(void)
+ioapic_finalize(void)
 {
        uint32_t temp;
 
@@ -528,7 +528,7 @@ apic_finalize(void)
         * from the BSP.  The 8259 may still be connected to LINT0 on
         * the BSP's LAPIC.
         */
-       if (apic_imcr_present) {
+       if (ioapic_imcr_present) {
                outb(0x22, 0x70);       /* select IMCR */
                outb(0x23, 0x01);       /* disconnect 8259 */
        }
@@ -546,7 +546,7 @@ apic_finalize(void)
         * 8259 is completely disconnected; switch to IOAPIC MachIntrABI
         * and reconfigure the default IDT entries.
         */
-       MachIntrABI = MachIntrABI_APIC;
+       MachIntrABI = MachIntrABI_IOAPIC;
        MachIntrABI.setdefault();
 
        /*
@@ -566,13 +566,13 @@ apic_finalize(void)
  * that had already been posted to the cpu.
  */
 static void
-apic_cleanup(void)
+ioapic_cleanup(void)
 {
        bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
 }
 
 static int
-apic_vectorctl(int op, int intr, int flags)
+ioapic_vectorctl(int op, int intr, int flags)
 {
        int error;
        int vector;
@@ -580,7 +580,7 @@ apic_vectorctl(int op, int intr, int flags)
        uint32_t value;
        u_long ef;
 
-       if (intr < 0 || intr >= APIC_HWI_VECTORS ||
+       if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
            intr == IDT_OFFSET_SYSCALL - IDT_OFFSET)
                return EINVAL;
 
@@ -591,7 +591,7 @@ apic_vectorctl(int op, int intr, int flags)
        switch(op) {
        case MACHINTR_VECTOR_SETUP:
                vector = IDT_OFFSET + intr;
-               setidt(vector, apic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
+               setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
 
                /*
                 * Now reprogram the vector in the IO APIC.  In order to avoid
@@ -604,14 +604,14 @@ apic_vectorctl(int op, int intr, int flags)
                        imen_lock();
 
                        select = int_to_apicintpin[intr].redirindex;
-                       value = io_apic_read(int_to_apicintpin[intr].ioapic,
-                                            select);
+                       value = ioapic_read(int_to_apicintpin[intr].ioapic,
+                                           select);
                        value |= IOART_INTMSET;
 
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~APIC_TRIGMOD_MASK));
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~IOART_INTVEC) | vector);
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~APIC_TRIGMOD_MASK));
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~IOART_INTVEC) | vector);
 
                        imen_unlock();
                }
@@ -627,7 +627,7 @@ apic_vectorctl(int op, int intr, int flags)
                machintr_intrdis(intr);
 
                vector = IDT_OFFSET + intr;
-               setidt(vector, apic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
+               setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
 
                /*
                 * In order to avoid losing an EOI for a level interrupt, which
@@ -639,13 +639,13 @@ apic_vectorctl(int op, int intr, int flags)
                        imen_lock();
 
                        select = int_to_apicintpin[intr].redirindex;
-                       value = io_apic_read(int_to_apicintpin[intr].ioapic,
-                                            select);
+                       value = ioapic_read(int_to_apicintpin[intr].ioapic,
+                                           select);
 
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~APIC_TRIGMOD_MASK));
-                       io_apic_write(int_to_apicintpin[intr].ioapic,
-                                     select, (value & ~IOART_INTVEC) | vector);
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~APIC_TRIGMOD_MASK));
+                       ioapic_write(int_to_apicintpin[intr].ioapic,
+                                    select, (value & ~IOART_INTVEC) | vector);
 
                        imen_unlock();
                }
@@ -661,14 +661,14 @@ apic_vectorctl(int op, int intr, int flags)
 }
 
 static void
-apic_setdefault(void)
+ioapic_setdefault(void)
 {
        int intr;
 
-       for (intr = 0; intr < APIC_HWI_VECTORS; ++intr) {
+       for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
                if (intr == IDT_OFFSET_SYSCALL - IDT_OFFSET)
                        continue;
-               setidt(IDT_OFFSET + intr, apic_intr[intr], SDT_SYSIGT,
+               setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
                       SEL_KPL, 0);
        }
 }
index 3981574..d8157de 100644 (file)
@@ -32,7 +32,7 @@
 
 #ifdef SMP /* APIC-IO */
 
-#define APIC_HWI_VECTORS 192
+#define IOAPIC_HWI_VECTORS 192
 
 #endif
 
 /*
  * Interrupts may or may not be disabled when using these functions.
  */
-#define APIC_IMASK_LOCK                                                        \
+#define IOAPIC_IMASK_LOCK                                              \
         SPIN_LOCK(imen_spinlock) ;                                     \
 
-#define APIC_IMASK_UNLOCK                                              \
+#define IOAPIC_IMASK_UNLOCK                                            \
         SPIN_UNLOCK(imen_spinlock) ;                                   \
 
 #endif
index 2bb52f3..7b54ac3 100644 (file)
@@ -75,8 +75,8 @@
         * Functions to enable and disable a hardware interrupt.  The
         * IRQ number is passed as an argument.
         */
-ENTRY(APIC_INTRDIS)
-       APIC_IMASK_LOCK                 /* enter critical reg */
+ENTRY(IOAPIC_INTRDIS)
+       IOAPIC_IMASK_LOCK               /* enter critical reg */
        movl    %edi, %eax
 1:
        shll    $IOAPIC_IM_SZSHIFT, %eax
@@ -87,13 +87,13 @@ ENTRY(APIC_INTRDIS)
        jz      2f
        movl    %ecx, (%rdx)            /* target register index */
        orl     $IOART_INTMASK, IOAPIC_WINDOW(%rdx)
-                                       /* set intmask in target apic reg */
+                                       /* set intmask in target ioapic reg */
 2:
-       APIC_IMASK_UNLOCK               /* exit critical reg */
+       IOAPIC_IMASK_UNLOCK             /* exit critical reg */
        ret
 
-ENTRY(APIC_INTREN)
-       APIC_IMASK_LOCK                 /* enter critical reg */
+ENTRY(IOAPIC_INTREN)
+       IOAPIC_IMASK_LOCK               /* enter critical reg */
        movl    %edi, %eax
 1:
        shll    $IOAPIC_IM_SZSHIFT, %eax
@@ -106,7 +106,7 @@ ENTRY(APIC_INTREN)
        andl    $~IOART_INTMASK, IOAPIC_WINDOW(%rdx)
                                        /* clear mask bit */
 2:     
-       APIC_IMASK_UNLOCK               /* exit critical reg */
+       IOAPIC_IMASK_UNLOCK             /* exit critical reg */
        ret
 
 /******************************************************************************
@@ -114,24 +114,24 @@ ENTRY(APIC_INTREN)
  */
 
 /*
- * u_int io_apic_read(int apic, int select);
+ * u_int ioapic_read(int apic, int select);
  */
-ENTRY(io_apic_read)
-       movl    %edi, %ecx              /* APIC # */
+ENTRY(ioapic_read)
+       movl    %edi, %ecx              /* IOAPIC # */
        movq    ioapic, %rax
-       movq    (%rax,%rcx,8), %rdx     /* APIC base register address */
+       movq    (%rax,%rcx,8), %rdx     /* IOAPIC base register address */
        movl    %esi, (%rdx)            /* write the target register index */
-       movl    IOAPIC_WINDOW(%rdx), %eax /* read the APIC register data */
+       movl    IOAPIC_WINDOW(%rdx), %eax /* read the IOAPIC register data */
        ret                             /* %eax = register value */
 
 /*
- * void io_apic_write(int apic, int select, u_int value);
+ * void ioapic_write(int apic, int select, u_int value);
  */
-ENTRY(io_apic_write)
-       movl    %edi, %ecx              /* APIC # */
+ENTRY(ioapic_write)
+       movl    %edi, %ecx              /* IOAPIC # */
        movq    ioapic, %rax
-       movq    (%rax,%rcx,8), %r8      /* APIC base register address */
+       movq    (%rax,%rcx,8), %r8      /* IOAPIC base register address */
        movl    %esi, (%r8)             /* write the target register index */
-       movl    %edx, IOAPIC_WINDOW(%r8) /* write the APIC register data */
+       movl    %edx, IOAPIC_WINDOW(%r8) /* write the IOAPIC register data */
        ret                             /* %eax = void */
 #endif
index 3603069..6248e29 100644 (file)
@@ -63,7 +63,7 @@
        CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_FLAGS
  
 #define MASK_IRQ(irq_num)                                              \
-       APIC_IMASK_LOCK ;                       /* into critical reg */ \
+       IOAPIC_IMASK_LOCK ;                     /* into critical reg */ \
        testl   $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
        jne     7f ;                    /* masked, don't mask */        \
        orl     $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
@@ -73,7 +73,7 @@
        movl    %eax, (%rcx) ;                  /* write the index */   \
        orl     $IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* set the mask */  \
 7: ;                                           /* already masked */    \
-       APIC_IMASK_UNLOCK ;                                             \
+       IOAPIC_IMASK_UNLOCK ;                                           \
 
 /*
  * Test to see whether we are handling an edge or level triggered INT.
@@ -92,7 +92,7 @@
 #define UNMASK_IRQ(irq_num)                                    \
        cmpl    $0,%eax ;                                               \
        jnz     8f ;                                                    \
-       APIC_IMASK_LOCK ;                       /* into critical reg */ \
+       IOAPIC_IMASK_LOCK ;                     /* into critical reg */ \
        testl   $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;          \
        je      7f ;                    /* bit clear, not masked */     \
        andl    $~IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ;         \
        movl    %eax,(%rcx) ;                   /* write the index */   \
        andl    $~IOART_INTMASK,IOAPIC_WINDOW(%rcx) ;/* clear the mask */ \
 7: ;                                                                   \
-       APIC_IMASK_UNLOCK ;                                             \
+       IOAPIC_IMASK_UNLOCK ;                                           \
 8: ;                                                                   \
 
 #ifdef SMP /* APIC-IO */
 #define        INTR_HANDLER(irq_num)                                           \
        .text ;                                                         \
        SUPERALIGN_TEXT ;                                               \
-IDTVEC(apic_intr##irq_num) ;                                           \
+IDTVEC(ioapic_intr##irq_num) ;                                         \
        APIC_PUSH_FRAME ;                                               \
        FAKE_MCOUNT(TF_RIP(%rsp)) ;                                     \
        MASK_LEVEL_IRQ(irq_num) ;                                       \
similarity index 51%
copy from sys/sys/machintr.h
copy to sys/platform/pc64/apic/ioapic_abi.h
index 4254666..0e6f843 100644 (file)
@@ -1,8 +1,14 @@
 /*
- * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
+ * Copyright (c) 1991 The Regents of the University of California.
+ * Copyright (c) 1996, by Steve Passe.  All rights reserved.
+ * Copyright (c) 2005,2008 The DragonFly Project.  All rights reserved.
+ * All rights reserved.
  * 
  * This code is derived from software contributed to The DragonFly Project
  * by Matthew Dillon <dillon@backplane.com>
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
  * 
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- * 
- * $DragonFly: src/sys/sys/machintr.h,v 1.7 2007/04/30 16:46:01 dillon Exp $
- */
-/*
- * This module defines the ABI for the machine-independant cpu interrupt
- * vector and masking layer.
- */
-
-#ifndef _SYS_QUEUE_H_
-#include <sys/queue.h>
-#endif
-
-enum machintr_type { MACHINTR_GENERIC, MACHINTR_ICU, MACHINTR_APIC };
-
-#define MACHINTR_VAR_SIZEMASK  0xFFFF
-
-#define MACHINTR_VAR_IMCR_PRESENT      (0x00010000|sizeof(int))
-
-#define MACHINTR_VECTOR_SETUP          1
-#define MACHINTR_VECTOR_TEARDOWN       2
-
-/*
- * Machine interrupt ABIs - registered at boot-time
  */
-struct machintr_abi {
-    enum machintr_type type;
-    void       (*intrdis)(int);                /* hardware disable irq */
-    void       (*intren)(int);                 /* hardware enable irq */
-    int                (*vectorctl)(int, int, int);    /* hardware intr vector ctl */
-    int                (*setvar)(int, const void *);   /* set miscellanious info */
-    int                (*getvar)(int, void *);         /* get miscellanious info */
-    void       (*finalize)(void);              /* final before ints enabled */
-    void       (*cleanup)(void);               /* cleanup */
-    void       (*setdefault)(void);            /* set default vectors */
-};
-
-#define machintr_intren(intr)  MachIntrABI.intren(intr)
-#define machintr_intrdis(intr) MachIntrABI.intrdis(intr)
-#define machintr_vector_setup(intr, flags)     \
-           MachIntrABI.vectorctl(MACHINTR_VECTOR_SETUP, intr, flags)
-#define machintr_vector_teardown(intr)         \
-           MachIntrABI.vectorctl(MACHINTR_VECTOR_TEARDOWN, intr, 0)
 
-#ifdef _KERNEL
+#ifndef _ARCH_APIC_IOAPIC_ABI_H_
+#define _ARCH_APIC_IOAPIC_ABI_H_
 
-extern struct machintr_abi MachIntrABI;
-extern int machintr_setvar_simple(int, int);
+extern struct machintr_abi MachIntrABI_IOAPIC;
 
-#endif
+#endif /* !_ARCH_APIC_IOAPIC_ABI_H_ */
index d9e474f..cda5dcf 100644 (file)
@@ -500,15 +500,15 @@ io_apic_set_id(int apic, int id)
 {
        u_int32_t ux;
        
-       ux = io_apic_read(apic, IOAPIC_ID);     /* get current contents */
+       ux = ioapic_read(apic, IOAPIC_ID);      /* get current contents */
        if (((ux & APIC_ID_MASK) >> 24) != id) {
                kprintf("Changing APIC ID for IO APIC #%d"
                       " from %d to %d on chip\n",
                       apic, ((ux & APIC_ID_MASK) >> 24), id);
                ux &= ~APIC_ID_MASK;    /* clear the ID field */
                ux |= (id << 24);
-               io_apic_write(apic, IOAPIC_ID, ux);     /* write new value */
-               ux = io_apic_read(apic, IOAPIC_ID);     /* re-read && test */
+               ioapic_write(apic, IOAPIC_ID, ux);      /* write new value */
+               ux = ioapic_read(apic, IOAPIC_ID);      /* re-read && test */
                if (((ux & APIC_ID_MASK) >> 24) != id)
                        panic("can't control IO APIC #%d ID, reg: 0x%08x",
                              apic, ux);
@@ -519,7 +519,7 @@ io_apic_set_id(int apic, int id)
 int
 io_apic_get_id(int apic)
 {
-  return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
+  return (ioapic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
 }
   
 
@@ -555,17 +555,17 @@ io_apic_setup_intpin(int apic, int pin)
         */
        imen_lock();
 
-       flags = io_apic_read(apic, select) & IOART_RESV;
+       flags = ioapic_read(apic, select) & IOART_RESV;
        flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
        flags |= IOART_DESTPHY | IOART_DELFIXED;
 
-       target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
+       target = ioapic_read(apic, select + 1) & IOART_HI_DEST_RESV;
        target |= 0;    /* fixed mode cpu mask of 0 - don't deliver anywhere */
 
        vector = 0;
 
-       io_apic_write(apic, select, flags | vector);
-       io_apic_write(apic, select + 1, target);
+       ioapic_write(apic, select, flags | vector);
+       ioapic_write(apic, select + 1, target);
 
        imen_unlock();
 
@@ -641,13 +641,13 @@ io_apic_setup_intpin(int apic, int pin)
        imen_lock();
 
        vector = IDT_OFFSET + irq;                      /* IDT vec */
-       target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
+       target = ioapic_read(apic, select + 1) & IOART_HI_DEST_RESV;
        /* Deliver all interrupts to CPU0 (BSP) */
        target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
                  IOART_HI_DEST_MASK;
-       flags |= io_apic_read(apic, select) & IOART_RESV;
-       io_apic_write(apic, select, flags | vector);
-       io_apic_write(apic, select + 1, target);
+       flags |= ioapic_read(apic, select) & IOART_RESV;
+       ioapic_write(apic, select, flags | vector);
+       ioapic_write(apic, select + 1, target);
 
        imen_unlock();
 }
@@ -719,8 +719,8 @@ ext_int_setup(int apic, int intr)
        vector = IDT_OFFSET + intr;
        flags = DEFAULT_EXTINT_FLAGS;
 
-       io_apic_write(apic, select, flags | vector);
-       io_apic_write(apic, select + 1, target);
+       ioapic_write(apic, select, flags | vector);
+       ioapic_write(apic, select + 1, target);
 
        return 0;
 }
index 751dace..6312c43 100644 (file)
 
 #include <sys/thread2.h>
 
+#include <machine_base/apic/ioapic_abi.h>
+
 #include "icu.h"
 #include "icu_ipl.h"
 
-extern struct machintr_abi MachIntrABI_APIC;
-
 extern inthand_t
        IDTVEC(icu_intr0),      IDTVEC(icu_intr1),
        IDTVEC(icu_intr2),      IDTVEC(icu_intr3),
@@ -152,9 +152,9 @@ icu_finalize(void)
 #ifdef SMP
        if (apic_io_enable) {
                KKASSERT(MachIntrABI.type == MACHINTR_ICU);
-               MachIntrABI_APIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
-                                       &icu_imcr_present);
-               MachIntrABI_APIC.finalize();
+               MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
+                                         &icu_imcr_present);
+               MachIntrABI_IOAPIC.finalize();
                return;
        }
 #endif
index b240565..8f9ade9 100644 (file)
@@ -61,8 +61,8 @@ extern volatile u_int         checkstate_probed_cpus;
 extern void (*cpustop_restartfunc) (void);
 
 /* functions in apic_ipl.s */
-u_int  io_apic_read            (int, int);
-void   io_apic_write           (int, int, u_int);
+u_int  ioapic_read             (int, int);
+void   ioapic_write            (int, int, u_int);
 
 /* global data in mp_machdep.c */
 extern int                     apic_io_enable;
index bdd5c4b..24676d8 100644 (file)
@@ -1679,7 +1679,6 @@ int apic_io_enable = 1; /* Enabled by default for kernels compiled w/APIC_IO */
 int apic_io_enable = 0; /* Disabled by default for kernels compiled without */
 #endif
 TUNABLE_INT("hw.apic_io_enable", &apic_io_enable);
-extern struct machintr_abi MachIntrABI_APIC;
 #endif
 
 extern struct machintr_abi MachIntrABI_ICU;
index c426c1b..f7fef5e 100644 (file)
@@ -707,7 +707,7 @@ if (apic_io_enable) {
 
        /* fill the LOGICAL io_apic_versions table */
        for (apic = 0; apic < mp_napics; ++apic) {
-               ux = io_apic_read(apic, IOAPIC_VER);
+               ux = ioapic_read(apic, IOAPIC_VER);
                io_apic_versions[apic] = ux;
                io_apic_set_id(apic, IO_TO_ID(apic));
        }
@@ -1662,7 +1662,7 @@ int_entry(const struct INTENTRY *entry, int intr)
                /* This signal goes to all IO APICS.  Select an IO APIC
                   with sufficient number of interrupt pins */
                for (apic = 0; apic < mp_napics; apic++)
-                       if (((io_apic_read(apic, IOAPIC_VER) & 
+                       if (((ioapic_read(apic, IOAPIC_VER) & 
                              IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >= 
                            entry->dst_apic_int)
                                break;
@@ -2064,7 +2064,7 @@ mptable_default(int type)
 #endif /* 0 */
 
        /* one and only IO APIC */
-       io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
+       io_apic_id = (ioapic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
 
        /*
         * sanity check, refer to MP spec section 3.6.6, last paragraph
index 4254666..bc338ee 100644 (file)
@@ -42,7 +42,7 @@
 #include <sys/queue.h>
 #endif
 
-enum machintr_type { MACHINTR_GENERIC, MACHINTR_ICU, MACHINTR_APIC };
+enum machintr_type { MACHINTR_GENERIC, MACHINTR_ICU, MACHINTR_IOAPIC };
 
 #define MACHINTR_VAR_SIZEMASK  0xFFFF