--- /dev/null
+/*-
+ * Copyright (c) 2004 Texas A&M University
+ * All rights reserved.
+ *
+ * Developer: Wm. Daryl Hawkins
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Intel ICH Watchdog Timer (WDT) driver
+ *
+ * Originally developed by Wm. Daryl Hawkins of Texas A&M
+ * Heavily modified by <des@FreeBSD.org>
+ *
+ * This is a tricky one. The ICH WDT can't be treated as a regular PCI
+ * device as it's actually an integrated function of the ICH LPC interface
+ * bridge. Detection is also awkward, because we can only infer the
+ * presence of the watchdog timer from the fact that the machine has an
+ * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT'
+ * ACPI table (although this driver does not support the ACPI detection
+ * method).
+ *
+ * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
+ * way of knowing if the WDT is permanently disabled (either by the BIOS
+ * or in hardware).
+ *
+ * The WDT is programmed through I/O registers in the ACPI I/O space.
+ * Intel swears it's always at offset 0x60, so we use that.
+ *
+ * For details about the ICH WDT, see Intel Application Note AP-725
+ * (document no. 292273-001). The WDT is also described in the individual
+ * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet
+ * (document no. 252516-001) sections 9.10 and 9.11.
+ *
+ * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
+ *
+ * $FreeBSD: src/sys/dev/ichwd/ichwd.c,v 1.34 2012/01/05 16:27:32 jhb Exp $
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/resource.h>
+#include <sys/wdog.h>
+
+#include <bus/isa/isavar.h>
+#include <bus/pci/pcivar.h>
+
+#include "ichwd.h"
+
+static struct ichwd_device ichwd_devices[] = {
+ { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 },
+ { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 },
+ { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 },
+ { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 },
+ { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 },
+ { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 },
+ { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 },
+ { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 },
+ { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 },
+ { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 },
+ { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 },
+ { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 },
+ { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 },
+ { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 },
+ { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 },
+ { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 },
+ { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 },
+ { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 },
+ { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 },
+ { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 },
+ { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 },
+ { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 },
+ { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 },
+ { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 },
+ { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 },
+ { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 },
+ { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 },
+ { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 },
+ { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 },
+ { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 },
+ { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 },
+ { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 },
+ { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 },
+ { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 },
+ { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 },
+ { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 },
+ { DEVICEID_PCH, "Intel PCH watchdog timer", 10 },
+ { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 },
+ { DEVICEID_P55, "Intel P55 watchdog timer", 10 },
+ { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 },
+ { DEVICEID_H55, "Intel H55 watchdog timer", 10 },
+ { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 },
+ { DEVICEID_H57, "Intel H57 watchdog timer", 10 },
+ { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 },
+ { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 },
+ { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 },
+ { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 },
+ { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 },
+ { DEVICEID_3400, "Intel 3400 watchdog timer", 10 },
+ { DEVICEID_3420, "Intel 3420 watchdog timer", 10 },
+ { DEVICEID_3450, "Intel 3450 watchdog timer", 10 },
+ { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 },
+ { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 },
+ { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 },
+ { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10 },
+ { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 },
+ { 0, NULL, 0 },
+};
+
+static devclass_t ichwd_devclass;
+
+static struct ichwd_softc ichwd_sc;
+
+#define ichwd_read_tco_1(sc, off) \
+ bus_read_1((sc)->tco_res, (off))
+#define ichwd_read_tco_2(sc, off) \
+ bus_read_2((sc)->tco_res, (off))
+#define ichwd_read_tco_4(sc, off) \
+ bus_read_4((sc)->tco_res, (off))
+#define ichwd_read_smi_4(sc, off) \
+ bus_read_4((sc)->smi_res, (off))
+#define ichwd_read_gcs_4(sc, off) \
+ bus_read_4((sc)->gcs_res, (off))
+
+#define ichwd_write_tco_1(sc, off, val) \
+ bus_write_1((sc)->tco_res, (off), (val))
+#define ichwd_write_tco_2(sc, off, val) \
+ bus_write_2((sc)->tco_res, (off), (val))
+#define ichwd_write_tco_4(sc, off, val) \
+ bus_write_4((sc)->tco_res, (off), (val))
+#define ichwd_write_smi_4(sc, off, val) \
+ bus_write_4((sc)->smi_res, (off), (val))
+#define ichwd_write_gcs_4(sc, off, val) \
+ bus_write_4((sc)->gcs_res, (off), (val))
+
+#define ichwd_verbose_printf(dev, ...) \
+ do { \
+ if (bootverbose) \
+ device_printf(dev, __VA_ARGS__);\
+ } while (0)
+
+/*
+ * Disable the watchdog timeout SMI handler.
+ *
+ * Apparently, some BIOSes install handlers that reset or disable the
+ * watchdog timer instead of resetting the system, so we disable the SMI
+ * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this
+ * from happening.
+ */
+static __inline void
+ichwd_smi_disable(struct ichwd_softc *sc)
+{
+ ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN);
+}
+
+/*
+ * Enable the watchdog timeout SMI handler. See above for details.
+ */
+static __inline void
+ichwd_smi_enable(struct ichwd_softc *sc)
+{
+ ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN);
+}
+
+/*
+ * Check if the watchdog SMI triggering is enabled.
+ */
+static __inline int
+ichwd_smi_is_enabled(struct ichwd_softc *sc)
+{
+ return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0);
+}
+
+/*
+ * Reset the watchdog status bits.
+ */
+static __inline void
+ichwd_sts_reset(struct ichwd_softc *sc)
+{
+ /*
+ * The watchdog status bits are set to 1 by the hardware to
+ * indicate various conditions. They can be cleared by software
+ * by writing a 1, not a 0.
+ */
+ ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT);
+ /*
+ * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must
+ * be done in two separate operations.
+ */
+ ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS);
+ ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS);
+}
+
+/*
+ * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the
+ * TCO1_CNT register. This is complicated by the need to preserve bit 9
+ * of that same register, and the requirement that all other bits must be
+ * written back as zero.
+ */
+static __inline void
+ichwd_tmr_enable(struct ichwd_softc *sc)
+{
+ uint16_t cnt;
+
+ cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
+ ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT);
+ sc->active = 1;
+ ichwd_verbose_printf(sc->device, "timer enabled\n");
+}
+
+/*
+ * Disable the watchdog timer. See above for details.
+ */
+static __inline void
+ichwd_tmr_disable(struct ichwd_softc *sc)
+{
+ uint16_t cnt;
+
+ cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
+ ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT);
+ sc->active = 0;
+ ichwd_verbose_printf(sc->device, "timer disabled\n");
+}
+
+/*
+ * Reload the watchdog timer: writing anything to any of the lower five
+ * bits of the TCO_RLD register reloads the timer from the last value
+ * written to TCO_TMR.
+ */
+static __inline void
+ichwd_tmr_reload(struct ichwd_softc *sc)
+{
+ if (sc->ich_version <= 5)
+ ichwd_write_tco_1(sc, TCO_RLD, 1);
+ else
+ ichwd_write_tco_2(sc, TCO_RLD, 1);
+
+ ichwd_verbose_printf(sc->device, "timer reloaded\n");
+}
+
+/*
+ * Set the initial timeout value. Note that this must always be followed
+ * by a reload.
+ */
+static __inline void
+ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
+{
+
+ if (timeout < TCO_RLD_TMR_MIN)
+ timeout = TCO_RLD_TMR_MIN;
+
+ if (sc->ich_version <= 5) {
+ uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
+
+ tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
+ if (timeout > TCO_RLD1_TMR_MAX)
+ timeout = TCO_RLD1_TMR_MAX;
+ tmr_val8 |= timeout;
+ ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
+ } else {
+ uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
+
+ tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff);
+ if (timeout > TCO_RLD2_TMR_MAX)
+ timeout = TCO_RLD2_TMR_MAX;
+ tmr_val16 |= timeout;
+ ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
+ }
+
+ sc->timeout = timeout;
+
+ ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout);
+}
+
+static __inline int
+ichwd_clear_noreboot(struct ichwd_softc *sc)
+{
+ uint32_t status;
+ int rc = 0;
+
+ /* try to clear the NO_REBOOT bit */
+ if (sc->ich_version <= 5) {
+ status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
+ status &= ~ICH_GEN_STA_NO_REBOOT;
+ pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
+ status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
+ if (status & ICH_GEN_STA_NO_REBOOT)
+ rc = EIO;
+ } else {
+ status = ichwd_read_gcs_4(sc, 0);
+ status &= ~ICH_GCS_NO_REBOOT;
+ ichwd_write_gcs_4(sc, 0, status);
+ status = ichwd_read_gcs_4(sc, 0);
+ if (status & ICH_GCS_NO_REBOOT)
+ rc = EIO;
+ }
+
+ if (rc)
+ device_printf(sc->device,
+ "ICH WDT present but disabled in BIOS or hardware\n");
+
+ return (rc);
+}
+
+static device_t
+ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p)
+{
+ struct ichwd_device *id;
+ device_t ich = NULL;
+
+ /* look for an ICH LPC interface bridge */
+ for (id = ichwd_devices; id->desc != NULL; ++id)
+ if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL)
+ break;
+
+ if (ich == NULL)
+ return (NULL);
+
+ ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n",
+ id->version, id->desc);
+
+ if (id_p)
+ *id_p = id;
+
+ return (ich);
+}
+
+/*
+ * Look for an ICH LPC interface bridge. If one is found, register an
+ * ichwd device. There can be only one.
+ */
+static void
+ichwd_identify(driver_t *driver, device_t parent)
+{
+ struct ichwd_device *id_p;
+ device_t ich = NULL;
+ device_t dev;
+ uint32_t rcba;
+ int rc;
+
+ ich = ichwd_find_ich_lpc_bridge(&id_p);
+ if (ich == NULL)
+ return;
+
+ /* good, add child to bus */
+ if ((dev = device_find_child(parent, driver->name, 0)) == NULL)
+ dev = BUS_ADD_CHILD(parent, parent, 0, driver->name, 0);
+
+ if (dev == NULL)
+ return;
+
+ device_set_desc_copy(dev, id_p->desc);
+
+ if (id_p->version >= 6) {
+ /* get RCBA (root complex base address) */
+ rcba = pci_read_config(ich, ICH_RCBA, 4);
+ rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
+ (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE, -1);
+ if (rc)
+ ichwd_verbose_printf(dev,
+ "Can not set memory resource for RCBA\n");
+ }
+}
+
+static int
+ich_watchdog(void *unused, int period)
+{
+ unsigned int timeout;
+
+ /* convert from seconds to WDT ticks */
+ timeout = (period * 1000) / ICHWD_TICK;
+
+ ichwd_tmr_set(&ichwd_sc, timeout);
+ ichwd_tmr_reload(&ichwd_sc);
+
+ return period;
+}
+
+static struct watchdog ich_wdog = {
+ .name = "Intel ICH",
+ .wdog_fn = ich_watchdog,
+ .arg = NULL,
+ .period_max = (TCO_RLD1_TMR_MAX * ICHWD_TICK) / 1000,
+};
+
+static int
+ichwd_probe(device_t dev)
+{
+
+ /* Do not claim some ISA PnP device by accident. */
+ if (isa_get_logicalid(dev) != 0)
+ return (ENXIO);
+ return (0);
+}
+
+static int
+ichwd_attach(device_t dev)
+{
+ struct ichwd_softc *sc;
+ struct ichwd_device *id_p;
+ device_t ich;
+ unsigned int pmbase = 0;
+
+ sc = &ichwd_sc;
+ sc->device = dev;
+
+ ich = ichwd_find_ich_lpc_bridge(&id_p);
+ if (ich == NULL) {
+ device_printf(sc->device, "Can not find ICH device.\n");
+ goto fail;
+ }
+ sc->ich = ich;
+ sc->ich_version = id_p->version;
+
+ /* get ACPI base address */
+ pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
+ if (pmbase == 0) {
+ device_printf(dev, "ICH PMBASE register is empty\n");
+ goto fail;
+ }
+
+ /* allocate I/O register space */
+ sc->smi_rid = 0;
+ sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
+ pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN,
+ RF_ACTIVE | RF_SHAREABLE);
+ if (sc->smi_res == NULL) {
+ device_printf(dev, "unable to reserve SMI registers\n");
+ goto fail;
+ }
+
+ sc->tco_rid = 1;
+ sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid,
+ pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN,
+ RF_ACTIVE | RF_SHAREABLE);
+ if (sc->tco_res == NULL) {
+ device_printf(dev, "unable to reserve TCO registers\n");
+ goto fail;
+ }
+
+ sc->gcs_rid = 0;
+ if (sc->ich_version >= 6) {
+ sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
+ &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
+ if (sc->gcs_res == NULL) {
+ device_printf(dev, "unable to reserve GCS registers\n");
+ goto fail;
+ }
+ }
+
+ if (ichwd_clear_noreboot(sc) != 0)
+ goto fail;
+
+ ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n",
+ device_get_desc(dev), sc->ich_version);
+
+ /*
+ * Determine if we are coming up after a watchdog-induced reset. Some
+ * BIOSes may clear this bit at bootup, preventing us from reporting
+ * this case on such systems. We clear this bit in ichwd_sts_reset().
+ */
+ if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0)
+ device_printf(dev,
+ "resuming after hardware watchdog timeout\n");
+
+ /* reset the watchdog status registers */
+ ichwd_sts_reset(sc);
+
+ /* make sure the WDT starts out inactive */
+ ichwd_tmr_disable(sc);
+
+ /* register the watchdog event handler */
+ wdog_register(&ich_wdog);
+
+ /* disable the SMI handler */
+ sc->smi_enabled = ichwd_smi_is_enabled(sc);
+ ichwd_smi_disable(sc);
+
+ /* and enable the watchdog */
+ ichwd_tmr_enable(sc);
+
+ return (0);
+ fail:
+ sc = device_get_softc(dev);
+ if (sc->tco_res != NULL)
+ bus_release_resource(dev, SYS_RES_IOPORT,
+ sc->tco_rid, sc->tco_res);
+ if (sc->smi_res != NULL)
+ bus_release_resource(dev, SYS_RES_IOPORT,
+ sc->smi_rid, sc->smi_res);
+ if (sc->gcs_res != NULL)
+ bus_release_resource(ich, SYS_RES_MEMORY,
+ sc->gcs_rid, sc->gcs_res);
+
+ return (ENXIO);
+}
+
+static int
+ichwd_detach(device_t dev)
+{
+ struct ichwd_softc *sc;
+ device_t ich = NULL;
+
+ sc = &ichwd_sc;
+
+ /* halt the watchdog timer */
+ if (sc->active)
+ ichwd_tmr_disable(sc);
+
+ /* enable the SMI handler */
+ if (sc->smi_enabled != 0)
+ ichwd_smi_enable(sc);
+
+ /* deregister event handler */
+ wdog_unregister(&ich_wdog);
+
+ /* reset the watchdog status registers */
+ ichwd_sts_reset(sc);
+
+ /* deallocate I/O register space */
+ bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res);
+ bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res);
+
+ /* deallocate memory resource */
+ ich = ichwd_find_ich_lpc_bridge(NULL);
+ if (sc->gcs_res && ich)
+ bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res);
+
+ return (0);
+}
+
+static device_method_t ichwd_methods[] = {
+ DEVMETHOD(device_identify, ichwd_identify),
+ DEVMETHOD(device_probe, ichwd_probe),
+ DEVMETHOD(device_attach, ichwd_attach),
+ DEVMETHOD(device_detach, ichwd_detach),
+ DEVMETHOD(device_shutdown, ichwd_detach),
+ {0,0}
+};
+
+static driver_t ichwd_driver = {
+ "ichwd",
+ ichwd_methods,
+ 0
+};
+
+DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL);
+MODULE_VERSION(ichwd, 1);
--- /dev/null
+/*-
+ * Copyright (c) 2004 Texas A&M University
+ * All rights reserved.
+ *
+ * Developer: Wm. Daryl Hawkins
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/ichwd/ichwd.h,v 1.19 2012/01/05 16:27:32 jhb Exp $
+ */
+
+#ifndef _ICHWD_H_
+#define _ICHWD_H_
+
+struct ichwd_device {
+ uint16_t device;
+ char *desc;
+ unsigned int version;
+};
+
+struct ichwd_softc {
+ device_t device;
+ device_t ich;
+ int ich_version;
+
+ int active;
+ unsigned int timeout;
+
+ int smi_enabled;
+ int smi_rid;
+ struct resource *smi_res;
+
+ int tco_rid;
+ struct resource *tco_res;
+
+ int gcs_rid;
+ struct resource *gcs_res;
+};
+
+#define VENDORID_INTEL 0x8086
+#define DEVICEID_CPT0 0x1c40
+#define DEVICEID_CPT1 0x1c41
+#define DEVICEID_CPT2 0x1c42
+#define DEVICEID_CPT3 0x1c43
+#define DEVICEID_CPT4 0x1c44
+#define DEVICEID_CPT5 0x1c45
+#define DEVICEID_CPT6 0x1c46
+#define DEVICEID_CPT7 0x1c47
+#define DEVICEID_CPT8 0x1c48
+#define DEVICEID_CPT9 0x1c49
+#define DEVICEID_CPT10 0x1c4a
+#define DEVICEID_CPT11 0x1c4b
+#define DEVICEID_CPT12 0x1c4c
+#define DEVICEID_CPT13 0x1c4d
+#define DEVICEID_CPT14 0x1c4e
+#define DEVICEID_CPT15 0x1c4f
+#define DEVICEID_CPT16 0x1c50
+#define DEVICEID_CPT17 0x1c51
+#define DEVICEID_CPT18 0x1c52
+#define DEVICEID_CPT19 0x1c53
+#define DEVICEID_CPT20 0x1c54
+#define DEVICEID_CPT21 0x1c55
+#define DEVICEID_CPT22 0x1c56
+#define DEVICEID_CPT23 0x1c57
+#define DEVICEID_CPT24 0x1c58
+#define DEVICEID_CPT25 0x1c59
+#define DEVICEID_CPT26 0x1c5a
+#define DEVICEID_CPT27 0x1c5b
+#define DEVICEID_CPT28 0x1c5c
+#define DEVICEID_CPT29 0x1c5d
+#define DEVICEID_CPT30 0x1c5e
+#define DEVICEID_CPT31 0x1c5f
+#define DEVICEID_PATSBURG_LPC1 0x1d40
+#define DEVICEID_PATSBURG_LPC2 0x1d41
+#define DEVICEID_PPT0 0x1e40
+#define DEVICEID_PPT1 0x1e41
+#define DEVICEID_PPT2 0x1e42
+#define DEVICEID_PPT3 0x1e43
+#define DEVICEID_PPT4 0x1e44
+#define DEVICEID_PPT5 0x1e45
+#define DEVICEID_PPT6 0x1e46
+#define DEVICEID_PPT7 0x1e47
+#define DEVICEID_PPT8 0x1e48
+#define DEVICEID_PPT9 0x1e49
+#define DEVICEID_PPT10 0x1e4a
+#define DEVICEID_PPT11 0x1e4b
+#define DEVICEID_PPT12 0x1e4c
+#define DEVICEID_PPT13 0x1e4d
+#define DEVICEID_PPT14 0x1e4e
+#define DEVICEID_PPT15 0x1e4f
+#define DEVICEID_PPT16 0x1e50
+#define DEVICEID_PPT17 0x1e51
+#define DEVICEID_PPT18 0x1e52
+#define DEVICEID_PPT19 0x1e53
+#define DEVICEID_PPT20 0x1e54
+#define DEVICEID_PPT21 0x1e55
+#define DEVICEID_PPT22 0x1e56
+#define DEVICEID_PPT23 0x1e57
+#define DEVICEID_PPT24 0x1e58
+#define DEVICEID_PPT25 0x1e59
+#define DEVICEID_PPT26 0x1e5a
+#define DEVICEID_PPT27 0x1e5b
+#define DEVICEID_PPT28 0x1e5c
+#define DEVICEID_PPT29 0x1e5d
+#define DEVICEID_PPT30 0x1e5e
+#define DEVICEID_PPT31 0x1e5f
+#define DEVICEID_DH89XXCC_LPC 0x2310
+#define DEVICEID_82801AA 0x2410
+#define DEVICEID_82801AB 0x2420
+#define DEVICEID_82801BA 0x2440
+#define DEVICEID_82801BAM 0x244c
+#define DEVICEID_82801CA 0x2480
+#define DEVICEID_82801CAM 0x248c
+#define DEVICEID_82801DB 0x24c0
+#define DEVICEID_82801DBM 0x24cc
+#define DEVICEID_82801E 0x2450
+#define DEVICEID_82801EB 0x24dc
+#define DEVICEID_82801EBR 0x24d0
+#define DEVICEID_6300ESB 0x25a1
+#define DEVICEID_82801FBR 0x2640
+#define DEVICEID_ICH6M 0x2641
+#define DEVICEID_ICH6W 0x2642
+#define DEVICEID_63XXESB 0x2670
+#define DEVICEID_ICH7 0x27b8
+#define DEVICEID_ICH7DH 0x27b0
+#define DEVICEID_ICH7M 0x27b9
+#define DEVICEID_NM10 0x27bc
+#define DEVICEID_ICH7MDH 0x27bd
+#define DEVICEID_ICH8 0x2810
+#define DEVICEID_ICH8DH 0x2812
+#define DEVICEID_ICH8DO 0x2814
+#define DEVICEID_ICH8M 0x2815
+#define DEVICEID_ICH8ME 0x2811
+#define DEVICEID_ICH9 0x2918
+#define DEVICEID_ICH9DH 0x2912
+#define DEVICEID_ICH9DO 0x2914
+#define DEVICEID_ICH9M 0x2919
+#define DEVICEID_ICH9ME 0x2917
+#define DEVICEID_ICH9R 0x2916
+#define DEVICEID_ICH10 0x3a18
+#define DEVICEID_ICH10D 0x3a1a
+#define DEVICEID_ICH10DO 0x3a14
+#define DEVICEID_ICH10R 0x3a16
+#define DEVICEID_PCH 0x3b00
+#define DEVICEID_PCHM 0x3b01
+#define DEVICEID_P55 0x3b02
+#define DEVICEID_PM55 0x3b03
+#define DEVICEID_H55 0x3b06
+#define DEVICEID_QM57 0x3b07
+#define DEVICEID_H57 0x3b08
+#define DEVICEID_HM55 0x3b09
+#define DEVICEID_Q57 0x3b0a
+#define DEVICEID_HM57 0x3b0b
+#define DEVICEID_PCHMSFF 0x3b0d
+#define DEVICEID_QS57 0x3b0f
+#define DEVICEID_3400 0x3b12
+#define DEVICEID_3420 0x3b14
+#define DEVICEID_3450 0x3b16
+
+/* ICH LPC Interface Bridge Registers (ICH5 and older) */
+#define ICH_GEN_STA 0xd4
+#define ICH_GEN_STA_NO_REBOOT 0x02
+#define ICH_PMBASE 0x40 /* ACPI base address register */
+#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */
+
+/* ICH Chipset Configuration Registers (ICH6 and newer) */
+#define ICH_RCBA 0xf0
+#define ICH_GCS_OFFSET 0x3410
+#define ICH_GCS_SIZE 0x4
+#define ICH_GCS_NO_REBOOT 0x20
+
+/* register names and locations (relative to PMBASE) */
+#define SMI_BASE 0x30 /* base address for SMI registers */
+#define SMI_LEN 0x08
+#define SMI_EN 0x00 /* SMI Control and Enable Register */
+#define SMI_STS 0x04 /* SMI Status Register */
+#define TCO_BASE 0x60 /* base address for TCO registers */
+#define TCO_LEN 0x20
+#define TCO_RLD 0x00 /* TCO Reload and Current Value */
+#define TCO_TMR1 0x01 /* TCO Timer Initial Value
+ (ICH5 and older, 8 bits) */
+#define TCO_TMR2 0x12 /* TCO Timer Initial Value
+ (ICH6 and newer, 16 bits) */
+#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */
+#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */
+#define TCO1_STS 0x04 /* TCO Status 1 */
+#define TCO2_STS 0x06 /* TCO Status 2 */
+#define TCO1_CNT 0x08 /* TCO Control 1 */
+#define TCO2_CNT 0x08 /* TCO Control 2 */
+#define TCO_MESSAGE1 0x0c /* TCO Message 1 */
+#define TCO_MESSAGE2 0x0d /* TCO Message 2 */
+
+/* bit definitions for SMI_EN and SMI_STS */
+#define SMI_TCO_EN 0x2000
+#define SMI_TCO_STS 0x2000
+#define SMI_GBL_EN 0x0001
+
+/* timer value mask for TCO_RLD and TCO_TMR */
+#define TCO_TIMER_MASK 0x1f
+
+/* status bits for TCO1_STS */
+#define TCO_NEWCENTURY 0x80 /* set for RTC year roll over (99 to 00) */
+#define TCO_TIMEOUT 0x08 /* timed out */
+#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */
+#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */
+
+/* status bits for TCO2_STS */
+#define TCO_BOOT_STS 0x04 /* failed to come out of reset */
+#define TCO_SECOND_TO_STS 0x02 /* ran down twice */
+
+/* control bits for TCO1_CNT */
+#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */
+#define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */
+#define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */
+#define TCO_NMI_NOW 0x0100 /* trigger an NMI */
+
+/*
+ * Masks for the TCO timer value field in TCO_RLD.
+ * If the datasheets are to be believed, the minimum value actually varies
+ * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets.
+ * I suspect this is a bug in the ICH5 datasheet and that the minimum is
+ * uniformly 2, but I'd rather err on the side of caution.
+ */
+#define TCO_RLD_TMR_MIN 0x0004
+#define TCO_RLD1_TMR_MAX 0x003f
+#define TCO_RLD2_TMR_MAX 0x03ff
+
+/* approximate length in milliseconds of one WDT tick (about 0.6 sec) */
+#define ICHWD_TICK 600
+
+#endif
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