bnx: Add support for BCM5762 chips
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Wed, 20 Mar 2013 13:34:20 +0000 (21:34 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Wed, 20 Mar 2013 13:34:20 +0000 (21:34 +0800)
Taken-from: tg3

sys/dev/netif/bge/if_bgereg.h
sys/dev/netif/bnx/if_bnx.c
sys/dev/netif/mii_layer/brgphy.c
sys/dev/netif/mii_layer/brgphyreg.h

index 8dc7034..8ff0912 100644 (file)
 #define BGE_CHIPID_BCM5717_C0          0x05717200
 #define BGE_CHIPID_BCM5719_A0          0x05719000
 #define BGE_CHIPID_BCM5720_A0          0x05720000
+#define BGE_CHIPID_BCM5762_A0          0x05762000
 #define BGE_CHIPID_BCM57765_A0         0x57785000
 #define BGE_CHIPID_BCM57765_B0         0x57785100
 
 #define BGE_ASICREV_BCM5719            0x5719
 #define BGE_ASICREV_BCM5720            0x5720
 #define BGE_ASICREV_BCM5761            0x5761
+#define BGE_ASICREV_BCM5762            0x5762
 #define BGE_ASICREV_BCM5784            0x5784
 #define BGE_ASICREV_BCM5785            0x5785
 #define BGE_ASICREV_BCM57765           0x57785
  */
 #define BGE_RDMA_MODE                  0x4800
 #define BGE_RDMA_STATUS                        0x4804
+#define BGE_RDMA_RSRVCTRL2             0x4890
+#define BGE_RDMA_LSO_CRPTEN_CTRL2      0x48a0
 #define BGE_RDMA_RSRVCTRL              0x4900
 #define BGE_RDMA_LSO_CRPTEN_CTRL       0x4910
 
index 2e07193..1c25ca0 100644 (file)
@@ -99,6 +99,13 @@ static const struct bnx_type {
        { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
                "Broadcom BCM5720 Gigabit Ethernet" },
 
+       { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
+               "Broadcom BCM5725 Gigabit Ethernet" },
+       { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
+               "Broadcom BCM5727 Gigabit Ethernet" },
+       { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
+               "Broadcom BCM5762 Gigabit Ethernet" },
+
        { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
                "Broadcom BCM57761 Gigabit Ethernet" },
        { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
@@ -1131,6 +1138,7 @@ bnx_chipinit(struct bnx_softc *sc)
         * disabled.
         */
        if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
+           sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
            !BNX_IS_57765_FAMILY(sc))
                dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
        if (bootverbose) {
@@ -1393,7 +1401,8 @@ bnx_blockinit(struct bnx_softc *sc)
         */
        if (BNX_IS_5717_PLUS(sc))
                limit = 4;
-       else if (BNX_IS_57765_FAMILY(sc))
+       else if (BNX_IS_57765_FAMILY(sc) ||
+           sc->bnx_asicrev == BGE_ASICREV_BCM5762)
                limit = 2;
        else
                limit = 1;
@@ -1427,7 +1436,8 @@ bnx_blockinit(struct bnx_softc *sc)
        if (BNX_IS_5717_PLUS(sc)) {
                /* Should be 17, use 16 until we get an SRAM map. */
                limit = 16;
-       } else if (BNX_IS_57765_FAMILY(sc)) {
+       } else if (BNX_IS_57765_FAMILY(sc) ||
+           sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
                limit = 4;
        } else {
                limit = 1;
@@ -1467,7 +1477,8 @@ bnx_blockinit(struct bnx_softc *sc)
 
        /* Set inter-packet gap */
        val = 0x2620;
-       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
+       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
+           sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
                val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
                    (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
        }
@@ -1578,15 +1589,21 @@ bnx_blockinit(struct bnx_softc *sc)
        DELAY(40);
 
        if (BNX_IS_57765_PLUS(sc)) {
-               uint32_t dmactl;
+               uint32_t dmactl, dmactl_reg;
+
+               if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
+                       dmactl_reg = BGE_RDMA_RSRVCTRL2;
+               else
+                       dmactl_reg = BGE_RDMA_RSRVCTRL;
 
-               dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
+               dmactl = CSR_READ_4(sc, dmactl_reg);
                /*
                 * Adjust tx margin to prevent TX data corruption and
                 * fix internal FIFO overflow.
                 */
                if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
-                   sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
+                   sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
+                   sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
                        dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
                            BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
                            BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
@@ -1599,7 +1616,7 @@ bnx_blockinit(struct bnx_softc *sc)
                 * The fix is to limit the number of RX BDs
                 * the hardware would fetch at a fime.
                 */
-               CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
+               CSR_WRITE_4(sc, dmactl_reg,
                    dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
        }
 
@@ -1608,13 +1625,21 @@ bnx_blockinit(struct bnx_softc *sc)
                    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
                    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
                    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
-       } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
+       } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
+           sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
+               uint32_t ctrl_reg;
+
+               if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
+                       ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
+               else
+                       ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
+
                /*
                 * Allow 4KB burst length reads for non-LSO frames.
                 * Enable 512B burst length reads for buffer descriptors.
                 */
-               CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
-                   CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
+               CSR_WRITE_4(sc, ctrl_reg,
+                   CSR_READ_4(sc, ctrl_reg) |
                    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
                    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
        }
@@ -1630,7 +1655,8 @@ bnx_blockinit(struct bnx_softc *sc)
                    BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
                    BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
        }
-       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
+       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
+           sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
                val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
                    BGE_RDMAMODE_H2BNC_VLAN_DET;
                /*
@@ -1821,6 +1847,9 @@ bnx_attach(device_t dev)
                case PCI_PRODUCT_BROADCOM_BCM5718:
                case PCI_PRODUCT_BROADCOM_BCM5719:
                case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
+               case PCI_PRODUCT_BROADCOM_BCM5725:
+               case PCI_PRODUCT_BROADCOM_BCM5727:
+               case PCI_PRODUCT_BROADCOM_BCM5762:
                        sc->bnx_chipid = pci_read_config(dev,
                            BGE_PCI_GEN2_PRODID_ASICREV, 4);
                        break;
@@ -1858,6 +1887,10 @@ bnx_attach(device_t dev)
                sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
                break;
 
+       case BGE_ASICREV_BCM5762:
+               sc->bnx_flags |= BNX_FLAG_57765_PLUS;
+               break;
+
        case BGE_ASICREV_BCM57765:
        case BGE_ASICREV_BCM57766:
                sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
@@ -1912,6 +1945,8 @@ bnx_attach(device_t dev)
        }
 
        mii_priv |= BRGPHY_FLAG_WIRESPEED;
+       if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
+               mii_priv |= BRGPHY_FLAG_5762_A0;
 
        /*
         * Allocate interrupt
@@ -3107,7 +3142,8 @@ bnx_init(void *xsc)
        /* Enable TX MAC state machine lockup fix. */
        mode = CSR_READ_4(sc, BGE_TX_MODE);
        mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
-       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
+       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
+           sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
                mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
                mode |= CSR_READ_4(sc, BGE_TX_MODE) &
                    (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
@@ -4285,7 +4321,8 @@ bnx_dma_swap_options(struct bnx_softc *sc)
 #if BYTE_ORDER == BIG_ENDIAN
        dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
 #endif
-       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
+       if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
+           sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
                dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
                    BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
                    BGE_MODECTL_HTX2B_ENABLE;
index 5358553..0eb9f33 100644 (file)
@@ -105,6 +105,8 @@ static const struct mii_phydesc brgphys[] = {
        MII_PHYDESC(xxBROADCOM3, BCM57765),
        MII_PHYDESC(xxBROADCOM3, BCM57780),
 
+       MII_PHYDESC(xxBROADCOM4, BCM5762),
+
        MII_PHYDESC(BROADCOM2, BCM5906),
 
        MII_PHYDESC_NULL
@@ -549,6 +551,11 @@ brgphy_reset(struct mii_softc *sc)
        if (sc->mii_priv & BRGPHY_FLAG_5906)
                PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
 
+       if (sc->mii_priv & BRGPHY_FLAG_5762_A0) {
+               PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0xffb);
+               PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x4000);
+       }
+
        /* Enable Ethernet@Wirespeed */
        if (sc->mii_priv & BRGPHY_FLAG_WIRESPEED)
                brgphy_eth_wirespeed(sc);
index 4b45419..49b8316 100644 (file)
 #define BRGPHY_FLAG_WIRESPEED  0x080
 #define BRGPHY_FLAG_NO_3LED    0x100
 #define BRGPHY_FLAG_NO_EARLYDAC        0x200
+#define BRGPHY_FLAG_5762_A0    0x400
 
 #endif /* _DEV_BRGPHY_MIIREG_H_ */