kernel: Remove now obsolete CPU_AMD64X2_INTR_SPAM option.

diff --git a/sys/config/LINT b/sys/config/LINT
index defec90..c286936 100644 (file)
--- a/sys/config/LINT
+++ b/sys/config/LINT
@@ -136,15 +136,6 @@ cpu                I686_CPU                # aka Pentium Pro(tm)
 #
 # Options for CPU features.
 #
-# CPU_AMD64X2_INTR_SPAM tries to route HyperTransport EXTINT and NMI
-# messages to LINT0 on the local APIC when the BIOS has forgotten to
-# do that.  If this is not done on a multi-core cpu, EXTINT and NMI
-# get routed to the INTR/NMI pins on *BOTH* cores simultaneously, causing
-# two INTA ack cycles one of which will almost certainly result in a
-# spurious interrupt vector being presented.  This is often visible as
-# an unmaskable IRQ 7 which occurs for every normal interrupt that occurs
-# on a system.
-#
 # CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has
 # forgotten to enable them.
 #
@@ -243,7 +234,6 @@ cpu         I686_CPU                # aka Pentium Pro(tm)
 # NOTE 3: This option may cause failures for software that requires
 # locked cycles in order to operate correctly.
 #
-options                CPU_AMD64X2_INTR_SPAM
 options        CPU_ATHLON_SSE_HACK
 options        CPU_BLUELIGHTNING_FPU_OP_CACHE
 options        CPU_BLUELIGHTNING_3X

diff --git a/sys/config/LINT64 b/sys/config/LINT64
index c17a6b4..ca20bcd 100644 (file)
--- a/sys/config/LINT64
+++ b/sys/config/LINT64
@@ -127,21 +127,11 @@ cpu               HAMMER_CPU
 #
 # Options for CPU features.
 #
-# CPU_AMD64X2_INTR_SPAM tries to route HyperTransport EXTINT and NMI
-# messages to LINT0 on the local APIC when the BIOS has forgotten to
-# do that.  If this is not done on a multi-core cpu, EXTINT and NMI
-# get routed to the INTR/NMI pins on *BOTH* cores simultaneously, causing
-# two INTA ack cycles one of which will almost certainly result in a
-# spurious interrupt vector being presented.  This is often visible as
-# an unmaskable IRQ 7 which occurs for every normal interrupt that occurs
-# on a system.
-#
 # CPU_DISABLE_SSE disables SSE/MMX2 instructions support.
 #
 # CPU_ENABLE_EST enables support for Enhanced SpeedStep technology
 # found in Pentium(tm) M processors.
 #
-options                CPU_AMD64X2_INTR_SPAM
 #options       CPU_DISABLE_SSE
 options                CPU_ENABLE_EST
 

diff --git a/sys/platform/pc32/conf/options b/sys/platform/pc32/conf/options
index 84c5678..c67fe04 100644 (file)
--- a/sys/platform/pc32/conf/options
+++ b/sys/platform/pc32/conf/options
@@ -36,7 +36,6 @@ TIMER_FREQ                    opt_clock.h
 KERN_TIMESTAMP                 opt_global.h
 
 NO_F00F_HACK                   opt_cpu.h
-CPU_AMD64X2_INTR_SPAM          opt_cpu.h
 CPU_BLUELIGHTNING_FPU_OP_CACHE opt_cpu.h
 CPU_BLUELIGHTNING_3X           opt_cpu.h
 CPU_BTB_EN                     opt_cpu.h

diff --git a/sys/platform/pc64/conf/options b/sys/platform/pc64/conf/options
index dccae23..6831778 100644 (file)
--- a/sys/platform/pc64/conf/options
+++ b/sys/platform/pc64/conf/options
@@ -18,7 +18,6 @@ APIC_IO                       opt_apic.h
 NDISAPI                        opt_dontuse.h
 
 # x86_64 SMP options
-CPU_AMD64X2_INTR_SPAM  opt_cpu.h
 CPU_ENABLE_EST         opt_cpu.h
 
 # The cpu type