acpi_cpu: fixup for PIIX4E PCI config related to C2.
authorHasso Tepper <hasso@estpak.ee>
Mon, 4 May 2009 08:41:24 +0000 (11:41 +0300)
committerHasso Tepper <hasso@estpak.ee>
Mon, 4 May 2009 08:50:44 +0000 (11:50 +0300)
If you have seen
cpu0: too many short sleeps, backing off to C1
with this chipset before you may want to try cx_lowest of C2 again.

Obtained-from: FreeBSD

sys/dev/acpica5/acpi_cpu.c

index 164370d..237cd49 100644 (file)
@@ -1111,6 +1111,10 @@ acpi_cpu_quirks(void)
         *
         * Also, make sure that all interrupts cause a "Stop Break"
         * event to exit from C2 state.
+        * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
+        * should be set to zero, otherwise it causes C2 to short-sleep.
+        * PIIX4 doesn't properly support C3 and bus master activity
+        * need not break out of C2.
         */
        case PCI_REVISION_A_STEP:
        case PCI_REVISION_B_STEP:
@@ -1123,10 +1127,16 @@ acpi_cpu_quirks(void)
            val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
            if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
                ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-                   "PIIX4: enabling IRQs to generate Stop Break\n"));
+                   "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
                val |= PIIX4_STOP_BREAK_MASK;
                pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
            }
+           AcpiGetRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
+           if (val) {
+               ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+                   "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
+               AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
+           }
            break;
        default:
            break;