ixgbe(4): Sync with FreeBSD
authorFrançois Tigeot <ftigeot@wolfpond.org>
Thu, 9 Aug 2012 10:52:34 +0000 (12:52 +0200)
committerFrançois Tigeot <ftigeot@wolfpond.org>
Thu, 9 Aug 2012 13:47:51 +0000 (15:47 +0200)
Update to the ixgbe driver:
  - Add a couple of new devices
  - Flow control changes in shared and core code
  - Bug fix to Flow Director for 82598
  - Shared code sync to internal with required core change

13 files changed:
sys/dev/netif/ixgbe/ixgbe.c
sys/dev/netif/ixgbe/ixgbe_82598.c
sys/dev/netif/ixgbe/ixgbe_82598.h
sys/dev/netif/ixgbe/ixgbe_82599.c
sys/dev/netif/ixgbe/ixgbe_api.c
sys/dev/netif/ixgbe/ixgbe_api.h
sys/dev/netif/ixgbe/ixgbe_common.c
sys/dev/netif/ixgbe/ixgbe_common.h
sys/dev/netif/ixgbe/ixgbe_osdep.h
sys/dev/netif/ixgbe/ixgbe_phy.c
sys/dev/netif/ixgbe/ixgbe_type.h
sys/dev/netif/ixgbe/ixgbe_vf.c
sys/dev/netif/ixgbe/ixgbe_x540.c

index b78133f..00ed301 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe.c,v 1.69 2012/06/07 22:57:26 emax Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe.c,v 1.70 2012/07/05 20:51:44 jfv Exp $*/
 
 #include "opt_inet.h"
 #include "opt_inet6.h"
@@ -45,7 +45,7 @@ int             ixgbe_display_debug_stats = 0;
 /*********************************************************************
  *  Driver version
  *********************************************************************/
-char ixgbe_driver_version[] = "2.4.5";
+char ixgbe_driver_version[] = "2.4.8";
 
 /*********************************************************************
  *  PCI Device ID Table
@@ -78,8 +78,10 @@ static ixgbe_vendor_info_t ixgbe_vendor_info_array[] =
        {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM, 0, 0, 0},
        {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE, 0, 0, 0},
        {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE, 0, 0, 0},
+       {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, 0, 0, 0},
        {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, 0, 0, 0},
        {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, 0, 0, 0},
+       {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, 0, 0, 0},
        {IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, 0, 0, 0},
        /* required last entry */
        {0, 0, 0, 0, 0}
@@ -246,10 +248,6 @@ TUNABLE_INT("hw.ixgbe.max_interrupt_rate", &ixgbe_max_interrupt_rate);
 static int ixgbe_rx_process_limit = 128;
 TUNABLE_INT("hw.ixgbe.rx_process_limit", &ixgbe_rx_process_limit);
 
-/* Flow control setting, default to full */
-static int ixgbe_flow_control = ixgbe_fc_full;
-TUNABLE_INT("hw.ixgbe.flow_control", &ixgbe_flow_control);
-
 /*
 ** Smart speed setting, default to on
 ** this only works as a compile option
@@ -544,28 +542,25 @@ ixgbe_attach(device_t dev)
                goto err_late;
        }
 
-       /* Get Hardware Flow Control setting */
-       hw->fc.requested_mode = ixgbe_fc_full;
-       adapter->fc = hw->fc.requested_mode;
-       hw->fc.pause_time = IXGBE_FC_PAUSE;
-       hw->fc.low_water = IXGBE_FC_LO;
-       hw->fc.high_water[0] = IXGBE_FC_HI;
-       hw->fc.send_xon = TRUE;
-
        error = ixgbe_init_hw(hw);
-       if (error == IXGBE_ERR_EEPROM_VERSION) {
+       switch (error) {
+       case IXGBE_ERR_EEPROM_VERSION:
                device_printf(dev, "This device is a pre-production adapter/"
                    "LOM.  Please be aware there may be issues associated "
                    "with your hardware.\n If you are experiencing problems "
                    "please contact your Intel or hardware representative "
                    "who provided you with this hardware.\n");
-       } else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED)
+               break;
+       case IXGBE_ERR_SFP_NOT_SUPPORTED:
                device_printf(dev,"Unsupported SFP+ Module\n");
-
-       if (error) {
                error = EIO;
                device_printf(dev,"Hardware Initialization Failure\n");
                goto err_late;
+       case IXGBE_ERR_SFP_NOT_PRESENT:
+               device_printf(dev,"No SFP+ Module found\n");
+               /* falls thru */
+       default:
+               break;
        }
 
        /* Detect and set physical type */
@@ -1272,7 +1267,7 @@ ixgbe_init_locked(struct adapter *adapter)
 #ifdef IXGBE_FDIR
        /* Init Flow director */
        if (hw->mac.type != ixgbe_mac_82598EB) {
-               u32 hdrm = 64 << fdir_pballoc;
+               u32 hdrm = 32 << fdir_pballoc;
 
                hw->mac.ops.setup_rxpba(hw, 0, hdrm, PBA_STRATEGY_EQUAL);
                ixgbe_init_fdir_signature_82599(&adapter->hw, fdir_pballoc);
@@ -1298,6 +1293,35 @@ ixgbe_init_locked(struct adapter *adapter)
        /* Config/Enable Link */
        ixgbe_config_link(adapter);
 
+       /* Hardware Packet Buffer & Flow Control setup */
+       {
+               u32 rxpb, frame, size, tmp;
+
+               frame = adapter->max_frame_size;
+
+               /* Calculate High Water */
+               if (hw->mac.type == ixgbe_mac_X540)
+                       tmp = IXGBE_DV_X540(frame, frame);
+               else
+                       tmp = IXGBE_DV(frame, frame);
+               size = IXGBE_BT2KB(tmp);
+               rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10;
+               hw->fc.high_water[0] = rxpb - size;
+
+               /* Now calculate Low Water */
+               if (hw->mac.type == ixgbe_mac_X540)
+                       tmp = IXGBE_LOW_DV_X540(frame);
+               else
+                       tmp = IXGBE_LOW_DV(frame);
+               hw->fc.low_water[0] = IXGBE_BT2KB(tmp);
+               
+               adapter->fc = hw->fc.requested_mode = ixgbe_fc_full;
+               hw->fc.pause_time = IXGBE_FC_PAUSE;
+               hw->fc.send_xon = TRUE;
+       }
+       /* Initialize the FC settings */
+       ixgbe_start_hw(hw);
+
        /* And now turn on interrupts */
        ixgbe_enable_intr(adapter);
 
@@ -1590,10 +1614,8 @@ ixgbe_msix_link(void *arg)
                        /* This is probably overkill :) */
                        if (!atomic_cmpset_int(&adapter->fdir_reinit, 0, 1))
                                return;
-                       /* Clear the interrupt */
-                       IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
-                       /* Turn off the interface */
-                       adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+                       /* Disable the interrupt */
+                       IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FLOW_DIR);
                        taskqueue_enqueue(adapter->tq, &adapter->fdir_task);
                } else
 #endif
@@ -2094,6 +2116,8 @@ ixgbe_update_link_status(struct adapter *adapter)
                                    ((adapter->link_speed == 128)? 10:1),
                                    "Full Duplex");
                        adapter->link_active = TRUE;
+                       /* Update any Flow Control changes */
+                       ixgbe_fc_enable(&adapter->hw);
                        ifp->if_link_state = LINK_STATE_UP;
                        if_link_state_change(ifp);
                }
@@ -3116,7 +3140,7 @@ ixgbe_initialize_transmit_units(struct adapter *adapter)
                        txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
                        break;
                 }
-               txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+               txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
                switch (hw->mac.type) {
                case ixgbe_mac_82598EB:
                        IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
@@ -5182,6 +5206,8 @@ ixgbe_reinit_fdir(void *context, int pending)
                return;
        ixgbe_reinit_fdir_tables_82599(&adapter->hw);
        adapter->fdir_reinit = 0;
+       /* re-enable flow director interrupts */
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
        /* Restart the interface */
        ifp->if_drv_flags |= IFF_DRV_RUNNING;
        return;
@@ -5742,8 +5768,9 @@ ixgbe_set_flowcntl(SYSCTL_HANDLER_ARGS)
                default:
                        adapter->hw.fc.requested_mode = ixgbe_fc_none;
        }
-
-       ixgbe_fc_enable(&adapter->hw, 0);
+       /* Don't autoneg if forcing a value */
+       adapter->hw.fc.disable_fc_autoneg = TRUE;
+       ixgbe_fc_enable(&adapter->hw);
        return error;
 }
 
@@ -5759,9 +5786,9 @@ ixgbe_add_rx_process_limit(struct adapter *adapter, const char *name,
 
 /*
 ** Control link advertise speed:
-**     0 - normal
 **     1 - advertise only 1G
 **     2 - advertise 100Mb
+**     3 - advertise normal
 */
 static int
 ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
@@ -5775,13 +5802,15 @@ ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
        adapter = (struct adapter *) arg1;
        dev = adapter->dev;
        hw = &adapter->hw;
-       last = hw->phy.autoneg_advertised;
+       last = adapter->advertise;
 
        error = sysctl_handle_int(oidp, &adapter->advertise, 0, req);
-
        if ((error) || (adapter->advertise == -1))
                return (error);
 
+       if (adapter->advertise == last) /* no change */
+               return (0);
+
        if (!((hw->phy.media_type == ixgbe_media_type_copper) ||
             (hw->phy.multispeed_fiber)))
                return (error);
@@ -5795,11 +5824,10 @@ ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
                 speed = IXGBE_LINK_SPEED_1GB_FULL;
        else if (adapter->advertise == 2)
                 speed = IXGBE_LINK_SPEED_100_FULL;
-       else
+       else if (adapter->advertise == 3)
                 speed = IXGBE_LINK_SPEED_1GB_FULL |
                        IXGBE_LINK_SPEED_10GB_FULL;
-
-       if (speed == last) /* no change */
+       else /* bogus value */
                return (error);
 
        hw->mac.autotry_restart = TRUE;
index 212127e..15ece96 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.12 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
 
 #include "ixgbe_type.h"
 #include "ixgbe_82598.h"
@@ -104,31 +104,6 @@ out:
 }
 
 /**
- *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
- *  @hw: pointer to hardware structure
- *
- *  Read PCIe configuration space, and get the MSI-X vector count from
- *  the capabilities table.
- **/
-u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
-{
-       u32 msix_count = 18;
-
-       DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
-
-       if (hw->mac.msix_vectors_from_pcie) {
-               msix_count = IXGBE_READ_PCIE_WORD(hw,
-                                                 IXGBE_PCIE_MSIX_82598_CAPS);
-               msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
-
-               /* MSI-X count is zero-based in HW, so increment to give
-                * proper value */
-               msix_count++;
-       }
-       return msix_count;
-}
-
-/**
  *  ixgbe_init_ops_82598 - Inits func ptrs and MAC type
  *  @hw: pointer to hardware structure
  *
@@ -176,7 +151,7 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
        mac->rx_pb_size         = 512;
        mac->max_tx_queues      = 32;
        mac->max_rx_queues      = 64;
-       mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_82598(hw);
+       mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 
        /* SFP+ Module */
        phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
@@ -280,15 +255,15 @@ s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
        for (i = 0; ((i < hw->mac.max_tx_queues) &&
             (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
-               regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+               regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
        }
 
        for (i = 0; ((i < hw->mac.max_rx_queues) &&
             (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
-               regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-                           IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+               regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+                           IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
                IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
        }
 
@@ -416,21 +391,41 @@ out:
 /**
  *  ixgbe_fc_enable_82598 - Enable flow control
  *  @hw: pointer to hardware structure
- *  @packetbuf_num: packet buffer number (0-7)
  *
  *  Enable flow control according to the current settings.
  **/
-s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
+s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
 {
        s32 ret_val = IXGBE_SUCCESS;
        u32 fctrl_reg;
        u32 rmcs_reg;
        u32 reg;
+       u32 fcrtl, fcrth;
        u32 link_speed = 0;
+       int i;
        bool link_up;
 
        DEBUGFUNC("ixgbe_fc_enable_82598");
 
+       /* Validate the water mark configuration */
+       if (!hw->fc.pause_time) {
+               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+               goto out;
+       }
+
+       /* Low water mark of zero causes XOFF floods */
+       for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+               if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+                   hw->fc.high_water[i]) {
+                       if (!hw->fc.low_water[i] ||
+                           hw->fc.low_water[i] >= hw->fc.high_water[i]) {
+                               DEBUGOUT("Invalid water mark configuration\n");
+                               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+                               goto out;
+                       }
+               }
+       }
+
        /*
         * On 82598 having Rx FC on causes resets while doing 1G
         * so if it's on turn it off once we know link_speed. For
@@ -452,9 +447,7 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
        }
 
        /* Negotiate the fc mode to use */
-       ret_val = ixgbe_fc_autoneg(hw);
-       if (ret_val == IXGBE_ERR_FLOW_CONTROL)
-               goto out;
+       ixgbe_fc_autoneg(hw);
 
        /* Disable any previous flow control settings */
        fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
@@ -516,28 +509,27 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
        IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 
        /* Set up and enable Rx high/low water mark thresholds, enable XON. */
-       if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
-               reg = hw->fc.low_water << 6;
-               if (hw->fc.send_xon)
-                       reg |= IXGBE_FCRTL_XONE;
-
-               IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
-
-               reg = hw->fc.high_water[packetbuf_num] << 6;
-               reg |= IXGBE_FCRTH_FCEN;
+       for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+               if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+                   hw->fc.high_water[i]) {
+                       fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
+                       fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
+               } else {
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
+               }
 
-               IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
        }
 
        /* Configure pause time (2 TCs per register) */
-       reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
-       if ((packetbuf_num & 1) == 0)
-               reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
-       else
-               reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
-       IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
+       reg = hw->fc.pause_time * 0x00010001;
+       for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
+               IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
 
-       IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
+       /* Configure flow control refresh threshold value */
+       IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
 
 out:
        return ret_val;
@@ -1325,15 +1317,15 @@ void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
        for (i = 0; ((i < hw->mac.max_tx_queues) &&
             (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
-               regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+               regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
        }
 
        for (i = 0; ((i < hw->mac.max_rx_queues) &&
             (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
-               regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-                          IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+               regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+                         IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
        }
 
index 0ee80f5..734e8fb 100644 (file)
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.h,v 1.1 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.h,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
 
 #ifndef _IXGBE_82598_H_
 #define _IXGBE_82598_H_
 
 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
-s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
+s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw);
 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
index c8d652b..43bfc7d 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.7 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/
 
 #include "ixgbe_type.h"
 #include "ixgbe_82599.h"
@@ -243,6 +243,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
 
        /* RAR, Multicast, VLAN */
        mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
+       mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
        mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
        mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
        mac->rar_highwater = 1;
@@ -304,7 +305,9 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
 
        /* Check if 1G SFP module. */
        if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
-           hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
+           hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+           hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
+           hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
                *speed = IXGBE_LINK_SPEED_1GB_FULL;
                *negotiation = TRUE;
                goto out;
@@ -420,6 +423,7 @@ enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
        case IXGBE_DEV_ID_82599_SFP:
        case IXGBE_DEV_ID_82599_SFP_FCOE:
        case IXGBE_DEV_ID_82599_SFP_EM:
+       case IXGBE_DEV_ID_82599_SFP_SF2:
        case IXGBE_DEV_ID_82599EN_SFP:
                media_type = ixgbe_media_type_fiber;
                break;
@@ -1088,6 +1092,9 @@ mac_reset_top:
                hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
                                    hw->mac.san_addr, 0, IXGBE_RAH_AV);
 
+               /* Save the SAN MAC RAR index */
+               hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
+
                /* Reserve the last RAR for the SAN MAC address */
                hw->mac.num_rar_entries--;
        }
@@ -2037,6 +2044,8 @@ sfp_check:
                        physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
                else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
                        physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
+               else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
+                       physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
                break;
        default:
                break;
@@ -2233,3 +2242,4 @@ static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
        return ret_val;
 }
 
+
index 9fcf560..7abbcc5 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.12 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
 
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
@@ -118,6 +118,7 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
                case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
                case IXGBE_DEV_ID_82599_SFP_FCOE:
                case IXGBE_DEV_ID_82599_SFP_EM:
+               case IXGBE_DEV_ID_82599_SFP_SF2:
                case IXGBE_DEV_ID_82599EN_SFP:
                case IXGBE_DEV_ID_82599_CX4:
                case IXGBE_DEV_ID_82599_T3_LOM:
@@ -130,6 +131,7 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
                        hw->mac.type = ixgbe_mac_X540_vf;
                        break;
                case IXGBE_DEV_ID_X540T:
+               case IXGBE_DEV_ID_X540T1:
                        hw->mac.type = ixgbe_mac_X540;
                        break;
                default:
@@ -811,6 +813,18 @@ s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
        return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
                               IXGBE_NOT_IMPLEMENTED);
+
+}
+
+/**
+ *  ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
+ *  @hw: pointer to hardware structure
+ *  @vmdq: VMDq default pool index
+ **/
+s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
+                              (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
 }
 
 /**
@@ -960,13 +974,12 @@ s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
 /**
  *  ixgbe_fc_enable - Enable flow control
  *  @hw: pointer to hardware structure
- *  @packetbuf_num: packet buffer number (0-7)
  *
  *  Configures the flow control settings based on SW configuration.
  **/
-s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
+s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
 {
-       return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num),
+       return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
                               IXGBE_NOT_IMPLEMENTED);
 }
 
@@ -1102,7 +1115,7 @@ u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics
+ *  ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
  *  @hw: pointer to hardware structure
  *  @regval: bitfield to write to the Rx DMA register
  *
index 1ab6f6b..b5f5a1b 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.h,v 1.13 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.h,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
 
 #ifndef _IXGBE_API_H_
 #define _IXGBE_API_H_
@@ -104,6 +104,7 @@ s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
                  u32 enable_addr);
 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
@@ -120,7 +121,7 @@ s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
                   u32 vind, bool vlan_on);
 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
                   bool vlan_on, bool *vfta_changed);
-s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num);
+s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
                         u8 ver);
 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
index 08cc938..12bfb0c 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.13 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
 
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
@@ -51,13 +51,6 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
                                         u16 *san_mac_offset);
-static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
-static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
-static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
-static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
-static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
-                             u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
-static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
                                             u16 words, u16 *data);
 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
@@ -146,6 +139,177 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
 }
 
 /**
+ *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
+ *  control
+ *  @hw: pointer to hardware structure
+ *
+ *  There are several phys that do not support autoneg flow control. This
+ *  function check the device id to see if the associated phy supports
+ *  autoneg flow control.
+ **/
+static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
+{
+
+       DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
+
+       switch (hw->device_id) {
+       case IXGBE_DEV_ID_X540T:
+       case IXGBE_DEV_ID_X540T1:
+               return IXGBE_SUCCESS;
+       case IXGBE_DEV_ID_82599_T3_LOM:
+               return IXGBE_SUCCESS;
+       default:
+               return IXGBE_ERR_FC_NOT_SUPPORTED;
+       }
+}
+
+/**
+ *  ixgbe_setup_fc - Set up flow control
+ *  @hw: pointer to hardware structure
+ *
+ *  Called at init time to set up flow control.
+ **/
+static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
+{
+       s32 ret_val = IXGBE_SUCCESS;
+       u32 reg = 0, reg_bp = 0;
+       u16 reg_cu = 0;
+
+       DEBUGFUNC("ixgbe_setup_fc");
+
+       /*
+        * Validate the requested mode.  Strict IEEE mode does not allow
+        * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
+        */
+       if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
+               DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
+               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+               goto out;
+       }
+
+       /*
+        * 10gig parts do not have a word in the EEPROM to determine the
+        * default flow control setting, so we explicitly set it to full.
+        */
+       if (hw->fc.requested_mode == ixgbe_fc_default)
+               hw->fc.requested_mode = ixgbe_fc_full;
+
+       /*
+        * Set up the 1G and 10G flow control advertisement registers so the
+        * HW will be able to do fc autoneg once the cable is plugged in.  If
+        * we link at 10G, the 1G advertisement is harmless and vice versa.
+        */
+       switch (hw->phy.media_type) {
+       case ixgbe_media_type_fiber:
+       case ixgbe_media_type_backplane:
+               reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
+               reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+               break;
+       case ixgbe_media_type_copper:
+               hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
+                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
+               break;
+       default:
+               break;
+       }
+
+       /*
+        * The possible values of fc.requested_mode are:
+        * 0: Flow control is completely disabled
+        * 1: Rx flow control is enabled (we can receive pause frames,
+        *    but not send pause frames).
+        * 2: Tx flow control is enabled (we can send pause frames but
+        *    we do not support receiving pause frames).
+        * 3: Both Rx and Tx flow control (symmetric) are enabled.
+        * other: Invalid.
+        */
+       switch (hw->fc.requested_mode) {
+       case ixgbe_fc_none:
+               /* Flow control completely disabled by software override. */
+               reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
+               if (hw->phy.media_type == ixgbe_media_type_backplane)
+                       reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
+                                   IXGBE_AUTOC_ASM_PAUSE);
+               else if (hw->phy.media_type == ixgbe_media_type_copper)
+                       reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
+               break;
+       case ixgbe_fc_tx_pause:
+               /*
+                * Tx Flow control is enabled, and Rx Flow control is
+                * disabled by software override.
+                */
+               reg |= IXGBE_PCS1GANA_ASM_PAUSE;
+               reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
+               if (hw->phy.media_type == ixgbe_media_type_backplane) {
+                       reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
+                       reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
+               } else if (hw->phy.media_type == ixgbe_media_type_copper) {
+                       reg_cu |= IXGBE_TAF_ASM_PAUSE;
+                       reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
+               }
+               break;
+       case ixgbe_fc_rx_pause:
+               /*
+                * Rx Flow control is enabled and Tx Flow control is
+                * disabled by software override. Since there really
+                * isn't a way to advertise that we are capable of RX
+                * Pause ONLY, we will advertise that we support both
+                * symmetric and asymmetric Rx PAUSE, as such we fall
+                * through to the fc_full statement.  Later, we will
+                * disable the adapter's ability to send PAUSE frames.
+                */
+       case ixgbe_fc_full:
+               /* Flow control (both Rx and Tx) is enabled by SW override. */
+               reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
+               if (hw->phy.media_type == ixgbe_media_type_backplane)
+                       reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
+                                 IXGBE_AUTOC_ASM_PAUSE;
+               else if (hw->phy.media_type == ixgbe_media_type_copper)
+                       reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
+               break;
+       default:
+               DEBUGOUT("Flow control param set incorrectly\n");
+               ret_val = IXGBE_ERR_CONFIG;
+               goto out;
+               break;
+       }
+
+       if (hw->mac.type != ixgbe_mac_X540) {
+               /*
+                * Enable auto-negotiation between the MAC & PHY;
+                * the MAC will advertise clause 37 flow control.
+                */
+               IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
+               reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
+
+               /* Disable AN timeout */
+               if (hw->fc.strict_ieee)
+                       reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
+
+               IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
+               DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
+       }
+
+       /*
+        * AUTOC restart handles negotiation of 1G and 10G on backplane
+        * and copper. There is no need to set the PCS1GCTL register.
+        *
+        */
+       if (hw->phy.media_type == ixgbe_media_type_backplane) {
+               reg_bp |= IXGBE_AUTOC_AN_RESTART;
+               IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
+       } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
+                   (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
+               hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
+                                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
+       }
+
+       DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
+out:
+       return ret_val;
+}
+
+/**
  *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
  *  @hw: pointer to hardware structure
  *
@@ -156,6 +320,7 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
  **/
 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
 {
+       s32 ret_val;
        u32 ctrl_ext;
 
        DEBUGFUNC("ixgbe_start_hw_generic");
@@ -178,12 +343,15 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
        IXGBE_WRITE_FLUSH(hw);
 
        /* Setup flow control */
-       ixgbe_setup_fc(hw, 0);
+       ret_val = ixgbe_setup_fc(hw);
+       if (ret_val != IXGBE_SUCCESS)
+               goto out;
 
        /* Clear adapter stopped flag */
        hw->adapter_stopped = FALSE;
 
-       return IXGBE_SUCCESS;
+out:
+       return ret_val;
 }
 
 /**
@@ -211,14 +379,14 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
        /* Disable relaxed ordering */
        for (i = 0; i < hw->mac.max_tx_queues; i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
-               regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+               regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
        }
 
        for (i = 0; i < hw->mac.max_rx_queues; i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
-               regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-                           IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+               regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+                           IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
                IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
        }
 
@@ -583,6 +751,9 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
        case IXGBE_PCI_LINK_SPEED_5000:
                hw->bus.speed = ixgbe_bus_speed_5000;
                break;
+       case IXGBE_PCI_LINK_SPEED_8000:
+               hw->bus.speed = ixgbe_bus_speed_8000;
+               break;
        default:
                hw->bus.speed = ixgbe_bus_speed_unknown;
                break;
@@ -2242,27 +2413,44 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
 /**
  *  ixgbe_fc_enable_generic - Enable flow control
  *  @hw: pointer to hardware structure
- *  @packetbuf_num: packet buffer number (0-7)
  *
  *  Enable flow control according to the current settings.
  **/
-s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
+s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
 {
        s32 ret_val = IXGBE_SUCCESS;
        u32 mflcn_reg, fccfg_reg;
        u32 reg;
        u32 fcrtl, fcrth;
+       int i;
 
        DEBUGFUNC("ixgbe_fc_enable_generic");
 
-       /* Negotiate the fc mode to use */
-       ret_val = ixgbe_fc_autoneg(hw);
-       if (ret_val == IXGBE_ERR_FLOW_CONTROL)
+       /* Validate the water mark configuration */
+       if (!hw->fc.pause_time) {
+               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
                goto out;
+       }
+
+       /* Low water mark of zero causes XOFF floods */
+       for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+               if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+                   hw->fc.high_water[i]) {
+                       if (!hw->fc.low_water[i] ||
+                           hw->fc.low_water[i] >= hw->fc.high_water[i]) {
+                               DEBUGOUT("Invalid water mark configuration\n");
+                               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+                               goto out;
+                       }
+               }
+       }
+
+       /* Negotiate the fc mode to use */
+       ixgbe_fc_autoneg(hw);
 
        /* Disable any previous flow control settings */
        mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
-       mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
+       mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
 
        fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
        fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
@@ -2319,120 +2507,110 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
        IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
        IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
 
-       fcrth = hw->fc.high_water[packetbuf_num] << 10;
-       fcrtl = hw->fc.low_water << 10;
 
-       if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
-               fcrth |= IXGBE_FCRTH_FCEN;
-               if (hw->fc.send_xon)
-                       fcrtl |= IXGBE_FCRTL_XONE;
-       }
+       /* Set up and enable Rx high/low water mark thresholds, enable XON. */
+       for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
+               if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
+                   hw->fc.high_water[i]) {
+                       fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
+                       fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
+               } else {
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
+                       /*
+                        * In order to prevent Tx hangs when the internal Tx
+                        * switch is enabled we must set the high water mark
+                        * to the maximum FCRTH value.  This allows the Tx
+                        * switch to function even under heavy Rx workloads.
+                        */
+                       fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
+               }
 
-       IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
-       IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
+               IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
+       }
 
        /* Configure pause time (2 TCs per register) */
-       reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
-       if ((packetbuf_num & 1) == 0)
-               reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
-       else
-               reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
-       IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
+       reg = hw->fc.pause_time * 0x00010001;
+       for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
+               IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
 
-       IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
+       /* Configure flow control refresh threshold value */
+       IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
 
 out:
        return ret_val;
 }
 
 /**
- *  ixgbe_fc_autoneg - Configure flow control
+ *  ixgbe_negotiate_fc - Negotiate flow control
  *  @hw: pointer to hardware structure
+ *  @adv_reg: flow control advertised settings
+ *  @lp_reg: link partner's flow control settings
+ *  @adv_sym: symmetric pause bit in advertisement
+ *  @adv_asm: asymmetric pause bit in advertisement
+ *  @lp_sym: symmetric pause bit in link partner advertisement
+ *  @lp_asm: asymmetric pause bit in link partner advertisement
  *
- *  Compares our advertised flow control capabilities to those advertised by
- *  our link partner, and determines the proper flow control mode to use.
+ *  Find the intersection between advertised settings and link partner's
+ *  advertised settings
  **/
-s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
+static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
+                             u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
 {
-       s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
-       ixgbe_link_speed speed;
-       bool link_up;
+       if ((!(adv_reg)) ||  (!(lp_reg)))
+               return IXGBE_ERR_FC_NOT_NEGOTIATED;
 
-       DEBUGFUNC("ixgbe_fc_autoneg");
+       if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
+               /*
+                * Now we need to check if the user selected Rx ONLY
+                * of pause frames.  In this case, we had to advertise
+                * FULL flow control because we could not advertise RX
+                * ONLY. Hence, we must now check to see if we need to
+                * turn OFF the TRANSMISSION of PAUSE frames.
+                */
+               if (hw->fc.requested_mode == ixgbe_fc_full) {
+                       hw->fc.current_mode = ixgbe_fc_full;
+                       DEBUGOUT("Flow Control = FULL.\n");
+               } else {
+                       hw->fc.current_mode = ixgbe_fc_rx_pause;
+                       DEBUGOUT("Flow Control=RX PAUSE frames only\n");
+               }
+       } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
+                  (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
+               hw->fc.current_mode = ixgbe_fc_tx_pause;
+               DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
+       } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
+                  !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
+               hw->fc.current_mode = ixgbe_fc_rx_pause;
+               DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
+       } else {
+               hw->fc.current_mode = ixgbe_fc_none;
+               DEBUGOUT("Flow Control = NONE.\n");
+       }
+       return IXGBE_SUCCESS;
+}
 
-       if (hw->fc.disable_fc_autoneg)
-               goto out;
+/**
+ *  ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
+ *  @hw: pointer to hardware structure
+ *
+ *  Enable flow control according on 1 gig fiber.
+ **/
+static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
+{
+       u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
+       s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 
        /*
-        * AN should have completed when the cable was plugged in.
-        * Look for reasons to bail out.  Bail out if:
-        * - FC autoneg is disabled, or if
-        * - link is not up.
-        *
-        * Since we're being called from an LSC, link is already known to be up.
-        * So use link_up_wait_to_complete=FALSE.
-        */
-       hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
-       if (!link_up) {
-               ret_val = IXGBE_ERR_FLOW_CONTROL;
-               goto out;
-       }
-
-       switch (hw->phy.media_type) {
-       /* Autoneg flow control on fiber adapters */
-       case ixgbe_media_type_fiber:
-               if (speed == IXGBE_LINK_SPEED_1GB_FULL)
-                       ret_val = ixgbe_fc_autoneg_fiber(hw);
-               break;
-
-       /* Autoneg flow control on backplane adapters */
-       case ixgbe_media_type_backplane:
-               ret_val = ixgbe_fc_autoneg_backplane(hw);
-               break;
-
-       /* Autoneg flow control on copper adapters */
-       case ixgbe_media_type_copper:
-               if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
-                       ret_val = ixgbe_fc_autoneg_copper(hw);
-               break;
-
-       default:
-               break;
-       }
-
-out:
-       if (ret_val == IXGBE_SUCCESS) {
-               hw->fc.fc_was_autonegged = TRUE;
-       } else {
-               hw->fc.fc_was_autonegged = FALSE;
-               hw->fc.current_mode = hw->fc.requested_mode;
-       }
-       return ret_val;
-}
-
-/**
- *  ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
- *  @hw: pointer to hardware structure
- *
- *  Enable flow control according on 1 gig fiber.
- **/
-static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
-{
-       u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
-       s32 ret_val;
-
-       /*
-        * On multispeed fiber at 1g, bail out if
-        * - link is up but AN did not complete, or if
-        * - link is up and AN completed but timed out
+        * On multispeed fiber at 1g, bail out if
+        * - link is up but AN did not complete, or if
+        * - link is up and AN completed but timed out
         */
 
        linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
        if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
-           (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
-               ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
+           (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
                goto out;
-       }
 
        pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
        pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
@@ -2456,7 +2634,7 @@ out:
 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
 {
        u32 links2, anlp1_reg, autoc_reg, links;
-       s32 ret_val;
+       s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 
        /*
         * On backplane, bail out if
@@ -2464,21 +2642,13 @@ static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
         * - we are 82599 and link partner is not AN enabled
         */
        links = IXGBE_READ_REG(hw, IXGBE_LINKS);
-       if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
-               hw->fc.fc_was_autonegged = FALSE;
-               hw->fc.current_mode = hw->fc.requested_mode;
-               ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
+       if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
                goto out;
-       }
 
        if (hw->mac.type == ixgbe_mac_82599EB) {
                links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
-               if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
-                       hw->fc.fc_was_autonegged = FALSE;
-                       hw->fc.current_mode = hw->fc.requested_mode;
-                       ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
+               if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
                        goto out;
-               }
        }
        /*
         * Read the 10g AN autoc and LP ability registers and resolve
@@ -2520,227 +2690,62 @@ static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_negotiate_fc - Negotiate flow control
- *  @hw: pointer to hardware structure
- *  @adv_reg: flow control advertised settings
- *  @lp_reg: link partner's flow control settings
- *  @adv_sym: symmetric pause bit in advertisement
- *  @adv_asm: asymmetric pause bit in advertisement
- *  @lp_sym: symmetric pause bit in link partner advertisement
- *  @lp_asm: asymmetric pause bit in link partner advertisement
- *
- *  Find the intersection between advertised settings and link partner's
- *  advertised settings
- **/
-static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
-                             u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
-{
-       if ((!(adv_reg)) ||  (!(lp_reg)))
-               return IXGBE_ERR_FC_NOT_NEGOTIATED;
-
-       if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
-               /*
-                * Now we need to check if the user selected Rx ONLY
-                * of pause frames.  In this case, we had to advertise
-                * FULL flow control because we could not advertise RX
-                * ONLY. Hence, we must now check to see if we need to
-                * turn OFF the TRANSMISSION of PAUSE frames.
-                */
-               if (hw->fc.requested_mode == ixgbe_fc_full) {
-                       hw->fc.current_mode = ixgbe_fc_full;
-                       DEBUGOUT("Flow Control = FULL.\n");
-               } else {
-                       hw->fc.current_mode = ixgbe_fc_rx_pause;
-                       DEBUGOUT("Flow Control=RX PAUSE frames only\n");
-               }
-       } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
-                  (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
-               hw->fc.current_mode = ixgbe_fc_tx_pause;
-               DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
-       } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
-                  !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
-               hw->fc.current_mode = ixgbe_fc_rx_pause;
-               DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
-       } else {
-               hw->fc.current_mode = ixgbe_fc_none;
-               DEBUGOUT("Flow Control = NONE.\n");
-       }
-       return IXGBE_SUCCESS;
-}
-
-/**
- *  ixgbe_setup_fc - Set up flow control
+ *  ixgbe_fc_autoneg - Configure flow control
  *  @hw: pointer to hardware structure
  *
- *  Called at init time to set up flow control.
+ *  Compares our advertised flow control capabilities to those advertised by
+ *  our link partner, and determines the proper flow control mode to use.
  **/
-static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
+void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
 {
-       s32 ret_val = IXGBE_SUCCESS;
-       u32 reg = 0, reg_bp = 0;
-       u16 reg_cu = 0;
-
-       DEBUGFUNC("ixgbe_setup_fc");
+       s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
+       ixgbe_link_speed speed;
+       bool link_up;
 
-       /* Validate the packetbuf configuration */
-       if (packetbuf_num < 0 || packetbuf_num > 7) {
-               DEBUGOUT1("Invalid packet buffer number [%d], expected range "
-                         "is 0-7\n", packetbuf_num);
-               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
-               goto out;
-       }
+       DEBUGFUNC("ixgbe_fc_autoneg");
 
        /*
-        * Validate the water mark configuration.  Zero water marks are invalid
-        * because it causes the controller to just blast out fc packets.
+        * AN should have completed when the cable was plugged in.
+        * Look for reasons to bail out.  Bail out if:
+        * - FC autoneg is disabled, or if
+        * - link is not up.
         */
-       if (!hw->fc.low_water ||
-           !hw->fc.high_water[packetbuf_num] ||
-           !hw->fc.pause_time) {
-               DEBUGOUT("Invalid water mark configuration\n");
-               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+       if (hw->fc.disable_fc_autoneg)
                goto out;
-       }
 
-       /*
-        * Validate the requested mode.  Strict IEEE mode does not allow
-        * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
-        */
-       if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
-               DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
-               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+       hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
+       if (!link_up)
                goto out;
-       }
-
-       /*
-        * 10gig parts do not have a word in the EEPROM to determine the
-        * default flow control setting, so we explicitly set it to full.
-        */
-       if (hw->fc.requested_mode == ixgbe_fc_default)
-               hw->fc.requested_mode = ixgbe_fc_full;
-
-       /*
-        * Set up the 1G and 10G flow control advertisement registers so the
-        * HW will be able to do fc autoneg once the cable is plugged in.  If
-        * we link at 10G, the 1G advertisement is harmless and vice versa.
-        */
 
        switch (hw->phy.media_type) {
+       /* Autoneg flow control on fiber adapters */
        case ixgbe_media_type_fiber:
+               if (speed == IXGBE_LINK_SPEED_1GB_FULL)
+                       ret_val = ixgbe_fc_autoneg_fiber(hw);
+               break;
+
+       /* Autoneg flow control on backplane adapters */
        case ixgbe_media_type_backplane:
-               reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
-               reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+               ret_val = ixgbe_fc_autoneg_backplane(hw);
                break;
 
+       /* Autoneg flow control on copper adapters */
        case ixgbe_media_type_copper:
-               hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
-                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
+               if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
+                       ret_val = ixgbe_fc_autoneg_copper(hw);
                break;
 
        default:
-               ;
-       }
-
-       /*
-        * The possible values of fc.requested_mode are:
-        * 0: Flow control is completely disabled
-        * 1: Rx flow control is enabled (we can receive pause frames,
-        *    but not send pause frames).
-        * 2: Tx flow control is enabled (we can send pause frames but
-        *    we do not support receiving pause frames).
-        * 3: Both Rx and Tx flow control (symmetric) are enabled.
-        * other: Invalid.
-        */
-       switch (hw->fc.requested_mode) {
-       case ixgbe_fc_none:
-               /* Flow control completely disabled by software override. */
-               reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
-               if (hw->phy.media_type == ixgbe_media_type_backplane)
-                       reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
-                                   IXGBE_AUTOC_ASM_PAUSE);
-               else if (hw->phy.media_type == ixgbe_media_type_copper)
-                       reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
-               break;
-       case ixgbe_fc_rx_pause:
-               /*
-                * Rx Flow control is enabled and Tx Flow control is
-                * disabled by software override. Since there really
-                * isn't a way to advertise that we are capable of RX
-                * Pause ONLY, we will advertise that we support both
-                * symmetric and asymmetric Rx PAUSE.  Later, we will
-                * disable the adapter's ability to send PAUSE frames.
-                */
-               reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
-               if (hw->phy.media_type == ixgbe_media_type_backplane)
-                       reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
-                                  IXGBE_AUTOC_ASM_PAUSE);
-               else if (hw->phy.media_type == ixgbe_media_type_copper)
-                       reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
-               break;
-       case ixgbe_fc_tx_pause:
-               /*
-                * Tx Flow control is enabled, and Rx Flow control is
-                * disabled by software override.
-                */
-               reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
-               reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
-               if (hw->phy.media_type == ixgbe_media_type_backplane) {
-                       reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
-                       reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
-               } else if (hw->phy.media_type == ixgbe_media_type_copper) {
-                       reg_cu |= (IXGBE_TAF_ASM_PAUSE);
-                       reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
-               }
-               break;
-       case ixgbe_fc_full:
-               /* Flow control (both Rx and Tx) is enabled by SW override. */
-               reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
-               if (hw->phy.media_type == ixgbe_media_type_backplane)
-                       reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
-                                  IXGBE_AUTOC_ASM_PAUSE);
-               else if (hw->phy.media_type == ixgbe_media_type_copper)
-                       reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
-               break;
-       default:
-               DEBUGOUT("Flow control param set incorrectly\n");
-               ret_val = IXGBE_ERR_CONFIG;
-               goto out;
                break;
        }
 
-       if (hw->mac.type != ixgbe_mac_X540) {
-               /*
-                * Enable auto-negotiation between the MAC & PHY;
-                * the MAC will advertise clause 37 flow control.
-                */
-               IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
-               reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
-
-               /* Disable AN timeout */
-               if (hw->fc.strict_ieee)
-                       reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
-
-               IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
-               DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
-       }
-
-       /*
-        * AUTOC restart handles negotiation of 1G and 10G on backplane
-        * and copper. There is no need to set the PCS1GCTL register.
-        *
-        */
-       if (hw->phy.media_type == ixgbe_media_type_backplane) {
-               reg_bp |= IXGBE_AUTOC_AN_RESTART;
-               IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
-       } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
-                   (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
-               hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
-                                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
-       }
-
-       DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
 out:
-       return ret_val;
+       if (ret_val == IXGBE_SUCCESS) {
+               hw->fc.fc_was_autonegged = TRUE;
+       } else {
+               hw->fc.fc_was_autonegged = FALSE;
+               hw->fc.current_mode = hw->fc.requested_mode;
+       }
 }
 
 /**
@@ -3131,20 +3136,35 @@ san_mac_addr_out:
  *  Read PCIe configuration space, and get the MSI-X vector count from
  *  the capabilities table.
  **/
-u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
+u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
 {
-       u32 msix_count = 64;
+       u16 msix_count = 1;
+       u16 max_msix_count;
+       u16 pcie_offset;
+
+       switch (hw->mac.type) {
+       case ixgbe_mac_82598EB:
+               pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
+               max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
+               break;
+       case ixgbe_mac_82599EB:
+       case ixgbe_mac_X540:
+               pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
+               max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
+               break;
+       default:
+               return msix_count;
+       }
 
        DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
-       if (hw->mac.msix_vectors_from_pcie) {
-               msix_count = IXGBE_READ_PCIE_WORD(hw,
-                                                 IXGBE_PCIE_MSIX_82599_CAPS);
-               msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
-
-               /* MSI-X count is zero-based in HW, so increment to give
-                * proper value */
-               msix_count++;
-       }
+       msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
+       msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
+
+       /* MSI-X count is zero-based in HW */
+       msix_count++;
+
+       if (msix_count > max_msix_count)
+               msix_count = max_msix_count;
 
        return msix_count;
 }
@@ -3299,6 +3319,33 @@ s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 }
 
 /**
+ *  This function should only be involved in the IOV mode.
+ *  In IOV mode, Default pool is next pool after the number of
+ *  VFs advertized and not 0.
+ *  MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
+ *
+ *  ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
+ *  @hw: pointer to hardware struct
+ *  @vmdq: VMDq pool index
+ **/
+s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
+{
+       u32 rar = hw->mac.san_mac_rar_index;
+
+       DEBUGFUNC("ixgbe_set_vmdq_san_mac");
+
+       if (vmdq < 32) {
+               IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
+               IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
+       } else {
+               IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
+       }
+
+       return IXGBE_SUCCESS;
+}
+
+/**
  *  ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
  *  @hw: pointer to hardware structure
  **/
@@ -3718,30 +3765,6 @@ out:
 }
 
 /**
- *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
- *  control
- *  @hw: pointer to hardware structure
- *
- *  There are several phys that do not support autoneg flow control. This
- *  function check the device id to see if the associated phy supports
- *  autoneg flow control.
- **/
-static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
-{
-
-       DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
-
-       switch (hw->device_id) {
-       case IXGBE_DEV_ID_X540T:
-               return IXGBE_SUCCESS;
-       case IXGBE_DEV_ID_82599_T3_LOM:
-               return IXGBE_SUCCESS;
-       default:
-               return IXGBE_ERR_FC_NOT_SUPPORTED;
-       }
-}
-
-/**
  *  ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
  *  @hw: pointer to hardware structure
  *  @enable: enable or disable switch for anti-spoofing
@@ -3765,20 +3788,22 @@ void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
         * PFVFSPOOF register array is size 8 with 8 bits assigned to
         * MAC anti-spoof enables in each register array element.
         */
-       for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
+       for (j = 0; j < pf_target_reg; j++)
                IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
 
-       /* If not enabling anti-spoofing then done */
-       if (!enable)
-               return;
-
        /*
         * The PF should be allowed to spoof so that it can support
-        * emulation mode NICs.  Reset the bit assigned to the PF
+        * emulation mode NICs.  Do not set the bits assigned to the PF
+        */
+       pfvfspoof &= (1 << pf_target_shift) - 1;
+       IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
+
+       /*
+        * Remaining pools belong to the PF so they do not need to have
+        * anti-spoofing enabled.
         */
-       pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
-       pfvfspoof ^= (1 << pf_target_shift);
-       IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
+       for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
+               IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
 }
 
 /**
@@ -3837,14 +3862,14 @@ void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
        /* Enable relaxed ordering */
        for (i = 0; i < hw->mac.max_tx_queues; i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
-               regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+               regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
        }
 
        for (i = 0; i < hw->mac.max_rx_queues; i++) {
                regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
-               regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-                          IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+               regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+                         IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
                IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
        }
 
@@ -3878,7 +3903,7 @@ static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
  *  @hw: pointer to the HW structure
  *  @buffer: contains the command to write and where the return status will
  *   be placed
- *  @lenght: lenght of buffer, must be multiple of 4 bytes
+ *  @length: length of buffer, must be multiple of 4 bytes
  *
  *  Communicates with the manageability block.  On success return IXGBE_SUCCESS
  *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
@@ -4057,17 +4082,17 @@ void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
         * buffers requested using supplied strategy.
         */
        switch (strategy) {
-       case (PBA_STRATEGY_WEIGHTED):
+       case PBA_STRATEGY_WEIGHTED:
                /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
                 * buffer with 5/8 of the packet buffer space.
                 */
-               rxpktsize = (pbsize * 5 * 2) / (num_pb * 8);
+               rxpktsize = (pbsize * 5) / (num_pb * 4);
                pbsize -= rxpktsize * (num_pb / 2);
                rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
                for (; i < (num_pb / 2); i++)
                        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
                /* Fall through to configure remaining packet buffers */
-       case (PBA_STRATEGY_EQUAL):
+       case PBA_STRATEGY_EQUAL:
                rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
                for (; i < num_pb; i++)
                        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
index 47b1631..0dad30e 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.h,v 1.11 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.h,v 1.12 2012/07/05 20:51:44 jfv Exp $*/
 
 #ifndef _IXGBE_COMMON_H_
 #define _IXGBE_COMMON_H_
@@ -42,7 +42,7 @@
                IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
        } while (0)
 
-u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
+u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
 
 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
@@ -95,8 +95,8 @@ s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw);
 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw);
 
-s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
-s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
+s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
+void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
 
 s32 ixgbe_validate_mac_addr(u8 *mac_addr);
 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
@@ -110,6 +110,7 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
 
 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
index 8dbfa96..7134dcd 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_osdep.h,v 1.12 2012/01/30 23:03:21 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_osdep.h,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
 
 #ifndef _IXGBE_OS_H_
 #define _IXGBE_OS_H_
@@ -53,6 +53,7 @@
 #include <bus/pci/pcireg.h>
 
 #define ASSERT(x) if(!(x)) panic("IXGBE: x")
+#define EWARN(H, W, S) kprintf(W)
 
 /* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
 #define usec_delay(x) DELAY(x)
@@ -109,6 +110,14 @@ typedef uint64_t   u64;
 typedef boolean_t      bool;
 #endif
 
+/* shared code requires this */
+#define __le16  u16
+#define __le32  u32
+#define __le64  u64
+#define __be16  u16
+#define __be32  u32
+#define __be64  u64
+
 #define le16_to_cpu 
 
 #if defined(__i386__) || defined(__amd64__)
index 46d08b1..9277eb0 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.12 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
 
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
@@ -1020,6 +1020,8 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
                  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
                  * 9   SFP_1g_cu_CORE0 - 82599-specific
                  * 10  SFP_1g_cu_CORE1 - 82599-specific
+                 * 11  SFP_1g_sx_CORE0 - 82599-specific
+                 * 12  SFP_1g_sx_CORE1 - 82599-specific
                  */
                if (hw->mac.type == ixgbe_mac_82598EB) {
                        if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
@@ -1070,6 +1072,13 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
                                else
                                        hw->phy.sfp_type =
                                                ixgbe_sfp_type_1g_cu_core1;
+                       } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
+                               if (hw->bus.lan_id == 0)
+                                       hw->phy.sfp_type =
+                                               ixgbe_sfp_type_1g_sx_core0;
+                               else
+                                       hw->phy.sfp_type =
+                                               ixgbe_sfp_type_1g_sx_core1;
                        } else {
                                hw->phy.sfp_type = ixgbe_sfp_type_unknown;
                        }
@@ -1162,7 +1171,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
                /* Verify supported 1G SFP modules */
                if (comp_codes_10g == 0 &&
                    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
-                     hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
+                     hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
+                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0  ||
+                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
                        hw->phy.type = ixgbe_phy_sfp_unsupported;
                        status = IXGBE_ERR_SFP_NOT_SUPPORTED;
                        goto out;
@@ -1177,14 +1188,31 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
                ixgbe_get_device_caps(hw, &enforce_sfp);
                if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
                    !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
-                     (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
+                     (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
+                     (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0)  ||
+                     (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
                        /* Make sure we're a supported PHY type */
                        if (hw->phy.type == ixgbe_phy_sfp_intel) {
                                status = IXGBE_SUCCESS;
                        } else {
-                               DEBUGOUT("SFP+ module not supported\n");
-                               hw->phy.type = ixgbe_phy_sfp_unsupported;
-                               status = IXGBE_ERR_SFP_NOT_SUPPORTED;
+                               if (hw->allow_unsupported_sfp == TRUE) {
+                                       EWARN(hw, "WARNING: Intel (R) Network "
+                                             "Connections are quality tested "
+                                             "using Intel (R) Ethernet Optics."
+                                             " Using untested modules is not "
+                                             "supported and may cause unstable"
+                                             " operation or damage to the "
+                                             "module or the adapter. Intel "
+                                             "Corporation is not responsible "
+                                             "for any harm caused by using "
+                                             "untested modules.\n", status);
+                                       status = IXGBE_SUCCESS;
+                               } else {
+                                       DEBUGOUT("SFP+ module not supported\n");
+                                       hw->phy.type =
+                                               ixgbe_phy_sfp_unsupported;
+                                       status = IXGBE_ERR_SFP_NOT_SUPPORTED;
+                               }
                        }
                } else {
                        status = IXGBE_SUCCESS;
@@ -1238,10 +1266,12 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
         * SR modules
         */
        if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
-           sfp_type == ixgbe_sfp_type_1g_cu_core0)
+           sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
+           sfp_type == ixgbe_sfp_type_1g_sx_core0)
                sfp_type = ixgbe_sfp_type_srlr_core0;
        else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
-                sfp_type == ixgbe_sfp_type_1g_cu_core1)
+                sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+                sfp_type == ixgbe_sfp_type_1g_sx_core1)
                sfp_type = ixgbe_sfp_type_srlr_core1;
 
        /* Read offset to PHY init contents */
@@ -1715,15 +1745,24 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
  **/
 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
 {
+       u32 i = 0;
+       u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
+       u32 i2cctl_r = 0;
+
        DEBUGFUNC("ixgbe_raise_i2c_clk");
 
-       *i2cctl |= IXGBE_I2C_CLK_OUT;
+       for (i = 0; i < timeout; i++) {
+               *i2cctl |= IXGBE_I2C_CLK_OUT;
 
-       IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
-       IXGBE_WRITE_FLUSH(hw);
+               IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+               IXGBE_WRITE_FLUSH(hw);
+               /* SCL rise time (1000ns) */
+               usec_delay(IXGBE_I2C_T_RISE);
 
-       /* SCL rise time (1000ns) */
-       usec_delay(IXGBE_I2C_T_RISE);
+               i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+               if (i2cctl_r & IXGBE_I2C_CLK_IN)
+                       break;
+       }
 }
 
 /**
@@ -1840,7 +1879,7 @@ void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_tn_check_overtemp - Checks if an overtemp occured.
+ *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
  *  @hw: pointer to hardware structure
  *
  *  Checks if the LASI temp alarm status was triggered due to overtemp
index 79a5d95..c6892c4 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_type.h,v 1.13 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_type.h,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
 
 #ifndef _IXGBE_TYPE_H_
 #define _IXGBE_TYPE_H_
 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE      0x152A
 #define IXGBE_DEV_ID_82599_SFP_FCOE            0x1529
 #define IXGBE_DEV_ID_82599_SFP_EM              0x1507
+#define IXGBE_DEV_ID_82599_SFP_SF2             0x154D
 #define IXGBE_DEV_ID_82599EN_SFP               0x1557
 #define IXGBE_DEV_ID_82599_XAUI_LOM            0x10FC
 #define IXGBE_DEV_ID_82599_T3_LOM              0x151C
 #define IXGBE_DEV_ID_82599_VF                  0x10ED
 #define IXGBE_DEV_ID_X540_VF                   0x1515
 #define IXGBE_DEV_ID_X540T                     0x1528
+#define IXGBE_DEV_ID_X540T1                    0x1560
 
 /* General Registers */
 #define IXGBE_CTRL             0x00000
 #define IXGBE_I2C_CLK_OUT      0x00000002
 #define IXGBE_I2C_DATA_IN      0x00000004
 #define IXGBE_I2C_DATA_OUT     0x00000008
+#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT     500
+
 
 /* Interrupt Registers */
 #define IXGBE_EICR             0x00800
 #define IXGBE_GCR_EXT_VT_MODE_64       0x00000003
 #define IXGBE_GCR_EXT_SRIOV            (IXGBE_GCR_EXT_MSIX_EN | \
                                         IXGBE_GCR_EXT_VT_MODE_64)
+#define IXGBE_GCR_EXT_VT_MODE_MASK     0x00000003
 /* Time Sync Registers */
 #define IXGBE_TSYNCRXCTL       0x05188 /* Rx Time Sync Control register - RW */
 #define IXGBE_TSYNCTXCTL       0x08C00 /* Tx Time Sync Control register - RW */
 #define IXGBE_TRGTTIMH0        0x08C28 /* Target Time Register 0 High - RW */
 #define IXGBE_TRGTTIML1        0x08C2C /* Target Time Register 1 Low - RW */
 #define IXGBE_TRGTTIMH1        0x08C30 /* Target Time Register 1 High - RW */
+#define IXGBE_CLKTIML  0x08C34 /* Clock Out Time Register Low - RW */
+#define IXGBE_CLKTIMH  0x08C38 /* Clock Out Time Register High - RW */
 #define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
 #define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
 #define IXGBE_AUXSTMPL0        0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN   (1 << 6) /* Rx Desc header ena */
 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN   (1 << 7) /* Rx Desc payload ena */
 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN   (1 << 9) /* Rx rd Desc Relax Order */
-#define IXGBE_DCA_RXCTRL_DESC_WRO_EN   (1 << 13) /* Rx wr Desc Relax Order */
-#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN  (1 << 15) /* Rx Split Header RO */
+#define IXGBE_DCA_RXCTRL_DATA_WRO_EN   (1 << 13) /* Rx wr data Relax Order */
+#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN   (1 << 15) /* Rx wr header RO */
 
 #define IXGBE_DCA_TXCTRL_CPUID_MASK    0x0000001F /* Tx CPUID Mask */
 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599      0xFF000000 /* Tx CPUID Mask */
 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599     24 /* Tx CPUID Shift */
 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN   (1 << 5) /* DCA Tx Desc enable */
-#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN   (1 << 11) /* Tx Desc writeback RO bit */
+#define IXGBE_DCA_TXCTRL_DESC_RRO_EN   (1 << 9) /* Tx rd Desc Relax Order */
+#define IXGBE_DCA_TXCTRL_DESC_WRO_EN   (1 << 11) /* Tx Desc writeback RO bit */
+#define IXGBE_DCA_TXCTRL_DATA_RRO_EN   (1 << 13) /* Tx rd data Relax Order */
 #define IXGBE_DCA_MAX_QUEUES_82598     16 /* DCA regs only on 16 queues */
 
 /* MSCA Bit Masks */
@@ -1382,6 +1391,7 @@ enum {
 #define IXGBE_EICR_LINKSEC     0x00200000 /* PN Threshold */
 #define IXGBE_EICR_MNG         0x00400000 /* Manageability Event Interrupt */
 #define IXGBE_EICR_TS          0x00800000 /* Thermal Sensor Event */
+#define IXGBE_EICR_TIMESYNC    0x01000000 /* Timesync Event */
 #define IXGBE_EICR_GPI_SDP0    0x01000000 /* Gen Purpose Interrupt on SDP0 */
 #define IXGBE_EICR_GPI_SDP1    0x02000000 /* Gen Purpose Interrupt on SDP1 */
 #define IXGBE_EICR_GPI_SDP2    0x04000000 /* Gen Purpose Interrupt on SDP2 */
@@ -1399,6 +1409,7 @@ enum {
 #define IXGBE_EICS_MAILBOX     IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
 #define IXGBE_EICS_LSC         IXGBE_EICR_LSC /* Link Status Change */
 #define IXGBE_EICS_MNG         IXGBE_EICR_MNG /* MNG Event Interrupt */
+#define IXGBE_EICS_TIMESYNC    IXGBE_EICR_TIMESYNC /* Timesync Event */
 #define IXGBE_EICS_GPI_SDP0    IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
 #define IXGBE_EICS_GPI_SDP1    IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
 #define IXGBE_EICS_GPI_SDP2    IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
@@ -1417,6 +1428,7 @@ enum {
 #define IXGBE_EIMS_LSC         IXGBE_EICR_LSC /* Link Status Change */
 #define IXGBE_EIMS_MNG         IXGBE_EICR_MNG /* MNG Event Interrupt */
 #define IXGBE_EIMS_TS          IXGBE_EICR_TS /* Thermal Sensor Event */
+#define IXGBE_EIMS_TIMESYNC    IXGBE_EICR_TIMESYNC /* Timesync Event */
 #define IXGBE_EIMS_GPI_SDP0    IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
 #define IXGBE_EIMS_GPI_SDP1    IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
 #define IXGBE_EIMS_GPI_SDP2    IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
@@ -1434,6 +1446,7 @@ enum {
 #define IXGBE_EIMC_MAILBOX     IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
 #define IXGBE_EIMC_LSC         IXGBE_EICR_LSC /* Link Status Change */
 #define IXGBE_EIMC_MNG         IXGBE_EICR_MNG /* MNG Event Interrupt */
+#define IXGBE_EIMC_TIMESYNC    IXGBE_EICR_TIMESYNC /* Timesync Event */
 #define IXGBE_EIMC_GPI_SDP0    IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
 #define IXGBE_EIMC_GPI_SDP1    IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
 #define IXGBE_EIMC_GPI_SDP2    IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
@@ -1519,6 +1532,7 @@ enum {
 #define IXGBE_ETQF_1588                        0x40000000 /* bit 30 */
 #define IXGBE_ETQF_FILTER_EN           0x80000000 /* bit 31 */
 #define IXGBE_ETQF_POOL_ENABLE         (1 << 26) /* bit 26 */
+#define IXGBE_ETQF_POOL_SHIFT          20
 
 #define IXGBE_ETQS_RX_QUEUE            0x007F0000 /* bits 22:16 */
 #define IXGBE_ETQS_RX_QUEUE_SHIFT      16
@@ -1573,8 +1587,17 @@ enum {
 #define IXGBE_ESDP_SDP4                0x00000010 /* SDP4 Data Value */
 #define IXGBE_ESDP_SDP5                0x00000020 /* SDP5 Data Value */
 #define IXGBE_ESDP_SDP6                0x00000040 /* SDP6 Data Value */
-#define IXGBE_ESDP_SDP4_DIR    0x00000004 /* SDP4 IO direction */
+#define IXGBE_ESDP_SDP7                0x00000080 /* SDP7 Data Value */
+#define IXGBE_ESDP_SDP0_DIR    0x00000100 /* SDP0 IO direction */
+#define IXGBE_ESDP_SDP1_DIR    0x00000200 /* SDP1 IO direction */
+#define IXGBE_ESDP_SDP3_DIR    0x00000800 /* SDP3 IO direction */
+#define IXGBE_ESDP_SDP4_DIR    0x00001000 /* SDP4 IO direction */
 #define IXGBE_ESDP_SDP5_DIR    0x00002000 /* SDP5 IO direction */
+#define IXGBE_ESDP_SDP6_DIR    0x00004000 /* SDP6 IO direction */
+#define IXGBE_ESDP_SDP7_DIR    0x00008000 /* SDP7 IO direction */
+#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */
+#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
+
 
 /* LEDCTL Bit Masks */
 #define IXGBE_LED_IVRT_BASE            0x00000040
@@ -1777,7 +1800,9 @@ enum {
 #define IXGBE_DEVICE_CAPS              0x2C
 #define IXGBE_SERIAL_NUMBER_MAC_ADDR   0x11
 #define IXGBE_PCIE_MSIX_82599_CAPS     0x72
+#define IXGBE_MAX_MSIX_VECTORS_82599   0x40
 #define IXGBE_PCIE_MSIX_82598_CAPS     0x62
+#define IXGBE_MAX_MSIX_VECTORS_82598   0x13
 
 /* MSI-X capability fields masks */
 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK    0x7FF
@@ -1872,6 +1897,7 @@ enum {
 #define IXGBE_PCI_LINK_SPEED           0xF
 #define IXGBE_PCI_LINK_SPEED_2500      0x1
 #define IXGBE_PCI_LINK_SPEED_5000      0x2
+#define IXGBE_PCI_LINK_SPEED_8000      0x3
 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC        0x80
 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
@@ -1934,6 +1960,10 @@ enum {
 #define IXGBE_RXDCTL_RLPML_EN          0x00008000
 #define IXGBE_RXDCTL_VME               0x40000000 /* VLAN mode enable */
 
+#define IXGBE_TSAUXC_EN_CLK            0x00000004
+#define IXGBE_TSAUXC_SYNCLK            0x00000008
+#define IXGBE_TSAUXC_SDP0_INT          0x00000040
+
 #define IXGBE_TSYNCTXCTL_VALID         0x00000001 /* Tx timestamp valid */
 #define IXGBE_TSYNCTXCTL_ENABLED       0x00000010 /* Tx timestamping enabled */
 
@@ -1977,8 +2007,7 @@ enum {
 #define IXGBE_MFLCN_DPF                0x00000002 /* Discard Pause Frame */
 #define IXGBE_MFLCN_RPFCE      0x00000004 /* Receive Priority FC Enable */
 #define IXGBE_MFLCN_RFCE       0x00000008 /* Receive FC Enable */
-#define IXGBE_MFLCN_RPFCM      0x00000004 /* Receive Priority FC Mode */
-#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF0 /* Rx Priority FC bitmap mask */
+#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */
 #define IXGBE_MFLCN_RPFCE_SHIFT        4 /* Rx Priority FC bitmap shift */
 
 /* Multiple Receive Queue Control */
@@ -2513,13 +2542,14 @@ typedef u32 ixgbe_physical_layer;
 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR                0x0800
 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI      0x1000
 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA     0x2000
+#define IXGBE_PHYSICAL_LAYER_1000BASE_SX       0x4000
 
 /* Flow Control Data Sheet defined values
  * Calculation and defines taken from 802.1bb Annex O
  */
 
 /* BitTimes (BT) conversion */
-#define IXGBE_BT2KB(BT)                ((BT + 1023) / (8 * 1024))
+#define IXGBE_BT2KB(BT)                ((BT + (8 * 1024 - 1)) / (8 * 1024))
 #define IXGBE_B2BT(BT)         (BT * 8)
 
 /* Calculate Delay to respond to PFC */
@@ -2550,24 +2580,31 @@ typedef u32 ixgbe_physical_layer;
 #define IXGBE_PCI_DELAY        10000
 
 /* Calculate X540 delay value in bit times */
-#define IXGBE_FILL_RATE        (36 / 25)
-
-#define IXGBE_DV_X540(LINK, TC)        (IXGBE_FILL_RATE * \
-                                (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
-                                (2 * IXGBE_CABLE_DC) + \
-                                (2 * IXGBE_ID_X540) + \
-                                IXGBE_HD + IXGBE_B2BT(TC)))
+#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
+                       ((36 * \
+                         (IXGBE_B2BT(_max_frame_link) + \
+                          IXGBE_PFC_D + \
+                          (2 * IXGBE_CABLE_DC) + \
+                          (2 * IXGBE_ID_X540) + \
+                          IXGBE_HD) / 25 + 1) + \
+                        2 * IXGBE_B2BT(_max_frame_tc))
 
 /* Calculate 82599, 82598 delay value in bit times */
-#define IXGBE_DV(LINK, TC)     (IXGBE_FILL_RATE * \
-                                (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
-                                (2 * IXGBE_CABLE_DC) + (2 * IXGBE_ID) + \
-                                IXGBE_HD + IXGBE_B2BT(TC)))
+#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
+                       ((36 * \
+                         (IXGBE_B2BT(_max_frame_link) + \
+                          IXGBE_PFC_D + \
+                          (2 * IXGBE_CABLE_DC) + \
+                          (2 * IXGBE_ID) + \
+                          IXGBE_HD) / 25 + 1) + \
+                        2 * IXGBE_B2BT(_max_frame_tc))
 
 /* Calculate low threshold delay values */
-#define IXGBE_LOW_DV_X540(TC)  (2 * IXGBE_B2BT(TC) + \
-                               (IXGBE_FILL_RATE * IXGBE_PCI_DELAY))
-#define IXGBE_LOW_DV(TC)       (2 * IXGBE_LOW_DV_X540(TC))
+#define IXGBE_LOW_DV_X540(_max_frame_tc) \
+                       (2 * IXGBE_B2BT(_max_frame_tc) + \
+                       (36 * IXGBE_PCI_DELAY / 25) + 1)
+#define IXGBE_LOW_DV(_max_frame_tc) \
+                       (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
 
 /* Software ATR hash keys */
 #define IXGBE_ATR_BUCKET_HASH_KEY      0x3DAD14E2
@@ -2711,6 +2748,8 @@ enum ixgbe_sfp_type {
        ixgbe_sfp_type_da_act_lmt_core1 = 8,
        ixgbe_sfp_type_1g_cu_core0 = 9,
        ixgbe_sfp_type_1g_cu_core1 = 10,
+       ixgbe_sfp_type_1g_sx_core0 = 11,
+       ixgbe_sfp_type_1g_sx_core1 = 12,
        ixgbe_sfp_type_not_present = 0xFFFE,
        ixgbe_sfp_type_unknown = 0xFFFF
 };
@@ -2760,6 +2799,7 @@ enum ixgbe_bus_speed {
        ixgbe_bus_speed_133     = 133,
        ixgbe_bus_speed_2500    = 2500,
        ixgbe_bus_speed_5000    = 5000,
+       ixgbe_bus_speed_8000    = 8000,
        ixgbe_bus_speed_reserved
 };
 
@@ -2796,7 +2836,7 @@ struct ixgbe_bus_info {
 /* Flow control parameters */
 struct ixgbe_fc_info {
        u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
-       u32 low_water; /* Flow Control Low-water */
+       u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
        u16 pause_time; /* Flow Control Pause timer */
        bool send_xon; /* Flow control send XON */
        bool strict_ieee; /* Strict IEEE mode */
@@ -2955,6 +2995,7 @@ struct ixgbe_mac_operations {
        s32 (*clear_rar)(struct ixgbe_hw *, u32);
        s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
        s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
+       s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
        s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
        s32 (*init_rx_addrs)(struct ixgbe_hw *);
        s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
@@ -2971,7 +3012,7 @@ struct ixgbe_mac_operations {
        void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
 
        /* Flow Control */
-       s32 (*fc_enable)(struct ixgbe_hw *, s32);
+       s32 (*fc_enable)(struct ixgbe_hw *);
 
        /* Manageability interface */
        s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
@@ -3027,11 +3068,11 @@ struct ixgbe_mac_info {
        u32 rx_pb_size;
        u32 max_tx_queues;
        u32 max_rx_queues;
-       u32 max_msix_vectors;
-       bool msix_vectors_from_pcie;
        u32 orig_autoc;
-       bool arc_subsystem_valid;
+       u8  san_mac_rar_index;
        u32 orig_autoc2;
+       u16 max_msix_vectors;
+       bool arc_subsystem_valid;
        bool orig_link_settings_stored;
        bool autotry_restart;
        u8 flags;
@@ -3102,6 +3143,7 @@ struct ixgbe_hw {
        u8 revision_id;
        bool adapter_stopped;
        bool force_full_reset;
+       bool allow_unsupported_sfp;
 };
 
 #define ixgbe_call_func(hw, func, params, error) \
@@ -3138,7 +3180,6 @@ struct ixgbe_hw {
 #define IXGBE_ERR_OVERTEMP                     -26
 #define IXGBE_ERR_FC_NOT_NEGOTIATED            -27
 #define IXGBE_ERR_FC_NOT_SUPPORTED             -28
-#define IXGBE_ERR_FLOW_CONTROL                 -29
 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE       -30
 #define IXGBE_ERR_PBA_SECTION                  -31
 #define IXGBE_ERR_INVALID_ARGUMENT             -32
index a08b753..2b5ba21 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_vf.c,v 1.2 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_vf.c,v 1.3 2012/07/05 20:51:44 jfv Exp $*/
 
 
 #include "ixgbe_api.h"
@@ -366,6 +366,7 @@ s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
 {
        struct ixgbe_mbx_info *mbx = &hw->mbx;
        u32 msgbuf[2];
+       s32 ret_val;
        UNREFERENCED_1PARAMETER(vind);
 
        msgbuf[0] = IXGBE_VF_SET_VLAN;
@@ -373,7 +374,14 @@ s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
        /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
        msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT;
 
-       return mbx->ops.write_posted(hw, msgbuf, 2, 0);
+       ret_val = mbx->ops.write_posted(hw, msgbuf, 2, 0);
+       if (!ret_val)
+               ret_val = mbx->ops.read_posted(hw, msgbuf, 1, 0);
+
+       if (!ret_val && (msgbuf[0] & IXGBE_VT_MSGTYPE_ACK))
+               return IXGBE_SUCCESS;
+
+       return ret_val | (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK);
 }
 
 /**
@@ -491,11 +499,17 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
        else
                *link_up = FALSE;
 
-       if ((links_reg & IXGBE_LINKS_SPEED_10G_82599) ==
-           IXGBE_LINKS_SPEED_10G_82599)
+       switch (links_reg & IXGBE_LINKS_SPEED_10G_82599) {
+       case IXGBE_LINKS_SPEED_10G_82599:
                *speed = IXGBE_LINK_SPEED_10GB_FULL;
-       else
+               break;
+       case IXGBE_LINKS_SPEED_1G_82599:
                *speed = IXGBE_LINK_SPEED_1GB_FULL;
+               break;
+       case IXGBE_LINKS_SPEED_100_82599:
+               *speed = IXGBE_LINK_SPEED_100_FULL;
+               break;
+       }
 
        return IXGBE_SUCCESS;
 }
index 68ae5a0..f662c76 100644 (file)
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c,v 1.1 2012/01/30 16:42:02 jfv Exp $*/
+/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
 
 #include "ixgbe_x540.h"
 #include "ixgbe_type.h"
@@ -98,6 +98,7 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
 
        /* RAR, Multicast, VLAN */
        mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
+       mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
        mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
        mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
        mac->rar_highwater = 1;
@@ -262,6 +263,9 @@ mac_reset_top:
                hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
                                    hw->mac.san_addr, 0, IXGBE_RAH_AV);
 
+               /* Save the SAN MAC RAR index */
+               hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
+
                /* Reserve the last RAR for the SAN MAC address */
                hw->mac.num_rar_entries--;
        }
@@ -798,7 +802,7 @@ out:
  *  @hw: pointer to hardware structure
  *  @mask: Mask to specify which semaphore to release
  *
- *  Releases the SWFW semaphore throught the SW_FW_SYNC register
+ *  Releases the SWFW semaphore through the SW_FW_SYNC register
  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
  **/
 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)