static void pci_disable_msi(device_t dev);
static void pci_enable_msi(device_t dev, uint64_t address,
uint16_t data);
-static void pci_enable_msix(device_t dev, u_int index,
+static void pci_setup_msix_vector(device_t dev, u_int index,
uint64_t address, uint32_t data);
-static void pci_mask_msix(device_t dev, u_int index);
-static void pci_unmask_msix(device_t dev, u_int index);
+static void pci_mask_msix_vector(device_t dev, u_int index);
+static void pci_unmask_msix_vector(device_t dev, u_int index);
static int pci_msi_blacklisted(void);
static void pci_resume_msi(device_t dev);
static void pci_resume_msix(device_t dev);
/*
* Support for MSI-X message interrupts.
*/
-void
-pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
+static void
+pci_setup_msix_vector(device_t dev, u_int index, uint64_t address,
+ uint32_t data)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
pci_ht_map_msi(dev, address);
}
-void
-pci_mask_msix(device_t dev, u_int index)
+static void
+pci_mask_msix_vector(device_t dev, u_int index)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
}
}
-void
-pci_unmask_msix(device_t dev, u_int index)
+static void
+pci_unmask_msix_vector(device_t dev, u_int index)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
}
int
-pci_pending_msix(device_t dev, u_int index)
+pci_pending_msix_vector(device_t dev, u_int index)
{
struct pci_devinfo *dinfo = device_get_ivars(dev);
struct pcicfg_msix *msix = &dinfo->cfg.msix;
if (msix->msix_alloc > 0) {
/* First, mask all vectors. */
for (i = 0; i < msix->msix_msgnum; i++)
- pci_mask_msix(dev, i);
+ pci_mask_msix_vector(dev, i);
/* Second, program any messages with at least one handler. */
for (i = 0; i < msix->msix_table_len; i++) {
if (mte->mte_vector == 0 || mte->mte_handlers == 0)
continue;
mv = &msix->msix_vectors[mte->mte_vector - 1];
- pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
- pci_unmask_msix(dev, i);
+ pci_setup_msix_vector(dev, i, mv->mv_address,
+ mv->mv_data);
+ pci_unmask_msix_vector(dev, i);
}
}
pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
/* Mask all vectors. */
for (i = 0; i < cfg->msix.msix_msgnum; i++)
- pci_mask_msix(child, i);
+ pci_mask_msix_vector(child, i);
/* Allocate and initialize vector data and virtual table. */
cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
mv->mv_data = data;
}
if (mte->mte_handlers == 0) {
- pci_enable_msix(child, rid - 1, mv->mv_address,
- mv->mv_data);
- pci_unmask_msix(child, rid - 1);
+ pci_setup_msix_vector(child, rid - 1,
+ mv->mv_address, mv->mv_data);
+ pci_unmask_msix_vector(child, rid - 1);
}
mte->mte_handlers++;
}
return (EINVAL);
mte->mte_handlers--;
if (mte->mte_handlers == 0)
- pci_mask_msix(child, rid - 1);
+ pci_mask_msix_vector(child, rid - 1);
}
}
error = bus_generic_teardown_intr(dev, child, irq, cookie);