bnx: Properly configure PCI-E PL/DL registers and MAC clock speed
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Sun, 22 Jul 2012 13:20:11 +0000 (21:20 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Thu, 26 Jul 2012 09:21:19 +0000 (17:21 +0800)
According-to: tg3

sys/dev/netif/bge/if_bgereg.h
sys/dev/netif/bnx/if_bnx.c

index 75b5755..abf3bea 100644 (file)
 #define BGE_CHIPREV_5717_BX            0x57171
 #define BGE_CHIPREV_5761_AX            0x57611
 #define BGE_CHIPREV_5784_AX            0x57841
+#define BGE_CHIPREV_57765_AX           0x577850
 
 /* PCI DMA Read/Write Control register */
 #define BGE_PCIDMARWCTL_MINDMA         0x000000FF
 #define BGE_NVRAMACC_WRENABLE          0x00000002
 
 /* Mode control register */
+#define BGE_MODECTL_PCIE_TL_SEL                0x00000000
 #define BGE_MODECTL_INT_SNDCOAL_ONLY   0x00000001
 #define BGE_MODECTL_BYTESWAP_NONFRAME  0x00000002
 #define BGE_MODECTL_WORDSWAP_NONFRAME  0x00000004
 #define BGE_MODECTL_HOST_SEND_BDS      0x00020000
 #define BGE_MODECTL_HTX2B_ENABLE       0x00040000
 #define BGE_MODECTL_TX_NO_PHDR_CSUM    0x00100000
+#define BGE_MODECTL_PCIE_PL_SEL                0x00400000
 #define BGE_MODECTL_RX_NO_PHDR_CSUM    0x00800000
 #define BGE_MODECTL_TX_ATTN_INTR       0x01000000
 #define BGE_MODECTL_RX_ATTN_INTR       0x02000000
 #define BGE_MODECTL_DMA_ATTN_INTR      0x08000000
 #define BGE_MODECTL_FLOWCTL_ATTN_INTR  0x10000000
 #define BGE_MODECTL_4X_SENDRING_SZ     0x20000000
+#define BGE_MODECTL_PCIE_DL_SEL                0x20000000
 #define BGE_MODECTL_FW_PROCESS_MCASTS  0x40000000
+#define BGE_MODECTL_PCIE_HI1K_EN       0x80000000
+#define BGE_MODECTL_PCIE_PORTS \
+       (BGE_MODECTL_PCIE_HI1K_EN | \
+        BGE_MODECTL_PCIE_TL_SEL | \
+        BGE_MODECTL_PCIE_PL_SEL | \
+        BGE_MODECTL_PCIE_DL_SEL)
 
 /* Misc. config register */
 #define BGE_MISCCFG_RESET_CORE_CLOCKS  0x00000001
  * PCI-E Core Private Register Access to TL, DL & PL
  */
 #define BGE_PCIE_TLDLPL_PORT           0x7c00
+#define BGE_PCIE_PL_LO_PHYCTL5         0x7c14
+#define BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
+#define BGE_PCIE_DL_LO_FTSMAX          0x7c0c
+#define BGE_PCIE_DL_LO_FTSMAX_MASK     0x000000ff
+#define BGE_PCIE_DL_LO_FTSMAX_VAL      0x0000002c
 
 /*
  * PCI-E transaction configure register.
index 3dfc6f8..e9865ca 100644 (file)
@@ -1052,6 +1052,45 @@ bnx_chipinit(struct bnx_softc *sc)
            i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
                BNX_MEMWIN_WRITE(sc, i, 0);
 
+       if (BNX_IS_57765_FAMILY(sc)) {
+               uint32_t val;
+
+               if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
+                       mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
+                       val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
+
+                       /* Access the lower 1K of PL PCI-E block registers. */
+                       CSR_WRITE_4(sc, BGE_MODE_CTL,
+                           val | BGE_MODECTL_PCIE_PL_SEL);
+
+                       val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
+                       val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
+                       CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
+
+                       CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
+               }
+               if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
+                       mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
+                       val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
+
+                       /* Access the lower 1K of DL PCI-E block registers. */
+                       CSR_WRITE_4(sc, BGE_MODE_CTL,
+                           val | BGE_MODECTL_PCIE_DL_SEL);
+
+                       val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
+                       val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
+                       val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
+                       CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
+
+                       CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
+               }
+
+               val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
+               val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
+               val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
+               CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
+       }
+
        /* Set up the PCI DMA control register. */
        dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
            (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);