lapic: Move LAPIC related vector installation into lapic_init()
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Sat, 19 Mar 2011 06:46:36 +0000 (14:46 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Sat, 19 Mar 2011 07:52:09 +0000 (15:52 +0800)
sys/platform/pc32/apic/mpapic.c
sys/platform/pc32/i386/mp_machdep.c
sys/platform/pc64/apic/mpapic.c
sys/platform/pc64/x86_64/mp_machdep.c

index 51f6924..22e79a3 100644 (file)
@@ -130,6 +130,34 @@ lapic_init(boolean_t bsp)
        u_int   temp;
 
        /*
+        * Install vectors
+        *
+        * Since IDT is shared between BSP and APs, these vectors
+        * only need to be installed once; we do it on BSP.
+        */
+       if (bsp) {
+               /* Install a 'Spurious INTerrupt' vector */
+               setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
+                   SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
+               /* Install an inter-CPU IPI for TLB invalidation */
+               setidt(XINVLTLB_OFFSET, Xinvltlb,
+                   SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
+               /* Install an inter-CPU IPI for IPIQ messaging */
+               setidt(XIPIQ_OFFSET, Xipiq,
+                   SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+
+               /* Install a timer vector */
+               setidt(XTIMER_OFFSET, Xtimer,
+                   SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+               
+               /* Install an inter-CPU IPI for CPU stop/restart */
+               setidt(XCPUSTOP_OFFSET, Xcpustop,
+                   SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
+       }
+
+       /*
         * Setup LINT0 as ExtINT on the BSP.  This is theoretically an
         * aggregate interrupt input from the 8259.  The INTA cycle
         * will be routed to the external controller (the 8259) which
index 4b41073..3be06c9 100644 (file)
@@ -689,30 +689,6 @@ if (apic_io_enable && ioapic_use_old) {
 
 }
 
-       /*
-        * These are required for SMP operation
-        */
-
-       /* install a 'Spurious INTerrupt' vector */
-       setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
-              SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
-       /* install an inter-CPU IPI for TLB invalidation */
-       setidt(XINVLTLB_OFFSET, Xinvltlb,
-              SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
-       /* install an inter-CPU IPI for IPIQ messaging */
-       setidt(XIPIQ_OFFSET, Xipiq,
-              SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
-       /* install a timer vector */
-       setidt(XTIMER_OFFSET, Xtimer,
-              SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-       
-       /* install an inter-CPU IPI for CPU stop/restart */
-       setidt(XCPUSTOP_OFFSET, Xcpustop,
-              SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
-
        /* start each Application Processor */
        start_all_aps(boot_addr);
 }
index c4a5663..04a5921 100644 (file)
@@ -137,6 +137,34 @@ lapic_init(boolean_t bsp)
        u_int   temp;
 
        /*
+        * Install vectors
+        *
+        * Since IDT is shared between BSP and APs, these vectors
+        * only need to be installed once; we do it on BSP.
+        */
+       if (bsp) {
+               /* Install a 'Spurious INTerrupt' vector */
+               setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
+                   SDT_SYSIGT, SEL_KPL, 0);
+
+               /* Install an inter-CPU IPI for TLB invalidation */
+               setidt(XINVLTLB_OFFSET, Xinvltlb,
+                   SDT_SYSIGT, SEL_KPL, 0);
+
+               /* Install an inter-CPU IPI for IPIQ messaging */
+               setidt(XIPIQ_OFFSET, Xipiq,
+                   SDT_SYSIGT, SEL_KPL, 0);
+
+               /* Install a timer vector */
+               setidt(XTIMER_OFFSET, Xtimer,
+                   SDT_SYSIGT, SEL_KPL, 0);
+
+               /* Install an inter-CPU IPI for CPU stop/restart */
+               setidt(XCPUSTOP_OFFSET, Xcpustop,
+                   SDT_SYSIGT, SEL_KPL, 0);
+       }
+
+       /*
         * Setup LINT0 as ExtINT on the BSP.  This is theoretically an
         * aggregate interrupt input from the 8259.  The INTA cycle
         * will be routed to the external controller (the 8259) which
index 96ddde8..911f447 100644 (file)
@@ -710,30 +710,6 @@ if (apic_io_enable && ioapic_use_old) {
 
 }
 
-       /*
-        * These are required for SMP operation
-        */
-
-       /* install a 'Spurious INTerrupt' vector */
-       setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
-              SDT_SYSIGT, SEL_KPL, 0);
-
-       /* install an inter-CPU IPI for TLB invalidation */
-       setidt(XINVLTLB_OFFSET, Xinvltlb,
-              SDT_SYSIGT, SEL_KPL, 0);
-
-       /* install an inter-CPU IPI for IPIQ messaging */
-       setidt(XIPIQ_OFFSET, Xipiq,
-              SDT_SYSIGT, SEL_KPL, 0);
-
-       /* install a timer vector */
-       setidt(XTIMER_OFFSET, Xtimer,
-              SDT_SYSIGT, SEL_KPL, 0);
-       
-       /* install an inter-CPU IPI for CPU stop/restart */
-       setidt(XCPUSTOP_OFFSET, Xcpustop,
-              SDT_SYSIGT, SEL_KPL, 0);
-
        /* start each Application Processor */
        start_all_aps(boot_addr);
 }