ioapic: Move MachIntrABI switching from ABI finalize to I/O APIC configure
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Sat, 19 Mar 2011 11:11:10 +0000 (19:11 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Sat, 19 Mar 2011 11:21:16 +0000 (19:21 +0800)
sys/platform/pc32/apic/ioapic_abi.c
sys/platform/pc32/apic/mpapic.c
sys/platform/pc32/i386/mp_machdep.c
sys/platform/pc32/icu/icu_abi.c
sys/platform/pc64/apic/ioapic_abi.c
sys/platform/pc64/apic/mpapic.c
sys/platform/pc64/icu/icu_abi.c
sys/platform/pc64/x86_64/mp_machdep.c

index 427183a..9c1a350 100644 (file)
@@ -507,50 +507,20 @@ ioapic_getvar(int varid, void *buf)
        return ENOENT;
 }
 
-/*
- * Called from ICU's finalize if I/O APIC is enabled, after BSP's LAPIC
- * is initialized; some of the BSP's LAPIC configuration are adjusted.
- *
- * - disable 'pic mode'.
- * - switch MachIntrABI.
- * - disable 'virtual wire mode'.
- * - enable NMI.
- */
 static void
 ioapic_finalize(void)
 {
-       u_long ef;
-
-       KKASSERT(MachIntrABI.type == MACHINTR_ICU);
+       KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
        KKASSERT(apic_io_enable);
 
        /*
         * If an IMCR is present, program bit 0 to disconnect the 8259
-        * from the BSP.  The 8259 may still be connected to LINT0 on
-        * the BSP's LAPIC.
+        * from the BSP.
         */
        if (imcr_present) {
                outb(0x22, 0x70);       /* select IMCR */
                outb(0x23, 0x01);       /* disconnect 8259 */
        }
-
-       crit_enter();
-
-       ef = read_eflags();
-       cpu_disable_intr();
-
-       /*
-        * 8259 is completely disconnected; switch to IOAPIC MachIntrABI
-        * and reconfigure the default IDT entries.
-        */
-       MachIntrABI = MachIntrABI_IOAPIC;
-       MachIntrABI.setdefault();
-
-       write_eflags(ef);
-
-       MachIntrABI.cleanup();
-
-       crit_exit();
 }
 
 /*
index e88e81f..19f1dda 100644 (file)
@@ -29,6 +29,7 @@
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/bus.h>
+#include <sys/machintr.h>
 #include <machine/globaldata.h>
 #include <machine/smp.h>
 #include <machine/cputypes.h>
@@ -1121,6 +1122,7 @@ ioapic_config(void)
 {
        struct ioapic_enumerator *e;
        int error, i;
+       u_long ef = 0;
 
        TAILQ_INIT(&ioapic_conf.ioc_list);
        /* XXX magic number */
@@ -1141,6 +1143,20 @@ ioapic_config(void)
 #endif
        }
 
+       if (!ioapic_use_old) {
+               crit_enter();
+
+               ef = read_eflags();
+               cpu_disable_intr();
+
+               /*
+                * Switch to I/O APIC MachIntrABI and reconfigure
+                * the default IDT entries.
+                */
+               MachIntrABI = MachIntrABI_IOAPIC;
+               MachIntrABI.setdefault();
+       }
+
        e->ioapic_enumerate(e);
 
        if (!ioapic_use_old) {
@@ -1185,6 +1201,12 @@ ioapic_config(void)
                TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
                        ioapic_setup(info);
 
+               write_eflags(ef);
+
+               MachIntrABI.cleanup();
+
+               crit_exit();
+
                panic("ioapic_config: new ioapic not working yet\n");
        }
 }
index 41848a4..797fea9 100644 (file)
@@ -56,6 +56,7 @@
 #include <machine/atomic.h>
 #include <machine/cpufunc.h>
 #include <machine/cputypes.h>
+#include <machine_base/apic/ioapic_abi.h>
 #include <machine_base/apic/mpapic.h>
 #include <machine/psl.h>
 #include <machine/segments.h>
@@ -659,10 +660,23 @@ mp_enable(u_int boot_addr)
                ioapic_config();
 
 if (apic_io_enable && ioapic_use_old) {
+       u_long ef;
 
        if (!mptable_fps_phyaddr)
                panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
 
+       crit_enter();
+
+       ef = read_eflags();
+       cpu_disable_intr();
+
+       /*
+        * Switch to I/O APIC MachIntrABI and reconfigure
+        * the default IDT entries.
+        */
+       MachIntrABI = MachIntrABI_IOAPIC;
+       MachIntrABI.setdefault();
+
        mptable_map(&mpt);
 
        /*
@@ -690,6 +704,11 @@ if (apic_io_enable && ioapic_use_old) {
                if (io_apic_setup(apic) < 0)
                        panic("IO APIC setup failure");
 
+       write_eflags(ef);
+
+       MachIntrABI.cleanup();
+
+       crit_exit();
 }
 
        /* Finalize PIC */
index 63399bd..6fe5cc8 100644 (file)
@@ -54,7 +54,6 @@
 
 #include <sys/thread2.h>
 
-#include <machine_base/apic/ioapic_abi.h>
 #include <machine_base/isa/elcr_var.h>
 
 #include "icu.h"
@@ -160,9 +159,6 @@ icu_cleanup(void)
 /*
  * Called after stablize and cleanup; critical section is not
  * held and interrupts are not physically disabled.
- *
- * For SMP:
- * Further delayed after BSP's LAPIC is initialized
  */
 static void
 icu_finalize(void)
@@ -170,14 +166,7 @@ icu_finalize(void)
        KKASSERT(MachIntrABI.type == MACHINTR_ICU);
 
 #ifdef SMP
-       if (apic_io_enable) {
-               /*
-                * MachIntrABI switching will happen in
-                * MachIntrABI_IOAPIC.finalize()
-                */
-               MachIntrABI_IOAPIC.finalize();
-               return;
-       }
+       KKASSERT(!apic_io_enable);
 
        /*
         * If an IMCR is present, programming bit 0 disconnects the 8259
@@ -189,19 +178,8 @@ icu_finalize(void)
         * in addition to the 8259.
         */
        if (imcr_present) {
-               u_long ef;
-
-               crit_enter();
-
-               ef = read_eflags();
-               cpu_disable_intr();
-
                outb(0x22, 0x70);
                outb(0x23, 0x01);
-
-               write_eflags(ef);
-
-               crit_exit();
        }
 #endif /* SMP */
 }
index 09c1c02..e2f81a8 100644 (file)
@@ -507,50 +507,20 @@ ioapic_getvar(int varid, void *buf)
        return ENOENT;
 }
 
-/*
- * Called from ICU's finalize if I/O APIC is enabled, after BSP's LAPIC
- * is initialized; some of the BSP's LAPIC configuration are adjusted.
- *
- * - disable 'pic mode'.
- * - disable 'virtual wire mode'.
- * - switch MachIntrABI
- * - enable NMI.
- */
 static void
 ioapic_finalize(void)
 {
-       register_t ef;
-
-       KKASSERT(MachIntrABI.type == MACHINTR_ICU);
+       KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
        KKASSERT(apic_io_enable);
 
        /*
         * If an IMCR is present, program bit 0 to disconnect the 8259
-        * from the BSP.  The 8259 may still be connected to LINT0 on
-        * the BSP's LAPIC.
+        * from the BSP.
         */
        if (imcr_present) {
                outb(0x22, 0x70);       /* select IMCR */
                outb(0x23, 0x01);       /* disconnect 8259 */
        }
-
-       crit_enter();
-
-       ef = read_rflags();
-       cpu_disable_intr();
-
-       /*
-        * 8259 is completely disconnected; switch to IOAPIC MachIntrABI
-        * and reconfigure the default IDT entries.
-        */
-       MachIntrABI = MachIntrABI_IOAPIC;
-       MachIntrABI.setdefault();
-
-       write_rflags(ef);
-
-       MachIntrABI.cleanup();
-
-       crit_exit();
 }
 
 /*
index 0959ebd..f7a39be 100644 (file)
@@ -29,6 +29,7 @@
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/bus.h>
+#include <sys/machintr.h>
 #include <machine/globaldata.h>
 #include <machine/smp.h>
 #include <machine/md_var.h>
@@ -1183,6 +1184,7 @@ ioapic_config(void)
 {
        struct ioapic_enumerator *e;
        int error, i;
+       register_t ef = 0;
 
        TAILQ_INIT(&ioapic_conf.ioc_list);
        /* XXX magic number */
@@ -1203,6 +1205,20 @@ ioapic_config(void)
 #endif
        }
 
+       if (!ioapic_use_old) {
+               crit_enter();
+
+               ef = read_rflags();
+               cpu_disable_intr();
+
+               /*
+                * Switch to I/O APIC MachIntrABI and reconfigure
+                * the default IDT entries.
+                */
+               MachIntrABI = MachIntrABI_IOAPIC;
+               MachIntrABI.setdefault();
+       }
+
        e->ioapic_enumerate(e);
 
        if (!ioapic_use_old) {
@@ -1247,6 +1263,12 @@ ioapic_config(void)
                TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
                        ioapic_setup(info);
 
+               write_rflags(ef);
+
+               MachIntrABI.cleanup();
+
+               crit_exit();
+
                panic("ioapic_config: new ioapic not working yet\n");
        }
 }
index 8f82cef..78d01d7 100644 (file)
@@ -54,7 +54,6 @@
 
 #include <sys/thread2.h>
 
-#include <machine_base/apic/ioapic_abi.h>
 #include <machine_base/isa/elcr_var.h>
 
 #include "icu.h"
@@ -160,9 +159,6 @@ icu_cleanup(void)
 /*
  * Called after stablize and cleanup; critical section is not
  * held and interrupts are not physically disabled.
- *
- * For SMP:
- * Further delayed after BSP's LAPIC is initialized
  */
 static void
 icu_finalize(void)
@@ -170,14 +166,7 @@ icu_finalize(void)
        KKASSERT(MachIntrABI.type == MACHINTR_ICU);
 
 #ifdef SMP
-       if (apic_io_enable) {
-               /*
-                * MachIntrABI switching will happen in
-                * MachIntrABI_IOAPIC.finalize()
-                */
-               MachIntrABI_IOAPIC.finalize();
-               return;
-       }
+       KKASSERT(!apic_io_enable);
 
        /*
         * If an IMCR is present, programming bit 0 disconnects the 8259
@@ -189,19 +178,8 @@ icu_finalize(void)
         * in addition to the 8259.
         */
        if (imcr_present) {
-               register_t ef;
-
-               crit_enter();
-
-               ef = read_rflags();
-               cpu_disable_intr();
-
                outb(0x22, 0x70);
                outb(0x23, 0x01);
-
-               write_rflags(ef);
-
-               crit_exit();
        }
 #endif /* SMP */
 }
index 9dba673..babf010 100644 (file)
@@ -65,6 +65,7 @@
 
 #include <machine/md_var.h>            /* setidt() */
 #include <machine_base/icu/icu.h>      /* IPIs */
+#include <machine_base/apic/ioapic_abi.h>
 #include <machine/intr_machdep.h>      /* IPIs */
 
 #define FIXUP_EXTRA_APIC_INTS  8       /* additional entries we may create */
@@ -680,10 +681,23 @@ mp_enable(u_int boot_addr)
                ioapic_config();
 
 if (apic_io_enable && ioapic_use_old) {
+       register_t ef;
 
        if (!mptable_fps_phyaddr)
                panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
 
+       crit_enter();
+
+       ef = read_rflags();
+       cpu_disable_intr();
+
+       /*
+        * Switch to I/O APIC MachIntrABI and reconfigure
+        * the default IDT entries.
+        */
+       MachIntrABI = MachIntrABI_IOAPIC;
+       MachIntrABI.setdefault();
+
        mptable_map(&mpt);
 
        /*
@@ -711,6 +725,11 @@ if (apic_io_enable && ioapic_use_old) {
                if (io_apic_setup(apic) < 0)
                        panic("IO APIC setup failure");
 
+       write_rflags(ef);
+
+       MachIntrABI.cleanup();
+
+       crit_exit();
 }
 
        /* Finalize PIC */