bge: Add register and chip id values for BCM57785 and BCM5718 families
authorSepherosa Ziehau <sephe@dragonflybsd.org>
Tue, 17 Jul 2012 13:29:23 +0000 (21:29 +0800)
committerSepherosa Ziehau <sephe@dragonflybsd.org>
Tue, 17 Jul 2012 13:31:42 +0000 (21:31 +0800)
Obtained-from: FreeBSD

sys/dev/netif/bge/if_bgereg.h

index 9f271b2..815c7e7 100644 (file)
@@ -83,6 +83,7 @@
 #define BGE_UNMAPPED_END               0x00001FFF
 #define BGE_DMA_DESCRIPTORS            0x00002000
 #define BGE_DMA_DESCRIPTORS_END                0x00003FFF
+#define BGE_SEND_RING_5717             0x00004000
 #define BGE_SEND_RING_1_TO_4           0x00004000
 #define BGE_SEND_RING_1_TO_4_END       0x00005FFF
 
@@ -97,6 +98,8 @@
 #define BGE_BUFFPOOL_2_END             0x00017FFF
 #define BGE_BUFFPOOL_3                 0x00018000 /* or expansion ROM */
 #define BGE_BUFFPOOL_3_END             0x0001FFFF
+#define BGE_STD_RX_RINGS_5717          0x00040000
+#define BGE_JUMBO_RX_RINGS_5717                0x00044400
 
 /* Mappings for external SSRAM configurations */
 #define BGE_SEND_RING_5_TO_6           0x00006000
 #define BGE_PCI_ISR_MBX_HI             0xB0
 #define BGE_PCI_ISR_MBX_LO             0xB4
 #define BGE_PCI_PRODID_ASICREV         0xBC
+#define BGE_PCI_GEN2_PRODID_ASICREV    0xF4
+#define BGE_PCI_GEN15_PRODID_ASICREV   0xFC
 
 /* PCI Misc. Host control register */
 #define BGE_PCIMISCCTL_CLEAR_INTA      0x00000001
 #define BGE_CHIPID_BCM5906_A2          0xc002
 #define BGE_CHIPID_BCM57780_A0         0x57780000
 #define BGE_CHIPID_BCM57780_A1         0x57780001
+#define BGE_CHIPID_BCM5717_A0          0x5717000
+#define BGE_CHIPID_BCM5717_B0          0x5717100
+#define BGE_CHIPID_BCM5719_A0          0x5719000
+#define BGE_CHIPID_BCM5720_A0          0x05720000
+#define BGE_CHIPID_BCM57765_A0         0x57785000
+#define BGE_CHIPID_BCM57765_B0         0x57785100
 
 /* shorthand one */
 #define BGE_ASICREV(x)                 ((x) >> 12)
 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
 #define BGE_ASICREV_USE_PRODID_REG     0x0f
 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 
+#define BGE_ASICREV_BCM5717            0x5717
+#define BGE_ASICREV_BCM5719            0x5719
+#define BGE_ASICREV_BCM5720            0x5720
 #define BGE_ASICREV_BCM5761            0x5761
 #define BGE_ASICREV_BCM5784            0x5784
 #define BGE_ASICREV_BCM5785            0x5785
+#define BGE_ASICREV_BCM57765           0x57785
 #define BGE_ASICREV_BCM57780           0x57780
 
 /* chip revisions */
 #define BGE_CHIPREV_5750_AX            0x40
 #define BGE_CHIPREV_5750_BX            0x41
 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
+#define BGE_CHIPREV_5717_AX            0x57170
+#define BGE_CHIPREV_5717_BX            0x57171
 #define BGE_CHIPREV_5761_AX            0x57611
 #define BGE_CHIPREV_5784_AX            0x57841
 
 /* PCI DMA Read/Write Control register */
 #define BGE_PCIDMARWCTL_MINDMA         0x000000FF
+#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001
+#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080
+#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380
 #define BGE_PCIDMARWCTL_RDADRR_BNDRY   0x00000700
 #define BGE_PCIDMARWCTL_WRADDR_BNDRY   0x00003800
 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
 #define BGE_TX_RINGS_MAX               4
 #define BGE_TX_RINGS_EXTSSRAM_MAX      16
 #define BGE_RX_RINGS_MAX               16
+#define BGE_RX_RINGS_MAX_5717          17
 
 /* Ethernet MAC control registers */
 #define BGE_MAC_MODE                   0x0400
 #define BGE_TXMODE_BIGBACKOFF_ENABLE   0x00000020
 #define BGE_TXMODE_LONGPAUSE_ENABLE    0x00000040
 #define BGE_TXMODE_MBUF_LOCKUP_FIX     0x00000100
+#define BGE_TXMODE_JMB_FRM_LEN         0x00400000
+#define BGE_TXMODE_CNT_DN_MODE         0x00800000
 
 /* Transmit MAC status register */
 #define BGE_TXSTAT_RX_XOFFED           0x00000001
 #define BGE_TXLEN_SLOTTIME             0x000000FF
 #define BGE_TXLEN_IPG                  0x00000F00
 #define BGE_TXLEN_CRS                  0x00003000
+#define BGE_TXLEN_JMB_FRM_LEN_MSK      0x00FF0000
+#define BGE_TXLEN_CNT_DN_VAL_MSK       0xFF000000
 
 /* Receive MAC mode register */
 #define BGE_RXMODE_RESET               0x00000001
 #define BGE_SDIMODE_RESET              0x00000001
 #define BGE_SDIMODE_ENABLE             0x00000002
 #define BGE_SDIMODE_STATS_OFLOW_ATTN   0x00000004
+#define BGE_SDIMODE_HW_LSO_PRE_DMA     0x00000008
 
 /* Send Data Initiator stats register */
 #define BGE_SDISTAT_STATS_OFLOW_ATTN   0x00000004
 #define BGE_RBDI_STD_REPL_THRESH       0x2C18
 #define BGE_RBDI_JUMBO_REPL_THRESH     0x2C1C
 
+#define BGE_STD_REPLENISH_LWM          0x2D00
+#define BGE_JMB_REPLENISH_LWM          0x2D04
+
 /* Receive BD Initiator Mode register */
 #define BGE_RBDIMODE_RESET             0x00000001
 #define BGE_RBDIMODE_ENABLE            0x00000002
 #define        BGE_CPMU_LNK_AWARE_PWRMD        0x3610
 #define        BGE_CPMU_HST_ACC                0x361C
 #define        BGE_CPMU_CLCK_STAT              0x3630
+#define BGE_CPMU_CLCK_ORIDE            0x3624
 #define        BGE_CPMU_MUTEX_REQ              0x365C
 #define        BGE_CPMU_MUTEX_GNT              0x3660
 #define        BGE_CPMU_PHY_STRAP              0x3664
 #define        BGE_CPMU_HST_ACC_MACCLK_MASK    0x001F0000
 #define        BGE_CPMU_HST_ACC_MACCLK_6_25    0x00130000
 
+/* Clock Speed Override Policy register */
+#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN   0x80000000
+
 /* CPMU Clock Status register */
 #define        BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK        0x001F0000
 #define        BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5        0x00000000
 #define BGE_BMANMODE_ATTN              0x00000004
 #define BGE_BMANMODE_TESTMODE          0x00000008
 #define BGE_BMANMODE_LOMBUF_ATTN       0x00000010
+#define BGE_BMANMODE_NO_TX_UNDERRUN    0x80000000
 
 /* Buffer manager status register */
 #define BGE_BMANSTAT_ERRO              0x00000004
 #define BGE_RDMA_MODE                  0x4800
 #define BGE_RDMA_STATUS                        0x4804
 #define BGE_RDMA_RSRVCTRL              0x4900
+#define BGE_RDMA_LSO_CRPTEN_CTRL       0x4910
 
 /* Read DMA mode register */
 #define BGE_RDMAMODE_RESET             0x00000001
 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN        0x00002000
 #define BGE_RDMAMODE_FIFO_SIZE_128     0x00020000
 #define BGE_RDMAMODE_FIFO_LONG_BURST   0x00030000
+#define BGE_RDMAMODE_MULT_DMA_RD_DIS   0x01000000
+#define BGE_RDMAMODE_H2BNC_VLAN_DET    0x20000000
 
 /* Read DMA status register */
 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
 
 /* Read DMA Reserved Control register */
 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX        0x00000004
+#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K        0x00000C00
+#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K        0x000C0000
+#define BGE_RDMA_RSRVCTRL_TXMRGN_320B  0x28000000
+#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK        0x00000FF0
+#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK        0x000FF000
+#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK  0xFFE00000
+
+#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512   0x00020000
+#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
+#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K   0x000C0000
 
 /*
  * Write DMA control registers
 #define BGE_MODECTL_WORDSWAP_NONFRAME  0x00000004
 #define BGE_MODECTL_BYTESWAP_DATA      0x00000010
 #define BGE_MODECTL_WORDSWAP_DATA      0x00000020
+#define BGE_MODECTL_BYTESWAP_B2HRX_DATA        0x00000040
+#define BGE_MODECTL_WORDSWAP_B2HRX_DATA        0x00000080
 #define BGE_MODECTL_NO_FRAME_CRACKING  0x00000200
 #define BGE_MODECTL_NO_RX_CRC          0x00000400
 #define BGE_MODECTL_RX_BADFRAMES       0x00000800
 #define BGE_MODECTL_NO_TX_INTR         0x00002000
 #define BGE_MODECTL_NO_RX_INTR         0x00004000
 #define BGE_MODECTL_FORCE_PCI32                0x00008000
+#define BGE_MODECTL_B2HRX_ENABLE       0x00008000
 #define BGE_MODECTL_STACKUP            0x00010000
 #define BGE_MODECTL_HOST_SEND_BDS      0x00020000
+#define BGE_MODECTL_HTX2B_ENABLE       0x00040000
 #define BGE_MODECTL_TX_NO_PHDR_CSUM    0x00100000
 #define BGE_MODECTL_RX_NO_PHDR_CSUM    0x00800000
 #define BGE_MODECTL_TX_ATTN_INTR       0x01000000
@@ -2008,7 +2059,9 @@ struct bge_tx_bd {
 #define BGE_TXBDFLAG_IP_CSUM           0x0002
 #define BGE_TXBDFLAG_END               0x0004
 #define BGE_TXBDFLAG_IP_FRAG           0x0008
+#define BGE_TXBDFLAG_JUMBO_FRAME       0x0008  /* 5717 */
 #define BGE_TXBDFLAG_IP_FRAG_END       0x0010
+#define BGE_TXBDFLAG_SNAP              0x0020  /* 5717 */
 #define BGE_TXBDFLAG_VLAN_TAG          0x0040
 #define BGE_TXBDFLAG_COAL_NOW          0x0080
 #define BGE_TXBDFLAG_CPU_PRE_DMA       0x0100
@@ -2017,6 +2070,10 @@ struct bge_tx_bd {
 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR   0x6000
 #define BGE_TXBDFLAG_NO_CRC            0x8000
 
+#define BGE_TXBDFLAG_MSS_SIZE_MASK     0x3FFF  /* 5717 */
+/* Bits [1:0] of the MSS header length. */
+#define BGE_TXBDFLAG_MSS_HDRLEN_MASK   0xC000  /* 5717 */
+
 #define BGE_NIC_TXRING_ADDR(ringno, size)      \
        BGE_SEND_RING_1_TO_4 +                  \
        ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
@@ -2054,6 +2111,7 @@ struct bge_rx_bd {
 #define BGE_RXBDFLAG_IP_CSUM           0x1000
 #define BGE_RXBDFLAG_TCP_UDP_CSUM      0x2000
 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP    0x4000
+#define BGE_RXBDFLAG_IPV6              0x8000
 
 #define BGE_RXERRFLAG_BAD_CRC          0x0001
 #define BGE_RXERRFLAG_COLL_DETECT      0x0002
@@ -2063,6 +2121,7 @@ struct bge_rx_bd {
 #define BGE_RXERRFLAG_RUNT             0x0020
 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS   0x0040
 #define BGE_RXERRFLAG_GIANT            0x0080
+#define BGE_RXERRFLAG_IP_CSUM_NOK      0x1000  /* 5717 */
 
 struct bge_sts_idx {
 #if BYTE_ORDER == LITTLE_ENDIAN