#ifdef APIC_IO
- .data
- ALIGN_DATA
-
- /*
- * Interrupt mask for APIC interrupts, defaults to all hardware
- * interrupts turned off.
- */
-
- .p2align 2 /* MUST be 32bit aligned */
-
- .globl apic_imen
-apic_imen:
- .long APIC_HWI_MASK
-
.text
SUPERALIGN_TEXT
APIC_IMASK_LOCK /* enter critical reg */
movl 4(%esp),%eax
1:
- btsl %eax, apic_imen
shll $IOAPIC_IM_SZSHIFT, %eax
+ orl $IOAPIC_IM_FLAG_MASKED, CNAME(int_to_apicintpin) + IOAPIC_IM_FLAGS(%eax)
movl CNAME(int_to_apicintpin) + IOAPIC_IM_ADDR(%eax), %edx
movl CNAME(int_to_apicintpin) + IOAPIC_IM_ENTIDX(%eax), %ecx
testl %edx, %edx
APIC_IMASK_LOCK /* enter critical reg */
movl 4(%esp), %eax /* mask into %eax */
1:
- btrl %eax, apic_imen /* update apic_imen */
shll $IOAPIC_IM_SZSHIFT, %eax
+ andl $~IOAPIC_IM_FLAG_MASKED, CNAME(int_to_apicintpin) + IOAPIC_IM_FLAGS(%eax)
movl CNAME(int_to_apicintpin) + IOAPIC_IM_ADDR(%eax), %edx
movl CNAME(int_to_apicintpin) + IOAPIC_IM_ENTIDX(%eax), %ecx
testl %edx, %edx
#define MASK_IRQ(irq_num) \
APIC_IMASK_LOCK ; /* into critical reg */ \
- testl $IRQ_LBIT(irq_num), apic_imen ; \
+ testl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
jne 7f ; /* masked, don't mask */ \
- orl $IRQ_LBIT(irq_num), apic_imen ; /* set the mask bit */ \
+ orl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
+ /* set the mask bit */ \
movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
movl REDIRIDX(irq_num), %eax ; /* get the index */ \
movl %eax, (%ecx) ; /* write the index */ \
/*
* Test to see if the source is currntly masked, clear if so.
*/
-#define UNMASK_IRQ(irq_num) \
+#define UNMASK_IRQ(irq_num) \
cmpl $0,%eax ; \
jnz 8f ; \
APIC_IMASK_LOCK ; /* into critical reg */ \
- testl $IRQ_LBIT(irq_num), apic_imen ; \
+ testl $IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
je 7f ; /* bit clear, not masked */ \
- andl $~IRQ_LBIT(irq_num), apic_imen ;/* clear mask bit */ \
+ andl $~IOAPIC_IM_FLAG_MASKED, IOAPICFLAGS(irq_num) ; \
+ /* clear mask bit */ \
movl IOAPICADDR(irq_num),%ecx ; /* ioapic addr */ \
movl REDIRIDX(irq_num), %eax ; /* get the index */ \
movl %eax,(%ecx) ; /* write the index */ \
/*
- * Print contents of apic_imen.
+ * Print contents of unmasked IRQs.
*/
-extern u_int apic_imen; /* keep apic_imen 'opaque' */
void
imen_dump(void)
{
int x;
kprintf("SMP: enabled INTs: ");
- for (x = 0; x < 24; ++x)
- if ((apic_imen & (1 << x)) == 0)
- kprintf("%d, ", x);
- kprintf("apic_imen: 0x%08x\n", apic_imen);
+ for (x = 0; x < APIC_INTMAPSIZE; ++x) {
+ if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
+ kprintf("%d ", x);
+ }
+ kprintf("\n");
}
ASSYM(IOAPIC_IM_SIZE, sizeof(struct apic_intmapinfo));
ASSYM(IOAPIC_IM_SZSHIFT, IOAPIC_IM_SZSHIFT);
ASSYM(IOAPIC_IM_FLAG_LEVEL, IOAPIC_IM_FLAG_LEVEL);
+ASSYM(IOAPIC_IM_FLAG_MASKED, IOAPIC_IM_FLAG_MASKED);
#endif
int_to_apicintpin[x].int_pin = 0;
int_to_apicintpin[x].apic_address = NULL;
int_to_apicintpin[x].redirindex = 0;
+
+ /* Default to masked */
+ int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
}
/* First assign ISA/EISA interrupts */
#define IOAPIC_IM_SZSHIFT 5
#define IOAPIC_IM_FLAG_LEVEL 0x1 /* default to edge trigger */
+#define IOAPIC_IM_FLAG_MASKED 0x2
extern struct apic_intmapinfo int_to_apicintpin[];
extern struct pcb stoppcbs[];