kernel: Remove Cyrix CPUs specific handling
authorFrançois Tigeot <ftigeot@wolfpond.org>
Wed, 17 Jul 2013 21:18:26 +0000 (23:18 +0200)
committerFrançois Tigeot <ftigeot@wolfpond.org>
Thu, 18 Jul 2013 05:59:52 +0000 (07:59 +0200)
* Remove kernel options, constants, detection code and special
  initialization routines for Cyrix CPUs

* Part of this code prevents the i386 vkernel from beeing compiled
  from a source tree with PAT support

* Recent versions of DragonFly cannot possibly run on machines using
  these processors anyway

sys/config/LINT
sys/cpu/i386/include/cputypes.h
sys/cpu/i386/include/specialreg.h
sys/emulation/linux/i386/linprocfs/linprocfs_misc.c
sys/platform/pc32/conf/options
sys/platform/pc32/i386/identcpu.c
sys/platform/pc32/i386/initcpu.c

index 2e3f7e0..8f18d48 100644 (file)
@@ -130,15 +130,6 @@ cpu                I686_CPU                # aka Pentium Pro(tm)
 # CPU if CPU supports it. The default is double-clock mode on
 # BlueLightning CPU box.
 #
-# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
-#
-# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
-# mapped mode.  Default is 2-way set associative mode.
-#
-# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
-# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
-# Otherwise, the NO_LOCK bit of CCR1 is cleared.  (NOTE 3)
-#
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s).
@@ -167,10 +158,6 @@ cpu                I686_CPU                # aka Pentium Pro(tm)
 # CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
 # for i386 machines.
 #
-# CPU_IORT defines I/O clock delay time (NOTE 1).  Default values of
-# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
-# (no clock delay).
-#
 # CPU_L2_LATENCY specified the L2 cache latency value.  This option is used
 # only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
 # The default value is 5.
@@ -179,28 +166,14 @@ cpu               I686_CPU                # aka Pentium Pro(tm)
 #
 # CPU_GEODE enables support for AMD Geode LX, Geode SC1100 and AMD CS5536
 #
-# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
-# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
-# 1).
-#
 # CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs.  This option
 # is useful when you use Socket 8 to Socket 370 converter, because most Pentium
 # Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
 #
-# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
-#
 # CPU_SUSP_HLT enables suspend on HALT.  If this option is set, CPU
 # enters suspend mode following execution of HALT instruction.
 #
-# CPU_WT_ALLOC enables write allocation on Cyrix 6x86/6x86MX and AMD
-# K5/K6/K6-2 cpus.
-#
-# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
-# flush at hold state.
-#
-# CYRIX_CACHE_REALLY_WORKS enables (1) CPU cache on Cyrix 486 CPUs
-# without cache flush at hold state, and (2) write-back CPU cache on
-# Cyrix 6x86 whose revision < 2.7 (NOTE 2).
+# CPU_WT_ALLOC enables write allocation on AMD K5/K6/K6-2 cpus.
 #
 # NO_F00F_HACK disables the hack that prevents Pentiums (and ONLY
 # Pentiums) from locking up when a LOCK CMPXCHG8B instruction is
@@ -211,22 +184,12 @@ cpu               I686_CPU                # aka Pentium Pro(tm)
 # which indicates that the 15-16MB range is *definitely* not being
 # occupied by an ISA memory hole.
 #
-# NOTE 1: The CPU_BTB_EN, CPU_IORT, CPU_LOOP_EN and CPU_RSTK_EN options
-# should not be used because of CPU bugs. They may crash your system.
-#
-# NOTE 2: If CYRIX_CACHE_REALLY_WORKS is not set, CPU cache is enabled
-# in write-through mode when revision < 2.7.  If revision of Cyrix
-# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
-#
 # NOTE 3: This option may cause failures for software that requires
 # locked cycles in order to operate correctly.
 #
 options        CPU_ATHLON_SSE_HACK
 options        CPU_BLUELIGHTNING_FPU_OP_CACHE
 options        CPU_BLUELIGHTNING_3X
-options        CPU_BTB_EN
-options                CPU_CYRIX_NO_LOCK
-options        CPU_DIRECT_MAPPED_CACHE
 options        CPU_DISABLE_5X86_LSSER
 options        CPU_DISABLE_SSE
 options        CPU_ELAN
@@ -237,15 +200,10 @@ options   CPU_FASTER_5X86_FPU
 options                CPU_GEODE
 options                CPU_HAS_SSE2
 options        CPU_I486_ON_386
-options        CPU_IORT
 options        CPU_L2_LATENCY=5
-options        CPU_LOOP_EN
 options        CPU_PPRO2CELERON
-options        CPU_RSTK_EN
 options        CPU_SUSP_HLT
 options        CPU_WT_ALLOC
-options        CYRIX_CACHE_WORKS
-options        CYRIX_CACHE_REALLY_WORKS
 #options       NO_F00F_HACK
 options                NO_MEMORY_HOLE
 
index 4da9929..2b0ad0b 100644 (file)
 #define        CPU_486SX       3       /* Intel 80486SX */
 #define        CPU_486         4       /* Intel 80486DX */
 #define        CPU_586         5       /* Intel P.....m (I hate lawyers; it's TM) */
-#define        CPU_486DLC      6       /* Cyrix 486DLC */
 #define        CPU_686         7       /* Pentium Pro */
-#define        CPU_M1SC        8       /* Cyrix M1sc (aka 5x86) */
-#define        CPU_M1          9       /* Cyrix M1 (aka 6x86) */
 #define        CPU_BLUE        10      /* IBM BlueLighting CPU */
-#define        CPU_M2          11      /* Cyrix M2 (aka enhanced 6x86 with MMX */
 #define        CPU_NX586       12      /* NexGen (now AMD) 586 */
-#define        CPU_CY486DX     13      /* Cyrix 486S/DX/DX2/DX4 */
 #define        CPU_PII         14      /* Intel Pentium II */
 #define        CPU_PIII        15      /* Intel Pentium III */
 #define        CPU_P4          16      /* Intel Pentium 4 */
@@ -71,7 +66,6 @@
 #define        CPU_VENDOR_SIS          0x1039          /* SiS */
 #define        CPU_VENDOR_UMC          0x1060          /* UMC */
 #define        CPU_VENDOR_NEXGEN       0x1074          /* Nexgen */
-#define        CPU_VENDOR_CYRIX        0x1078          /* Cyrix */
 #define        CPU_VENDOR_IDT          0x111d          /* Centaur/IDT/VIA */
 #define        CPU_VENDOR_TRANSMETA    0x1279          /* Transmeta */
 #define        CPU_VENDOR_INTEL        0x8086          /* Intel */
index e203099..22548b2 100644 (file)
  */
 #define        AMD_VENDOR_ID           "AuthenticAMD"
 #define        CENTAUR_VENDOR_ID       "CentaurHauls"
-#define        CYRIX_VENDOR_ID         "CyrixInstead"
 #define        INTEL_VENDOR_ID         "GenuineIntel"
 #define        NEXGEN_VENDOR_ID        "NexGenDriven"
 #define        NSC_VENDOR_ID           "Geode by NSC"
 #define        MTRR_PHYSMASK_VALID     0x0000000000000800ULL
 
 /*
- * Cyrix configuration registers, accessible as IO ports.
- */
-#define        CCR0                    0xc0    /* Configuration control register 0 */
-#define        CCR0_NC0                0x01    /* First 64K of each 1M memory region is
-                                                                  non-cacheable */
-#define        CCR0_NC1                0x02    /* 640K-1M region is non-cacheable */
-#define        CCR0_A20M               0x04    /* Enables A20M# input pin */
-#define        CCR0_KEN                0x08    /* Enables KEN# input pin */
-#define        CCR0_FLUSH              0x10    /* Enables FLUSH# input pin */
-#define        CCR0_BARB               0x20    /* Flushes internal cache when entering hold
-                                                                  state */
-#define        CCR0_CO                 0x40    /* Cache org: 1=direct mapped, 0=2x set
-                                                                  assoc */
-#define        CCR0_SUSPEND    0x80    /* Enables SUSP# and SUSPA# pins */
-
-#define        CCR1                    0xc1    /* Configuration control register 1 */
-#define        CCR1_RPL                0x01    /* Enables RPLSET and RPLVAL# pins */
-#define        CCR1_SMI                0x02    /* Enables SMM pins */
-#define        CCR1_SMAC               0x04    /* System management memory access */
-#define        CCR1_MMAC               0x08    /* Main memory access */
-#define        CCR1_NO_LOCK    0x10    /* Negate LOCK# */
-#define        CCR1_SM3                0x80    /* SMM address space address region 3 */
-
-#define        CCR2                    0xc2
-#define        CCR2_WB                 0x02    /* Enables WB cache interface pins */
-#define        CCR2_SADS               0x02    /* Slow ADS */
-#define        CCR2_LOCK_NW    0x04    /* LOCK NW Bit */
-#define        CCR2_SUSP_HLT   0x08    /* Suspend on HALT */
-#define        CCR2_WT1                0x10    /* WT region 1 */
-#define        CCR2_WPR1               0x10    /* Write-protect region 1 */
-#define        CCR2_BARB               0x20    /* Flushes write-back cache when entering
-                                                                  hold state. */
-#define        CCR2_BWRT               0x40    /* Enables burst write cycles */
-#define        CCR2_USE_SUSP   0x80    /* Enables suspend pins */
-
-#define        CCR3                    0xc3
-#define        CCR3_SMILOCK    0x01    /* SMM register lock */
-#define        CCR3_NMI                0x02    /* Enables NMI during SMM */
-#define        CCR3_LINBRST    0x04    /* Linear address burst cycles */
-#define        CCR3_SMMMODE    0x08    /* SMM Mode */
-#define        CCR3_MAPEN0             0x10    /* Enables Map0 */
-#define        CCR3_MAPEN1             0x20    /* Enables Map1 */
-#define        CCR3_MAPEN2             0x40    /* Enables Map2 */
-#define        CCR3_MAPEN3             0x80    /* Enables Map3 */
-
-#define        CCR4                    0xe8
-#define        CCR4_IOMASK             0x07
-#define        CCR4_MEM                0x08    /* Enables momory bypassing */
-#define        CCR4_DTE                0x10    /* Enables directory table entry cache */
-#define        CCR4_FASTFPE    0x20    /* Fast FPU exception */
-#define        CCR4_CPUID              0x80    /* Enables CPUID instruction */
-
-#define        CCR5                    0xe9
-#define        CCR5_WT_ALLOC   0x01    /* Write-through allocate */
-#define        CCR5_SLOP               0x02    /* LOOP instruction slowed down */
-#define        CCR5_LBR1               0x10    /* Local bus region 1 */
-#define        CCR5_ARREN              0x20    /* Enables ARR region */
-
-#define        CCR6                    0xea
-
-#define        CCR7                    0xeb
-
-/* Performance Control Register (5x86 only). */
-#define        PCR0                    0x20
-#define        PCR0_RSTK               0x01    /* Enables return stack */
-#define        PCR0_BTB                0x02    /* Enables branch target buffer */
-#define        PCR0_LOOP               0x04    /* Enables loop */
-#define        PCR0_AIS                0x08    /* Enables all instrcutions stalled to
-                                                                  serialize pipe. */
-#define        PCR0_MLR                0x10    /* Enables reordering of misaligned loads */
-#define        PCR0_BTBRT              0x40    /* Enables BTB test register. */
-#define        PCR0_LSSER              0x80    /* Disable reorder */
-
-/* Device Identification Registers */
-#define        DIR0                    0xfe
-#define        DIR1                    0xff
-
-/*
  * Machine Check register constants.
  */
 #define        MCG_CAP_COUNT           0x000000ff
 #define        VIA_CRYPT_CWLO_KEY192           0x0000040c      /* 192bit, 12 rds */
 #define        VIA_CRYPT_CWLO_KEY256           0x0000080e      /* 256bit, 15 rds */
 
-#ifndef LOCORE
-
-#ifndef _SYS_TYPES_H_
-#include <sys/types.h>
-#endif
-#ifndef _CPU_CPUFUNC_H_
-#include <cpu/cpufunc.h>
-#endif
-
-static __inline u_char
-read_cyrix_reg(u_char reg)
-{
-        outb(0x22, reg);
-        return inb(0x23);
-}
-
-static __inline void
-write_cyrix_reg(u_char reg, u_char data)
-{
-        outb(0x22, reg);
-        outb(0x23, data);
-}
-#endif
-
 #endif /* !_CPU_SPECIALREG_H_ */
index b492c7e..da7ba8a 100644 (file)
@@ -247,8 +247,6 @@ linprocfs_docpuinfo(struct proc *curp, struct proc *p, struct pfsnode *pfs,
 
         if (cpu_vendor_id == CPU_VENDOR_AMD && (class < 6)) {
                flags[16] = "fcmov";
-        } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
-               flags[24] = "cxmmx";
         }
         
         for (i = 0; i < 32; i++)
index d4c89cb..2513b89 100644 (file)
@@ -41,9 +41,6 @@ KERN_TIMESTAMP                        opt_global.h
 NO_F00F_HACK                   opt_cpu.h
 CPU_BLUELIGHTNING_FPU_OP_CACHE opt_cpu.h
 CPU_BLUELIGHTNING_3X           opt_cpu.h
-CPU_BTB_EN                     opt_cpu.h
-CPU_CYRIX_NO_LOCK              opt_cpu.h
-CPU_DIRECT_MAPPED_CACHE                opt_cpu.h
 CPU_DISABLE_5X86_LSSER         opt_cpu.h
 CPU_ELAN                       opt_cpu.h
 CPU_ENABLE_EST                 opt_cpu.h
@@ -52,15 +49,10 @@ CPU_ENABLE_TCC                      opt_cpu.h
 CPU_FASTER_5X86_FPU            opt_cpu.h
 CPU_GEODE                      opt_cpu.h
 CPU_I486_ON_386                        opt_cpu.h
-CPU_IORT                       opt_cpu.h
 CPU_L2_LATENCY                 opt_cpu.h
-CPU_LOOP_EN                    opt_cpu.h
 CPU_PPRO2CELERON               opt_cpu.h
-CPU_RSTK_EN                    opt_cpu.h
 CPU_SUSP_HLT                   opt_cpu.h
 CPU_WT_ALLOC                   opt_cpu.h
-CYRIX_CACHE_WORKS              opt_cpu.h
-CYRIX_CACHE_REALLY_WORKS       opt_cpu.h
 NO_MEMORY_HOLE                 opt_cpu.h
 CPU_DISABLE_SSE                        opt_cpu.h
 CPU_ATHLON_SSE_HACK            opt_cpu.h
index e5c9ab1..37586da 100644 (file)
@@ -69,7 +69,6 @@ void  enable_K6_2_wt_alloc(void);
 #endif
 void panicifcpuunsupported(void);
 
-static void identifycyrix(void);
 static void init_exthigh(void);
 static u_int find_cpu_vendor_id(void);
 static void print_AMD_info(void);
@@ -81,7 +80,6 @@ static void print_via_padlock_info(void);
 
 int    cpu_class;
 u_int  cpu_exthigh;            /* Highest arg to extended CPUID */
-u_int  cyrix_did;              /* Device ID of Cyrix CPU */
 char machine[] = MACHINE;
 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
     machine, 0, "Machine class");
@@ -125,14 +123,9 @@ static struct {
        { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
        { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
        { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
-       { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
        { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
-       { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
-       { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
        { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
-       { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
        { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
-       { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
        { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
        { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
        { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
@@ -146,7 +139,6 @@ static struct {
        { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
        { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
        { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
-       { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
        { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
        { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
        { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
@@ -423,142 +415,6 @@ printcpuinfo(void)
                                enable_K6_wt_alloc();
                }
 #endif
-       } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
-               strcpy(cpu_model, "Cyrix ");
-               switch (cpu_id & 0xff0) {
-               case 0x440:
-                       strcat(cpu_model, "MediaGX");
-                       break;
-               case 0x520:
-                       strcat(cpu_model, "6x86");
-                       break;
-               case 0x540:
-                       cpu_class = CPUCLASS_586;
-                       strcat(cpu_model, "GXm");
-                       break;
-               case 0x600:
-                       strcat(cpu_model, "6x86MX");
-                       break;
-               default:
-                       /*
-                        * Even though CPU supports the cpuid
-                        * instruction, it can be disabled.
-                        * Therefore, this routine supports all Cyrix
-                        * CPUs.
-                        */
-                       switch (cyrix_did & 0xf0) {
-                       case 0x00:
-                               switch (cyrix_did & 0x0f) {
-                               case 0x00:
-                                       strcat(cpu_model, "486SLC");
-                                       break;
-                               case 0x01:
-                                       strcat(cpu_model, "486DLC");
-                                       break;
-                               case 0x02:
-                                       strcat(cpu_model, "486SLC2");
-                                       break;
-                               case 0x03:
-                                       strcat(cpu_model, "486DLC2");
-                                       break;
-                               case 0x04:
-                                       strcat(cpu_model, "486SRx");
-                                       break;
-                               case 0x05:
-                                       strcat(cpu_model, "486DRx");
-                                       break;
-                               case 0x06:
-                                       strcat(cpu_model, "486SRx2");
-                                       break;
-                               case 0x07:
-                                       strcat(cpu_model, "486DRx2");
-                                       break;
-                               case 0x08:
-                                       strcat(cpu_model, "486SRu");
-                                       break;
-                               case 0x09:
-                                       strcat(cpu_model, "486DRu");
-                                       break;
-                               case 0x0a:
-                                       strcat(cpu_model, "486SRu2");
-                                       break;
-                               case 0x0b:
-                                       strcat(cpu_model, "486DRu2");
-                                       break;
-                               default:
-                                       strcat(cpu_model, "Unknown");
-                                       break;
-                               }
-                               break;
-                       case 0x10:
-                               switch (cyrix_did & 0x0f) {
-                               case 0x00:
-                                       strcat(cpu_model, "486S");
-                                       break;
-                               case 0x01:
-                                       strcat(cpu_model, "486S2");
-                                       break;
-                               case 0x02:
-                                       strcat(cpu_model, "486Se");
-                                       break;
-                               case 0x03:
-                                       strcat(cpu_model, "486S2e");
-                                       break;
-                               case 0x0a:
-                                       strcat(cpu_model, "486DX");
-                                       break;
-                               case 0x0b:
-                                       strcat(cpu_model, "486DX2");
-                                       break;
-                               case 0x0f:
-                                       strcat(cpu_model, "486DX4");
-                                       break;
-                               default:
-                                       strcat(cpu_model, "Unknown");
-                                       break;
-                               }
-                               break;
-                       case 0x20:
-                               if ((cyrix_did & 0x0f) < 8)
-                                       strcat(cpu_model, "6x86");      /* Where did you get it? */
-                               else
-                                       strcat(cpu_model, "5x86");
-                               break;
-                       case 0x30:
-                               strcat(cpu_model, "6x86");
-                               break;
-                       case 0x40:
-                               if ((cyrix_did & 0xf000) == 0x3000) {
-                                       cpu_class = CPUCLASS_586;
-                                       strcat(cpu_model, "GXm");
-                               } else
-                                       strcat(cpu_model, "MediaGX");
-                               break;
-                       case 0x50:
-                               strcat(cpu_model, "6x86MX");
-                               break;
-                       case 0xf0:
-                               switch (cyrix_did & 0x0f) {
-                               case 0x0d:
-                                       strcat(cpu_model, "Overdrive CPU");
-                                       break;
-                               case 0x0e:
-                                       strcpy(cpu_model, "Texas Instruments 486SXL");
-                                       break;
-                               case 0x0f:
-                                       strcat(cpu_model, "486SLC/DLC");
-                                       break;
-                               default:
-                                       strcat(cpu_model, "Unknown");
-                                       break;
-                               }
-                               break;
-                       default:
-                               strcat(cpu_model, "Unknown");
-                               break;
-                       }
-                       break;
-               }
        } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
                strcpy(cpu_model, "Rise ");
                switch (cpu_id & 0xff0) {
@@ -672,12 +528,8 @@ printcpuinfo(void)
            cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
            cpu_vendor_id == CPU_VENDOR_RISE ||
            cpu_vendor_id == CPU_VENDOR_CENTAUR ||
-           cpu_vendor_id == CPU_VENDOR_NSC ||
-               (cpu_vendor_id == CPU_VENDOR_CYRIX &&
-                ((cpu_id & 0xf00) > 0x500))) {
+           cpu_vendor_id == CPU_VENDOR_NSC) {
                kprintf("  Stepping = %u", cpu_id & 0xf);
-               if (cpu_vendor_id == CPU_VENDOR_CYRIX)
-                       kprintf("  DIR=0x%04x", cyrix_did);
                if (cpu_high > 0) {
 #if 0
                        u_int cmp = 1, htt = 1;
@@ -932,14 +784,6 @@ printcpuinfo(void)
 #endif
 
                }
-       } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
-               kprintf("  DIR=0x%04x", cyrix_did);
-               kprintf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
-               kprintf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
-#ifndef CYRIX_CACHE_REALLY_WORKS
-               if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
-                       kprintf("\n  CPU cache: write-through mode");
-#endif
        }
 
        /* Avoid ugly blank lines: only print newline when we have to. */
@@ -1080,49 +924,6 @@ identblue(void)
        return IDENTBLUE_IBMCPU;
 }
 
-
-/*
- * identifycyrix() set lower 16 bits of cyrix_did as follows:
- *
- *  F E D C B A 9 8 7 6 5 4 3 2 1 0
- * +-------+-------+---------------+
- * |  SID  |  RID  |   Device ID   |
- * |    (DIR 1)    |    (DIR 0)    |
- * +-------+-------+---------------+
- */
-static void
-identifycyrix(void)
-{
-       int     ccr2_test = 0, dir_test = 0;
-       u_char  ccr2, ccr3;
-
-       mpintr_lock();
-
-       ccr2 = read_cyrix_reg(CCR2);
-       write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
-       read_cyrix_reg(CCR2);
-       if (read_cyrix_reg(CCR2) != ccr2)
-               ccr2_test = 1;
-       write_cyrix_reg(CCR2, ccr2);
-
-       ccr3 = read_cyrix_reg(CCR3);
-       write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
-       read_cyrix_reg(CCR3);
-       if (read_cyrix_reg(CCR3) != ccr3)
-               dir_test = 1;                                   /* CPU supports DIRs. */
-       write_cyrix_reg(CCR3, ccr3);
-
-       if (dir_test) {
-               /* Device ID registers are available. */
-               cyrix_did = read_cyrix_reg(DIR1) << 8;
-               cyrix_did += read_cyrix_reg(DIR0);
-       } else if (ccr2_test)
-               cyrix_did = 0x0010;             /* 486S A-step */
-       else
-               cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
-       mpintr_unlock();
-}
-
 #if 0
 /* Update TSC freq with the value indicated by the caller. */
 static void
@@ -1147,7 +948,6 @@ void
 finishidentcpu(void)
 {
        int     isblue = 0;
-       u_char  ccr3;
        u_int   regs[4];
 
        cpu_vendor_id = find_cpu_vendor_id();
@@ -1189,79 +989,6 @@ finishidentcpu(void)
                        do_cpuid(0x80000008, regs);
                        cpu_procinfo2 = regs[2];
                }
-       } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
-               if (cpu == CPU_486) {
-                       /*
-                        * These conditions are equivalent to:
-                        *     - CPU does not support cpuid instruction.
-                        *     - Cyrix/IBM CPU is detected.
-                        */
-                       isblue = identblue();
-                       if (isblue == IDENTBLUE_IBMCPU) {
-                               strcpy(cpu_vendor, "IBM");
-                               cpu_vendor_id = CPU_VENDOR_IBM;
-                               cpu = CPU_BLUE;
-                               goto finish;
-                       }
-               }
-               switch (cpu_id & 0xf00) {
-               case 0x600:
-                       /*
-                        * Cyrix's datasheet does not describe DIRs.
-                        * Therefor, I assume it does not have them
-                        * and use the result of the cpuid instruction.
-                        * XXX they seem to have it for now at least. -Peter
-                        */
-                       identifycyrix();
-                       cpu = CPU_M2;
-                       break;
-               default:
-                       identifycyrix();
-                       /*
-                        * This routine contains a trick.
-                        * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
-                        */
-                       switch (cyrix_did & 0x00f0) {
-                       case 0x00:
-                       case 0xf0:
-                               cpu = CPU_486DLC;
-                               break;
-                       case 0x10:
-                               cpu = CPU_CY486DX;
-                               break;
-                       case 0x20:
-                               if ((cyrix_did & 0x000f) < 8)
-                                       cpu = CPU_M1;
-                               else
-                                       cpu = CPU_M1SC;
-                               break;
-                       case 0x30:
-                               cpu = CPU_M1;
-                               break;
-                       case 0x40:
-                               /* MediaGX CPU */
-                               cpu = CPU_M1SC;
-                               break;
-                       default:
-                               /* M2 and later CPUs are treated as M2. */
-                               cpu = CPU_M2;
-
-                               /*
-                                * enable cpuid instruction.
-                                */
-                               ccr3 = read_cyrix_reg(CCR3);
-                               write_cyrix_reg(CCR3, CCR3_MAPEN0);
-                               write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
-                               write_cyrix_reg(CCR3, ccr3);
-
-                               do_cpuid(0, regs);
-                               cpu_high = regs[0];     /* eax */
-                               do_cpuid(1, regs);
-                               cpu_id = regs[0];       /* eax */
-                               cpu_feature = regs[3];  /* edx */
-                               break;
-                       }
-               }
        } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
                /*
                 * There are BlueLightning CPUs that do not change
@@ -1282,7 +1009,6 @@ finishidentcpu(void)
         * Set MI flags for MI procedures implemented using machine-specific
         * features.
         */
-finish:
        if (cpu_feature & CPUID_SSE2)
                cpu_mi_feature |= CPU_MI_BZERONT;
 
index d79e747..ce1f08d 100644 (file)
@@ -48,18 +48,13 @@ void        enable_K6_2_wt_alloc(void);
 #endif
 
 #ifdef I486_CPU
-static void init_5x86(void);
 static void init_bluelightning(void);
-static void init_486dlc(void);
-static void init_cy486dx(void);
 #ifdef CPU_I486_ON_386
 static void init_i486_on_386(void);
 #endif
-static void init_6x86(void);
 #endif /* I486_CPU */
 
 #ifdef I686_CPU
-static void    init_6x86MX(void);
 static void    init_ppro(void);
 static void    init_mendocino(void);
 #endif
@@ -139,174 +134,6 @@ init_bluelightning(void)
        write_eflags(eflags);
 }
 
-/*
- * Cyrix 486SLC/DLC/SR/DR series
- */
-static void
-init_486dlc(void)
-{
-       u_long  eflags;
-       u_char  ccr0;
-
-       eflags = read_eflags();
-       cpu_disable_intr();
-       invd();
-
-       ccr0 = read_cyrix_reg(CCR0);
-#ifndef CYRIX_CACHE_WORKS
-       ccr0 |= CCR0_NC1 | CCR0_BARB;
-       write_cyrix_reg(CCR0, ccr0);
-       invd();
-#else
-       ccr0 &= ~CCR0_NC0;
-#ifndef CYRIX_CACHE_REALLY_WORKS
-       ccr0 |= CCR0_NC1 | CCR0_BARB;
-#else
-       ccr0 |= CCR0_NC1;
-#endif
-#ifdef CPU_DIRECT_MAPPED_CACHE
-       ccr0 |= CCR0_CO;                        /* Direct mapped mode. */
-#endif
-       write_cyrix_reg(CCR0, ccr0);
-
-       /* Clear non-cacheable region. */
-       write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
-       write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
-       write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
-       write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
-
-       write_cyrix_reg(0, 0);  /* dummy write */
-
-       /* Enable caching in CR0. */
-       load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
-       invd();
-#endif /* !CYRIX_CACHE_WORKS */
-       write_eflags(eflags);
-}
-
-
-/*
- * Cyrix 486S/DX series
- */
-static void
-init_cy486dx(void)
-{
-       u_long  eflags;
-       u_char  ccr2;
-
-       eflags = read_eflags();
-       cpu_disable_intr();
-       invd();
-
-       ccr2 = read_cyrix_reg(CCR2);
-#ifdef CPU_SUSP_HLT
-       ccr2 |= CCR2_SUSP_HLT;
-#endif
-
-       write_cyrix_reg(CCR2, ccr2);
-       write_eflags(eflags);
-}
-
-
-/*
- * Cyrix 5x86
- */
-static void
-init_5x86(void)
-{
-       u_long  eflags;
-       u_char  ccr2, ccr3, ccr4, pcr0;
-
-       eflags = read_eflags();
-       cpu_disable_intr();
-
-       load_cr0(rcr0() | CR0_CD | CR0_NW);
-       wbinvd();
-
-       read_cyrix_reg(CCR3);           /* dummy */
-
-       /* Initialize CCR2. */
-       ccr2 = read_cyrix_reg(CCR2);
-       ccr2 |= CCR2_WB;
-#ifdef CPU_SUSP_HLT
-       ccr2 |= CCR2_SUSP_HLT;
-#else
-       ccr2 &= ~CCR2_SUSP_HLT;
-#endif
-       ccr2 |= CCR2_WT1;
-       write_cyrix_reg(CCR2, ccr2);
-
-       /* Initialize CCR4. */
-       ccr3 = read_cyrix_reg(CCR3);
-       write_cyrix_reg(CCR3, CCR3_MAPEN0);
-
-       ccr4 = read_cyrix_reg(CCR4);
-       ccr4 |= CCR4_DTE;
-       ccr4 |= CCR4_MEM;
-#ifdef CPU_FASTER_5X86_FPU
-       ccr4 |= CCR4_FASTFPE;
-#else
-       ccr4 &= ~CCR4_FASTFPE;
-#endif
-       ccr4 &= ~CCR4_IOMASK;
-       /********************************************************************
-        * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
-        * should be 0 for errata fix.
-        ********************************************************************/
-#ifdef CPU_IORT
-       ccr4 |= CPU_IORT & CCR4_IOMASK;
-#endif
-       write_cyrix_reg(CCR4, ccr4);
-
-       /* Initialize PCR0. */
-       /****************************************************************
-        * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
-        * BTB_EN might make your system unstable.
-        ****************************************************************/
-       pcr0 = read_cyrix_reg(PCR0);
-#ifdef CPU_RSTK_EN
-       pcr0 |= PCR0_RSTK;
-#else
-       pcr0 &= ~PCR0_RSTK;
-#endif
-#ifdef CPU_BTB_EN
-       pcr0 |= PCR0_BTB;
-#else
-       pcr0 &= ~PCR0_BTB;
-#endif
-#ifdef CPU_LOOP_EN
-       pcr0 |= PCR0_LOOP;
-#else
-       pcr0 &= ~PCR0_LOOP;
-#endif
-
-       /****************************************************************
-        * WARNING: if you use a memory mapped I/O device, don't use
-        * DISABLE_5X86_LSSER option, which may reorder memory mapped
-        * I/O access.
-        * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
-        ****************************************************************/
-#ifdef CPU_DISABLE_5X86_LSSER
-       pcr0 &= ~PCR0_LSSER;
-#else
-       pcr0 |= PCR0_LSSER;
-#endif
-       write_cyrix_reg(PCR0, pcr0);
-
-       /* Restore CCR3. */
-       write_cyrix_reg(CCR3, ccr3);
-
-       read_cyrix_reg(0x80);           /* dummy */
-
-       /* Unlock NW bit in CR0. */
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
-       load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0, NW = 1 */
-       /* Lock NW bit in CR0. */
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
-
-       write_eflags(eflags);
-}
-
 #ifdef CPU_I486_ON_386
 /*
  * There are i486 based upgrade products for i386 machines.
@@ -326,152 +153,6 @@ init_i486_on_386(void)
 }
 #endif
 
-/*
- * Cyrix 6x86
- *
- * XXX - What should I do here?  Please let me know.
- */
-static void
-init_6x86(void)
-{
-       u_long  eflags;
-       u_char  ccr3, ccr4;
-
-       eflags = read_eflags();
-       cpu_disable_intr();
-
-       load_cr0(rcr0() | CR0_CD | CR0_NW);
-       wbinvd();
-
-       /* Initialize CCR0. */
-       write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
-
-       /* Initialize CCR1. */
-#ifdef CPU_CYRIX_NO_LOCK
-       write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
-#else
-       write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
-#endif
-
-       /* Initialize CCR2. */
-#ifdef CPU_SUSP_HLT
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
-#else
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
-#endif
-
-       ccr3 = read_cyrix_reg(CCR3);
-       write_cyrix_reg(CCR3, CCR3_MAPEN0);
-
-       /* Initialize CCR4. */
-       ccr4 = read_cyrix_reg(CCR4);
-       ccr4 |= CCR4_DTE;
-       ccr4 &= ~CCR4_IOMASK;
-#ifdef CPU_IORT
-       write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
-#else
-       write_cyrix_reg(CCR4, ccr4 | 7);
-#endif
-
-       /* Initialize CCR5. */
-#ifdef CPU_WT_ALLOC
-       write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
-#endif
-
-       /* Restore CCR3. */
-       write_cyrix_reg(CCR3, ccr3);
-
-       /* Unlock NW bit in CR0. */
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
-
-       /*
-        * Earlier revision of the 6x86 CPU could crash the system if
-        * L1 cache is in write-back mode.
-        */
-       if ((cyrix_did & 0xff00) > 0x1600)
-               load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
-       else {
-               /* Revision 2.6 and lower. */
-#ifdef CYRIX_CACHE_REALLY_WORKS
-               load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
-#else
-               load_cr0((rcr0() & ~CR0_CD) | CR0_NW);  /* CD = 0 and NW = 1 */
-#endif
-       }
-
-       /* Lock NW bit in CR0. */
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
-
-       write_eflags(eflags);
-}
-#endif /* I486_CPU */
-
-#ifdef I686_CPU
-/*
- * Cyrix 6x86MX (code-named M2)
- *
- * XXX - What should I do here?  Please let me know.
- */
-static void
-init_6x86MX(void)
-{
-       u_long  eflags;
-       u_char  ccr3, ccr4;
-
-       eflags = read_eflags();
-       cpu_disable_intr();
-
-       load_cr0(rcr0() | CR0_CD | CR0_NW);
-       wbinvd();
-
-       /* Initialize CCR0. */
-       write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
-
-       /* Initialize CCR1. */
-#ifdef CPU_CYRIX_NO_LOCK
-       write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
-#else
-       write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
-#endif
-
-       /* Initialize CCR2. */
-#ifdef CPU_SUSP_HLT
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
-#else
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
-#endif
-
-       ccr3 = read_cyrix_reg(CCR3);
-       write_cyrix_reg(CCR3, CCR3_MAPEN0);
-
-       /* Initialize CCR4. */
-       ccr4 = read_cyrix_reg(CCR4);
-       ccr4 &= ~CCR4_IOMASK;
-#ifdef CPU_IORT
-       write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
-#else
-       write_cyrix_reg(CCR4, ccr4 | 7);
-#endif
-
-       /* Initialize CCR5. */
-#ifdef CPU_WT_ALLOC
-       write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
-#endif
-
-       /* Restore CCR3. */
-       write_cyrix_reg(CCR3, ccr3);
-
-       /* Unlock NW bit in CR0. */
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
-
-       load_cr0(rcr0() & ~(CR0_CD | CR0_NW));  /* CD = 0 and NW = 0 */
-
-       /* Lock NW bit in CR0. */
-       write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
-
-       write_eflags(eflags);
-}
-
 static void
 init_ppro(void)
 {
@@ -633,28 +314,13 @@ initializecpu(void)
        case CPU_BLUE:
                init_bluelightning();
                break;
-       case CPU_486DLC:
-               init_486dlc();
-               break;
-       case CPU_CY486DX:
-               init_cy486dx();
-               break;
-       case CPU_M1SC:
-               init_5x86();
-               break;
 #ifdef CPU_I486_ON_386
        case CPU_486:
                init_i486_on_386();
                break;
 #endif
-       case CPU_M1:
-               init_6x86();
-               break;
 #endif /* I486_CPU */
 #ifdef I686_CPU
-       case CPU_M2:
-               init_6x86MX();
-               break;
        case CPU_686:
                if (cpu_vendor_id == CPU_VENDOR_INTEL) {
                        switch (cpu_id & 0xff0) {
@@ -884,52 +550,3 @@ enable_K6_2_wt_alloc(void)
 #endif /* I585_CPU && CPU_WT_ALLOC */
 
 #include "opt_ddb.h"
-#ifdef DDB
-#include <ddb/ddb.h>
-
-DB_SHOW_COMMAND(cyrixreg, cyrixreg)
-{
-       u_long  eflags;
-       u_int   cr0;
-       u_char  ccr1, ccr2, ccr3;
-       u_char  ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
-
-       cr0 = rcr0();
-       if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
-               eflags = read_eflags();
-               cpu_disable_intr();
-
-
-               if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
-                       ccr0 = read_cyrix_reg(CCR0);
-               }
-               ccr1 = read_cyrix_reg(CCR1);
-               ccr2 = read_cyrix_reg(CCR2);
-               ccr3 = read_cyrix_reg(CCR3);
-               if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
-                       write_cyrix_reg(CCR3, CCR3_MAPEN0);
-                       ccr4 = read_cyrix_reg(CCR4);
-                       if ((cpu == CPU_M1) || (cpu == CPU_M2))
-                               ccr5 = read_cyrix_reg(CCR5);
-                       else
-                               pcr0 = read_cyrix_reg(PCR0);
-                       write_cyrix_reg(CCR3, ccr3);            /* Restore CCR3. */
-               }
-               write_eflags(eflags);
-
-               if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
-                       kprintf("CCR0=%x, ", (u_int)ccr0);
-
-               kprintf("CCR1=%x, CCR2=%x, CCR3=%x",
-                       (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
-               if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
-                       kprintf(", CCR4=%x, ", (u_int)ccr4);
-                       if (cpu == CPU_M1SC)
-                               kprintf("PCR0=%x\n", pcr0);
-                       else
-                               kprintf("CCR5=%x\n", ccr5);
-               }
-       }
-       kprintf("CR0=%x\n", cr0);
-}
-#endif /* DDB */