From: Sepherosa Ziehau Date: Sat, 26 May 2007 08:50:49 +0000 (+0000) Subject: Add support for Broadcom NetXtreme II GigE. Jumbo buffer support X-Git-Tag: v2.0.1~2975 X-Git-Url: https://gitweb.dragonflybsd.org/dragonfly.git/commitdiff_plain/43c2aeb0f980e1e05b72723a6f40647bb302368d Add support for Broadcom NetXtreme II GigE. Jumbo buffer support is missing currently, which will be added later. Thank David Christensen for sending us two sample NICs. Thank dillon@ for providing a blazing fast machine and environment to test the driver. Also thank Walter very much, who contacted Broadcom for me :) Obtained-from: FreeBSD (w/ modification) --- diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 4b9fcba331..a2bfd1ae82 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -1,6 +1,6 @@ # @(#)Makefile 8.1 (Berkeley) 6/18/93 # $FreeBSD: src/share/man/man4/Makefile,v 1.83.2.66 2003/06/04 17:10:30 sam Exp $ -# $DragonFly: src/share/man/man4/Makefile,v 1.52 2007/04/01 13:19:49 swildner Exp $ +# $DragonFly: src/share/man/man4/Makefile,v 1.53 2007/05/26 08:50:49 sephe Exp $ MAN= aac.4 \ acpi.4 \ @@ -26,6 +26,7 @@ MAN= aac.4 \ aue.4 \ awi.4 \ axe.4 \ + bce.4 \ bfe.4 \ bge.4 \ bktr.4 \ diff --git a/share/man/man4/bce.4 b/share/man/man4/bce.4 new file mode 100644 index 0000000000..c7368d7eea --- /dev/null +++ b/share/man/man4/bce.4 @@ -0,0 +1,295 @@ +.\" Copyright (c) 2006 Broadcom Corporation +.\" David Christensen . All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" 3. Neither the name of Broadcom Corporation nor the name of its contributors +.\" may be used to endorse or promote products derived from this software +.\" without specific prior written consent. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' +.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +.\" THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" $FreeBSD: src/share/man/man4/bce.4,v 1.7 2007/02/09 18:26:13 brueffer Exp $ +.\" $DragonFly: src/share/man/man4/bce.4,v 1.1 2007/05/26 08:50:49 sephe Exp $ +.\" +.Dd May 26, 2007 +.Dt BCE 4 +.Os +.Sh NAME +.Nm bce +.Nd "Broadcom NetXtreme II (BCM5706/BCM5708) PCI/PCIe Gigabit Ethernet adapter driver" +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "device miibus" +.Cd "device bce" +.Ed +.Pp +Alternatively, to load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +if_bce_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver supports Broadcom's NetXtreme II product family, including the +BCM5706 and BCM5708 Ethernet controllers. +.Pp +The NetXtreme II product family is composed of various Converged NIC (or CNIC) +Ethernet controllers which support a TCP Offload Engine (TOE), Remote DMA (RDMA), +and iSCSI acceleration, in addition to standard L2 Ethernet traffic, all on the +same controller. +The following features are supported in the +.Nm +driver under +.Dx : +.Pp +.Bl -item -offset indent -compact +.It +.\"IP/TCP/UDP checksum offload +TCP/UDP checksum offload +.\".It +.\"Jumbo frames (up to 9022 bytes) +.It +VLAN tag stripping +.It +Interrupt coalescing +.It +10/100/1000Mbps operation in full-duplex mode +.It +10/100Mbps operation in half-duplex mode +.El +.Pp +The +.Nm +driver supports the following media types: +.Bl -tag -width ".Cm 10baseT/UTP" +.It Cm autoselect +Enable autoselection of the media type and options. +The user can manually override +the autoselected mode by adding media options to +.Xr rc.conf 5 . +.It Cm 10baseT/UTP +Set 10Mbps operation. +The +.Xr ifconfig 8 +.Cm mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 100baseTX +Set 100Mbps (Fast Ethernet) operation. +The +.Xr ifconfig 8 +.Cm mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 1000baseT +Set 1000baseT operation over twisted pair. +Only +.Cm full-duplex +mode is supported. +.El +.Pp +The +.Nm +driver supports the following media options: +.Bl -tag -width ".Cm full-duplex" +.It Cm full-duplex +Force full duplex operation. +.It Cm half-duplex +Force half duplex operation. +.El +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh HARDWARE +The +.Nm +driver provides support for various NICs based on the Broadcom NetXtreme II +family of Gigabit Ethernet controllers, including the +following: +.Pp +.Bl -bullet -compact +.It +HP NC370T Multifunction Gigabit Server Adapter +.It +HP NC370i Multifunction Gigabit Server Adapter +.El +.Sh DIAGNOSTICS +.Bl -diag +.It "bce%d: PCI memory allocation failed!" +The driver has encountered a fatal initialization error. +.It "bce%d: PCI map interrupt failed!" +The driver has encountered a fatal initialization error. +.It "bce%d: Unsupported controller revision (%c%d)" +The driver does not support the controller revision in use. +.It "bce%d: Controller initialization failed!" +The driver has encountered a fatal initialization error. +.It "bce%d: NVRAM test failed!" +The driver could not access the controller NVRAM correctly. +.It "bce%d: DMA resource allocation failed!" +The driver could not allocate DMA memory to setup the controllers +host memory data structures. +.It "bce%d: Interface allocation failed!" +The driver could not create a network interface for the controller. +.It "bce%d: PHY probe failed!" +The driver could not access the PHY used by the controller. +.It "bce%d: Failed to setup IRQ!" +The driver could not initialize the IRQ handler. +.It "bce%d: Error: PHY read timeout!" +The driver could not read a PHY register before the timeout period expired. +.It "bce%d: PHY write timeout!" +The driver could not write to the PHY register because a timeout occurred. +.It "bce%d: Timeout error reading NVRAM at offset 0x%08X!" +The driver could not write to NVRAM because a timeout occurred. +.It "bce%d: Unknown Flash NVRAM found!" +The driver does not recognize the NVRAM device being used and therefore +cannot access it correctly. +.It "bce%d: Invalid NVRAM magic value!" +The driver cannot read NVRAM or the NVRAM is corrupt. +.It "bce%d: Invalid Manufacturing Information NVRAM CRC!" +The driver cannot read NVRAM or the NVRAM is corrupt. +.It "bce%d: Invalid Feature Configuration Information NVRAM CRC!" +The driver cannot read NVRAM or the NVRAM is corrupt. +.It "bce%d: DMA mapping error!" +The driver was unable to map memory into DMA addressable space required +by the controller. +.It "bce%d: Could not allocate parent DMA tag!" +The driver could not allocate a PCI compatible DMA tag. +.It "bce%d: Could not allocate status block DMA tag!" +The driver could not allocate a DMA tag for the controller's +status block. +.It "bce%d: Could not allocate status block DMA memory!" +The driver could not allocate DMA addressable memory for the controller's +status block. +.It "bce_d: Could not map status block DMA memory!" +The driver could not map the status block memory into the controller's DMA +address space. +.It "bce%d: Could not allocate statistics block DMA tag!" +The driver could not allocate a DMA tag for the controller's +statistics block. +.It "bce%d: Could not allocate statistics block DMA memory!" +The driver could not allocate DMA addressable memory for the controller's +statistics block. +.It "bce%d: Could not map statistics block DMA memory!" +The driver could not map the statistics block memory into the controller's DMA +address space. +.It "bce%d: Could not allocate TX descriptor chain DMA tag!" +The driver could not allocate a DMA tag for the controller's +TX chain. +.It "bce%d: Could not allocate TX descriptor chain DMA memory! +The driver could not allocate DMA addressable memory for the controller's +TX chain. +.It "bce%d: Could not map TX descriptor chain DMA memory!" +The driver could not map the TX descriptor chain memory into the controller's DMA +address space. +.It "bce%d: Could not allocate TX mbuf DMA tag!" +The driver could not allocate a DMA tag for the controller's +TX mbuf memory. +.It "bce%d: Unable to create TX mbuf DMA map!" +The driver could not map the TX mbuf memory into the controller's DMA +address space. +.It "bce%d: Could not allocate RX descriptor chain DMA tag!" +The driver could not allocate a DMA tag for the controller's +RX chain. +.It "bce%d: Could not allocate RX descriptor chain " +The driver could not allocate DMA addressable memory for the controller's +RX chain. +.It "bce%d: Could not map RX descriptor chain DMA memory!" +The driver could not map the RX descriptor chain memory into the controller's DMA +address space. +.It "bce%d: Could not allocate RX mbuf DMA tag!" +The driver could not allocate a DMA tag for the controller's +RX mbuf memory. +.It "bce%d: Unable to create RX mbuf DMA map!" +The driver could not map the RX mbuf memory into the controller's DMA +address space. +.It "bce%d: Firmware synchronization timeout!" +The driver was not able to synchronize with the firmware running on the +controller. +The firmware may be stopped or hung. +.It "bce%d: Invalid Ethernet address!" +The driver was not able to read a valid Ethernet MAC address from NVRAM. +.It "bce%d: Reset failed!" +The driver has encountered a fatal initialization error. +.It "bce%d: Byte swap is incorrect!" +The driver has encountered a fatal initialization error. +Contact the author +with details of the CPU architecture and system chipset in use. +.It "bce%d: Firmware did not complete initialization!" +The driver has encountered a fatal initialization error. +.It "bce%d: Bootcode not running!" +The driver has encountered a fatal initialization error. +.It "bce%d: Error mapping mbuf into RX chain!" +The driver could not map a RX mbuf into DMA addressable memory. +.It "bce%d: Error filling RX chain: rx_bd[0x%04X]!" +The driver was unable to allocate enough mbufs to fill the RX chain +during initialization. +Try increasing the number of mbufs available in +the system, increase system memory. +.\"or if using jumbo frames, make sure enough 9KB mbufs are available. +.It "bce%d: Failed to allocate new mbuf, incoming frame dropped!" +The driver was unable to allocate a new mbuf for the RX chain and reused +the mbuf for the received frame, dropping the incoming frame in the process. +Try increasing the number of mbufs available in the system or increase system +memory. +.It "bce%d: Controller reset failed!" +A fatal initialization error has occurred. +.It "bce%d: Controller initialization failed!" +A fatal initialization error has occurred. +.It "bce%d: Block initialization failed!" +A fatal initialization error has occurred. +.It "bce%d: Error mapping mbuf into TX chain!" +The driver could not map a TX mbuf into DMA addressable memory. +.It "bce%d: Watchdog timeout occurred, resetting!" +The device has stopped responding to the network, there is a problem +with the cable connection, or a driver logic problem has occurred.. +.It "bce%d: Fatal attention detected: 0x%08X!" +A controller hardware failure has occurred. +If the problem continues replace the controller. +.El +.Sh SEE ALSO +.Xr altq 4 , +.Xr arp 4 , +.Xr miibus 4 , +.Xr netintro 4 , +.Xr ng_ether 4 , +.Xr vlan 4 , +.Xr ifconfig 8 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 6.1 . +.Sh AUTHORS +The +.Nm +driver was written by +.An David Christensen Aq davidch@broadcom.com . diff --git a/sys/conf/files b/sys/conf/files index 92cd5b70b9..a4ee45db37 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -1,5 +1,5 @@ # $FreeBSD: src/sys/conf/files,v 1.340.2.137 2003/06/04 17:10:30 sam Exp $ -# $DragonFly: src/sys/conf/files,v 1.159 2007/04/29 01:29:30 dillon Exp $ +# $DragonFly: src/sys/conf/files,v 1.160 2007/05/26 08:50:49 sephe Exp $ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and @@ -179,6 +179,7 @@ dev/disk/aic7xxx/ahd_pci.c optional ahd pci dev/disk/aic7xxx/aic79xx.c optional ahd pci dev/disk/aic7xxx/aic79xx_osm.c optional ahd pci dev/disk/aic7xxx/aic79xx_pci.c optional ahd pci +dev/netif/bce/if_bce.c optional bce dev/netif/bfe/if_bfe.c optional bfe dev/netif/bge/if_bge.c optional bge dev/disk/buslogic/bt.c optional bt diff --git a/sys/conf/options b/sys/conf/options index 184ec98967..655625b1a6 100644 --- a/sys/conf/options +++ b/sys/conf/options @@ -1,5 +1,5 @@ # $FreeBSD: src/sys/conf/options,v 1.191.2.53 2003/06/04 17:56:58 sam Exp $ -# $DragonFly: src/sys/conf/options,v 1.64 2007/04/26 02:10:57 dillon Exp $ +# $DragonFly: src/sys/conf/options,v 1.65 2007/05/26 08:50:49 sephe Exp $ # # On the handling of kernel options # @@ -512,6 +512,10 @@ KTR_VERBOSE opt_ktr.h KTR_GIANT_CONTENTION opt_ktr.h KTR_SPIN_CONTENTION opt_ktr.h +# bce driver +BCE_DEBUG opt_bce.h +BCE_NVRAM_WRITE_SUPPORT opt_bce.h + # ed driver ED_NO_MIIBUS opt_ed.h diff --git a/sys/config/GENERIC b/sys/config/GENERIC index 65e368b5d9..40cee8b512 100644 --- a/sys/config/GENERIC +++ b/sys/config/GENERIC @@ -4,7 +4,7 @@ # Check the LINT configuration file in sys/config, for an # exhaustive list of options. # -# $DragonFly: src/sys/config/GENERIC,v 1.49 2007/04/01 13:59:41 sephe Exp $ +# $DragonFly: src/sys/config/GENERIC,v 1.50 2007/05/26 08:50:49 sephe Exp $ platform pc32 machine i386 @@ -192,6 +192,7 @@ device vx # 3Com 3c590, 3c595 (``Vortex'') # PCI Ethernet NICs that use the common MII bus controller code. # NOTE: Be sure to keep the 'device miibus' line in order to use these NICs! device miibus # MII bus support +device bce # Broadcom NetXtreme II Gigabit Ethernet device bfe # Broadcom BCM440x 10/100 Ethernet device dc # DEC/Intel 21143 and various workalikes device fxp # Intel EtherExpress PRO/100B (82557, 82558) diff --git a/sys/config/LINT b/sys/config/LINT index c74deac65b..58addddca2 100644 --- a/sys/config/LINT +++ b/sys/config/LINT @@ -3,7 +3,7 @@ # as much of the source tree as it can. # # $FreeBSD: src/sys/i386/conf/LINT,v 1.749.2.144 2003/06/04 17:56:59 sam Exp $ -# $DragonFly: src/sys/config/LINT,v 1.114 2007/05/23 17:07:55 swildner Exp $ +# $DragonFly: src/sys/config/LINT,v 1.115 2007/05/26 08:50:49 sephe Exp $ # # NB: You probably don't want to try running a kernel built from this # file. Instead, you should start from GENERIC, and add options from @@ -1961,6 +1961,7 @@ device trm # Tekram DC395U/UW/F and DC315U device miibus # PCI Ethernet NICs that use the common MII bus controller code. +device bce # Broadcom NetXtreme II Gigabit Ethernet device bfe # Broadcom BCM440x 10/100 Ethernet device dc # DEC/Intel 21143 and various workalikes device fxp # Intel EtherExpress PRO/100B (82557, 82558) @@ -2698,6 +2699,8 @@ options DEBUG_CRIT_SECTIONS options DEBUG_INTERRUPTS options DEVICE_SYSCTLS #options DISABLE_PSE +options BCE_DEBUG +options BCE_NVRAM_WRITE_SUPPORT #options ED_NO_MIIBUS options ENABLE_ALART options FB_DEBUG=2 diff --git a/sys/config/NATA b/sys/config/NATA index 40c2ee6270..ee62c0a25f 100644 --- a/sys/config/NATA +++ b/sys/config/NATA @@ -6,7 +6,7 @@ # Check the LINT configuration file in sys/config, for an # exhaustive list of options. # -# $DragonFly: src/sys/config/Attic/NATA,v 1.3 2007/05/18 02:07:57 dillon Exp $ +# $DragonFly: src/sys/config/Attic/NATA,v 1.4 2007/05/26 08:50:49 sephe Exp $ platform pc32 machine i386 @@ -194,6 +194,7 @@ device vx # 3Com 3c590, 3c595 (``Vortex'') # PCI Ethernet NICs that use the common MII bus controller code. # NOTE: Be sure to keep the 'device miibus' line in order to use these NICs! device miibus # MII bus support +device bce # Broadcom NetXtreme II Gigabit Ethernet device bfe # Broadcom BCM440x 10/100 Ethernet device dc # DEC/Intel 21143 and various workalikes device fxp # Intel EtherExpress PRO/100B (82557, 82558) diff --git a/sys/dev/netif/Makefile b/sys/dev/netif/Makefile index 7119422209..7e476ffff6 100644 --- a/sys/dev/netif/Makefile +++ b/sys/dev/netif/Makefile @@ -1,8 +1,8 @@ -# $DragonFly: src/sys/dev/netif/Makefile,v 1.24 2006/12/10 04:59:38 sephe Exp $ +# $DragonFly: src/sys/dev/netif/Makefile,v 1.25 2007/05/26 08:50:49 sephe Exp $ # -SUBDIR= an acx ar ath aue axe bfe bge cue dc ed em ep fwe fxp gx ipw iwi kue \ - lge lnc mii_layer my nfe nge nv pcn ral ray re rl rtw rue rum sbni \ - sbsh sf sis sk sr ste stge ti tl tx txp ural vge vr vx wb wi xe xl +SUBDIR= an acx ar ath aue axe bce bfe bge cue dc ed em ep fwe fxp gx ipw iwi \ + kue lge lnc mii_layer my nfe nge nv pcn ral ray re rl rtw rue rum \ + sbni sbsh sf sis sk sr ste stge ti tl tx txp ural vge vr vx wb wi xe xl .include diff --git a/sys/dev/netif/bce/Makefile b/sys/dev/netif/bce/Makefile new file mode 100644 index 0000000000..710d75db36 --- /dev/null +++ b/sys/dev/netif/bce/Makefile @@ -0,0 +1,18 @@ +# $DragonFly: src/sys/dev/netif/bce/Makefile,v 1.1 2007/05/26 08:50:49 sephe Exp $ + +KMOD= if_bce +SRCS= if_bce.c +SRCS+= miibus_if.h device_if.h bus_if.h pci_if.h +SRCS+= opt_bce.h opt_polling.h + +KMODDEPS = miibus + +#ifndef BUILDING_WITH_KERNEL +opt_polling.h: + echo '#define DEVICE_POLLING 1' > ${.OBJDIR}/${.TARGET} + +opt_bce.h: + touch ${.OBJDIR}/${.TARGET} +#endif + +.include diff --git a/sys/dev/netif/bce/if_bce.c b/sys/dev/netif/bce/if_bce.c new file mode 100644 index 0000000000..0517cfd9c9 --- /dev/null +++ b/sys/dev/netif/bce/if_bce.c @@ -0,0 +1,7136 @@ +/*- + * Copyright (c) 2006-2007 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $ + * $DragonFly: src/sys/dev/netif/bce/if_bce.c,v 1.1 2007/05/26 08:50:49 sephe Exp $ + */ + +/* + * The following controllers are supported by this driver: + * BCM5706C A2, A3 + * BCM5708C B1, B2 + * + * The following controllers are not supported by this driver: + * BCM5706C A0, A1 + * BCM5706S A0, A1, A2, A3 + * BCM5708C A0, B0 + * BCM5708S A0, B0, B1, B2 + */ + +#include "opt_bce.h" +#include "opt_polling.h" + +#include +#include +#include +#include +#include +#include +#include +#ifdef BCE_DEBUG +#include +#endif +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "miibus_if.h" + +#include "if_bcereg.h" +#include "if_bcefw.h" + +/****************************************************************************/ +/* BCE Debug Options */ +/****************************************************************************/ +#ifdef BCE_DEBUG + +static uint32_t bce_debug = BCE_WARN; + +/* + * 0 = Never + * 1 = 1 in 2,147,483,648 + * 256 = 1 in 8,388,608 + * 2048 = 1 in 1,048,576 + * 65536 = 1 in 32,768 + * 1048576 = 1 in 2,048 + * 268435456 = 1 in 8 + * 536870912 = 1 in 4 + * 1073741824 = 1 in 2 + * + * bce_debug_l2fhdr_status_check: + * How often the l2_fhdr frame error check will fail. + * + * bce_debug_unexpected_attention: + * How often the unexpected attention check will fail. + * + * bce_debug_mbuf_allocation_failure: + * How often to simulate an mbuf allocation failure. + * + * bce_debug_dma_map_addr_failure: + * How often to simulate a DMA mapping failure. + * + * bce_debug_bootcode_running_failure: + * How often to simulate a bootcode failure. + */ +static int bce_debug_l2fhdr_status_check = 0; +static int bce_debug_unexpected_attention = 0; +static int bce_debug_mbuf_allocation_failure = 0; +static int bce_debug_dma_map_addr_failure = 0; +static int bce_debug_bootcode_running_failure = 0; + +#endif /* BCE_DEBUG */ + + +/****************************************************************************/ +/* PCI Device ID Table */ +/* */ +/* Used by bce_probe() to identify the devices supported by this driver. */ +/****************************************************************************/ +#define BCE_DEVDESC_MAX 64 + +static struct bce_type bce_devs[] = { + /* BCM5706C Controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, + "HP NC370T Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, + "HP NC370i Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5706 1000Base-T" }, + + /* BCM5706S controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, + "HP NC370F Multifunction Gigabit Server Adapter" }, + { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5706 1000Base-SX" }, + + /* BCM5708C controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5708 1000Base-T" }, + + /* BCM5708S controllers and OEM boards. */ + { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, + "Broadcom NetXtreme II BCM5708S 1000Base-T" }, + { 0, 0, 0, 0, NULL } +}; + + +/****************************************************************************/ +/* Supported Flash NVRAM device data. */ +/****************************************************************************/ +static const struct flash_spec flash_table[] = +{ + /* Slow EEPROM */ + {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - slow"}, + /* Expansion entry 0001 */ + {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0001"}, + /* Saifun SA25F010 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, + "Non-buffered flash (128kB)"}, + /* Saifun SA25F020 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, + "Non-buffered flash (256kB)"}, + /* Expansion entry 0100 */ + {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 0100"}, + /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ + {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, + "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, + /* Entry 0110: ST M45PE20 (non-buffered flash)*/ + {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, + 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, + ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, + "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, + /* Saifun SA25F005 (non-buffered flash) */ + /* strap, cfg1, & write1 need updates */ + {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, + "Non-buffered flash (64kB)"}, + /* Fast EEPROM */ + {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, + 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, + SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, + "EEPROM - fast"}, + /* Expansion entry 1001 */ + {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1001"}, + /* Expansion entry 1010 */ + {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1010"}, + /* ATMEL AT45DB011B (buffered flash) */ + {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, + "Buffered flash (128kB)"}, + /* Expansion entry 1100 */ + {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1100"}, + /* Expansion entry 1101 */ + {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, + 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, + SAIFUN_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1101"}, + /* Ateml Expansion entry 1110 */ + {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, 0, + "Entry 1110 (Atmel)"}, + /* ATMEL AT45DB021B (buffered flash) */ + {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, + 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, + BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, + "Buffered flash (256kB)"}, +}; + + +/****************************************************************************/ +/* DragonFly device entry points. */ +/****************************************************************************/ +static int bce_probe(device_t); +static int bce_attach(device_t); +static int bce_detach(device_t); +static void bce_shutdown(device_t); + +/****************************************************************************/ +/* BCE Debug Data Structure Dump Routines */ +/****************************************************************************/ +#ifdef BCE_DEBUG +static void bce_dump_mbuf(struct bce_softc *, struct mbuf *); +static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int); +static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int); +static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *); +static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *); +static void bce_dump_l2fhdr(struct bce_softc *, int, + struct l2_fhdr *) __unused; +static void bce_dump_tx_chain(struct bce_softc *, int, int); +static void bce_dump_rx_chain(struct bce_softc *, int, int); +static void bce_dump_status_block(struct bce_softc *); +static void bce_dump_driver_state(struct bce_softc *); +static void bce_dump_stats_block(struct bce_softc *) __unused; +static void bce_dump_hw_state(struct bce_softc *); +static void bce_dump_txp_state(struct bce_softc *); +static void bce_dump_rxp_state(struct bce_softc *) __unused; +static void bce_dump_tpat_state(struct bce_softc *) __unused; +static void bce_freeze_controller(struct bce_softc *) __unused; +static void bce_unfreeze_controller(struct bce_softc *) __unused; +static void bce_breakpoint(struct bce_softc *); +#endif /* BCE_DEBUG */ + + +/****************************************************************************/ +/* BCE Register/Memory Access Routines */ +/****************************************************************************/ +static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t); +static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t); +static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t); +static int bce_miibus_read_reg(device_t, int, int); +static int bce_miibus_write_reg(device_t, int, int, int); +static void bce_miibus_statchg(device_t); + + +/****************************************************************************/ +/* BCE NVRAM Access Routines */ +/****************************************************************************/ +static int bce_acquire_nvram_lock(struct bce_softc *); +static int bce_release_nvram_lock(struct bce_softc *); +static void bce_enable_nvram_access(struct bce_softc *); +static void bce_disable_nvram_access(struct bce_softc *); +static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *, + uint32_t); +static int bce_init_nvram(struct bce_softc *); +static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int); +static int bce_nvram_test(struct bce_softc *); +#ifdef BCE_NVRAM_WRITE_SUPPORT +static int bce_enable_nvram_write(struct bce_softc *); +static void bce_disable_nvram_write(struct bce_softc *); +static int bce_nvram_erase_page(struct bce_softc *, uint32_t); +static int bce_nvram_write_dword(struct bce_softc *, uint32_t, uint8_t *, uint32_t); +static int bce_nvram_write(struct bce_softc *, uint32_t, uint8_t *, + int) __unused; +#endif + +/****************************************************************************/ +/* BCE DMA Allocate/Free Routines */ +/****************************************************************************/ +static int bce_dma_alloc(struct bce_softc *); +static void bce_dma_free(struct bce_softc *); +static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int); +static void bce_dma_map_mbuf(void *, bus_dma_segment_t *, int, + bus_size_t, int); + +/****************************************************************************/ +/* BCE Firmware Synchronization and Load */ +/****************************************************************************/ +static int bce_fw_sync(struct bce_softc *, uint32_t); +static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *, + uint32_t, uint32_t); +static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *, + struct fw_info *); +static void bce_init_cpus(struct bce_softc *); + +static void bce_stop(struct bce_softc *); +static int bce_reset(struct bce_softc *, uint32_t); +static int bce_chipinit(struct bce_softc *); +static int bce_blockinit(struct bce_softc *); +static int bce_newbuf_std(struct bce_softc *, struct mbuf *, + uint16_t *, uint16_t *, uint32_t *); + +static int bce_init_tx_chain(struct bce_softc *); +static int bce_init_rx_chain(struct bce_softc *); +static void bce_free_rx_chain(struct bce_softc *); +static void bce_free_tx_chain(struct bce_softc *); + +static int bce_encap(struct bce_softc *, struct mbuf **); +static void bce_start(struct ifnet *); +static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); +static void bce_watchdog(struct ifnet *); +static int bce_ifmedia_upd(struct ifnet *); +static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *); +static void bce_init(void *); +static void bce_mgmt_init(struct bce_softc *); + +static void bce_init_context(struct bce_softc *); +static void bce_get_mac_addr(struct bce_softc *); +static void bce_set_mac_addr(struct bce_softc *); +static void bce_phy_intr(struct bce_softc *); +static void bce_rx_intr(struct bce_softc *, int); +static void bce_tx_intr(struct bce_softc *); +static void bce_disable_intr(struct bce_softc *); +static void bce_enable_intr(struct bce_softc *); + +#ifdef DEVICE_POLLING +static void bce_poll(struct ifnet *, enum poll_cmd, int); +#endif +static void bce_intr(void *); +static void bce_set_rx_mode(struct bce_softc *); +static void bce_stats_update(struct bce_softc *); +static void bce_tick(void *); +static void bce_tick_serialized(struct bce_softc *); +static void bce_add_sysctls(struct bce_softc *); + + +/****************************************************************************/ +/* DragonFly device dispatch table. */ +/****************************************************************************/ +static device_method_t bce_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bce_probe), + DEVMETHOD(device_attach, bce_attach), + DEVMETHOD(device_detach, bce_detach), + DEVMETHOD(device_shutdown, bce_shutdown), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, bce_miibus_read_reg), + DEVMETHOD(miibus_writereg, bce_miibus_write_reg), + DEVMETHOD(miibus_statchg, bce_miibus_statchg), + + { 0, 0 } +}; + +static driver_t bce_driver = { + "bce", + bce_methods, + sizeof(struct bce_softc) +}; + +static devclass_t bce_devclass; + +MODULE_DEPEND(bce, pci, 1, 1, 1); +MODULE_DEPEND(bce, ether, 1, 1, 1); +MODULE_DEPEND(bce, miibus, 1, 1, 1); + +DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); +DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); + + +/****************************************************************************/ +/* Device probe function. */ +/* */ +/* Compares the device to the driver's list of supported devices and */ +/* reports back to the OS whether this is the right driver for the device. */ +/* */ +/* Returns: */ +/* BUS_PROBE_DEFAULT on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_probe(device_t dev) +{ + struct bce_type *t; + uint16_t vid, did, svid, sdid; + + /* Get the data for the device to be probed. */ + vid = pci_get_vendor(dev); + did = pci_get_device(dev); + svid = pci_get_subvendor(dev); + sdid = pci_get_subdevice(dev); + + /* Look through the list of known devices for a match. */ + for (t = bce_devs; t->bce_name != NULL; ++t) { + if (vid == t->bce_vid && did == t->bce_did && + (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) && + (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) { + uint32_t revid = pci_read_config(dev, PCIR_REVID, 4); + char *descbuf; + + descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK); + + /* Print out the device identity. */ + ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", + t->bce_name, + ((revid & 0xf0) >> 4) + 'A', revid & 0xf); + + device_set_desc_copy(dev, descbuf); + kfree(descbuf, M_TEMP); + return 0; + } + } + return ENXIO; +} + + +/****************************************************************************/ +/* Device attach function. */ +/* */ +/* Allocates device resources, performs secondary chip identification, */ +/* resets and initializes the hardware, and initializes driver instance */ +/* variables. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_attach(device_t dev) +{ + struct bce_softc *sc = device_get_softc(dev); + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val; + int rid, rc = 0; +#ifdef notyet + int count; +#endif + + sc->bce_dev = dev; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + + pci_enable_busmaster(dev); + + /* Allocate PCI memory resources. */ + rid = PCIR_BAR(0); + sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE | PCI_RF_DENSE); + if (sc->bce_res_mem == NULL) { + device_printf(dev, "PCI memory allocation failed\n"); + return ENXIO; + } + sc->bce_btag = rman_get_bustag(sc->bce_res_mem); + sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); + + /* Allocate PCI IRQ resources. */ +#ifdef notyet + count = pci_msi_count(dev); + if (count == 1 && pci_alloc_msi(dev, &count) == 0) { + rid = 1; + sc->bce_flags |= BCE_USING_MSI_FLAG; + } else +#endif + rid = 0; + sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->bce_res_irq == NULL) { + device_printf(dev, "PCI map interrupt failed\n"); + rc = ENXIO; + goto fail; + } + + /* + * Configure byte swap and enable indirect register access. + * Rely on CPU to do target byte swapping on big endian systems. + * Access to registers outside of PCI configurtion space are not + * valid until this is done. + */ + pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, + BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); + + /* Save ASIC revsion info. */ + sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); + + /* Weed out any non-production controller revisions. */ + switch(BCE_CHIP_ID(sc)) { + case BCE_CHIP_ID_5706_A0: + case BCE_CHIP_ID_5706_A1: + case BCE_CHIP_ID_5708_A0: + case BCE_CHIP_ID_5708_B0: + device_printf(dev, "Unsupported chip id 0x%08x!\n", + BCE_CHIP_ID(sc)); + rc = ENODEV; + goto fail; + } + + /* + * The embedded PCIe to PCI-X bridge (EPB) + * in the 5708 cannot address memory above + * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). + */ + if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) + sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; + else + sc->max_bus_addr = BUS_SPACE_MAXADDR; + + /* + * Find the base address for shared memory access. + * Newer versions of bootcode use a signature and offset + * while older versions use a fixed address. + */ + val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); + if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) + sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0); + else + sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; + + DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base); + + /* Get PCI bus information (speed and type). */ + val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); + if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { + uint32_t clkreg; + + sc->bce_flags |= BCE_PCIX_FLAG; + + clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) & + BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; + switch (clkreg) { + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: + sc->bus_speed_mhz = 133; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: + sc->bus_speed_mhz = 100; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: + sc->bus_speed_mhz = 66; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: + sc->bus_speed_mhz = 50; + break; + + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: + case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: + sc->bus_speed_mhz = 33; + break; + } + } else { + if (val & BCE_PCICFG_MISC_STATUS_M66EN) + sc->bus_speed_mhz = 66; + else + sc->bus_speed_mhz = 33; + } + + if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) + sc->bce_flags |= BCE_PCI_32BIT_FLAG; + + device_printf(dev, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n", + sc->bce_chipid, + ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', + (BCE_CHIP_ID(sc) & 0x0ff0) >> 4, + (sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : "", + (sc->bce_flags & BCE_PCI_32BIT_FLAG) ? + "32-bit" : "64-bit", sc->bus_speed_mhz); + + /* Reset the controller. */ + rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET); + if (rc != 0) + goto fail; + + /* Initialize the controller. */ + rc = bce_chipinit(sc); + if (rc != 0) { + device_printf(dev, "Controller initialization failed!\n"); + goto fail; + } + + /* Perform NVRAM test. */ + rc = bce_nvram_test(sc); + if (rc != 0) { + device_printf(dev, "NVRAM test failed!\n"); + goto fail; + } + + /* Fetch the permanent Ethernet MAC address. */ + bce_get_mac_addr(sc); + + /* + * Trip points control how many BDs + * should be ready before generating an + * interrupt while ticks control how long + * a BD can sit in the chain before + * generating an interrupt. Set the default + * values for the RX and TX rings. + */ + +#ifdef BCE_DRBUG + /* Force more frequent interrupts. */ + sc->bce_tx_quick_cons_trip_int = 1; + sc->bce_tx_quick_cons_trip = 1; + sc->bce_tx_ticks_int = 0; + sc->bce_tx_ticks = 0; + + sc->bce_rx_quick_cons_trip_int = 1; + sc->bce_rx_quick_cons_trip = 1; + sc->bce_rx_ticks_int = 0; + sc->bce_rx_ticks = 0; +#else + sc->bce_tx_quick_cons_trip_int = 20; + sc->bce_tx_quick_cons_trip = 20; + sc->bce_tx_ticks_int = 80; + sc->bce_tx_ticks = 80; + + sc->bce_rx_quick_cons_trip_int = 6; + sc->bce_rx_quick_cons_trip = 6; + sc->bce_rx_ticks_int = 18; + sc->bce_rx_ticks = 18; +#endif + + /* Update statistics once every second. */ + sc->bce_stats_ticks = 1000000 & 0xffff00; + + /* + * The copper based NetXtreme II controllers + * use an integrated PHY at address 1 while + * the SerDes controllers use a PHY at + * address 2. + */ + sc->bce_phy_addr = 1; + + if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { + sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; + sc->bce_flags |= BCE_NO_WOL_FLAG; + if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) { + sc->bce_phy_addr = 2; + val = REG_RD_IND(sc, sc->bce_shmem_base + + BCE_SHARED_HW_CFG_CONFIG); + if (val & BCE_SHARED_HW_CFG_PHY_2_5G) + sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; + } + } + + /* Allocate DMA memory resources. */ + rc = bce_dma_alloc(sc); + if (rc != 0) { + device_printf(dev, "DMA resource allocation failed!\n"); + goto fail; + } + + /* Initialize the ifnet interface. */ + ifp->if_softc = sc; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = bce_ioctl; + ifp->if_start = bce_start; + ifp->if_init = bce_init; + ifp->if_watchdog = bce_watchdog; +#ifdef DEVICE_POLLING + ifp->if_poll = bce_poll; +#endif + ifp->if_mtu = ETHERMTU; + ifp->if_hwassist = BCE_IF_HWASSIST; + ifp->if_capabilities = BCE_IF_CAPABILITIES; + ifp->if_capenable = ifp->if_capabilities; + ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD); + ifq_set_ready(&ifp->if_snd); + + if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) + ifp->if_baudrate = IF_Gbps(2.5); + else + ifp->if_baudrate = IF_Gbps(1); + + /* Assume a standard 1500 byte MTU size for mbuf allocations. */ + sc->mbuf_alloc_size = MCLBYTES; + + /* Look for our PHY. */ + rc = mii_phy_probe(dev, &sc->bce_miibus, + bce_ifmedia_upd, bce_ifmedia_sts); + if (rc != 0) { + device_printf(dev, "PHY probe failed!\n"); + goto fail; + } + + /* Attach to the Ethernet interface list. */ + ether_ifattach(ifp, sc->eaddr, NULL); + + callout_init(&sc->bce_stat_ch); + + /* Hookup IRQ last. */ + rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_NETSAFE, bce_intr, sc, + &sc->bce_intrhand, ifp->if_serializer); + if (rc != 0) { + device_printf(dev, "Failed to setup IRQ!\n"); + ether_ifdetach(ifp); + goto fail; + } + + /* Print some important debugging info. */ + DBRUN(BCE_INFO, bce_dump_driver_state(sc)); + + /* Add the supported sysctls to the kernel. */ + bce_add_sysctls(sc); + + /* Get the firmware running so IPMI still works */ + bce_mgmt_init(sc); + + return 0; +fail: + bce_detach(dev); + return(rc); +} + + +/****************************************************************************/ +/* Device detach function. */ +/* */ +/* Stops the controller, resets the controller, and releases resources. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_detach(device_t dev) +{ + struct bce_softc *sc = device_get_softc(dev); + + if (device_is_attached(dev)) { + struct ifnet *ifp = &sc->arpcom.ac_if; + + /* Stop and reset the controller. */ + lwkt_serialize_enter(ifp->if_serializer); + bce_stop(sc); + bce_reset(sc, BCE_DRV_MSG_CODE_RESET); + bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); + lwkt_serialize_exit(ifp->if_serializer); + + ether_ifdetach(ifp); + } + + /* If we have a child device on the MII bus remove it too. */ + if (sc->bce_miibus) + device_delete_child(dev, sc->bce_miibus); + bus_generic_detach(dev); + + if (sc->bce_res_irq != NULL) { + bus_release_resource(dev, SYS_RES_IRQ, + sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0, + sc->bce_res_irq); + } + +#ifdef notyet + if (sc->bce_flags & BCE_USING_MSI_FLAG) + pci_release_msi(dev); +#endif + + if (sc->bce_res_mem != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), + sc->bce_res_mem); + } + + bce_dma_free(sc); + + if (sc->bce_sysctl_tree != NULL) + sysctl_ctx_free(&sc->bce_sysctl_ctx); + + return 0; +} + + +/****************************************************************************/ +/* Device shutdown function. */ +/* */ +/* Stops and resets the controller. */ +/* */ +/* Returns: */ +/* Nothing */ +/****************************************************************************/ +static void +bce_shutdown(device_t dev) +{ + struct bce_softc *sc = device_get_softc(dev); + struct ifnet *ifp = &sc->arpcom.ac_if; + + lwkt_serialize_enter(ifp->if_serializer); + bce_stop(sc); + bce_reset(sc, BCE_DRV_MSG_CODE_RESET); + lwkt_serialize_exit(ifp->if_serializer); +} + + +/****************************************************************************/ +/* Indirect register read. */ +/* */ +/* Reads NetXtreme II registers using an index/data register pair in PCI */ +/* configuration space. Using this mechanism avoids issues with posted */ +/* reads but is much slower than memory-mapped I/O. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +static uint32_t +bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset) +{ + device_t dev = sc->bce_dev; + + pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); +#ifdef BCE_DEBUG + { + uint32_t val; + val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); + DBPRINT(sc, BCE_EXCESSIVE, + "%s(); offset = 0x%08X, val = 0x%08X\n", + __func__, offset, val); + return val; + } +#else + return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); +#endif +} + + +/****************************************************************************/ +/* Indirect register write. */ +/* */ +/* Writes NetXtreme II registers using an index/data register pair in PCI */ +/* configuration space. Using this mechanism avoids issues with posted */ +/* writes but is muchh slower than memory-mapped I/O. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val) +{ + device_t dev = sc->bce_dev; + + DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", + __func__, offset, val); + + pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); + pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); +} + + +/****************************************************************************/ +/* Context memory write. */ +/* */ +/* The NetXtreme II controller uses context memory to track connection */ +/* information for L2 and higher network protocols. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t offset, + uint32_t val) +{ + DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " + "val = 0x%08X\n", __func__, cid_addr, offset, val); + + offset += cid_addr; + REG_WR(sc, BCE_CTX_DATA_ADR, offset); + REG_WR(sc, BCE_CTX_DATA, val); +} + + +/****************************************************************************/ +/* PHY register read. */ +/* */ +/* Implements register reads on the MII bus. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +static int +bce_miibus_read_reg(device_t dev, int phy, int reg) +{ + struct bce_softc *sc = device_get_softc(dev); + uint32_t val; + int i; + + /* Make sure we are accessing the correct PHY address. */ + if (phy != sc->bce_phy_addr) { + DBPRINT(sc, BCE_VERBOSE, + "Invalid PHY address %d for PHY read!\n", phy); + return 0; + } + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + + val = BCE_MIPHY(phy) | BCE_MIREG(reg) | + BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | + BCE_EMAC_MDIO_COMM_START_BUSY; + REG_WR(sc, BCE_EMAC_MDIO_COMM, val); + + for (i = 0; i < BCE_PHY_TIMEOUT; i++) { + DELAY(10); + + val = REG_RD(sc, BCE_EMAC_MDIO_COMM); + if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + + val = REG_RD(sc, BCE_EMAC_MDIO_COMM); + val &= BCE_EMAC_MDIO_COMM_DATA; + break; + } + } + + if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { + if_printf(&sc->arpcom.ac_if, + "Error: PHY read timeout! phy = %d, reg = 0x%04X\n", + phy, reg); + val = 0x0; + } else { + val = REG_RD(sc, BCE_EMAC_MDIO_COMM); + } + + DBPRINT(sc, BCE_EXCESSIVE, + "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", + __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff); + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + return (val & 0xffff); +} + + +/****************************************************************************/ +/* PHY register write. */ +/* */ +/* Implements register writes on the MII bus. */ +/* */ +/* Returns: */ +/* The value of the register. */ +/****************************************************************************/ +static int +bce_miibus_write_reg(device_t dev, int phy, int reg, int val) +{ + struct bce_softc *sc = device_get_softc(dev); + uint32_t val1; + int i; + + /* Make sure we are accessing the correct PHY address. */ + if (phy != sc->bce_phy_addr) { + DBPRINT(sc, BCE_WARN, + "Invalid PHY address %d for PHY write!\n", phy); + return(0); + } + + DBPRINT(sc, BCE_EXCESSIVE, + "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", + __func__, phy, (uint16_t)(reg & 0xffff), + (uint16_t)(val & 0xffff)); + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + + val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | + BCE_EMAC_MDIO_COMM_COMMAND_WRITE | + BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; + REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); + + for (i = 0; i < BCE_PHY_TIMEOUT; i++) { + DELAY(10); + + val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); + if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { + DELAY(5); + break; + } + } + + if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) + if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n"); + + if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { + val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); + val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; + + REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); + REG_RD(sc, BCE_EMAC_MDIO_MODE); + + DELAY(40); + } + return 0; +} + + +/****************************************************************************/ +/* MII bus status change. */ +/* */ +/* Called by the MII bus driver when the PHY establishes link to set the */ +/* MAC interface registers. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_miibus_statchg(device_t dev) +{ + struct bce_softc *sc = device_get_softc(dev); + struct mii_data *mii = device_get_softc(sc->bce_miibus); + + DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n", + mii->mii_media_active); + +#ifdef BCE_DEBUG + /* Decode the interface media flags. */ + if_printf(&sc->arpcom.ac_if, "Media: ( "); + switch(IFM_TYPE(mii->mii_media_active)) { + case IFM_ETHER: + kprintf("Ethernet )"); + break; + default: + kprintf("Unknown )"); + break; + } + + kprintf(" Media Options: ( "); + switch(IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_AUTO: + kprintf("Autoselect )"); + break; + case IFM_MANUAL: + kprintf("Manual )"); + break; + case IFM_NONE: + kprintf("None )"); + break; + case IFM_10_T: + kprintf("10Base-T )"); + break; + case IFM_100_TX: + kprintf("100Base-TX )"); + break; + case IFM_1000_SX: + kprintf("1000Base-SX )"); + break; + case IFM_1000_T: + kprintf("1000Base-T )"); + break; + default: + kprintf("Other )"); + break; + } + + kprintf(" Global Options: ("); + if (mii->mii_media_active & IFM_FDX) + kprintf(" FullDuplex"); + if (mii->mii_media_active & IFM_HDX) + kprintf(" HalfDuplex"); + if (mii->mii_media_active & IFM_LOOP) + kprintf(" Loopback"); + if (mii->mii_media_active & IFM_FLAG0) + kprintf(" Flag0"); + if (mii->mii_media_active & IFM_FLAG1) + kprintf(" Flag1"); + if (mii->mii_media_active & IFM_FLAG2) + kprintf(" Flag2"); + kprintf(" )\n"); +#endif + + BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT); + + /* + * Set MII or GMII interface based on the speed negotiated + * by the PHY. + */ + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || + IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { + DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n"); + BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII); + } else { + DBPRINT(sc, BCE_INFO, "Setting MII interface.\n"); + BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII); + } + + /* + * Set half or full duplex based on the duplicity negotiated + * by the PHY. + */ + if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { + DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); + BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX); + } else { + DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); + BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX); + } +} + + +/****************************************************************************/ +/* Acquire NVRAM lock. */ +/* */ +/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ +/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ +/* for use by the driver. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_acquire_nvram_lock(struct bce_softc *sc) +{ + uint32_t val; + int j; + + DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n"); + + /* Request access to the flash interface. */ + REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + val = REG_RD(sc, BCE_NVM_SW_ARB); + if (val & BCE_NVM_SW_ARB_ARB_ARB2) + break; + + DELAY(5); + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); + return EBUSY; + } + return 0; +} + + +/****************************************************************************/ +/* Release NVRAM lock. */ +/* */ +/* When the caller is finished accessing NVRAM the lock must be released. */ +/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ +/* for use by the driver. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_release_nvram_lock(struct bce_softc *sc) +{ + int j; + uint32_t val; + + DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n"); + + /* + * Relinquish nvram interface. + */ + REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); + + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + val = REG_RD(sc, BCE_NVM_SW_ARB); + if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) + break; + + DELAY(5); + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n"); + return EBUSY; + } + return 0; +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Enable NVRAM write access. */ +/* */ +/* Before writing to NVRAM the caller must enable NVRAM writes. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_enable_nvram_write(struct bce_softc *sc) +{ + uint32_t val; + + DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n"); + + val = REG_RD(sc, BCE_MISC_CFG); + REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); + + if (!sc->bce_flash_info->buffered) { + int j; + + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + REG_WR(sc, BCE_NVM_COMMAND, + BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); + + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + DELAY(5); + + val = REG_RD(sc, BCE_NVM_COMMAND); + if (val & BCE_NVM_COMMAND_DONE) + break; + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); + return EBUSY; + } + } + return 0; +} + + +/****************************************************************************/ +/* Disable NVRAM write access. */ +/* */ +/* When the caller is finished writing to NVRAM write access must be */ +/* disabled. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_disable_nvram_write(struct bce_softc *sc) +{ + uint32_t val; + + DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n"); + + val = REG_RD(sc, BCE_MISC_CFG); + REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); +} +#endif /* BCE_NVRAM_WRITE_SUPPORT */ + + +/****************************************************************************/ +/* Enable NVRAM access. */ +/* */ +/* Before accessing NVRAM for read or write operations the caller must */ +/* enabled NVRAM access. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_enable_nvram_access(struct bce_softc *sc) +{ + uint32_t val; + + DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n"); + + val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); + /* Enable both bits, even on read. */ + REG_WR(sc, BCE_NVM_ACCESS_ENABLE, + val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); +} + + +/****************************************************************************/ +/* Disable NVRAM access. */ +/* */ +/* When the caller is finished accessing NVRAM access must be disabled. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_disable_nvram_access(struct bce_softc *sc) +{ + uint32_t val; + + DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n"); + + val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); + + /* Disable both bits, even after read. */ + REG_WR(sc, BCE_NVM_ACCESS_ENABLE, + val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Erase NVRAM page before writing. */ +/* */ +/* Non-buffered flash parts require that a page be erased before it is */ +/* written. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_erase_page(struct bce_softc *sc, uint32_t offset) +{ + uint32_t cmd; + int j; + + /* Buffered flash doesn't require an erase. */ + if (sc->bce_flash_info->buffered) + return 0; + + DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n"); + + /* Build an erase command. */ + cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | + BCE_NVM_COMMAND_DOIT; + + /* + * Clear the DONE bit separately, set the NVRAM adress to erase, + * and issue the erase command. + */ + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BCE_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + uint32_t val; + + DELAY(5); + + val = REG_RD(sc, BCE_NVM_COMMAND); + if (val & BCE_NVM_COMMAND_DONE) + break; + } + + if (j >= NVRAM_TIMEOUT_COUNT) { + DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); + return EBUSY; + } + return 0; +} +#endif /* BCE_NVRAM_WRITE_SUPPORT */ + + +/****************************************************************************/ +/* Read a dword (32 bits) from NVRAM. */ +/* */ +/* Read a 32 bit word from NVRAM. The caller is assumed to have already */ +/* obtained the NVRAM lock and enabled the controller for NVRAM access. */ +/* */ +/* Returns: */ +/* 0 on success and the 32 bit value read, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val, + uint32_t cmd_flags) +{ + uint32_t cmd; + int i, rc = 0; + + /* Build the command word. */ + cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; + + /* Calculate the offset for buffered flash. */ + if (sc->bce_flash_info->buffered) { + offset = ((offset / sc->bce_flash_info->page_size) << + sc->bce_flash_info->page_bits) + + (offset % sc->bce_flash_info->page_size); + } + + /* + * Clear the DONE bit separately, set the address to read, + * and issue the read. + */ + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BCE_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { + uint32_t val; + + DELAY(5); + + val = REG_RD(sc, BCE_NVM_COMMAND); + if (val & BCE_NVM_COMMAND_DONE) { + val = REG_RD(sc, BCE_NVM_READ); + + val = be32toh(val); + memcpy(ret_val, &val, 4); + break; + } + } + + /* Check for errors. */ + if (i >= NVRAM_TIMEOUT_COUNT) { + if_printf(&sc->arpcom.ac_if, + "Timeout error reading NVRAM at offset 0x%08X!\n", + offset); + rc = EBUSY; + } + return rc; +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Write a dword (32 bits) to NVRAM. */ +/* */ +/* Write a 32 bit word to NVRAM. The caller is assumed to have already */ +/* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ +/* enabled NVRAM write access. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_write_dword(struct bce_softc *sc, uint32_t offset, uint8_t *val, + uint32_t cmd_flags) +{ + uint32_t cmd, val32; + int j; + + /* Build the command word. */ + cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; + + /* Calculate the offset for buffered flash. */ + if (sc->bce_flash_info->buffered) { + offset = ((offset / sc->bce_flash_info->page_size) << + sc->bce_flash_info->page_bits) + + (offset % sc->bce_flash_info->page_size); + } + + /* + * Clear the DONE bit separately, convert NVRAM data to big-endian, + * set the NVRAM address to write, and issue the write command + */ + REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); + memcpy(&val32, val, 4); + val32 = htobe32(val32); + REG_WR(sc, BCE_NVM_WRITE, val32); + REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); + REG_WR(sc, BCE_NVM_COMMAND, cmd); + + /* Wait for completion. */ + for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { + DELAY(5); + + if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) + break; + } + if (j >= NVRAM_TIMEOUT_COUNT) { + if_printf(&sc->arpcom.ac_if, + "Timeout error writing NVRAM at offset 0x%08X\n", + offset); + return EBUSY; + } + return 0; +} +#endif /* BCE_NVRAM_WRITE_SUPPORT */ + + +/****************************************************************************/ +/* Initialize NVRAM access. */ +/* */ +/* Identify the NVRAM device in use and prepare the NVRAM interface to */ +/* access that device. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_init_nvram(struct bce_softc *sc) +{ + uint32_t val; + int j, entry_count, rc = 0; + const struct flash_spec *flash; + + DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__); + + /* Determine the selected interface. */ + val = REG_RD(sc, BCE_NVM_CFG1); + + entry_count = sizeof(flash_table) / sizeof(struct flash_spec); + + /* + * Flash reconfiguration is required to support additional + * NVRAM devices not directly supported in hardware. + * Check if the flash interface was reconfigured + * by the bootcode. + */ + + if (val & 0x40000000) { + /* Flash interface reconfigured by bootcode. */ + + DBPRINT(sc, BCE_INFO_LOAD, + "%s(): Flash WAS reconfigured.\n", __func__); + + for (j = 0, flash = flash_table; j < entry_count; + j++, flash++) { + if ((val & FLASH_BACKUP_STRAP_MASK) == + (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { + sc->bce_flash_info = flash; + break; + } + } + } else { + /* Flash interface not yet reconfigured. */ + uint32_t mask; + + DBPRINT(sc, BCE_INFO_LOAD, + "%s(): Flash was NOT reconfigured.\n", __func__); + + if (val & (1 << 23)) + mask = FLASH_BACKUP_STRAP_MASK; + else + mask = FLASH_STRAP_MASK; + + /* Look for the matching NVRAM device configuration data. */ + for (j = 0, flash = flash_table; j < entry_count; + j++, flash++) { + /* Check if the device matches any of the known devices. */ + if ((val & mask) == (flash->strapping & mask)) { + /* Found a device match. */ + sc->bce_flash_info = flash; + + /* Request access to the flash interface. */ + rc = bce_acquire_nvram_lock(sc); + if (rc != 0) + return rc; + + /* Reconfigure the flash interface. */ + bce_enable_nvram_access(sc); + REG_WR(sc, BCE_NVM_CFG1, flash->config1); + REG_WR(sc, BCE_NVM_CFG2, flash->config2); + REG_WR(sc, BCE_NVM_CFG3, flash->config3); + REG_WR(sc, BCE_NVM_WRITE1, flash->write1); + bce_disable_nvram_access(sc); + bce_release_nvram_lock(sc); + break; + } + } + } + + /* Check if a matching device was found. */ + if (j == entry_count) { + sc->bce_flash_info = NULL; + if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n"); + rc = ENODEV; + } + + /* Write the flash config data to the shared memory interface. */ + val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) & + BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; + if (val) + sc->bce_flash_size = val; + else + sc->bce_flash_size = sc->bce_flash_info->total_size; + + DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n", + __func__, sc->bce_flash_info->total_size); + + DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__); + + return rc; +} + + +/****************************************************************************/ +/* Read an arbitrary range of data from NVRAM. */ +/* */ +/* Prepares the NVRAM interface for access and reads the requested data */ +/* into the supplied buffer. */ +/* */ +/* Returns: */ +/* 0 on success and the data read, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf, + int buf_size) +{ + uint32_t cmd_flags, offset32, len32, extra; + int rc = 0; + + if (buf_size == 0) + return 0; + + /* Request access to the flash interface. */ + rc = bce_acquire_nvram_lock(sc); + if (rc != 0) + return rc; + + /* Enable access to flash interface */ + bce_enable_nvram_access(sc); + + len32 = buf_size; + offset32 = offset; + extra = 0; + + cmd_flags = 0; + + /* XXX should we release nvram lock if read_dword() fails? */ + if (offset32 & 3) { + uint8_t buf[4]; + uint32_t pre_len; + + offset32 &= ~3; + pre_len = 4 - (offset & 3); + + if (pre_len >= len32) { + pre_len = len32; + cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; + } else { + cmd_flags = BCE_NVM_COMMAND_FIRST; + } + + rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); + if (rc) + return rc; + + memcpy(ret_buf, buf + (offset & 3), pre_len); + + offset32 += 4; + ret_buf += pre_len; + len32 -= pre_len; + } + + if (len32 & 3) { + extra = 4 - (len32 & 3); + len32 = (len32 + 4) & ~3; + } + + if (len32 == 4) { + uint8_t buf[4]; + + if (cmd_flags) + cmd_flags = BCE_NVM_COMMAND_LAST; + else + cmd_flags = BCE_NVM_COMMAND_FIRST | + BCE_NVM_COMMAND_LAST; + + rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); + + memcpy(ret_buf, buf, 4 - extra); + } else if (len32 > 0) { + uint8_t buf[4]; + + /* Read the first word. */ + if (cmd_flags) + cmd_flags = 0; + else + cmd_flags = BCE_NVM_COMMAND_FIRST; + + rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); + + /* Advance to the next dword. */ + offset32 += 4; + ret_buf += 4; + len32 -= 4; + + while (len32 > 4 && rc == 0) { + rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); + + /* Advance to the next dword. */ + offset32 += 4; + ret_buf += 4; + len32 -= 4; + } + + if (rc) + return rc; + + cmd_flags = BCE_NVM_COMMAND_LAST; + rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); + + memcpy(ret_buf, buf, 4 - extra); + } + + /* Disable access to flash interface and release the lock. */ + bce_disable_nvram_access(sc); + bce_release_nvram_lock(sc); + + return rc; +} + + +#ifdef BCE_NVRAM_WRITE_SUPPORT +/****************************************************************************/ +/* Write an arbitrary range of data from NVRAM. */ +/* */ +/* Prepares the NVRAM interface for write access and writes the requested */ +/* data from the supplied buffer. The caller is responsible for */ +/* calculating any appropriate CRCs. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_write(struct bce_softc *sc, uint32_t offset, uint8_t *data_buf, + int buf_size) +{ + uint32_t written, offset32, len32; + uint8_t *buf, start[4], end[4]; + int rc = 0; + int align_start, align_end; + + buf = data_buf; + offset32 = offset; + len32 = buf_size; + align_end = 0; + align_start = (offset32 & 3); + + if (align_start) { + offset32 &= ~3; + len32 += align_start; + rc = bce_nvram_read(sc, offset32, start, 4); + if (rc) + return rc; + } + + if (len32 & 3) { + if (len32 > 4 || !align_start) { + align_end = 4 - (len32 & 3); + len32 += align_end; + rc = bce_nvram_read(sc, offset32 + len32 - 4, end, 4); + if (rc) + return rc; + } + } + + if (align_start || align_end) { + buf = kmalloc(len32, M_DEVBUF, M_NOWAIT); + if (buf == NULL) + return ENOMEM; + if (align_start) + memcpy(buf, start, 4); + if (align_end) + memcpy(buf + len32 - 4, end, 4); + memcpy(buf + align_start, data_buf, buf_size); + } + + written = 0; + while (written < len32 && rc == 0) { + uint32_t page_start, page_end, data_start, data_end; + uint32_t addr, cmd_flags; + int i; + uint8_t flash_buffer[264]; + + /* Find the page_start addr */ + page_start = offset32 + written; + page_start -= (page_start % sc->bce_flash_info->page_size); + /* Find the page_end addr */ + page_end = page_start + sc->bce_flash_info->page_size; + /* Find the data_start addr */ + data_start = (written == 0) ? offset32 : page_start; + /* Find the data_end addr */ + data_end = (page_end > offset32 + len32) ? (offset32 + len32) + : page_end; + + /* Request access to the flash interface. */ + rc = bce_acquire_nvram_lock(sc); + if (rc != 0) + goto nvram_write_end; + + /* Enable access to flash interface */ + bce_enable_nvram_access(sc); + + cmd_flags = BCE_NVM_COMMAND_FIRST; + if (sc->bce_flash_info->buffered == 0) { + int j; + + /* + * Read the whole page into the buffer + * (non-buffer flash only) + */ + for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { + if (j == (sc->bce_flash_info->page_size - 4)) + cmd_flags |= BCE_NVM_COMMAND_LAST; + + rc = bce_nvram_read_dword(sc, page_start + j, + &flash_buffer[j], + cmd_flags); + if (rc) + goto nvram_write_end; + + cmd_flags = 0; + } + } + + /* Enable writes to flash interface (unlock write-protect) */ + rc = bce_enable_nvram_write(sc); + if (rc != 0) + goto nvram_write_end; + + /* Erase the page */ + rc = bce_nvram_erase_page(sc, page_start); + if (rc != 0) + goto nvram_write_end; + + /* Re-enable the write again for the actual write */ + bce_enable_nvram_write(sc); + + /* Loop to write back the buffer data from page_start to + * data_start */ + i = 0; + if (sc->bce_flash_info->buffered == 0) { + for (addr = page_start; addr < data_start; + addr += 4, i += 4) { + rc = bce_nvram_write_dword(sc, addr, + &flash_buffer[i], + cmd_flags); + if (rc != 0) + goto nvram_write_end; + + cmd_flags = 0; + } + } + + /* Loop to write the new data from data_start to data_end */ + for (addr = data_start; addr < data_end; addr += 4, i++) { + if (addr == page_end - 4 || + (sc->bce_flash_info->buffered && + addr == data_end - 4)) + cmd_flags |= BCE_NVM_COMMAND_LAST; + + rc = bce_nvram_write_dword(sc, addr, buf, cmd_flags); + if (rc != 0) + goto nvram_write_end; + + cmd_flags = 0; + buf += 4; + } + + /* Loop to write back the buffer data from data_end + * to page_end */ + if (sc->bce_flash_info->buffered == 0) { + for (addr = data_end; addr < page_end; + addr += 4, i += 4) { + if (addr == page_end-4) + cmd_flags = BCE_NVM_COMMAND_LAST; + + rc = bce_nvram_write_dword(sc, addr, + &flash_buffer[i], cmd_flags); + if (rc != 0) + goto nvram_write_end; + + cmd_flags = 0; + } + } + + /* Disable writes to flash interface (lock write-protect) */ + bce_disable_nvram_write(sc); + + /* Disable access to flash interface */ + bce_disable_nvram_access(sc); + bce_release_nvram_lock(sc); + + /* Increment written */ + written += data_end - data_start; + } + +nvram_write_end: + if (align_start || align_end) + kfree(buf, M_DEVBUF); + return rc; +} +#endif /* BCE_NVRAM_WRITE_SUPPORT */ + + +/****************************************************************************/ +/* Verifies that NVRAM is accessible and contains valid data. */ +/* */ +/* Reads the configuration data from NVRAM and verifies that the CRC is */ +/* correct. */ +/* */ +/* Returns: */ +/* 0 on success, positive value on failure. */ +/****************************************************************************/ +static int +bce_nvram_test(struct bce_softc *sc) +{ + uint32_t buf[BCE_NVRAM_SIZE / 4]; + uint32_t magic, csum; + uint8_t *data = (uint8_t *)buf; + int rc = 0; + + /* + * Check that the device NVRAM is valid by reading + * the magic value at offset 0. + */ + rc = bce_nvram_read(sc, 0, data, 4); + if (rc != 0) + return rc; + + magic = be32toh(buf[0]); + if (magic != BCE_NVRAM_MAGIC) { + if_printf(&sc->arpcom.ac_if, + "Invalid NVRAM magic value! Expected: 0x%08X, " + "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic); + return ENODEV; + } + + /* + * Verify that the device NVRAM includes valid + * configuration data. + */ + rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE); + if (rc != 0) + return rc; + + csum = ether_crc32_le(data, 0x100); + if (csum != BCE_CRC32_RESIDUAL) { + if_printf(&sc->arpcom.ac_if, + "Invalid Manufacturing Information NVRAM CRC! " + "Expected: 0x%08X, Found: 0x%08X\n", + BCE_CRC32_RESIDUAL, csum); + return ENODEV; + } + + csum = ether_crc32_le(data + 0x100, 0x100); + if (csum != BCE_CRC32_RESIDUAL) { + if_printf(&sc->arpcom.ac_if, + "Invalid Feature Configuration Information " + "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", + BCE_CRC32_RESIDUAL, csum); + rc = ENODEV; + } + return rc; +} + + +/****************************************************************************/ +/* Free any DMA memory owned by the driver. */ +/* */ +/* Scans through each data structre that requires DMA memory and frees */ +/* the memory if allocated. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dma_free(struct bce_softc *sc) +{ + int i; + + /* Destroy the status block. */ + if (sc->status_tag != NULL) { + if (sc->status_block != NULL) { + bus_dmamap_unload(sc->status_tag, sc->status_map); + bus_dmamem_free(sc->status_tag, sc->status_block, + sc->status_map); + } + bus_dma_tag_destroy(sc->status_tag); + } + + + /* Destroy the statistics block. */ + if (sc->stats_tag != NULL) { + if (sc->stats_block != NULL) { + bus_dmamap_unload(sc->stats_tag, sc->stats_map); + bus_dmamem_free(sc->stats_tag, sc->stats_block, + sc->stats_map); + } + bus_dma_tag_destroy(sc->stats_tag); + } + + /* Destroy the TX buffer descriptor DMA stuffs. */ + if (sc->tx_bd_chain_tag != NULL) { + for (i = 0; i < TX_PAGES; i++) { + if (sc->tx_bd_chain[i] != NULL) { + bus_dmamap_unload(sc->tx_bd_chain_tag, + sc->tx_bd_chain_map[i]); + bus_dmamem_free(sc->tx_bd_chain_tag, + sc->tx_bd_chain[i], + sc->tx_bd_chain_map[i]); + } + } + bus_dma_tag_destroy(sc->tx_bd_chain_tag); + } + + /* Destroy the RX buffer descriptor DMA stuffs. */ + if (sc->rx_bd_chain_tag != NULL) { + for (i = 0; i < RX_PAGES; i++) { + if (sc->rx_bd_chain[i] != NULL) { + bus_dmamap_unload(sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i]); + bus_dmamem_free(sc->rx_bd_chain_tag, + sc->rx_bd_chain[i], + sc->rx_bd_chain_map[i]); + } + } + bus_dma_tag_destroy(sc->rx_bd_chain_tag); + } + + /* Destroy the TX mbuf DMA stuffs. */ + if (sc->tx_mbuf_tag != NULL) { + for (i = 0; i < TOTAL_TX_BD; i++) { + /* Must have been unloaded in bce_stop() */ + KKASSERT(sc->tx_mbuf_ptr[i] == NULL); + bus_dmamap_destroy(sc->tx_mbuf_tag, + sc->tx_mbuf_map[i]); + } + bus_dma_tag_destroy(sc->tx_mbuf_tag); + } + + /* Destroy the RX mbuf DMA stuffs. */ + if (sc->rx_mbuf_tag != NULL) { + for (i = 0; i < TOTAL_RX_BD; i++) { + /* Must have been unloaded in bce_stop() */ + KKASSERT(sc->rx_mbuf_ptr[i] == NULL); + bus_dmamap_destroy(sc->rx_mbuf_tag, + sc->rx_mbuf_map[i]); + } + bus_dma_tag_destroy(sc->rx_mbuf_tag); + } + + /* Destroy the parent tag */ + if (sc->parent_tag != NULL) + bus_dma_tag_destroy(sc->parent_tag); +} + + +/****************************************************************************/ +/* Get DMA memory from the OS. */ +/* */ +/* Validates that the OS has provided DMA buffers in response to a */ +/* bus_dmamap_load() call and saves the physical address of those buffers. */ +/* When the callback is used the OS will return 0 for the mapping function */ +/* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ +/* failures back to the caller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + bus_addr_t *busaddr = arg; + + /* + * Simulate a mapping failure. + * XXX not correct. + */ + DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure), + kprintf("bce: %s(%d): Simulating DMA mapping error.\n", + __FILE__, __LINE__); + error = ENOMEM); + + /* Check for an error and signal the caller that an error occurred. */ + if (error) + return; + + KASSERT(nseg == 1, ("only one segment is allowed\n")); + *busaddr = segs->ds_addr; +} + + +static void +bce_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs, + bus_size_t mapsz __unused, int error) +{ + struct bce_dmamap_arg *ctx = arg; + int i; + + if (error) + return; + + if (nsegs > ctx->bce_maxsegs) { + ctx->bce_maxsegs = 0; + return; + } + + ctx->bce_maxsegs = nsegs; + for (i = 0; i < nsegs; ++i) + ctx->bce_segs[i] = segs[i]; +} + + +/****************************************************************************/ +/* Allocate any DMA memory needed by the driver. */ +/* */ +/* Allocates DMA memory needed for the various global structures needed by */ +/* hardware. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_dma_alloc(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + int i, j, rc = 0; + bus_addr_t busaddr; + + /* + * Allocate the parent bus DMA tag appropriate for PCI. + */ + rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, + MAXBSIZE, BUS_SPACE_UNRESTRICTED, + BUS_SPACE_MAXSIZE_32BIT, + 0, &sc->parent_tag); + if (rc != 0) { + if_printf(ifp, "Could not allocate parent DMA tag!\n"); + return rc; + } + + /* + * Create a DMA tag for the status block, allocate and clear the + * memory, map the memory into DMA space, and fetch the physical + * address of the block. + */ + rc = bus_dma_tag_create(sc->parent_tag, + BCE_DMA_ALIGN, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, + BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, + 0, &sc->status_tag); + if (rc != 0) { + if_printf(ifp, "Could not allocate status block DMA tag!\n"); + return rc; + } + + rc = bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, + BUS_DMA_WAITOK | BUS_DMA_ZERO, + &sc->status_map); + if (rc != 0) { + if_printf(ifp, "Could not allocate status block DMA memory!\n"); + return rc; + } + + rc = bus_dmamap_load(sc->status_tag, sc->status_map, + sc->status_block, BCE_STATUS_BLK_SZ, + bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK); + if (rc != 0) { + if_printf(ifp, "Could not map status block DMA memory!\n"); + bus_dmamem_free(sc->status_tag, sc->status_block, + sc->status_map); + sc->status_block = NULL; + return rc; + } + + sc->status_block_paddr = busaddr; + /* DRC - Fix for 64 bit addresses. */ + DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n", + (uint32_t)sc->status_block_paddr); + + /* + * Create a DMA tag for the statistics block, allocate and clear the + * memory, map the memory into DMA space, and fetch the physical + * address of the block. + */ + rc = bus_dma_tag_create(sc->parent_tag, + BCE_DMA_ALIGN, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, + BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, + 0, &sc->stats_tag); + if (rc != 0) { + if_printf(ifp, "Could not allocate " + "statistics block DMA tag!\n"); + return rc; + } + + rc = bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, + BUS_DMA_WAITOK | BUS_DMA_ZERO, + &sc->stats_map); + if (rc != 0) { + if_printf(ifp, "Could not allocate " + "statistics block DMA memory!\n"); + return rc; + } + + rc = bus_dmamap_load(sc->stats_tag, sc->stats_map, + sc->stats_block, BCE_STATS_BLK_SZ, + bce_dma_map_addr, &busaddr, BUS_DMA_WAITOK); + if (rc != 0) { + if_printf(ifp, "Could not map statistics block DMA memory!\n"); + bus_dmamem_free(sc->stats_tag, sc->stats_block, sc->stats_map); + sc->stats_block = NULL; + return rc; + } + + sc->stats_block_paddr = busaddr; + /* DRC - Fix for 64 bit address. */ + DBPRINT(sc, BCE_INFO, "stats_block_paddr = 0x%08X\n", + (uint32_t)sc->stats_block_paddr); + + /* + * Create a DMA tag for the TX buffer descriptor chain, + * allocate and clear the memory, and fetch the + * physical address of the block. + */ + rc = bus_dma_tag_create(sc->parent_tag, + BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, + BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, + 0, &sc->tx_bd_chain_tag); + if (rc != 0) { + if_printf(ifp, "Could not allocate " + "TX descriptor chain DMA tag!\n"); + return rc; + } + + for (i = 0; i < TX_PAGES; i++) { + rc = bus_dmamem_alloc(sc->tx_bd_chain_tag, + (void **)&sc->tx_bd_chain[i], + BUS_DMA_WAITOK, &sc->tx_bd_chain_map[i]); + if (rc != 0) { + if_printf(ifp, "Could not allocate %dth TX descriptor " + "chain DMA memory!\n", i); + return rc; + } + + rc = bus_dmamap_load(sc->tx_bd_chain_tag, + sc->tx_bd_chain_map[i], + sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ, + bce_dma_map_addr, &busaddr, + BUS_DMA_WAITOK); + if (rc != 0) { + if_printf(ifp, "Could not map %dth TX descriptor " + "chain DMA memory!\n", i); + bus_dmamem_free(sc->tx_bd_chain_tag, + sc->tx_bd_chain[i], + sc->tx_bd_chain_map[i]); + sc->tx_bd_chain[i] = NULL; + return rc; + } + + sc->tx_bd_chain_paddr[i] = busaddr; + /* DRC - Fix for 64 bit systems. */ + DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", + i, (uint32_t)sc->tx_bd_chain_paddr[i]); + } + + /* Create a DMA tag for TX mbufs. */ + rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, + MCLBYTES * BCE_MAX_SEGMENTS, + BCE_MAX_SEGMENTS, MCLBYTES, + 0, &sc->tx_mbuf_tag); + if (rc != 0) { + if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n"); + return rc; + } + + /* Create DMA maps for the TX mbufs clusters. */ + for (i = 0; i < TOTAL_TX_BD; i++) { + rc = bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_WAITOK, + &sc->tx_mbuf_map[i]); + if (rc != 0) { + for (j = 0; j < i; ++j) { + bus_dmamap_destroy(sc->tx_mbuf_tag, + sc->tx_mbuf_map[i]); + } + bus_dma_tag_destroy(sc->tx_mbuf_tag); + sc->tx_mbuf_tag = NULL; + + if_printf(ifp, "Unable to create " + "%dth TX mbuf DMA map!\n", i); + return rc; + } + } + + /* + * Create a DMA tag for the RX buffer descriptor chain, + * allocate and clear the memory, and fetch the physical + * address of the blocks. + */ + rc = bus_dma_tag_create(sc->parent_tag, + BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, + BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, + 0, &sc->rx_bd_chain_tag); + if (rc != 0) { + if_printf(ifp, "Could not allocate " + "RX descriptor chain DMA tag!\n"); + return rc; + } + + for (i = 0; i < RX_PAGES; i++) { + rc = bus_dmamem_alloc(sc->rx_bd_chain_tag, + (void **)&sc->rx_bd_chain[i], + BUS_DMA_WAITOK | BUS_DMA_ZERO, + &sc->rx_bd_chain_map[i]); + if (rc != 0) { + if_printf(ifp, "Could not allocate %dth RX descriptor " + "chain DMA memory!\n", i); + return rc; + } + + rc = bus_dmamap_load(sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i], + sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ, + bce_dma_map_addr, &busaddr, + BUS_DMA_WAITOK); + if (rc != 0) { + if_printf(ifp, "Could not map %dth RX descriptor " + "chain DMA memory!\n", i); + bus_dmamem_free(sc->rx_bd_chain_tag, + sc->rx_bd_chain[i], + sc->rx_bd_chain_map[i]); + sc->rx_bd_chain[i] = NULL; + return rc; + } + + sc->rx_bd_chain_paddr[i] = busaddr; + /* DRC - Fix for 64 bit systems. */ + DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", + i, (uint32_t)sc->rx_bd_chain_paddr[i]); + } + + /* Create a DMA tag for RX mbufs. */ + rc = bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, + sc->max_bus_addr, BUS_SPACE_MAXADDR, + NULL, NULL, + MCLBYTES, 1/* BCE_MAX_SEGMENTS */, MCLBYTES, + 0, &sc->rx_mbuf_tag); + if (rc != 0) { + if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n"); + return rc; + } + + /* Create DMA maps for the RX mbuf clusters. */ + for (i = 0; i < TOTAL_RX_BD; i++) { + rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK, + &sc->rx_mbuf_map[i]); + if (rc != 0) { + for (j = 0; j < i; ++j) { + bus_dmamap_destroy(sc->rx_mbuf_tag, + sc->rx_mbuf_map[j]); + } + bus_dma_tag_destroy(sc->rx_mbuf_tag); + sc->rx_mbuf_tag = NULL; + + if_printf(ifp, "Unable to create " + "%dth RX mbuf DMA map!\n", i); + return rc; + } + } + return 0; +} + + +/****************************************************************************/ +/* Firmware synchronization. */ +/* */ +/* Before performing certain events such as a chip reset, synchronize with */ +/* the firmware first. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_fw_sync(struct bce_softc *sc, uint32_t msg_data) +{ + int i, rc = 0; + uint32_t val; + + /* Don't waste any time if we've timed out before. */ + if (sc->bce_fw_timed_out) + return EBUSY; + + /* Increment the message sequence number. */ + sc->bce_fw_wr_seq++; + msg_data |= sc->bce_fw_wr_seq; + + DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data); + + /* Send the message to the bootcode driver mailbox. */ + REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); + + /* Wait for the bootcode to acknowledge the message. */ + for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { + /* Check for a response in the bootcode firmware mailbox. */ + val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); + if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) + break; + DELAY(1000); + } + + /* If we've timed out, tell the bootcode that we've stopped waiting. */ + if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) && + (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) { + if_printf(&sc->arpcom.ac_if, + "Firmware synchronization timeout! " + "msg_data = 0x%08X\n", msg_data); + + msg_data &= ~BCE_DRV_MSG_CODE; + msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; + + REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); + + sc->bce_fw_timed_out = 1; + rc = EBUSY; + } + return rc; +} + + +/****************************************************************************/ +/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code, + uint32_t rv2p_code_len, uint32_t rv2p_proc) +{ + int i; + uint32_t val; + + for (i = 0; i < rv2p_code_len; i += 8) { + REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); + rv2p_code++; + REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); + rv2p_code++; + + if (rv2p_proc == RV2P_PROC1) { + val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; + REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); + } else { + val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; + REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); + } + } + + /* Reset the processor, un-stall is done later. */ + if (rv2p_proc == RV2P_PROC1) + REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); + else + REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); +} + + +/****************************************************************************/ +/* Load RISC processor firmware. */ +/* */ +/* Loads firmware from the file if_bcefw.h into the scratchpad memory */ +/* associated with a particular processor. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, + struct fw_info *fw) +{ + uint32_t offset, val; + int j; + + /* Halt the CPU. */ + val = REG_RD_IND(sc, cpu_reg->mode); + val |= cpu_reg->mode_value_halt; + REG_WR_IND(sc, cpu_reg->mode, val); + REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); + + /* Load the Text area. */ + offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); + if (fw->text) { + for (j = 0; j < (fw->text_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->text[j]); + } + + /* Load the Data area. */ + offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); + if (fw->data) { + for (j = 0; j < (fw->data_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->data[j]); + } + + /* Load the SBSS area. */ + offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); + if (fw->sbss) { + for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->sbss[j]); + } + + /* Load the BSS area. */ + offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); + if (fw->bss) { + for (j = 0; j < (fw->bss_len/4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->bss[j]); + } + + /* Load the Read-Only area. */ + offset = cpu_reg->spad_base + + (fw->rodata_addr - cpu_reg->mips_view_base); + if (fw->rodata) { + for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) + REG_WR_IND(sc, offset, fw->rodata[j]); + } + + /* Clear the pre-fetch instruction. */ + REG_WR_IND(sc, cpu_reg->inst, 0); + REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); + + /* Start the CPU. */ + val = REG_RD_IND(sc, cpu_reg->mode); + val &= ~cpu_reg->mode_value_halt; + REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); + REG_WR_IND(sc, cpu_reg->mode, val); +} + + +/****************************************************************************/ +/* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ +/* */ +/* Loads the firmware for each CPU and starts the CPU. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_cpus(struct bce_softc *sc) +{ + struct cpu_reg cpu_reg; + struct fw_info fw; + + /* Initialize the RV2P processor. */ + bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1); + bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2); + + /* Initialize the RX Processor. */ + cpu_reg.mode = BCE_RXP_CPU_MODE; + cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_RXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; + cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; + cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; + cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_RXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bce_RXP_b06FwReleaseMajor; + fw.ver_minor = bce_RXP_b06FwReleaseMinor; + fw.ver_fix = bce_RXP_b06FwReleaseFix; + fw.start_addr = bce_RXP_b06FwStartAddr; + + fw.text_addr = bce_RXP_b06FwTextAddr; + fw.text_len = bce_RXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_RXP_b06FwText; + + fw.data_addr = bce_RXP_b06FwDataAddr; + fw.data_len = bce_RXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_RXP_b06FwData; + + fw.sbss_addr = bce_RXP_b06FwSbssAddr; + fw.sbss_len = bce_RXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_RXP_b06FwSbss; + + fw.bss_addr = bce_RXP_b06FwBssAddr; + fw.bss_len = bce_RXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_RXP_b06FwBss; + + fw.rodata_addr = bce_RXP_b06FwRodataAddr; + fw.rodata_len = bce_RXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_RXP_b06FwRodata; + + DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + + /* Initialize the TX Processor. */ + cpu_reg.mode = BCE_TXP_CPU_MODE; + cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_TXP_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; + cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; + cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; + cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_TXP_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bce_TXP_b06FwReleaseMajor; + fw.ver_minor = bce_TXP_b06FwReleaseMinor; + fw.ver_fix = bce_TXP_b06FwReleaseFix; + fw.start_addr = bce_TXP_b06FwStartAddr; + + fw.text_addr = bce_TXP_b06FwTextAddr; + fw.text_len = bce_TXP_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_TXP_b06FwText; + + fw.data_addr = bce_TXP_b06FwDataAddr; + fw.data_len = bce_TXP_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_TXP_b06FwData; + + fw.sbss_addr = bce_TXP_b06FwSbssAddr; + fw.sbss_len = bce_TXP_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_TXP_b06FwSbss; + + fw.bss_addr = bce_TXP_b06FwBssAddr; + fw.bss_len = bce_TXP_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_TXP_b06FwBss; + + fw.rodata_addr = bce_TXP_b06FwRodataAddr; + fw.rodata_len = bce_TXP_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_TXP_b06FwRodata; + + DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + + /* Initialize the TX Patch-up Processor. */ + cpu_reg.mode = BCE_TPAT_CPU_MODE; + cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_TPAT_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; + cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; + cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; + cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_TPAT_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bce_TPAT_b06FwReleaseMajor; + fw.ver_minor = bce_TPAT_b06FwReleaseMinor; + fw.ver_fix = bce_TPAT_b06FwReleaseFix; + fw.start_addr = bce_TPAT_b06FwStartAddr; + + fw.text_addr = bce_TPAT_b06FwTextAddr; + fw.text_len = bce_TPAT_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_TPAT_b06FwText; + + fw.data_addr = bce_TPAT_b06FwDataAddr; + fw.data_len = bce_TPAT_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_TPAT_b06FwData; + + fw.sbss_addr = bce_TPAT_b06FwSbssAddr; + fw.sbss_len = bce_TPAT_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_TPAT_b06FwSbss; + + fw.bss_addr = bce_TPAT_b06FwBssAddr; + fw.bss_len = bce_TPAT_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_TPAT_b06FwBss; + + fw.rodata_addr = bce_TPAT_b06FwRodataAddr; + fw.rodata_len = bce_TPAT_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_TPAT_b06FwRodata; + + DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); + + /* Initialize the Completion Processor. */ + cpu_reg.mode = BCE_COM_CPU_MODE; + cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; + cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; + cpu_reg.state = BCE_COM_CPU_STATE; + cpu_reg.state_value_clear = 0xffffff; + cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; + cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; + cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; + cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; + cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; + cpu_reg.spad_base = BCE_COM_SCRATCH; + cpu_reg.mips_view_base = 0x8000000; + + fw.ver_major = bce_COM_b06FwReleaseMajor; + fw.ver_minor = bce_COM_b06FwReleaseMinor; + fw.ver_fix = bce_COM_b06FwReleaseFix; + fw.start_addr = bce_COM_b06FwStartAddr; + + fw.text_addr = bce_COM_b06FwTextAddr; + fw.text_len = bce_COM_b06FwTextLen; + fw.text_index = 0; + fw.text = bce_COM_b06FwText; + + fw.data_addr = bce_COM_b06FwDataAddr; + fw.data_len = bce_COM_b06FwDataLen; + fw.data_index = 0; + fw.data = bce_COM_b06FwData; + + fw.sbss_addr = bce_COM_b06FwSbssAddr; + fw.sbss_len = bce_COM_b06FwSbssLen; + fw.sbss_index = 0; + fw.sbss = bce_COM_b06FwSbss; + + fw.bss_addr = bce_COM_b06FwBssAddr; + fw.bss_len = bce_COM_b06FwBssLen; + fw.bss_index = 0; + fw.bss = bce_COM_b06FwBss; + + fw.rodata_addr = bce_COM_b06FwRodataAddr; + fw.rodata_len = bce_COM_b06FwRodataLen; + fw.rodata_index = 0; + fw.rodata = bce_COM_b06FwRodata; + + DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); + bce_load_cpu_fw(sc, &cpu_reg, &fw); +} + + +/****************************************************************************/ +/* Initialize context memory. */ +/* */ +/* Clears the memory associated with each Context ID (CID). */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init_context(struct bce_softc *sc) +{ + uint32_t vcid; + + vcid = 96; + while (vcid) { + uint32_t vcid_addr, pcid_addr, offset; + + vcid--; + + vcid_addr = GET_CID_ADDR(vcid); + pcid_addr = vcid_addr; + + REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00); + REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); + + /* Zero out the context. */ + for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) + CTX_WR(sc, 0x00, offset, 0); + + REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); + REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); + } +} + + +/****************************************************************************/ +/* Fetch the permanent MAC address of the controller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_get_mac_addr(struct bce_softc *sc) +{ + uint32_t mac_lo = 0, mac_hi = 0; + + /* + * The NetXtreme II bootcode populates various NIC + * power-on and runtime configuration items in a + * shared memory area. The factory configured MAC + * address is available from both NVRAM and the + * shared memory area so we'll read the value from + * shared memory for speed. + */ + + mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER); + mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER); + + if (mac_lo == 0 && mac_hi == 0) { + if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n"); + } else { + sc->eaddr[0] = (u_char)(mac_hi >> 8); + sc->eaddr[1] = (u_char)(mac_hi >> 0); + sc->eaddr[2] = (u_char)(mac_lo >> 24); + sc->eaddr[3] = (u_char)(mac_lo >> 16); + sc->eaddr[4] = (u_char)(mac_lo >> 8); + sc->eaddr[5] = (u_char)(mac_lo >> 0); + } + + DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); +} + + +/****************************************************************************/ +/* Program the MAC address. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_set_mac_addr(struct bce_softc *sc) +{ + const uint8_t *mac_addr = sc->eaddr; + uint32_t val; + + DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n", + sc->eaddr, ":"); + + val = (mac_addr[0] << 8) | mac_addr[1]; + REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); + + val = (mac_addr[2] << 24) | + (mac_addr[3] << 16) | + (mac_addr[4] << 8) | + mac_addr[5]; + REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); +} + + +/****************************************************************************/ +/* Stop the controller. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_stop(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mii_data *mii = device_get_softc(sc->bce_miibus); + struct ifmedia_entry *ifm; + int mtmp, itmp; + + ASSERT_SERIALIZED(ifp->if_serializer); + + callout_stop(&sc->bce_stat_ch); + + /* Disable the transmit/receive blocks. */ + REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff); + REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); + DELAY(20); + + bce_disable_intr(sc); + + /* Tell firmware that the driver is going away. */ + bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL); + + /* Free the RX lists. */ + bce_free_rx_chain(sc); + + /* Free TX buffers. */ + bce_free_tx_chain(sc); + + /* + * Isolate/power down the PHY, but leave the media selection + * unchanged so that things will be put back to normal when + * we bring the interface back up. + */ + itmp = ifp->if_flags; + ifp->if_flags |= IFF_UP; + ifm = mii->mii_media.ifm_cur; + mtmp = ifm->ifm_media; + ifm->ifm_media = IFM_ETHER | IFM_NONE; + mii_mediachg(mii); + ifm->ifm_media = mtmp; + ifp->if_flags = itmp; + + sc->bce_link = 0; + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + ifp->if_timer = 0; + + bce_mgmt_init(sc); +} + + +static int +bce_reset(struct bce_softc *sc, uint32_t reset_code) +{ + uint32_t val; + int i, rc = 0; + + /* Wait for pending PCI transactions to complete. */ + REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, + BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | + BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | + BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | + BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); + val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); + DELAY(5); + + /* Assume bootcode is running. */ + sc->bce_fw_timed_out = 0; + + /* Give the firmware a chance to prepare for the reset. */ + rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); + if (rc) { + if_printf(&sc->arpcom.ac_if, + "Firmware is not ready for reset\n"); + return rc; + } + + /* Set a firmware reminder that this is a soft reset. */ + REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, + BCE_DRV_RESET_SIGNATURE_MAGIC); + + /* Dummy read to force the chip to complete all current transactions. */ + val = REG_RD(sc, BCE_MISC_ID); + + /* Chip reset. */ + val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | + BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; + REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); + + /* Allow up to 30us for reset to complete. */ + for (i = 0; i < 10; i++) { + val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); + if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { + break; + } + DELAY(10); + } + + /* Check that reset completed successfully. */ + if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | + BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { + if_printf(&sc->arpcom.ac_if, "Reset failed!\n"); + return EBUSY; + } + + /* Make sure byte swapping is properly configured. */ + val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); + if (val != 0x01020304) { + if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n"); + return ENODEV; + } + + /* Just completed a reset, assume that firmware is running again. */ + sc->bce_fw_timed_out = 0; + + /* Wait for the firmware to finish its initialization. */ + rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); + if (rc) { + if_printf(&sc->arpcom.ac_if, + "Firmware did not complete initialization!\n"); + } + return rc; +} + + +static int +bce_chipinit(struct bce_softc *sc) +{ + uint32_t val; + int rc = 0; + + /* Make sure the interrupt is not active. */ + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); + + /* + * Initialize DMA byte/word swapping, configure the number of DMA + * channels and PCI clock compensation delay. + */ + val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | + BCE_DMA_CONFIG_DATA_WORD_SWAP | +#if BYTE_ORDER == BIG_ENDIAN + BCE_DMA_CONFIG_CNTL_BYTE_SWAP | +#endif + BCE_DMA_CONFIG_CNTL_WORD_SWAP | + DMA_READ_CHANS << 12 | + DMA_WRITE_CHANS << 16; + + val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; + + if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133) + val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; + + /* + * This setting resolves a problem observed on certain Intel PCI + * chipsets that cannot handle multiple outstanding DMA operations. + * See errata E9_5706A1_65. + */ + if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 && + BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 && + !(sc->bce_flags & BCE_PCIX_FLAG)) + val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; + + REG_WR(sc, BCE_DMA_CONFIG, val); + + /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ + if (sc->bce_flags & BCE_PCIX_FLAG) { + uint16_t cmd; + + cmd = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2); + pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, cmd & ~0x2, 2); + } + + /* Enable the RX_V2P and Context state machines before access. */ + REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, + BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | + BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | + BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); + + /* Initialize context mapping and zero out the quick contexts. */ + bce_init_context(sc); + + /* Initialize the on-boards CPUs */ + bce_init_cpus(sc); + + /* Prepare NVRAM for access. */ + rc = bce_init_nvram(sc); + if (rc != 0) + return rc; + + /* Set the kernel bypass block size */ + val = REG_RD(sc, BCE_MQ_CONFIG); + val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; + val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; + REG_WR(sc, BCE_MQ_CONFIG, val); + + val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); + REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); + REG_WR(sc, BCE_MQ_KNL_WIND_END, val); + + /* Set the page size and clear the RV2P processor stall bits. */ + val = (BCM_PAGE_BITS - 8) << 24; + REG_WR(sc, BCE_RV2P_CONFIG, val); + + /* Configure page size. */ + val = REG_RD(sc, BCE_TBDR_CONFIG); + val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; + val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; + REG_WR(sc, BCE_TBDR_CONFIG, val); + + return 0; +} + + +/****************************************************************************/ +/* Initialize the controller in preparation to send/receive traffic. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_blockinit(struct bce_softc *sc) +{ + uint32_t reg, val; + int rc = 0; + + /* Load the hardware default MAC address. */ + bce_set_mac_addr(sc); + + /* Set the Ethernet backoff seed value */ + val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) + + sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); + REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); + + sc->last_status_idx = 0; + sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; + + /* Set up link change interrupt generation. */ + REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); + + /* Program the physical address of the status block. */ + REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr)); + REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr)); + + /* Program the physical address of the statistics block. */ + REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, + BCE_ADDR_LO(sc->stats_block_paddr)); + REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, + BCE_ADDR_HI(sc->stats_block_paddr)); + + /* Program various host coalescing parameters. */ + REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, + (sc->bce_tx_quick_cons_trip_int << 16) | + sc->bce_tx_quick_cons_trip); + REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, + (sc->bce_rx_quick_cons_trip_int << 16) | + sc->bce_rx_quick_cons_trip); + REG_WR(sc, BCE_HC_COMP_PROD_TRIP, + (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); + REG_WR(sc, BCE_HC_TX_TICKS, + (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); + REG_WR(sc, BCE_HC_RX_TICKS, + (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); + REG_WR(sc, BCE_HC_COM_TICKS, + (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); + REG_WR(sc, BCE_HC_CMD_TICKS, + (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); + REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00)); + REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ + REG_WR(sc, BCE_HC_CONFIG, + BCE_HC_CONFIG_RX_TMR_MODE | + BCE_HC_CONFIG_TX_TMR_MODE | + BCE_HC_CONFIG_COLLECT_STATS); + + /* Clear the internal statistics counters. */ + REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); + + /* Verify that bootcode is running. */ + reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); + + DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure), + if_printf(&sc->arpcom.ac_if, + "%s(%d): Simulating bootcode failure.\n", + __FILE__, __LINE__); + reg = 0); + + if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != + BCE_DEV_INFO_SIGNATURE_MAGIC) { + if_printf(&sc->arpcom.ac_if, + "Bootcode not running! Found: 0x%08X, " + "Expected: 08%08X\n", + reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK, + BCE_DEV_INFO_SIGNATURE_MAGIC); + return ENODEV; + } + + /* Check if any management firmware is running. */ + reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); + if (reg & (BCE_PORT_FEATURE_ASF_ENABLED | + BCE_PORT_FEATURE_IMD_ENABLED)) { + DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n"); + sc->bce_flags |= BCE_MFW_ENABLE_FLAG; + } + + sc->bce_fw_ver = + REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV); + DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver); + + /* Allow bootcode to apply any additional fixes before enabling MAC. */ + rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); + + /* Enable link state change interrupt generation. */ + REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); + + /* Enable all remaining blocks in the MAC. */ + REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); + REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); + DELAY(20); + + return 0; +} + + +/****************************************************************************/ +/* Encapsulate an mbuf cluster into the rx_bd chain. */ +/* */ +/* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ +/* This routine will map an mbuf cluster into 1 or more rx_bd's as */ +/* necessary. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_newbuf_std(struct bce_softc *sc, struct mbuf *m, + uint16_t *prod, uint16_t *chain_prod, uint32_t *prod_bseq) +{ + bus_dmamap_t map; + struct bce_dmamap_arg ctx; + bus_dma_segment_t seg; + struct mbuf *m_new; + struct rx_bd *rxbd; + int error; +#ifdef BCE_DEBUG + uint16_t debug_chain_prod = *chain_prod; +#endif + + /* Make sure the inputs are valid. */ + DBRUNIF((*chain_prod > MAX_RX_BD), + if_printf(&sc->arpcom.ac_if, "%s(%d): " + "RX producer out of range: 0x%04X > 0x%04X\n", + __FILE__, __LINE__, + *chain_prod, (uint16_t)MAX_RX_BD)); + + DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " + "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq); + + if (m == NULL) { + DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), + if_printf(&sc->arpcom.ac_if, "%s(%d): " + "Simulating mbuf allocation failure.\n", + __FILE__, __LINE__); + sc->mbuf_alloc_failed++; + return ENOBUFS); + + /* This is a new mbuf allocation. */ + m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); + if (m_new == NULL) + return ENOBUFS; + DBRUNIF(1, sc->rx_mbuf_alloc++); + } else { + m_new = m; + m_new->m_data = m_new->m_ext.ext_buf; + } + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + + /* Map the mbuf cluster into device memory. */ + map = sc->rx_mbuf_map[*chain_prod]; + + ctx.bce_maxsegs = 1; + ctx.bce_segs = &seg; + error = bus_dmamap_load_mbuf(sc->rx_mbuf_tag, map, m_new, + bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT); + if (error || ctx.bce_maxsegs == 0) { + if_printf(&sc->arpcom.ac_if, + "Error mapping mbuf into RX chain!\n"); + + if (m == NULL) + m_freem(m_new); + + DBRUNIF(1, sc->rx_mbuf_alloc--); + return ENOBUFS; + } + + /* Watch for overflow. */ + DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), + if_printf(&sc->arpcom.ac_if, "%s(%d): " + "Too many free rx_bd (0x%04X > 0x%04X)!\n", + __FILE__, __LINE__, sc->free_rx_bd, + (uint16_t)USABLE_RX_BD)); + + /* Update some debug statistic counters */ + DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), + sc->rx_low_watermark = sc->free_rx_bd); + DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++); + + /* Setup the rx_bd for the first segment. */ + rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; + + rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(seg.ds_addr)); + rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(seg.ds_addr)); + rxbd->rx_bd_len = htole32(seg.ds_len); + rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); + *prod_bseq += seg.ds_len; + + rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); + + /* Save the mbuf and update our counter. */ + sc->rx_mbuf_ptr[*chain_prod] = m_new; + sc->free_rx_bd--; + + DBRUN(BCE_VERBOSE_RECV, + bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1)); + + DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " + "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq); + + return 0; +} + + +/****************************************************************************/ +/* Allocate memory and initialize the TX data structures. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_init_tx_chain(struct bce_softc *sc) +{ + struct tx_bd *txbd; + uint32_t val; + int i, rc = 0; + + DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__); + + /* Set the initial TX producer/consumer indices. */ + sc->tx_prod = 0; + sc->tx_cons = 0; + sc->tx_prod_bseq = 0; + sc->used_tx_bd = 0; + sc->max_tx_bd = USABLE_TX_BD; + DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); + DBRUNIF(1, sc->tx_full_count = 0); + + /* + * The NetXtreme II supports a linked-list structre called + * a Buffer Descriptor Chain (or BD chain). A BD chain + * consists of a series of 1 or more chain pages, each of which + * consists of a fixed number of BD entries. + * The last BD entry on each page is a pointer to the next page + * in the chain, and the last pointer in the BD chain + * points back to the beginning of the chain. + */ + + /* Set the TX next pointer chain entries. */ + for (i = 0; i < TX_PAGES; i++) { + int j; + + txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; + + /* Check if we've reached the last page. */ + if (i == (TX_PAGES - 1)) + j = 0; + else + j = i + 1; + + txbd->tx_bd_haddr_hi = + htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); + txbd->tx_bd_haddr_lo = + htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); + } + + for (i = 0; i < TX_PAGES; ++i) { + bus_dmamap_sync(sc->tx_bd_chain_tag, sc->tx_bd_chain_map[i], + BUS_DMASYNC_PREWRITE); + } + + /* Initialize the context ID for an L2 TX chain. */ + val = BCE_L2CTX_TYPE_TYPE_L2; + val |= BCE_L2CTX_TYPE_SIZE_L2; + CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val); + + val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); + CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val); + + /* Point the hardware to the first page in the chain. */ + val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val); + val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val); + + DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); + + DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__); + + return(rc); +} + + +/****************************************************************************/ +/* Free memory and clear the TX data structures. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_free_tx_chain(struct bce_softc *sc) +{ + int i; + + DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__); + + /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ + for (i = 0; i < TOTAL_TX_BD; i++) { + if (sc->tx_mbuf_ptr[i] != NULL) { + bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]); + m_freem(sc->tx_mbuf_ptr[i]); + sc->tx_mbuf_ptr[i] = NULL; + DBRUNIF(1, sc->tx_mbuf_alloc--); + } + } + + /* Clear each TX chain page. */ + for (i = 0; i < TX_PAGES; i++) + bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); + + /* Check if we lost any mbufs in the process. */ + DBRUNIF((sc->tx_mbuf_alloc), + if_printf(&sc->arpcom.ac_if, + "%s(%d): Memory leak! " + "Lost %d mbufs from tx chain!\n", + __FILE__, __LINE__, sc->tx_mbuf_alloc)); + + DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__); +} + + +/****************************************************************************/ +/* Allocate memory and initialize the RX data structures. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_init_rx_chain(struct bce_softc *sc) +{ + struct rx_bd *rxbd; + int i, rc = 0; + uint16_t prod, chain_prod; + uint32_t prod_bseq, val; + + DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__); + + /* Initialize the RX producer and consumer indices. */ + sc->rx_prod = 0; + sc->rx_cons = 0; + sc->rx_prod_bseq = 0; + sc->free_rx_bd = USABLE_RX_BD; + sc->max_rx_bd = USABLE_RX_BD; + DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); + DBRUNIF(1, sc->rx_empty_count = 0); + + /* Initialize the RX next pointer chain entries. */ + for (i = 0; i < RX_PAGES; i++) { + int j; + + rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; + + /* Check if we've reached the last page. */ + if (i == (RX_PAGES - 1)) + j = 0; + else + j = i + 1; + + /* Setup the chain page pointers. */ + rxbd->rx_bd_haddr_hi = + htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); + rxbd->rx_bd_haddr_lo = + htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); + } + + /* Initialize the context ID for an L2 RX chain. */ + val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; + val |= BCE_L2CTX_CTX_TYPE_SIZE_L2; + val |= 0x02 << 8; + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val); + + /* Point the hardware to the first page in the chain. */ + /* XXX shouldn't this after RX descriptor initialization? */ + val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val); + val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); + CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val); + + /* Allocate mbuf clusters for the rx_bd chain. */ + prod = prod_bseq = 0; + while (prod < TOTAL_RX_BD) { + chain_prod = RX_CHAIN_IDX(prod); + if (bce_newbuf_std(sc, NULL, &prod, &chain_prod, &prod_bseq)) { + if_printf(&sc->arpcom.ac_if, + "Error filling RX chain: rx_bd[0x%04X]!\n", + chain_prod); + rc = ENOBUFS; + break; + } + prod = NEXT_RX_BD(prod); + } + + /* Save the RX chain producer index. */ + sc->rx_prod = prod; + sc->rx_prod_bseq = prod_bseq; + + for (i = 0; i < RX_PAGES; i++) { + bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], + BUS_DMASYNC_PREWRITE); + } + + /* Tell the chip about the waiting rx_bd's. */ + REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); + REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); + + DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); + + DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__); + + return(rc); +} + + +/****************************************************************************/ +/* Free memory and clear the RX data structures. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_free_rx_chain(struct bce_softc *sc) +{ + int i; + + DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__); + + /* Free any mbufs still in the RX mbuf chain. */ + for (i = 0; i < TOTAL_RX_BD; i++) { + if (sc->rx_mbuf_ptr[i] != NULL) { + bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]); + m_freem(sc->rx_mbuf_ptr[i]); + sc->rx_mbuf_ptr[i] = NULL; + DBRUNIF(1, sc->rx_mbuf_alloc--); + } + } + + /* Clear each RX chain page. */ + for (i = 0; i < RX_PAGES; i++) + bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); + + /* Check if we lost any mbufs in the process. */ + DBRUNIF((sc->rx_mbuf_alloc), + if_printf(&sc->arpcom.ac_if, + "%s(%d): Memory leak! " + "Lost %d mbufs from rx chain!\n", + __FILE__, __LINE__, sc->rx_mbuf_alloc)); + + DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__); +} + + +/****************************************************************************/ +/* Set media options. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_ifmedia_upd(struct ifnet *ifp) +{ + struct bce_softc *sc = ifp->if_softc; + struct mii_data *mii = device_get_softc(sc->bce_miibus); + + /* + * 'mii' will be NULL, when this function is called on following + * code path: bce_attach() -> bce_mgmt_init() + */ + if (mii != NULL) { + /* Make sure the MII bus has been enumerated. */ + sc->bce_link = 0; + if (mii->mii_instance) { + struct mii_softc *miisc; + + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + mii_phy_reset(miisc); + } + mii_mediachg(mii); + } + return 0; +} + + +/****************************************************************************/ +/* Reports current media status. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct bce_softc *sc = ifp->if_softc; + struct mii_data *mii = device_get_softc(sc->bce_miibus); + + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; +} + + +/****************************************************************************/ +/* Handles PHY generated interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_phy_intr(struct bce_softc *sc) +{ + uint32_t new_link_state, old_link_state; + struct ifnet *ifp = &sc->arpcom.ac_if; + + ASSERT_SERIALIZED(ifp->if_serializer); + + new_link_state = sc->status_block->status_attn_bits & + STATUS_ATTN_BITS_LINK_STATE; + old_link_state = sc->status_block->status_attn_bits_ack & + STATUS_ATTN_BITS_LINK_STATE; + + /* Handle any changes if the link state has changed. */ + if (new_link_state != old_link_state) { /* XXX redundant? */ + DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); + + sc->bce_link = 0; + callout_stop(&sc->bce_stat_ch); + bce_tick_serialized(sc); + + /* Update the status_attn_bits_ack field in the status block. */ + if (new_link_state) { + REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, + STATUS_ATTN_BITS_LINK_STATE); + if (bootverbose) + if_printf(ifp, "Link is now UP.\n"); + } else { + REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, + STATUS_ATTN_BITS_LINK_STATE); + if (bootverbose) + if_printf(ifp, "Link is now DOWN.\n"); + } + } + + /* Acknowledge the link change interrupt. */ + REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); +} + + +/****************************************************************************/ +/* Handles received frame interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_rx_intr(struct bce_softc *sc, int count) +{ + struct status_block *sblk = sc->status_block; + struct ifnet *ifp = &sc->arpcom.ac_if; + uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod; + uint32_t sw_prod_bseq; + int i; + + ASSERT_SERIALIZED(ifp->if_serializer); + + DBRUNIF(1, sc->rx_interrupts++); + + /* Prepare the RX chain pages to be accessed by the host CPU. */ + for (i = 0; i < RX_PAGES; i++) { + bus_dmamap_sync(sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); + } + + /* Get the hardware's view of the RX consumer index. */ + hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; + if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) + hw_cons++; + + /* Get working copies of the driver's view of the RX indices. */ + sw_cons = sc->rx_cons; + sw_prod = sc->rx_prod; + sw_prod_bseq = sc->rx_prod_bseq; + + DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " + "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", + __func__, sw_prod, sw_cons, sw_prod_bseq); + + /* Prevent speculative reads from getting ahead of the status block. */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + /* Update some debug statistics counters */ + DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), + sc->rx_low_watermark = sc->free_rx_bd); + DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++); + + /* Scan through the receive chain as long as there is work to do. */ + while (sw_cons != hw_cons) { + struct mbuf *m = NULL; + struct l2_fhdr *l2fhdr = NULL; + struct rx_bd *rxbd; + unsigned int len; + uint32_t status = 0; + +#ifdef foo /* DEVICE_POLLING */ + /* + * Even if polling(4) is enabled, we can't just reap + * 'count' RX descriptors and leave. It seems that RX + * engine would be left in a wired state, if we broke + * out the loop in the middle. + */ + if (count >= 0 && count-- == 0) + break; +#endif + + /* + * Convert the producer/consumer indices + * to an actual rx_bd index. + */ + sw_chain_cons = RX_CHAIN_IDX(sw_cons); + sw_chain_prod = RX_CHAIN_IDX(sw_prod); + + /* Get the used rx_bd. */ + rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)] + [RX_IDX(sw_chain_cons)]; + sc->free_rx_bd++; + + DBRUN(BCE_VERBOSE_RECV, + if_printf(ifp, "%s(): ", __func__); + bce_dump_rxbd(sc, sw_chain_cons, rxbd)); + + /* The mbuf is stored with the last rx_bd entry of a packet. */ + if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { + /* Validate that this is the last rx_bd. */ + DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), + if_printf(ifp, "%s(%d): " + "Unexpected mbuf found in rx_bd[0x%04X]!\n", + __FILE__, __LINE__, sw_chain_cons); + bce_breakpoint(sc)); + + /* + * ToDo: If the received packet is small enough + * to fit into a single, non-M_EXT mbuf, + * allocate a new mbuf here, copy the data to + * that mbuf, and recycle the mapped jumbo frame. + */ + + /* Unmap the mbuf from DMA space. */ + bus_dmamap_sync(sc->rx_mbuf_tag, + sc->rx_mbuf_map[sw_chain_cons], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rx_mbuf_tag, + sc->rx_mbuf_map[sw_chain_cons]); + + /* Remove the mbuf from the driver's chain. */ + m = sc->rx_mbuf_ptr[sw_chain_cons]; + sc->rx_mbuf_ptr[sw_chain_cons] = NULL; + + /* + * Frames received on the NetXteme II are prepended + * with an l2_fhdr structure which provides status + * information about the received frame (including + * VLAN tags and checksum info). The frames are also + * automatically adjusted to align the IP header + * (i.e. two null bytes are inserted before the + * Ethernet header). + */ + l2fhdr = mtod(m, struct l2_fhdr *); + + len = l2fhdr->l2_fhdr_pkt_len; + status = l2fhdr->l2_fhdr_status; + + DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check), + if_printf(ifp, + "Simulating l2_fhdr status error.\n"); + status = status | L2_FHDR_ERRORS_PHY_DECODE); + + /* Watch for unusual sized frames. */ + DBRUNIF((len < BCE_MIN_MTU || + len > BCE_MAX_JUMBO_ETHER_MTU_VLAN), + if_printf(ifp, + "%s(%d): Unusual frame size found. " + "Min(%d), Actual(%d), Max(%d)\n", + __FILE__, __LINE__, + (int)BCE_MIN_MTU, len, + (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN); + bce_dump_mbuf(sc, m); + bce_breakpoint(sc)); + + len -= ETHER_CRC_LEN; + + /* Check the received frame for errors. */ + if (status & (L2_FHDR_ERRORS_BAD_CRC | + L2_FHDR_ERRORS_PHY_DECODE | + L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_TOO_SHORT | + L2_FHDR_ERRORS_GIANT_FRAME)) { + ifp->if_ierrors++; + DBRUNIF(1, sc->l2fhdr_status_errors++); + + /* Reuse the mbuf for a new frame. */ + if (bce_newbuf_std(sc, m, &sw_prod, + &sw_chain_prod, + &sw_prod_bseq)) { + DBRUNIF(1, bce_breakpoint(sc)); + /* XXX */ + panic("%s: Can't reuse RX mbuf!\n", + ifp->if_xname); + } + m = NULL; + goto bce_rx_int_next_rx; + } + + /* + * Get a new mbuf for the rx_bd. If no new + * mbufs are available then reuse the current mbuf, + * log an ierror on the interface, and generate + * an error in the system log. + */ + if (bce_newbuf_std(sc, NULL, &sw_prod, &sw_chain_prod, + &sw_prod_bseq)) { + DBRUN(BCE_WARN, + if_printf(ifp, + "%s(%d): Failed to allocate new mbuf, " + "incoming frame dropped!\n", + __FILE__, __LINE__)); + + ifp->if_ierrors++; + + /* Try and reuse the exisitng mbuf. */ + if (bce_newbuf_std(sc, m, &sw_prod, + &sw_chain_prod, + &sw_prod_bseq)) { + DBRUNIF(1, bce_breakpoint(sc)); + /* XXX */ + panic("%s: Double mbuf allocation " + "failure!", ifp->if_xname); + } + m = NULL; + goto bce_rx_int_next_rx; + } + + /* + * Skip over the l2_fhdr when passing + * the data up the stack. + */ + m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); + + m->m_pkthdr.len = m->m_len = len; + m->m_pkthdr.rcvif = ifp; + + DBRUN(BCE_VERBOSE_RECV, + struct ether_header *eh; + eh = mtod(m, struct ether_header *); + if_printf(ifp, "%s(): to: %6D, from: %6D, " + "type: 0x%04X\n", __func__, + eh->ether_dhost, ":", + eh->ether_shost, ":", + htons(eh->ether_type))); + + /* Validate the checksum if offload enabled. */ + if (ifp->if_capenable & IFCAP_RXCSUM) { + /* Check for an IP datagram. */ + if (status & L2_FHDR_STATUS_IP_DATAGRAM) { + m->m_pkthdr.csum_flags |= + CSUM_IP_CHECKED; + + /* Check if the IP checksum is valid. */ + if ((l2fhdr->l2_fhdr_ip_xsum ^ + 0xffff) == 0) { + m->m_pkthdr.csum_flags |= + CSUM_IP_VALID; + } else { + DBPRINT(sc, BCE_WARN_RECV, + "%s(): Invalid IP checksum = 0x%04X!\n", + __func__, l2fhdr->l2_fhdr_ip_xsum); + } + } + + /* Check for a valid TCP/UDP frame. */ + if (status & (L2_FHDR_STATUS_TCP_SEGMENT | + L2_FHDR_STATUS_UDP_DATAGRAM)) { + + /* Check for a good TCP/UDP checksum. */ + if ((status & + (L2_FHDR_ERRORS_TCP_XSUM | + L2_FHDR_ERRORS_UDP_XSUM)) == 0) { + m->m_pkthdr.csum_data = + l2fhdr->l2_fhdr_tcp_udp_xsum; + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID | + CSUM_PSEUDO_HDR; + } else { + DBPRINT(sc, BCE_WARN_RECV, + "%s(): Invalid TCP/UDP checksum = 0x%04X!\n", + __func__, l2fhdr->l2_fhdr_tcp_udp_xsum); + } + } + } + + ifp->if_ipackets++; +bce_rx_int_next_rx: + sw_prod = NEXT_RX_BD(sw_prod); + } + + sw_cons = NEXT_RX_BD(sw_cons); + + /* If we have a packet, pass it up the stack */ + if (m) { + DBPRINT(sc, BCE_VERBOSE_RECV, + "%s(): Passing received frame up.\n", __func__); + + if (status & L2_FHDR_STATUS_L2_VLAN_TAG) + VLAN_INPUT_TAG(m, l2fhdr->l2_fhdr_vlan_tag); + else + ifp->if_input(ifp, m); + + DBRUNIF(1, sc->rx_mbuf_alloc--); + } + + /* + * If polling(4) is not enabled, refresh hw_cons to see + * whether there's new work. + * + * If polling(4) is enabled, i.e count >= 0, refreshing + * should not be performed, so that we would not spend + * too much time in RX processing. + */ + if (count < 0 && sw_cons == hw_cons) { + hw_cons = sc->hw_rx_cons = + sblk->status_rx_quick_consumer_index0; + if ((hw_cons & USABLE_RX_BD_PER_PAGE) == + USABLE_RX_BD_PER_PAGE) + hw_cons++; + } + + /* + * Prevent speculative reads from getting ahead + * of the status block. + */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + } + + for (i = 0; i < RX_PAGES; i++) { + bus_dmamap_sync(sc->rx_bd_chain_tag, + sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); + } + + sc->rx_cons = sw_cons; + sc->rx_prod = sw_prod; + sc->rx_prod_bseq = sw_prod_bseq; + + REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); + REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); + + DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " + "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", + __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); +} + + +/****************************************************************************/ +/* Handles transmit completion interrupt events. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_tx_intr(struct bce_softc *sc) +{ + struct status_block *sblk = sc->status_block; + struct ifnet *ifp = &sc->arpcom.ac_if; + uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; + + ASSERT_SERIALIZED(ifp->if_serializer); + + DBRUNIF(1, sc->tx_interrupts++); + + /* Get the hardware's view of the TX consumer index. */ + hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; + + /* Skip to the next entry if this is a chain page pointer. */ + if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) + hw_tx_cons++; + + sw_tx_cons = sc->tx_cons; + + /* Prevent speculative reads from getting ahead of the status block. */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + /* Cycle through any completed TX chain page entries. */ + while (sw_tx_cons != hw_tx_cons) { +#ifdef BCE_DEBUG + struct tx_bd *txbd = NULL; +#endif + sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); + + DBPRINT(sc, BCE_INFO_SEND, + "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " + "sw_tx_chain_cons = 0x%04X\n", + __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); + + DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), + if_printf(ifp, "%s(%d): " + "TX chain consumer out of range! " + " 0x%04X > 0x%04X\n", + __FILE__, __LINE__, sw_tx_chain_cons, + (int)MAX_TX_BD); + bce_breakpoint(sc)); + + DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] + [TX_IDX(sw_tx_chain_cons)]); + + DBRUNIF((txbd == NULL), + if_printf(ifp, "%s(%d): " + "Unexpected NULL tx_bd[0x%04X]!\n", + __FILE__, __LINE__, sw_tx_chain_cons); + bce_breakpoint(sc)); + + DBRUN(BCE_INFO_SEND, + if_printf(ifp, "%s(): ", __func__); + bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); + + /* + * Free the associated mbuf. Remember + * that only the last tx_bd of a packet + * has an mbuf pointer and DMA map. + */ + if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { + /* Validate that this is the last tx_bd. */ + DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), + if_printf(ifp, "%s(%d): " + "tx_bd END flag not set but " + "txmbuf == NULL!\n", __FILE__, __LINE__); + bce_breakpoint(sc)); + + DBRUN(BCE_INFO_SEND, + if_printf(ifp, "%s(): Unloading map/freeing mbuf " + "from tx_bd[0x%04X]\n", __func__, + sw_tx_chain_cons)); + + /* Unmap the mbuf. */ + bus_dmamap_unload(sc->tx_mbuf_tag, + sc->tx_mbuf_map[sw_tx_chain_cons]); + + /* Free the mbuf. */ + m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); + sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; + DBRUNIF(1, sc->tx_mbuf_alloc--); + + ifp->if_opackets++; + } + + sc->used_tx_bd--; + sw_tx_cons = NEXT_TX_BD(sw_tx_cons); + + if (sw_tx_cons == hw_tx_cons) { + /* Refresh hw_cons to see if there's new work. */ + hw_tx_cons = sc->hw_tx_cons = + sblk->status_tx_quick_consumer_index0; + if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == + USABLE_TX_BD_PER_PAGE) + hw_tx_cons++; + } + + /* + * Prevent speculative reads from getting + * ahead of the status block. + */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + } + + if (sc->used_tx_bd == 0) { + /* Clear the TX timeout timer. */ + ifp->if_timer = 0; + } + + /* Clear the tx hardware queue full flag. */ + if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) { + DBRUNIF((ifp->if_flags & IFF_OACTIVE), + DBPRINT(sc, BCE_WARN_SEND, + "%s(): Open TX chain! %d/%d (used/total)\n", + __func__, sc->used_tx_bd, sc->max_tx_bd)); + ifp->if_flags &= ~IFF_OACTIVE; + } + sc->tx_cons = sw_tx_cons; +} + + +/****************************************************************************/ +/* Disables interrupt generation. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_disable_intr(struct bce_softc *sc) +{ + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); + REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); + lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer); +} + + +/****************************************************************************/ +/* Enables interrupt generation. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_enable_intr(struct bce_softc *sc) +{ + uint32_t val; + + lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer); + + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | + BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); + + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); + + val = REG_RD(sc, BCE_HC_COMMAND); + REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW); +} + + +/****************************************************************************/ +/* Handles controller initialization. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_init(void *xsc) +{ + struct bce_softc *sc = xsc; + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t ether_mtu; + int error; + + ASSERT_SERIALIZED(ifp->if_serializer); + + /* Check if the driver is still running and bail out if it is. */ + if (ifp->if_flags & IFF_RUNNING) + return; + + bce_stop(sc); + + error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET); + if (error) { + if_printf(ifp, "Controller reset failed!\n"); + goto back; + } + + error = bce_chipinit(sc); + if (error) { + if_printf(ifp, "Controller initialization failed!\n"); + goto back; + } + + error = bce_blockinit(sc); + if (error) { + if_printf(ifp, "Block initialization failed!\n"); + goto back; + } + + /* Load our MAC address. */ + bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN); + bce_set_mac_addr(sc); + + /* Calculate and program the Ethernet MTU size. */ + ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN; + + DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu); + + /* + * Program the mtu, enabling jumbo frame + * support if necessary. Also set the mbuf + * allocation count for RX frames. + */ + if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) { +#ifdef notyet + REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, + min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | + BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); + sc->mbuf_alloc_size = MJUM9BYTES; +#else + panic("jumbo buffer is not supported yet\n"); +#endif + } else { + REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); + sc->mbuf_alloc_size = MCLBYTES; + } + + /* Calculate the RX Ethernet frame size for rx_bd's. */ + sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; + + DBPRINT(sc, BCE_INFO, + "%s(): mclbytes = %d, mbuf_alloc_size = %d, " + "max_frame_size = %d\n", + __func__, (int)MCLBYTES, sc->mbuf_alloc_size, + sc->max_frame_size); + + /* Program appropriate promiscuous/multicast filtering. */ + bce_set_rx_mode(sc); + + /* Init RX buffer descriptor chain. */ + bce_init_rx_chain(sc); /* XXX return value */ + + /* Init TX buffer descriptor chain. */ + bce_init_tx_chain(sc); /* XXX return value */ + +#ifdef DEVICE_POLLING + /* Disable interrupts if we are polling. */ + if (ifp->if_flags & IFF_POLLING) { + bce_disable_intr(sc); + + REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, + (1 << 16) | sc->bce_rx_quick_cons_trip); + REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, + (1 << 16) | sc->bce_tx_quick_cons_trip); + } else +#endif + /* Enable host interrupts. */ + bce_enable_intr(sc); + + bce_ifmedia_upd(ifp); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc); +back: + if (error) + bce_stop(sc); +} + + +/****************************************************************************/ +/* Initialize the controller just enough so that any management firmware */ +/* running on the device will continue to operate corectly. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_mgmt_init(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val; + + /* Check if the driver is still running and bail out if it is. */ + if (ifp->if_flags & IFF_RUNNING) + return; + + /* Initialize the on-boards CPUs */ + bce_init_cpus(sc); + + /* Set the page size and clear the RV2P processor stall bits. */ + val = (BCM_PAGE_BITS - 8) << 24; + REG_WR(sc, BCE_RV2P_CONFIG, val); + + /* Enable all critical blocks in the MAC. */ + REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, + BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | + BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | + BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); + REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); + DELAY(20); + + bce_ifmedia_upd(ifp); +} + + +/****************************************************************************/ +/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ +/* memory visible to the controller. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_encap(struct bce_softc *sc, struct mbuf **m_head) +{ + struct bce_dmamap_arg ctx; + bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; + bus_dmamap_t map, tmp_map; + struct mbuf *m0 = *m_head; + struct tx_bd *txbd = NULL; + uint16_t vlan_tag = 0, flags = 0; + uint16_t chain_prod, chain_prod_start, prod; + uint32_t prod_bseq; + int i, error, maxsegs; +#ifdef BCE_DEBUG + uint16_t debug_prod; +#endif + + /* Transfer any checksum offload flags to the bd. */ + if (m0->m_pkthdr.csum_flags) { + if (m0->m_pkthdr.csum_flags & CSUM_IP) + flags |= TX_BD_FLAGS_IP_CKSUM; + if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) + flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; + } + + /* Transfer any VLAN tags to the bd. */ + if ((m0->m_flags & (M_PROTO1 | M_PKTHDR)) == (M_PROTO1 | M_PKTHDR) && + m0->m_pkthdr.rcvif != NULL && + m0->m_pkthdr.rcvif->if_type == IFT_L2VLAN) { + struct ifvlan *ifv = m0->m_pkthdr.rcvif->if_softc; + + flags |= TX_BD_FLAGS_VLAN_TAG; + vlan_tag = ifv->ifv_tag; + } + + prod = sc->tx_prod; + chain_prod_start = chain_prod = TX_CHAIN_IDX(prod); + + /* Map the mbuf into DMAable memory. */ + map = sc->tx_mbuf_map[chain_prod_start]; + + maxsegs = sc->max_tx_bd - sc->used_tx_bd; + KASSERT(maxsegs >= BCE_TX_SPARE_SPACE, + ("not enough segements %d\n", maxsegs)); + if (maxsegs > BCE_MAX_SEGMENTS) + maxsegs = BCE_MAX_SEGMENTS; + + /* Map the mbuf into our DMA address space. */ + ctx.bce_maxsegs = maxsegs; + ctx.bce_segs = segs; + error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0, + bce_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT); + if (error == EFBIG || ctx.bce_maxsegs == 0) { + DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf\n", __func__); + DBRUNIF(1, bce_dump_mbuf(sc, m0);); + + m0 = m_defrag(*m_head, MB_DONTWAIT); + if (m0 == NULL) { + error = ENOBUFS; + goto back; + } + *m_head = m0; + + ctx.bce_maxsegs = maxsegs; + ctx.bce_segs = segs; + error = bus_dmamap_load_mbuf(sc->tx_mbuf_tag, map, m0, + bce_dma_map_mbuf, &ctx, + BUS_DMA_NOWAIT); + if (error || ctx.bce_maxsegs == 0) { + if_printf(&sc->arpcom.ac_if, + "Error mapping mbuf into TX chain\n"); + if (error == 0) + error = EFBIG; + goto back; + } + } else if (error) { + if_printf(&sc->arpcom.ac_if, + "Error mapping mbuf into TX chain\n"); + goto back; + } + + /* prod points to an empty tx_bd at this point. */ + prod_bseq = sc->tx_prod_bseq; + +#ifdef BCE_DEBUG + debug_prod = chain_prod; +#endif + + DBPRINT(sc, BCE_INFO_SEND, + "%s(): Start: prod = 0x%04X, chain_prod = %04X, " + "prod_bseq = 0x%08X\n", + __func__, prod, chain_prod, prod_bseq); + + /* + * Cycle through each mbuf segment that makes up + * the outgoing frame, gathering the mapping info + * for that segment and creating a tx_bd to for + * the mbuf. + */ + for (i = 0; i < ctx.bce_maxsegs; i++) { + chain_prod = TX_CHAIN_IDX(prod); + txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; + + txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); + txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); + txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len); + txbd->tx_bd_vlan_tag = htole16(vlan_tag); + txbd->tx_bd_flags = htole16(flags); + prod_bseq += segs[i].ds_len; + if (i == 0) + txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); + prod = NEXT_TX_BD(prod); + } + + /* Set the END flag on the last TX buffer descriptor. */ + txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); + + DBRUN(BCE_EXCESSIVE_SEND, + bce_dump_tx_chain(sc, debug_prod, ctx.bce_maxsegs)); + + DBPRINT(sc, BCE_INFO_SEND, + "%s(): End: prod = 0x%04X, chain_prod = %04X, " + "prod_bseq = 0x%08X\n", + __func__, prod, chain_prod, prod_bseq); + + bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE); + + /* + * Ensure that the mbuf pointer for this transmission + * is placed at the array index of the last + * descriptor in this chain. This is done + * because a single map is used for all + * segments of the mbuf and we don't want to + * unload the map before all of the segments + * have been freed. + */ + sc->tx_mbuf_ptr[chain_prod] = m0; + + tmp_map = sc->tx_mbuf_map[chain_prod]; + sc->tx_mbuf_map[chain_prod] = map; + sc->tx_mbuf_map[chain_prod_start] = tmp_map; + + sc->used_tx_bd += ctx.bce_maxsegs; + + /* Update some debug statistic counters */ + DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), + sc->tx_hi_watermark = sc->used_tx_bd); + DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); + DBRUNIF(1, sc->tx_mbuf_alloc++); + + DBRUN(BCE_VERBOSE_SEND, + bce_dump_tx_mbuf_chain(sc, chain_prod, ctx.bce_maxsegs)); + + /* prod points to the next free tx_bd at this point. */ + sc->tx_prod = prod; + sc->tx_prod_bseq = prod_bseq; +back: + if (error) { + m_freem(*m_head); + *m_head = NULL; + } + return error; +} + + +/****************************************************************************/ +/* Main transmit routine when called from another routine with a lock. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_start(struct ifnet *ifp) +{ + struct bce_softc *sc = ifp->if_softc; + int count = 0; + + ASSERT_SERIALIZED(ifp->if_serializer); + + /* If there's no link or the transmit queue is empty then just exit. */ + if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING || + !sc->bce_link) + return; + + DBPRINT(sc, BCE_INFO_SEND, + "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, " + "tx_prod_bseq = 0x%08X\n", + __func__, + sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq); + + for (;;) { + struct mbuf *m_head; + + /* + * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is + * unlikely to fail. + */ + if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) { + ifp->if_flags |= IFF_OACTIVE; + break; + } + + /* Check for any frames to send. */ + m_head = ifq_dequeue(&ifp->if_snd, NULL); + if (m_head == NULL) + break; + + /* + * Pack the data into the transmit ring. If we + * don't have room, place the mbuf back at the + * head of the queue and set the OACTIVE flag + * to wait for the NIC to drain the chain. + */ + if (bce_encap(sc, &m_head)) { + ifp->if_flags |= IFF_OACTIVE; + DBPRINT(sc, BCE_INFO_SEND, + "TX chain is closed for business! " + "Total tx_bd used = %d\n", + sc->used_tx_bd); + break; + } + + count++; + + /* Send a copy of the frame to any BPF listeners. */ + BPF_MTAP(ifp, m_head); + } + + if (count == 0) { + /* no packets were dequeued */ + DBPRINT(sc, BCE_VERBOSE_SEND, + "%s(): No packets were dequeued\n", __func__); + return; + } + + DBPRINT(sc, BCE_INFO_SEND, + "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " + "tx_prod_bseq = 0x%08X\n", + __func__, + sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq); + + /* Start the transmit. */ + REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); + REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); + + /* Set the tx timeout. */ + ifp->if_timer = BCE_TX_TIMEOUT; +} + + +/****************************************************************************/ +/* Handles any IOCTL calls from the operating system. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) +{ + struct bce_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *)data; + struct mii_data *mii; + int mask, error = 0; + + ASSERT_SERIALIZED(ifp->if_serializer); + + switch(command) { + case SIOCSIFMTU: + /* Check that the MTU setting is supported. */ + if (ifr->ifr_mtu < BCE_MIN_MTU || +#ifdef notyet + ifr->ifr_mtu > BCE_MAX_JUMBO_MTU +#else + ifr->ifr_mtu > ETHERMTU +#endif + ) { + error = EINVAL; + break; + } + + DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu); + + ifp->if_mtu = ifr->ifr_mtu; + ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */ + bce_init(sc); + break; + + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (ifp->if_flags & IFF_RUNNING) { + mask = ifp->if_flags ^ sc->bce_if_flags; + + if (mask & (IFF_PROMISC | IFF_ALLMULTI)) + bce_set_rx_mode(sc); + } else { + bce_init(sc); + } + } else if (ifp->if_flags & IFF_RUNNING) { + bce_stop(sc); + } + sc->bce_if_flags = ifp->if_flags; + break; + + case SIOCADDMULTI: + case SIOCDELMULTI: + if (ifp->if_flags & IFF_RUNNING) + bce_set_rx_mode(sc); + break; + + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n", + sc->bce_phy_flags); + DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n"); + + mii = device_get_softc(sc->bce_miibus); + error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); + break; + + case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; + DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n", + (uint32_t) mask); + + if (mask & IFCAP_HWCSUM) { + ifp->if_capenable ^= IFCAP_HWCSUM; + if (IFCAP_HWCSUM & ifp->if_capenable) + ifp->if_hwassist = BCE_IF_HWASSIST; + else + ifp->if_hwassist = 0; + } + break; + + default: + error = ether_ioctl(ifp, command, data); + break; + } + return error; +} + + +/****************************************************************************/ +/* Transmit timeout handler. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_watchdog(struct ifnet *ifp) +{ + struct bce_softc *sc = ifp->if_softc; + + ASSERT_SERIALIZED(ifp->if_serializer); + + DBRUN(BCE_VERBOSE_SEND, + bce_dump_driver_state(sc); + bce_dump_status_block(sc)); + + /* + * If we are in this routine because of pause frames, then + * don't reset the hardware. + */ + if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) + return; + + if_printf(ifp, "Watchdog timeout occurred, resetting!\n"); + + /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */ + + ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */ + bce_init(sc); + + ifp->if_oerrors++; + + if (!ifq_is_empty(&ifp->if_snd)) + ifp->if_start(ifp); +} + + +#ifdef DEVICE_POLLING + +static void +bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) +{ + struct bce_softc *sc = ifp->if_softc; + struct status_block *sblk = sc->status_block; + + ASSERT_SERIALIZED(ifp->if_serializer); + + switch (cmd) { + case POLL_REGISTER: + bce_disable_intr(sc); + + REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, + (1 << 16) | sc->bce_rx_quick_cons_trip); + REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, + (1 << 16) | sc->bce_tx_quick_cons_trip); + return; + case POLL_DEREGISTER: + bce_enable_intr(sc); + + REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, + (sc->bce_tx_quick_cons_trip_int << 16) | + sc->bce_tx_quick_cons_trip); + REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, + (sc->bce_rx_quick_cons_trip_int << 16) | + sc->bce_rx_quick_cons_trip); + return; + default: + break; + } + + bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); + + if (cmd == POLL_AND_CHECK_STATUS) { + uint32_t status_attn_bits; + + status_attn_bits = sblk->status_attn_bits; + + DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), + if_printf(ifp, + "Simulating unexpected status attention bit set."); + status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR); + + /* Was it a link change interrupt? */ + if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != + (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) + bce_phy_intr(sc); + + /* + * If any other attention is asserted then + * the chip is toast. + */ + if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != + (sblk->status_attn_bits_ack & + ~STATUS_ATTN_BITS_LINK_STATE)) { + DBRUN(1, sc->unexpected_attentions++); + + if_printf(ifp, "Fatal attention detected: 0x%08X\n", + sblk->status_attn_bits); + + DBRUN(BCE_FATAL, + if (bce_debug_unexpected_attention == 0) + bce_breakpoint(sc)); + + bce_init(sc); + return; + } + } + + /* Check for any completed RX frames. */ + if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) + bce_rx_intr(sc, count); + + /* Check for any completed TX frames. */ + if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) + bce_tx_intr(sc); + + bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE); + + /* Check for new frames to transmit. */ + if (!ifq_is_empty(&ifp->if_snd)) + ifp->if_start(ifp); +} + +#endif /* DEVICE_POLLING */ + + +#if 0 +static inline int +bce_has_work(struct bce_softc *sc) +{ + struct status_block *stat = sc->status_block; + + if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) || + (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons)) + return 1; + + if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) != + bp->link_up) + return 1; + + return 0; +} +#endif + + +/* + * Interrupt handler. + */ +/****************************************************************************/ +/* Main interrupt entry point. Verifies that the controller generated the */ +/* interrupt and then calls a separate routine for handle the various */ +/* interrupt causes (PHY, TX, RX). */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static void +bce_intr(void *xsc) +{ + struct bce_softc *sc = xsc; + struct ifnet *ifp = &sc->arpcom.ac_if; + struct status_block *sblk; + + ASSERT_SERIALIZED(ifp->if_serializer); + + DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__); + DBRUNIF(1, sc->interrupts_generated++); + + bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); + sblk = sc->status_block; + + /* + * If the hardware status block index matches the last value + * read by the driver and we haven't asserted our interrupt + * then there's nothing to do. + */ + if (sblk->status_idx == sc->last_status_idx && + (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & + BCE_PCICFG_MISC_STATUS_INTA_VALUE)) + return; + + /* Ack the interrupt and stop others from occuring. */ + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | + BCE_PCICFG_INT_ACK_CMD_MASK_INT); + + /* Keep processing data as long as there is work to do. */ + for (;;) { + uint32_t status_attn_bits; + + status_attn_bits = sblk->status_attn_bits; + + DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), + if_printf(ifp, + "Simulating unexpected status attention bit set."); + status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR); + + /* Was it a link change interrupt? */ + if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != + (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) + bce_phy_intr(sc); + + /* + * If any other attention is asserted then + * the chip is toast. + */ + if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != + (sblk->status_attn_bits_ack & + ~STATUS_ATTN_BITS_LINK_STATE)) { + DBRUN(1, sc->unexpected_attentions++); + + if_printf(ifp, "Fatal attention detected: 0x%08X\n", + sblk->status_attn_bits); + + DBRUN(BCE_FATAL, + if (bce_debug_unexpected_attention == 0) + bce_breakpoint(sc)); + + bce_init(sc); + return; + } + + /* Check for any completed RX frames. */ + if (sblk->status_rx_quick_consumer_index0 != sc->hw_rx_cons) + bce_rx_intr(sc, -1); + + /* Check for any completed TX frames. */ + if (sblk->status_tx_quick_consumer_index0 != sc->hw_tx_cons) + bce_tx_intr(sc); + + /* + * Save the status block index value + * for use during the next interrupt. + */ + sc->last_status_idx = sblk->status_idx; + + /* + * Prevent speculative reads from getting + * ahead of the status block. + */ + bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, + BUS_SPACE_BARRIER_READ); + + /* + * If there's no work left then exit the + * interrupt service routine. + */ + if (sblk->status_rx_quick_consumer_index0 == sc->hw_rx_cons && + sblk->status_tx_quick_consumer_index0 == sc->hw_tx_cons) + break; + } + + bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREWRITE); + + /* Re-enable interrupts. */ + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | + BCE_PCICFG_INT_ACK_CMD_MASK_INT); + REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, + BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); + + /* Handle any frames that arrived while handling the interrupt. */ + if (!ifq_is_empty(&ifp->if_snd)) + ifp->if_start(ifp); +} + + +/****************************************************************************/ +/* Programs the various packet receive modes (broadcast and multicast). */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_set_rx_mode(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + struct ifmultiaddr *ifma; + uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + uint32_t rx_mode, sort_mode; + int h, i; + + ASSERT_SERIALIZED(ifp->if_serializer); + + /* Initialize receive mode default settings. */ + rx_mode = sc->rx_mode & + ~(BCE_EMAC_RX_MODE_PROMISCUOUS | + BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); + sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; + + /* + * ASF/IPMI/UMP firmware requires that VLAN tag stripping + * be enbled. + */ + if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && + !(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) + rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; + + /* + * Check for promiscuous, all multicast, or selected + * multicast address filtering. + */ + if (ifp->if_flags & IFF_PROMISC) { + DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n"); + + /* Enable promiscuous mode. */ + rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; + sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; + } else if (ifp->if_flags & IFF_ALLMULTI) { + DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n"); + + /* Enable all multicast addresses. */ + for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { + REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), + 0xffffffff); + } + sort_mode |= BCE_RPM_SORT_USER0_MC_EN; + } else { + /* Accept one or more multicast(s). */ + DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n"); + + LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = ether_crc32_le( + LLADDR((struct sockaddr_dl *)ifma->ifma_addr), + ETHER_ADDR_LEN) & 0xFF; + hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); + } + + for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { + REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), + hashes[i]); + } + sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; + } + + /* Only make changes if the recive mode has actually changed. */ + if (rx_mode != sc->rx_mode) { + DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n", + rx_mode); + + sc->rx_mode = rx_mode; + REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); + } + + /* Disable and clear the exisitng sort before enabling a new sort. */ + REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); + REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); + REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); +} + + +/****************************************************************************/ +/* Called periodically to updates statistics from the controllers */ +/* statistics block. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_stats_update(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + struct statistics_block *stats = sc->stats_block; + + DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__); + + ASSERT_SERIALIZED(ifp->if_serializer); + + /* + * Update the interface statistics from the hardware statistics. + */ + ifp->if_collisions = (u_long)stats->stat_EtherStatsCollisions; + + ifp->if_ierrors = (u_long)stats->stat_EtherStatsUndersizePkts + + (u_long)stats->stat_EtherStatsOverrsizePkts + + (u_long)stats->stat_IfInMBUFDiscards + + (u_long)stats->stat_Dot3StatsAlignmentErrors + + (u_long)stats->stat_Dot3StatsFCSErrors; + + ifp->if_oerrors = + (u_long)stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + + (u_long)stats->stat_Dot3StatsExcessiveCollisions + + (u_long)stats->stat_Dot3StatsLateCollisions; + + /* + * Certain controllers don't report carrier sense errors correctly. + * See errata E11_5708CA0_1165. + */ + if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && + !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) { + ifp->if_oerrors += + (u_long)stats->stat_Dot3StatsCarrierSenseErrors; + } + + /* + * Update the sysctl statistics from the hardware statistics. + */ + sc->stat_IfHCInOctets = + ((uint64_t)stats->stat_IfHCInOctets_hi << 32) + + (uint64_t)stats->stat_IfHCInOctets_lo; + + sc->stat_IfHCInBadOctets = + ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) + + (uint64_t)stats->stat_IfHCInBadOctets_lo; + + sc->stat_IfHCOutOctets = + ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) + + (uint64_t)stats->stat_IfHCOutOctets_lo; + + sc->stat_IfHCOutBadOctets = + ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) + + (uint64_t)stats->stat_IfHCOutBadOctets_lo; + + sc->stat_IfHCInUcastPkts = + ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) + + (uint64_t)stats->stat_IfHCInUcastPkts_lo; + + sc->stat_IfHCInMulticastPkts = + ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) + + (uint64_t)stats->stat_IfHCInMulticastPkts_lo; + + sc->stat_IfHCInBroadcastPkts = + ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) + + (uint64_t)stats->stat_IfHCInBroadcastPkts_lo; + + sc->stat_IfHCOutUcastPkts = + ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) + + (uint64_t)stats->stat_IfHCOutUcastPkts_lo; + + sc->stat_IfHCOutMulticastPkts = + ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) + + (uint64_t)stats->stat_IfHCOutMulticastPkts_lo; + + sc->stat_IfHCOutBroadcastPkts = + ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) + + (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo; + + sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = + stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + + sc->stat_Dot3StatsCarrierSenseErrors = + stats->stat_Dot3StatsCarrierSenseErrors; + + sc->stat_Dot3StatsFCSErrors = + stats->stat_Dot3StatsFCSErrors; + + sc->stat_Dot3StatsAlignmentErrors = + stats->stat_Dot3StatsAlignmentErrors; + + sc->stat_Dot3StatsSingleCollisionFrames = + stats->stat_Dot3StatsSingleCollisionFrames; + + sc->stat_Dot3StatsMultipleCollisionFrames = + stats->stat_Dot3StatsMultipleCollisionFrames; + + sc->stat_Dot3StatsDeferredTransmissions = + stats->stat_Dot3StatsDeferredTransmissions; + + sc->stat_Dot3StatsExcessiveCollisions = + stats->stat_Dot3StatsExcessiveCollisions; + + sc->stat_Dot3StatsLateCollisions = + stats->stat_Dot3StatsLateCollisions; + + sc->stat_EtherStatsCollisions = + stats->stat_EtherStatsCollisions; + + sc->stat_EtherStatsFragments = + stats->stat_EtherStatsFragments; + + sc->stat_EtherStatsJabbers = + stats->stat_EtherStatsJabbers; + + sc->stat_EtherStatsUndersizePkts = + stats->stat_EtherStatsUndersizePkts; + + sc->stat_EtherStatsOverrsizePkts = + stats->stat_EtherStatsOverrsizePkts; + + sc->stat_EtherStatsPktsRx64Octets = + stats->stat_EtherStatsPktsRx64Octets; + + sc->stat_EtherStatsPktsRx65Octetsto127Octets = + stats->stat_EtherStatsPktsRx65Octetsto127Octets; + + sc->stat_EtherStatsPktsRx128Octetsto255Octets = + stats->stat_EtherStatsPktsRx128Octetsto255Octets; + + sc->stat_EtherStatsPktsRx256Octetsto511Octets = + stats->stat_EtherStatsPktsRx256Octetsto511Octets; + + sc->stat_EtherStatsPktsRx512Octetsto1023Octets = + stats->stat_EtherStatsPktsRx512Octetsto1023Octets; + + sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = + stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; + + sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = + stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; + + sc->stat_EtherStatsPktsTx64Octets = + stats->stat_EtherStatsPktsTx64Octets; + + sc->stat_EtherStatsPktsTx65Octetsto127Octets = + stats->stat_EtherStatsPktsTx65Octetsto127Octets; + + sc->stat_EtherStatsPktsTx128Octetsto255Octets = + stats->stat_EtherStatsPktsTx128Octetsto255Octets; + + sc->stat_EtherStatsPktsTx256Octetsto511Octets = + stats->stat_EtherStatsPktsTx256Octetsto511Octets; + + sc->stat_EtherStatsPktsTx512Octetsto1023Octets = + stats->stat_EtherStatsPktsTx512Octetsto1023Octets; + + sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = + stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; + + sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = + stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; + + sc->stat_XonPauseFramesReceived = + stats->stat_XonPauseFramesReceived; + + sc->stat_XoffPauseFramesReceived = + stats->stat_XoffPauseFramesReceived; + + sc->stat_OutXonSent = + stats->stat_OutXonSent; + + sc->stat_OutXoffSent = + stats->stat_OutXoffSent; + + sc->stat_FlowControlDone = + stats->stat_FlowControlDone; + + sc->stat_MacControlFramesReceived = + stats->stat_MacControlFramesReceived; + + sc->stat_XoffStateEntered = + stats->stat_XoffStateEntered; + + sc->stat_IfInFramesL2FilterDiscards = + stats->stat_IfInFramesL2FilterDiscards; + + sc->stat_IfInRuleCheckerDiscards = + stats->stat_IfInRuleCheckerDiscards; + + sc->stat_IfInFTQDiscards = + stats->stat_IfInFTQDiscards; + + sc->stat_IfInMBUFDiscards = + stats->stat_IfInMBUFDiscards; + + sc->stat_IfInRuleCheckerP4Hit = + stats->stat_IfInRuleCheckerP4Hit; + + sc->stat_CatchupInRuleCheckerDiscards = + stats->stat_CatchupInRuleCheckerDiscards; + + sc->stat_CatchupInFTQDiscards = + stats->stat_CatchupInFTQDiscards; + + sc->stat_CatchupInMBUFDiscards = + stats->stat_CatchupInMBUFDiscards; + + sc->stat_CatchupInRuleCheckerP4Hit = + stats->stat_CatchupInRuleCheckerP4Hit; + + sc->com_no_buffers = REG_RD_IND(sc, 0x120084); + + DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__); +} + + +/****************************************************************************/ +/* Periodic function to perform maintenance tasks. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_tick_serialized(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + struct mii_data *mii; + uint32_t msg; + + ASSERT_SERIALIZED(ifp->if_serializer); + + /* Tell the firmware that the driver is still running. */ +#ifdef BCE_DEBUG + msg = (uint32_t)BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; +#else + msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq; +#endif + REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); + + /* Update the statistics from the hardware statistics block. */ + bce_stats_update(sc); + + /* Schedule the next tick. */ + callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc); + + /* If link is up already up then we're done. */ + if (sc->bce_link) + return; + + mii = device_get_softc(sc->bce_miibus); + mii_tick(mii); + + /* Check if the link has come up. */ + if (!sc->bce_link && (mii->mii_media_status & IFM_ACTIVE) && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->bce_link++; + /* Now that link is up, handle any outstanding TX traffic. */ + if (!ifq_is_empty(&ifp->if_snd)) + ifp->if_start(ifp); + } +} + + +static void +bce_tick(void *xsc) +{ + struct bce_softc *sc = xsc; + struct ifnet *ifp = &sc->arpcom.ac_if; + + lwkt_serialize_enter(ifp->if_serializer); + bce_tick_serialized(sc); + lwkt_serialize_exit(ifp->if_serializer); +} + + +#ifdef BCE_DEBUG +/****************************************************************************/ +/* Allows the driver state to be dumped through the sysctl interface. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_driver_state(sc); + } + + return error; +} + + +/****************************************************************************/ +/* Allows the hardware state to be dumped through the sysctl interface. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_hw_state(sc); + } + + return error; +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allows dumping the RX chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_rx_chain(sc, 0, USABLE_RX_BD); + } + + return error; +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allows dumping the TX chain. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_dump_tx_chain(sc, 0, USABLE_TX_BD); + } + + return error; +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow reading arbitrary registers in the */ +/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) +{ + struct bce_softc *sc; + int error; + uint32_t val, result; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + /* Make sure the register is accessible. */ + if (result < 0x8000) { + sc = (struct bce_softc *)arg1; + val = REG_RD(sc, result); + if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n", + result, val); + } else if (result < 0x0280000) { + sc = (struct bce_softc *)arg1; + val = REG_RD_IND(sc, result); + if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n", + result, val); + } + return (error); +} + + +/****************************************************************************/ +/* Provides a sysctl interface to allow reading arbitrary PHY registers in */ +/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) +{ + struct bce_softc *sc; + device_t dev; + int error, result; + uint16_t val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + /* Make sure the register is accessible. */ + if (result < 0x20) { + sc = (struct bce_softc *)arg1; + dev = sc->bce_dev; + val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); + if_printf(&sc->arpcom.ac_if, + "phy 0x%02X = 0x%04X\n", result, val); + } + return (error); +} + + +/****************************************************************************/ +/* Provides a sysctl interface to forcing the driver to dump state and */ +/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static int +bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) +{ + int error; + int result; + struct bce_softc *sc; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + + if (error || !req->newptr) + return (error); + + if (result == 1) { + sc = (struct bce_softc *)arg1; + bce_breakpoint(sc); + } + + return error; +} +#endif + + +/****************************************************************************/ +/* Adds any sysctl parameters for tuning or debugging purposes. */ +/* */ +/* Returns: */ +/* 0 for success, positive value for failure. */ +/****************************************************************************/ +static void +bce_add_sysctls(struct bce_softc *sc) +{ + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *children; + + sysctl_ctx_init(&sc->bce_sysctl_ctx); + sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx, + SYSCTL_STATIC_CHILDREN(_hw), + OID_AUTO, + device_get_nameunit(sc->bce_dev), + CTLFLAG_RD, 0, ""); + if (sc->bce_sysctl_tree == NULL) { + device_printf(sc->bce_dev, "can't add sysctl node\n"); + return; + } + + ctx = &sc->bce_sysctl_ctx; + children = SYSCTL_CHILDREN(sc->bce_sysctl_tree); + +#ifdef BCE_DEBUG + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "rx_low_watermark", + CTLFLAG_RD, &sc->rx_low_watermark, + 0, "Lowest level of free rx_bd's"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "rx_empty_count", + CTLFLAG_RD, &sc->rx_empty_count, + 0, "Number of times the RX chain was empty"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "tx_hi_watermark", + CTLFLAG_RD, &sc->tx_hi_watermark, + 0, "Highest level of used tx_bd's"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "tx_full_count", + CTLFLAG_RD, &sc->tx_full_count, + 0, "Number of times the TX chain was full"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "l2fhdr_status_errors", + CTLFLAG_RD, &sc->l2fhdr_status_errors, + 0, "l2_fhdr status errors"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "unexpected_attentions", + CTLFLAG_RD, &sc->unexpected_attentions, + 0, "unexpected attentions"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "lost_status_block_updates", + CTLFLAG_RD, &sc->lost_status_block_updates, + 0, "lost status block updates"); + + SYSCTL_ADD_INT(ctx, children, OID_AUTO, + "mbuf_alloc_failed", + CTLFLAG_RD, &sc->mbuf_alloc_failed, + 0, "mbuf cluster allocation failures"); +#endif + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHcInOctets", + CTLFLAG_RD, &sc->stat_IfHCInOctets, + "Bytes received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInBadOctets", + CTLFLAG_RD, &sc->stat_IfHCInBadOctets, + "Bad bytes received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutOctets", + CTLFLAG_RD, &sc->stat_IfHCOutOctets, + "Bytes sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutBadOctets", + CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, + "Bad bytes sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInUcastPkts", + CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, + "Unicast packets received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInMulticastPkts", + CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, + "Multicast packets received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCInBroadcastPkts", + CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, + "Broadcast packets received"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutUcastPkts", + CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, + "Unicast packets sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutMulticastPkts", + CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, + "Multicast packets sent"); + + SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, + "stat_IfHCOutBroadcastPkts", + CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, + "Broadcast packets sent"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", + CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, + 0, "Internal MAC transmit errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsCarrierSenseErrors", + CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, + 0, "Carrier sense errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsFCSErrors", + CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, + 0, "Frame check sequence errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsAlignmentErrors", + CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, + 0, "Alignment errors"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsSingleCollisionFrames", + CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, + 0, "Single Collision Frames"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsMultipleCollisionFrames", + CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, + 0, "Multiple Collision Frames"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsDeferredTransmissions", + CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, + 0, "Deferred Transmissions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsExcessiveCollisions", + CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, + 0, "Excessive Collisions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_Dot3StatsLateCollisions", + CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, + 0, "Late Collisions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsCollisions", + CTLFLAG_RD, &sc->stat_EtherStatsCollisions, + 0, "Collisions"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsFragments", + CTLFLAG_RD, &sc->stat_EtherStatsFragments, + 0, "Fragments"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsJabbers", + CTLFLAG_RD, &sc->stat_EtherStatsJabbers, + 0, "Jabbers"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsUndersizePkts", + CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, + 0, "Undersize packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsOverrsizePkts", + CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts, + 0, "stat_EtherStatsOverrsizePkts"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx64Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, + 0, "Bytes received in 64 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx65Octetsto127Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, + 0, "Bytes received in 65 to 127 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx128Octetsto255Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, + 0, "Bytes received in 128 to 255 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx256Octetsto511Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, + 0, "Bytes received in 256 to 511 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx512Octetsto1023Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, + 0, "Bytes received in 512 to 1023 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx1024Octetsto1522Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, + 0, "Bytes received in 1024 t0 1522 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsRx1523Octetsto9022Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, + 0, "Bytes received in 1523 to 9022 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx64Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, + 0, "Bytes sent in 64 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx65Octetsto127Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, + 0, "Bytes sent in 65 to 127 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx128Octetsto255Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, + 0, "Bytes sent in 128 to 255 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx256Octetsto511Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, + 0, "Bytes sent in 256 to 511 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx512Octetsto1023Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, + 0, "Bytes sent in 512 to 1023 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx1024Octetsto1522Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, + 0, "Bytes sent in 1024 to 1522 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_EtherStatsPktsTx1523Octetsto9022Octets", + CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, + 0, "Bytes sent in 1523 to 9022 byte packets"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_XonPauseFramesReceived", + CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, + 0, "XON pause frames receved"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_XoffPauseFramesReceived", + CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, + 0, "XOFF pause frames received"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_OutXonSent", + CTLFLAG_RD, &sc->stat_OutXonSent, + 0, "XON pause frames sent"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_OutXoffSent", + CTLFLAG_RD, &sc->stat_OutXoffSent, + 0, "XOFF pause frames sent"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_FlowControlDone", + CTLFLAG_RD, &sc->stat_FlowControlDone, + 0, "Flow control done"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_MacControlFramesReceived", + CTLFLAG_RD, &sc->stat_MacControlFramesReceived, + 0, "MAC control frames received"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_XoffStateEntered", + CTLFLAG_RD, &sc->stat_XoffStateEntered, + 0, "XOFF state entered"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInFramesL2FilterDiscards", + CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, + 0, "Received L2 packets discarded"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInRuleCheckerDiscards", + CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, + 0, "Received packets discarded by rule"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInFTQDiscards", + CTLFLAG_RD, &sc->stat_IfInFTQDiscards, + 0, "Received packet FTQ discards"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInMBUFDiscards", + CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, + 0, "Received packets discarded due to lack of controller buffer memory"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_IfInRuleCheckerP4Hit", + CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, + 0, "Received packets rule checker hits"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInRuleCheckerDiscards", + CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, + 0, "Received packets discarded in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInFTQDiscards", + CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, + 0, "Received packets discarded in FTQ in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInMBUFDiscards", + CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, + 0, "Received packets discarded in controller buffer memory in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "stat_CatchupInRuleCheckerP4Hit", + CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, + 0, "Received packets rule checker hits in Catchup path"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, + "com_no_buffers", + CTLFLAG_RD, &sc->com_no_buffers, + 0, "Valid packets received but no RX buffers available"); + +#ifdef BCE_DEBUG + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "driver_state", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_driver_state, "I", "Drive state information"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "hw_state", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_hw_state, "I", "Hardware state information"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "breakpoint", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_breakpoint, "I", "Driver breakpoint"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "reg_read", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_reg_read, "I", "Register read"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, + "phy_read", CTLTYPE_INT | CTLFLAG_RW, + (void *)sc, 0, + bce_sysctl_phy_read, "I", "PHY register read"); + +#endif + +} + + +/****************************************************************************/ +/* BCE Debug Routines */ +/****************************************************************************/ +#ifdef BCE_DEBUG + +/****************************************************************************/ +/* Freezes the controller to allow for a cohesive state dump. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_freeze_controller(struct bce_softc *sc) +{ + uint32_t val; + + val = REG_RD(sc, BCE_MISC_COMMAND); + val |= BCE_MISC_COMMAND_DISABLE_ALL; + REG_WR(sc, BCE_MISC_COMMAND, val); +} + + +/****************************************************************************/ +/* Unfreezes the controller after a freeze operation. This may not always */ +/* work and the controller will require a reset! */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_unfreeze_controller(struct bce_softc *sc) +{ + uint32_t val; + + val = REG_RD(sc, BCE_MISC_COMMAND); + val |= BCE_MISC_COMMAND_ENABLE_ALL; + REG_WR(sc, BCE_MISC_COMMAND, val); +} + + +/****************************************************************************/ +/* Prints out information about an mbuf. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val_hi, val_lo; + struct mbuf *mp = m; + + if (m == NULL) { + /* Index out of range. */ + if_printf(ifp, "mbuf: null pointer\n"); + return; + } + + while (mp) { + val_hi = BCE_ADDR_HI(mp); + val_lo = BCE_ADDR_LO(mp); + if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, " + "m_flags = ( ", val_hi, val_lo, mp->m_len); + + if (mp->m_flags & M_EXT) + kprintf("M_EXT "); + if (mp->m_flags & M_PKTHDR) + kprintf("M_PKTHDR "); + if (mp->m_flags & M_EOR) + kprintf("M_EOR "); +#ifdef M_RDONLY + if (mp->m_flags & M_RDONLY) + kprintf("M_RDONLY "); +#endif + + val_hi = BCE_ADDR_HI(mp->m_data); + val_lo = BCE_ADDR_LO(mp->m_data); + kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo); + + if (mp->m_flags & M_PKTHDR) { + if_printf(ifp, "- m_pkthdr: flags = ( "); + if (mp->m_flags & M_BCAST) + kprintf("M_BCAST "); + if (mp->m_flags & M_MCAST) + kprintf("M_MCAST "); + if (mp->m_flags & M_FRAG) + kprintf("M_FRAG "); + if (mp->m_flags & M_FIRSTFRAG) + kprintf("M_FIRSTFRAG "); + if (mp->m_flags & M_LASTFRAG) + kprintf("M_LASTFRAG "); +#ifdef M_VLANTAG + if (mp->m_flags & M_VLANTAG) + kprintf("M_VLANTAG "); +#endif +#ifdef M_PROMISC + if (mp->m_flags & M_PROMISC) + kprintf("M_PROMISC "); +#endif + kprintf(") csum_flags = ( "); + if (mp->m_pkthdr.csum_flags & CSUM_IP) + kprintf("CSUM_IP "); + if (mp->m_pkthdr.csum_flags & CSUM_TCP) + kprintf("CSUM_TCP "); + if (mp->m_pkthdr.csum_flags & CSUM_UDP) + kprintf("CSUM_UDP "); + if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS) + kprintf("CSUM_IP_FRAGS "); + if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT) + kprintf("CSUM_FRAGMENT "); +#ifdef CSUM_TSO + if (mp->m_pkthdr.csum_flags & CSUM_TSO) + kprintf("CSUM_TSO "); +#endif + if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED) + kprintf("CSUM_IP_CHECKED "); + if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID) + kprintf("CSUM_IP_VALID "); + if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID) + kprintf("CSUM_DATA_VALID "); + kprintf(")\n"); + } + + if (mp->m_flags & M_EXT) { + val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf); + val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf); + if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, " + "ext_size = %d\n", + val_hi, val_lo, mp->m_ext.ext_size); + } + mp = mp->m_next; + } +} + + +/****************************************************************************/ +/* Prints out the mbufs in the TX mbuf chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + int i; + + if_printf(ifp, + "----------------------------" + " tx mbuf data " + "----------------------------\n"); + + for (i = 0; i < count; i++) { + if_printf(ifp, "txmbuf[%d]\n", chain_prod); + bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]); + chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the mbufs in the RX mbuf chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + int i; + + if_printf(ifp, + "----------------------------" + " rx mbuf data " + "----------------------------\n"); + + for (i = 0; i < count; i++) { + if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod); + bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]); + chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out a tx_bd structure. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + + if (idx > MAX_TX_BD) { + /* Index out of range. */ + if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); + } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) { + /* TX Chain page pointer. */ + if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, " + "chain page pointer\n", + idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); + } else { + /* Normal tx_bd entry. */ + if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, " + "nbytes = 0x%08X, " + "vlan tag= 0x%04X, flags = 0x%04X (", + idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, + txbd->tx_bd_mss_nbytes, + txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) + kprintf(" CONN_FAULT"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) + kprintf(" TCP_UDP_CKSUM"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) + kprintf(" IP_CKSUM"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) + kprintf(" VLAN"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) + kprintf(" COAL_NOW"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) + kprintf(" DONT_GEN_CRC"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_START) + kprintf(" START"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_END) + kprintf(" END"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) + kprintf(" LSO"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) + kprintf(" OPTION_WORD"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) + kprintf(" FLAGS"); + + if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) + kprintf(" SNAP"); + + kprintf(" )\n"); + } +} + + +/****************************************************************************/ +/* Prints out a rx_bd structure. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + + if (idx > MAX_RX_BD) { + /* Index out of range. */ + if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); + } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) { + /* TX Chain page pointer. */ + if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, " + "chain page pointer\n", + idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); + } else { + /* Normal tx_bd entry. */ + if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, " + "nbytes = 0x%08X, flags = 0x%08X\n", + idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, + rxbd->rx_bd_len, rxbd->rx_bd_flags); + } +} + + +/****************************************************************************/ +/* Prints out a l2_fhdr structure. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) +{ + if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, " + "pkt_len = 0x%04X, vlan = 0x%04x, " + "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n", + idx, l2fhdr->l2_fhdr_status, + l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, + l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); +} + + +/****************************************************************************/ +/* Prints out the tx chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + int i; + + /* First some info about the tx_bd chain structure. */ + if_printf(ifp, + "----------------------------" + " tx_bd chain " + "----------------------------\n"); + + if_printf(ifp, "page size = 0x%08X, " + "tx chain pages = 0x%08X\n", + (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES); + + if_printf(ifp, "tx_bd per page = 0x%08X, " + "usable tx_bd per page = 0x%08X\n", + (uint32_t)TOTAL_TX_BD_PER_PAGE, + (uint32_t)USABLE_TX_BD_PER_PAGE); + + if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD); + + if_printf(ifp, + "----------------------------" + " tx_bd data " + "----------------------------\n"); + + /* Now print out the tx_bd's themselves. */ + for (i = 0; i < count; i++) { + struct tx_bd *txbd; + + txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; + bce_dump_txbd(sc, tx_prod, txbd); + tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the rx chain. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + int i; + + /* First some info about the tx_bd chain structure. */ + if_printf(ifp, + "----------------------------" + " rx_bd chain " + "----------------------------\n"); + + if_printf(ifp, "page size = 0x%08X, " + "rx chain pages = 0x%08X\n", + (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES); + + if_printf(ifp, "rx_bd per page = 0x%08X, " + "usable rx_bd per page = 0x%08X\n", + (uint32_t)TOTAL_RX_BD_PER_PAGE, + (uint32_t)USABLE_RX_BD_PER_PAGE); + + if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD); + + if_printf(ifp, + "----------------------------" + " rx_bd data " + "----------------------------\n"); + + /* Now print out the rx_bd's themselves. */ + for (i = 0; i < count; i++) { + struct rx_bd *rxbd; + + rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; + bce_dump_rxbd(sc, rx_prod, rxbd); + rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the status block from host memory. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_status_block(struct bce_softc *sc) +{ + struct status_block *sblk = sc->status_block; + struct ifnet *ifp = &sc->arpcom.ac_if; + + if_printf(ifp, + "----------------------------" + " Status Block " + "----------------------------\n"); + + if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits); + + if_printf(ifp, " 0x%08X - attn_bits_ack\n", + sblk->status_attn_bits_ack); + + if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n", + sblk->status_rx_quick_consumer_index0, + (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0)); + + if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n", + sblk->status_tx_quick_consumer_index0, + (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0)); + + if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx); + + /* Theses indices are not used for normal L2 drivers. */ + if (sblk->status_rx_quick_consumer_index1) { + if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n", + sblk->status_rx_quick_consumer_index1, + (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1)); + } + + if (sblk->status_tx_quick_consumer_index1) { + if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n", + sblk->status_tx_quick_consumer_index1, + (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1)); + } + + if (sblk->status_rx_quick_consumer_index2) { + if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n", + sblk->status_rx_quick_consumer_index2, + (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2)); + } + + if (sblk->status_tx_quick_consumer_index2) { + if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n", + sblk->status_tx_quick_consumer_index2, + (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2)); + } + + if (sblk->status_rx_quick_consumer_index3) { + if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n", + sblk->status_rx_quick_consumer_index3, + (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3)); + } + + if (sblk->status_tx_quick_consumer_index3) { + if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n", + sblk->status_tx_quick_consumer_index3, + (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3)); + } + + if (sblk->status_rx_quick_consumer_index4 || + sblk->status_rx_quick_consumer_index5) { + if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", + sblk->status_rx_quick_consumer_index4, + sblk->status_rx_quick_consumer_index5); + } + + if (sblk->status_rx_quick_consumer_index6 || + sblk->status_rx_quick_consumer_index7) { + if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", + sblk->status_rx_quick_consumer_index6, + sblk->status_rx_quick_consumer_index7); + } + + if (sblk->status_rx_quick_consumer_index8 || + sblk->status_rx_quick_consumer_index9) { + if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", + sblk->status_rx_quick_consumer_index8, + sblk->status_rx_quick_consumer_index9); + } + + if (sblk->status_rx_quick_consumer_index10 || + sblk->status_rx_quick_consumer_index11) { + if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", + sblk->status_rx_quick_consumer_index10, + sblk->status_rx_quick_consumer_index11); + } + + if (sblk->status_rx_quick_consumer_index12 || + sblk->status_rx_quick_consumer_index13) { + if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", + sblk->status_rx_quick_consumer_index12, + sblk->status_rx_quick_consumer_index13); + } + + if (sblk->status_rx_quick_consumer_index14 || + sblk->status_rx_quick_consumer_index15) { + if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", + sblk->status_rx_quick_consumer_index14, + sblk->status_rx_quick_consumer_index15); + } + + if (sblk->status_completion_producer_index || + sblk->status_cmd_consumer_index) { + if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", + sblk->status_completion_producer_index, + sblk->status_cmd_consumer_index); + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the statistics block. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_stats_block(struct bce_softc *sc) +{ + struct statistics_block *sblk = sc->stats_block; + struct ifnet *ifp = &sc->arpcom.ac_if; + + if_printf(ifp, + "---------------" + " Stats Block (All Stats Not Shown Are 0) " + "---------------\n"); + + if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n", + sblk->stat_IfHCInOctets_hi, + sblk->stat_IfHCInOctets_lo); + } + + if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n", + sblk->stat_IfHCInBadOctets_hi, + sblk->stat_IfHCInBadOctets_lo); + } + + if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n", + sblk->stat_IfHCOutOctets_hi, + sblk->stat_IfHCOutOctets_lo); + } + + if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n", + sblk->stat_IfHCOutBadOctets_hi, + sblk->stat_IfHCOutBadOctets_lo); + } + + if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n", + sblk->stat_IfHCInUcastPkts_hi, + sblk->stat_IfHCInUcastPkts_lo); + } + + if (sblk->stat_IfHCInBroadcastPkts_hi || + sblk->stat_IfHCInBroadcastPkts_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n", + sblk->stat_IfHCInBroadcastPkts_hi, + sblk->stat_IfHCInBroadcastPkts_lo); + } + + if (sblk->stat_IfHCInMulticastPkts_hi || + sblk->stat_IfHCInMulticastPkts_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n", + sblk->stat_IfHCInMulticastPkts_hi, + sblk->stat_IfHCInMulticastPkts_lo); + } + + if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n", + sblk->stat_IfHCOutUcastPkts_hi, + sblk->stat_IfHCOutUcastPkts_lo); + } + + if (sblk->stat_IfHCOutBroadcastPkts_hi || + sblk->stat_IfHCOutBroadcastPkts_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n", + sblk->stat_IfHCOutBroadcastPkts_hi, + sblk->stat_IfHCOutBroadcastPkts_lo); + } + + if (sblk->stat_IfHCOutMulticastPkts_hi || + sblk->stat_IfHCOutMulticastPkts_lo) { + if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n", + sblk->stat_IfHCOutMulticastPkts_hi, + sblk->stat_IfHCOutMulticastPkts_lo); + } + + if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) { + if_printf(ifp, " 0x%08X : " + "emac_tx_stat_dot3statsinternalmactransmiterrors\n", + sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); + } + + if (sblk->stat_Dot3StatsCarrierSenseErrors) { + if_printf(ifp, " 0x%08X : " + "Dot3StatsCarrierSenseErrors\n", + sblk->stat_Dot3StatsCarrierSenseErrors); + } + + if (sblk->stat_Dot3StatsFCSErrors) { + if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n", + sblk->stat_Dot3StatsFCSErrors); + } + + if (sblk->stat_Dot3StatsAlignmentErrors) { + if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n", + sblk->stat_Dot3StatsAlignmentErrors); + } + + if (sblk->stat_Dot3StatsSingleCollisionFrames) { + if_printf(ifp, " 0x%08X : " + "Dot3StatsSingleCollisionFrames\n", + sblk->stat_Dot3StatsSingleCollisionFrames); + } + + if (sblk->stat_Dot3StatsMultipleCollisionFrames) { + if_printf(ifp, " 0x%08X : " + "Dot3StatsMultipleCollisionFrames\n", + sblk->stat_Dot3StatsMultipleCollisionFrames); + } + + if (sblk->stat_Dot3StatsDeferredTransmissions) { + if_printf(ifp, " 0x%08X : " + "Dot3StatsDeferredTransmissions\n", + sblk->stat_Dot3StatsDeferredTransmissions); + } + + if (sblk->stat_Dot3StatsExcessiveCollisions) { + if_printf(ifp, " 0x%08X : " + "Dot3StatsExcessiveCollisions\n", + sblk->stat_Dot3StatsExcessiveCollisions); + } + + if (sblk->stat_Dot3StatsLateCollisions) { + if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n", + sblk->stat_Dot3StatsLateCollisions); + } + + if (sblk->stat_EtherStatsCollisions) { + if_printf(ifp, " 0x%08X : EtherStatsCollisions\n", + sblk->stat_EtherStatsCollisions); + } + + if (sblk->stat_EtherStatsFragments) { + if_printf(ifp, " 0x%08X : EtherStatsFragments\n", + sblk->stat_EtherStatsFragments); + } + + if (sblk->stat_EtherStatsJabbers) { + if_printf(ifp, " 0x%08X : EtherStatsJabbers\n", + sblk->stat_EtherStatsJabbers); + } + + if (sblk->stat_EtherStatsUndersizePkts) { + if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n", + sblk->stat_EtherStatsUndersizePkts); + } + + if (sblk->stat_EtherStatsOverrsizePkts) { + if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n", + sblk->stat_EtherStatsOverrsizePkts); + } + + if (sblk->stat_EtherStatsPktsRx64Octets) { + if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n", + sblk->stat_EtherStatsPktsRx64Octets); + } + + if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsRx65Octetsto127Octets\n", + sblk->stat_EtherStatsPktsRx65Octetsto127Octets); + } + + if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsRx128Octetsto255Octets\n", + sblk->stat_EtherStatsPktsRx128Octetsto255Octets); + } + + if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsRx256Octetsto511Octets\n", + sblk->stat_EtherStatsPktsRx256Octetsto511Octets); + } + + if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsRx512Octetsto1023Octets\n", + sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); + } + + if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsRx1024Octetsto1522Octets\n", + sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); + } + + if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsRx1523Octetsto9022Octets\n", + sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); + } + + if (sblk->stat_EtherStatsPktsTx64Octets) { + if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n", + sblk->stat_EtherStatsPktsTx64Octets); + } + + if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsTx65Octetsto127Octets\n", + sblk->stat_EtherStatsPktsTx65Octetsto127Octets); + } + + if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsTx128Octetsto255Octets\n", + sblk->stat_EtherStatsPktsTx128Octetsto255Octets); + } + + if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsTx256Octetsto511Octets\n", + sblk->stat_EtherStatsPktsTx256Octetsto511Octets); + } + + if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsTx512Octetsto1023Octets\n", + sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); + } + + if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsTx1024Octetsto1522Octets\n", + sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); + } + + if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) { + if_printf(ifp, " 0x%08X : " + "EtherStatsPktsTx1523Octetsto9022Octets\n", + sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); + } + + if (sblk->stat_XonPauseFramesReceived) { + if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n", + sblk->stat_XonPauseFramesReceived); + } + + if (sblk->stat_XoffPauseFramesReceived) { + if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n", + sblk->stat_XoffPauseFramesReceived); + } + + if (sblk->stat_OutXonSent) { + if_printf(ifp, " 0x%08X : OutXoffSent\n", + sblk->stat_OutXonSent); + } + + if (sblk->stat_OutXoffSent) { + if_printf(ifp, " 0x%08X : OutXoffSent\n", + sblk->stat_OutXoffSent); + } + + if (sblk->stat_FlowControlDone) { + if_printf(ifp, " 0x%08X : FlowControlDone\n", + sblk->stat_FlowControlDone); + } + + if (sblk->stat_MacControlFramesReceived) { + if_printf(ifp, " 0x%08X : MacControlFramesReceived\n", + sblk->stat_MacControlFramesReceived); + } + + if (sblk->stat_XoffStateEntered) { + if_printf(ifp, " 0x%08X : XoffStateEntered\n", + sblk->stat_XoffStateEntered); + } + + if (sblk->stat_IfInFramesL2FilterDiscards) { + if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards); + } + + if (sblk->stat_IfInRuleCheckerDiscards) { + if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n", + sblk->stat_IfInRuleCheckerDiscards); + } + + if (sblk->stat_IfInFTQDiscards) { + if_printf(ifp, " 0x%08X : IfInFTQDiscards\n", + sblk->stat_IfInFTQDiscards); + } + + if (sblk->stat_IfInMBUFDiscards) { + if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n", + sblk->stat_IfInMBUFDiscards); + } + + if (sblk->stat_IfInRuleCheckerP4Hit) { + if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n", + sblk->stat_IfInRuleCheckerP4Hit); + } + + if (sblk->stat_CatchupInRuleCheckerDiscards) { + if_printf(ifp, " 0x%08X : " + "CatchupInRuleCheckerDiscards\n", + sblk->stat_CatchupInRuleCheckerDiscards); + } + + if (sblk->stat_CatchupInFTQDiscards) { + if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n", + sblk->stat_CatchupInFTQDiscards); + } + + if (sblk->stat_CatchupInMBUFDiscards) { + if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n", + sblk->stat_CatchupInMBUFDiscards); + } + + if (sblk->stat_CatchupInRuleCheckerP4Hit) { + if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n", + sblk->stat_CatchupInRuleCheckerP4Hit); + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out a summary of the driver state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_driver_state(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val_hi, val_lo; + + if_printf(ifp, + "-----------------------------" + " Driver State " + "-----------------------------\n"); + + val_hi = BCE_ADDR_HI(sc); + val_lo = BCE_ADDR_LO(sc); + if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->status_block); + val_lo = BCE_ADDR_LO(sc->status_block); + if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->stats_block); + val_lo = BCE_ADDR_LO(sc->stats_block); + if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->tx_bd_chain); + val_lo = BCE_ADDR_LO(sc->tx_bd_chain); + if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " + "virtual adddress\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->rx_bd_chain); + val_lo = BCE_ADDR_LO(sc->rx_bd_chain); + if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); + val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); + if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " + "virtual address\n", val_hi, val_lo); + + val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); + val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); + if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " + "virtual address\n", val_hi, val_lo); + + if_printf(ifp, " 0x%08X - (sc->interrupts_generated) " + "h/w intrs\n", sc->interrupts_generated); + + if_printf(ifp, " 0x%08X - (sc->rx_interrupts) " + "rx interrupts handled\n", sc->rx_interrupts); + + if_printf(ifp, " 0x%08X - (sc->tx_interrupts) " + "tx interrupts handled\n", sc->tx_interrupts); + + if_printf(ifp, " 0x%08X - (sc->last_status_idx) " + "status block index\n", sc->last_status_idx); + + if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) " + "tx producer index\n", + sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod)); + + if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) " + "tx consumer index\n", + sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons)); + + if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) " + "tx producer bseq index\n", sc->tx_prod_bseq); + + if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) " + "rx producer index\n", + sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod)); + + if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) " + "rx consumer index\n", + sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons)); + + if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) " + "rx producer bseq index\n", sc->rx_prod_bseq); + + if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) " + "rx mbufs allocated\n", sc->rx_mbuf_alloc); + + if_printf(ifp, " 0x%08X - (sc->free_rx_bd) " + "free rx_bd's\n", sc->free_rx_bd); + + if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx " + "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd); + + if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) " + "tx mbufs allocated\n", sc->tx_mbuf_alloc); + + if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) " + "rx mbufs allocated\n", sc->rx_mbuf_alloc); + + if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", + sc->used_tx_bd); + + if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", + sc->tx_hi_watermark, sc->max_tx_bd); + + if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) " + "failed mbuf alloc\n", sc->mbuf_alloc_failed); + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the hardware state through a summary of important registers, */ +/* followed by a complete register dump. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_hw_state(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val1; + int i; + + if_printf(ifp, + "----------------------------" + " Hardware State " + "----------------------------\n"); + + if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver); + + val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); + if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n", + val1, BCE_MISC_ENABLE_STATUS_BITS); + + val1 = REG_RD(sc, BCE_DMA_STATUS); + if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS); + + val1 = REG_RD(sc, BCE_CTX_STATUS); + if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS); + + val1 = REG_RD(sc, BCE_EMAC_STATUS); + if_printf(ifp, "0x%08X - (0x%04X) emac_status\n", + val1, BCE_EMAC_STATUS); + + val1 = REG_RD(sc, BCE_RPM_STATUS); + if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS); + + val1 = REG_RD(sc, BCE_TBDR_STATUS); + if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n", + val1, BCE_TBDR_STATUS); + + val1 = REG_RD(sc, BCE_TDMA_STATUS); + if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n", + val1, BCE_TDMA_STATUS); + + val1 = REG_RD(sc, BCE_HC_STATUS); + if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS); + + val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n", + val1, BCE_TXP_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n", + val1, BCE_TPAT_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n", + val1, BCE_RXP_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n", + val1, BCE_COM_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n", + val1, BCE_MCP_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n", + val1, BCE_CP_CPU_STATE); + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); + + if_printf(ifp, + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (i = 0x400; i < 0x8000; i += 0x10) { + if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, + REG_RD(sc, i), + REG_RD(sc, i + 0x4), + REG_RD(sc, i + 0x8), + REG_RD(sc, i + 0xc)); + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the TXP state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_txp_state(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val1; + int i; + + if_printf(ifp, + "----------------------------" + " TXP State " + "----------------------------\n"); + + val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE); + if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n", + val1, BCE_TXP_CPU_MODE); + + val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n", + val1, BCE_TXP_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); + if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n", + val1, BCE_TXP_CPU_EVENT_MASK); + + if_printf(ifp, + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { + /* Skip the big blank spaces */ + if (i < 0x454000 && i > 0x5ffff) { + if_printf(ifp, "0x%04X: " + "0x%08X 0x%08X 0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xc)); + } + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the RXP state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_rxp_state(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val1; + int i; + + if_printf(ifp, + "----------------------------" + " RXP State " + "----------------------------\n"); + + val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE); + if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n", + val1, BCE_RXP_CPU_MODE); + + val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n", + val1, BCE_RXP_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); + if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n", + val1, BCE_RXP_CPU_EVENT_MASK); + + if_printf(ifp, + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { + /* Skip the big blank sapces */ + if (i < 0xc5400 && i > 0xdffff) { + if_printf(ifp, "0x%04X: " + "0x%08X 0x%08X 0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xc)); + } + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the TPAT state. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_dump_tpat_state(struct bce_softc *sc) +{ + struct ifnet *ifp = &sc->arpcom.ac_if; + uint32_t val1; + int i; + + if_printf(ifp, + "----------------------------" + " TPAT State " + "----------------------------\n"); + + val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); + if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n", + val1, BCE_TPAT_CPU_MODE); + + val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); + if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n", + val1, BCE_TPAT_CPU_STATE); + + val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); + if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n", + val1, BCE_TPAT_CPU_EVENT_MASK); + + if_printf(ifp, + "----------------------------" + " Register Dump " + "----------------------------\n"); + + for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { + /* Skip the big blank spaces */ + if (i < 0x854000 && i > 0x9ffff) { + if_printf(ifp, "0x%04X: " + "0x%08X 0x%08X 0x%08X 0x%08X\n", i, + REG_RD_IND(sc, i), + REG_RD_IND(sc, i + 0x4), + REG_RD_IND(sc, i + 0x8), + REG_RD_IND(sc, i + 0xc)); + } + } + + if_printf(ifp, + "----------------------------" + "----------------" + "----------------------------\n"); +} + + +/****************************************************************************/ +/* Prints out the driver state and then enters the debugger. */ +/* */ +/* Returns: */ +/* Nothing. */ +/****************************************************************************/ +static void +bce_breakpoint(struct bce_softc *sc) +{ +#if 0 + bce_freeze_controller(sc); +#endif + + bce_dump_driver_state(sc); + bce_dump_status_block(sc); + bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); + bce_dump_hw_state(sc); + bce_dump_txp_state(sc); + +#if 0 + bce_unfreeze_controller(sc); +#endif + + /* Call the debugger. */ + breakpoint(); +} + +#endif /* BCE_DEBUG */ diff --git a/sys/dev/netif/bce/if_bcefw.h b/sys/dev/netif/bce/if_bcefw.h new file mode 100644 index 0000000000..dbabbebdd5 --- /dev/null +++ b/sys/dev/netif/bce/if_bcefw.h @@ -0,0 +1,5716 @@ +/*- + * Copyright (c) 2006-2007 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/bce/if_bcefw.h,v 1.3 2007/05/16 23:34:11 davidch Exp $ + * $DragonFly: src/sys/dev/netif/bce/if_bcefw.h,v 1.1 2007/05/26 08:50:49 sephe Exp $ + */ + +/* + * This file contains firmware data derived from proprietary unpublished + * source code, Copyright (c) 2004, 2005 Broadcom Corporation. + * + * Permission is hereby granted for the distribution of this firmware data + * in hexadecimal or equivalent format, provided this copyright notice is + * accompanying it. + */ + +#define u32 uint32_t + +/* Firmware release 3.4.8 */ + +static int bce_COM_b06FwReleaseMajor = 0x1; +static int bce_COM_b06FwReleaseMinor = 0x0; +static int bce_COM_b06FwReleaseFix = 0x0; +static u32 bce_COM_b06FwStartAddr = 0x080000b4; +static u32 bce_COM_b06FwTextAddr = 0x08000000; +static int bce_COM_b06FwTextLen = 0x7d28; +static u32 bce_COM_b06FwDataAddr = 0x08007de0; +static int bce_COM_b06FwDataLen = 0x0; +static u32 bce_COM_b06FwRodataAddr = 0x08007d28; +static int bce_COM_b06FwRodataLen = 0x88; +static u32 bce_COM_b06FwBssAddr = 0x08007e40; +static int bce_COM_b06FwBssLen = 0x88; +static u32 bce_COM_b06FwSbssAddr = 0x08007de0; +static int bce_COM_b06FwSbssLen = 0x60; +/* static u32 bce_COM_b06FwSDataAddr = 0x00000000; */ +/* static int bce_COM_b06FwSDataLen = 0x0; */ +static u32 bce_COM_b06FwText[(0x7d28/4) + 1] = { +0xa00002d, +0x0, 0x0, 0xd, 0x636f6d20, +0x332e342e, 0x38000000, 0x3040802, 0x0, +0x3, 0x14, 0x32, 0x3, +0x0, 0x0, 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0x3e00008, 0x27bd0020, 0x3c038000, +0x8f420278, 0x431024, 0x1440fffd, 0x24020002, +0x3c031000, 0xaf440240, 0xa3420244, 0x3e00008, +0xaf430278, 0x27bdffe0, 0x3c020008, 0x3421821, +0xafbf0018, 0xaf830038, 0x9062010d, 0x24090001, +0x805021, 0x30c700ff, 0xa001cfd, 0x304800ff, +0x8f820038, 0x9043010e, 0x25040001, 0x308800ff, +0x681826, 0x3182b, 0x31823, 0x1034024, +0x8f830038, 0x9062010c, 0x11020014, 0x81140, +0x24420120, 0x622021, 0x94830000, 0x30630200, +0x1060000f, 0x8fbf0018, 0x8c820018, 0xa21023, +0x440ffeb, 0x0, 0x8c82001c, 0xa21023, +0x1c40ffe7, 0x0, 0xafa50010, 0x1402821, +0xe001d18, 0x1003021, 0x4821, 0x8fbf0018, +0x1201021, 0x3e00008, 0x27bd0020, 0x27bdffd8, +0xafb10014, 0x808821, 0xafb40020, 0xa0a021, +0xafb00010, 0x30d000ff, 0xafb3001c, 0x30f300ff, +0x101080, 0x501021, 0x8f850038, 0x3c030800, +0x8c640020, 0x210c0, 0x24420088, 0xafbf0024, +0xafb20018, 0x1080002e, 0xa29021, 0xe001d7b, +0x0, 0x0, 0x0, 0x0, +0x8f820054, 0xac400000, 0x8f840054, 0x96230000, +0x1411c2, 0x21400, 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0xaf44003c, +0x8ca20020, 0xaf420038, 0x3c020050, 0x34420008, +0xaf420030, 0x0, 0x0, 0x0, +0x8f420000, 0x30420020, 0x1040fffd, 0x0, +0x8f430400, 0x24c67ea0, 0xacc30010, 0x8f420404, +0x3c030020, 0xacc20014, 0xaf430030, 0x94c40018, +0x94c3001c, 0x94c2001a, 0x94c5001e, 0x832021, +0x24420001, 0xa4c2001a, 0x3042ffff, 0x14450002, +0xa4c40018, 0xa4c0001a, 0x3e00008, 0x0, +0x8f82004c, 0x3c030006, 0x21140, 0x431025, +0xaf420030, 0x0, 0x0, 0x0, +0x27430400, 0x8f420000, 0x30420010, 0x1040fffd, +0x0, 0xaf80004c, 0xaf830054, 0x3e00008, +0x0, 0x27bdffe8, 0xafb00010, 0x3c100800, +0x26107ea0, 0x3c05000a, 0x2002021, 0x3452821, +0xafbf0014, 0xe001f35, 0x2406000a, 0x96020002, +0x9603001e, 0x3042000f, 0x24420003, 0x431804, +0x24027fff, 0x43102b, 0xaf830050, 0x10400002, +0x0, 0xd, 0xe001e39, 0x0, +0x8fbf0014, 0x8fb00010, 0x3e00008, 0x27bd0018, +0x8f86003c, 0x8f82005c, 0x8f830058, 0x27bdffe0, +0xafb10014, 0x8821, 0xafbf0018, 0xafb00010, +0x94c50008, 0x24420001, 0x24630020, 0xaf82005c, +0xaf830058, 0x24a50001, 0xa4c50008, 0x8cc3001c, +0x8cc2001c, 0x309000ff, 0x3c048000, 0x24420020, +0x4610008, 0xacc2001c, 0x8cc2001c, 0x441024, +0x14400004, 0x0, 0x8cc20018, 0x24420001, +0xacc20018, 0x8f84003c, 0x94830008, 0x94820010, +0x10620003, 0x0, 0x12000026, 0x0, +0x8f82005c, 0x24110001, 0x3c030006, 0x21140, +0x431025, 0xaf420030, 0x0, 0x0, +0x0, 0x27450400, 0x8f420000, 0x30420010, +0x1040fffd, 0x0, 0x8f82003c, 0x94440008, +0x94430010, 0xaf80005c, 0xaf850058, 0x14830013, +0x0, 0xe001f06, 0x0, 0x1600000f, +0x0, 0x8f84003c, 0x8c820018, 0xaf420038, +0x8c83001c, 0x3c020005, 0xaf43003c, 0xaf420030, +0x27420400, 0xaf80005c, 0xaf820058, 0xa001ed8, +0x0, 0x94820008, 0x94830010, 0x8f84003c, +0x9482000e, 0x24420001, 0xa482000e, 0x9483000e, +0x9482000c, 0x24420001, 0x43102a, 0x10400002, +0x24020001, 0xa482000e, 0x2201021, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020, +0x8f84003c, 0x8c820018, 0xaf420038, 0x8c83001c, +0x3c020005, 0xaf43003c, 0xaf420030, 0x27420400, +0xaf80005c, 0xaf820058, 0x3e00008, 0x0, +0x8f82005c, 0x3c030006, 0x21140, 0x431025, +0xaf420030, 0x0, 0x0, 0x0, +0x27430400, 0x8f420000, 0x30420010, 0x1040fffd, +0x0, 0xaf80005c, 0xaf830058, 0x3e00008, +0x0, 0x8f85003c, 0x8ca40004, 0x94a20012, +0x2403ff00, 0x832024, 0x210c0, 0x821021, +0xaf42003c, 0x8f43003c, 0x832023, 0x18800004, +0x0, 0x8ca20000, 0xa001f16, 0x24420001, +0x8ca20000, 0xaf420038, 0x3c020050, 0x34420008, +0xaf420030, 0x0, 0x0, 0x0, +0x8f420000, 0x30420020, 0x1040fffd, 0x0, +0x8f84003c, 0x8f420400, 0xac820018, 0x8f430404, +0x3c020020, 0xac83001c, 0xaf420030, 0x94830010, +0x9482000a, 0x621821, 0xa4830010, 0x94820012, +0x24420001, 0xa4820012, 0x94830012, 0x94820014, +0x50620001, 0xa4800012, 0x3e00008, 0x0, +0x10c00007, 0x0, 0x8ca20000, 0x24c6ffff, +0x24a50004, 0xac820000, 0x14c0fffb, 0x24840004, +0x3e00008, 0x0, 0xa001f46, 0xa01021, +0xac860000, 0x0, 0x0, 0x24840004, +0xa01021, 0x1440fffa, 0x24a5ffff, 0x3e00008, +0x0, 0x0 }; +static u32 bce_COM_b06FwData[(0x0/4) + 1] = { 0x0 }; +static u32 bce_COM_b06FwRodata[(0x88/4) + 1] = { +0x8001c1c, +0x8001c4c, 0x8001c4c, 0x8001c4c, 0x8001c4c, +0x8001c4c, 0x8001b74, 0x8001c4c, 0x8001bdc, +0x8001c4c, 0x8001b08, 0x8001c4c, 0x8001c4c, +0x8001c4c, 0x8001b14, 0x0, 0x8002b58, +0x8002ba8, 0x8002bd8, 0x8002c08, 0x8002c38, +0x0, 0x80060a0, 0x80060a0, 0x80060a0, +0x80060a0, 0x80060a0, 0x80060d4, 0x80060d4, +0x8006114, 0x8006120, 0x8006120, 0x80060a0, +0x0, 0x0 }; +static u32 bce_COM_b06FwBss[(0x88/4) + 1] = { 0x0 }; +static u32 bce_COM_b06FwSbss[(0x60/4) + 1] = { 0x0 }; +/* static u32 bce_COM_b06FwSdata[(0x0/4) + 1] = { 0x0 }; */ + +static int bce_RXP_b06FwReleaseMajor = 0x1; +static int bce_RXP_b06FwReleaseMinor = 0x0; +static int bce_RXP_b06FwReleaseFix = 0x0; +static u32 bce_RXP_b06FwStartAddr = 0x08003184; +static u32 bce_RXP_b06FwTextAddr = 0x08000000; +static int bce_RXP_b06FwTextLen = 0x6820; +static u32 bce_RXP_b06FwDataAddr = 0x08006ac0; +static int bce_RXP_b06FwDataLen = 0x0; +static u32 bce_RXP_b06FwRodataAddr = 0x08006820; +static int bce_RXP_b06FwRodataLen = 0x278; +static u32 bce_RXP_b06FwBssAddr = 0x08006af0; +static int bce_RXP_b06FwBssLen = 0x13dc; +static u32 bce_RXP_b06FwSbssAddr = 0x08006ac0; +static int bce_RXP_b06FwSbssLen = 0x28; +/* static u32 bce_RXP_b06FwSDataAddr = 0x00000000; */ +/* static int bce_RXP_b06FwSDataLen = 0x0; */ +static u32 bce_RXP_b06FwText[(0x6820/4) + 1] = { +0xa000c61, +0x0, 0x0, 0xd, 0x72787020, +0x332e342e, 0x38000000, 0x3040803, 0x0, +0xd, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, 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+0x2402ff80, 0x2021024, 0x431025, 0xaf420020, +0x8f420020, 0x440fffe, 0x3202007f, 0x3c030008, +0x431021, 0x3421021, 0xafa2003c, 0x8fa4003c, +0x9482001c, 0x3c038000, 0x34630007, 0x34420800, +0xa482001c, 0x2402ff80, 0x2021024, 0x431025, +0xaf420020, 0x8f420020, 0x440fffe, 0x0, +0xaf450020, 0x35ef0020, 0x8fa30038, 0x8fa40038, +0x93460120, 0x8fa20038, 0x9445001a, 0x9463001c, +0x9484001c, 0x8fa20038, 0xafa50010, 0x8c450004, +0x24020010, 0x3063000f, 0xafa20018, 0x24020100, +0x621004, 0x8fa30038, 0x2442ffff, 0xafb2001c, +0xa22824, 0xafa50014, 0x8c620008, 0x8fa30038, +0xafa20020, 0x8e820024, 0x8c63000c, 0x3203821, +0x3084000f, 0xafac0030, 0xafad0034, 0xafa20028, +0xafa30024, 0x9685000a, 0x42200, 0x1e42025, +0xa62821, 0x26660002, 0x30a5ffff, 0xe001943, +0x30c6ffff, 0x1021, 0x8fbf005c, 0x8fb40058, +0x8fb30054, 0x8fb20050, 0x8fb1004c, 0x8fb00048, +0x3e00008, 0x27bd0060, 0x27bdffd0, 0x5821, +0x806021, 0xe06821, 0x8faa0048, 0x97a80042, +0x97a90046, 0x30a5ffff, 0x30c7ffff, 0x31020001, +0x10400006, 0xafbf0028, 0x2d220009, 0x50400004, +0x8da30008, 0xa0017e1, 0x8da3000c, 0x8da30008, +0x2c620003, 0x54400003, 0x30a200c0, 0xa0017e8, +0x2402000d, 0x10400004, 0x2402000c, 0xad420000, +0xa001818, 0x2402ffff, 0x24020001, 0x1062001b, +0x30a2000f, 0x10600005, 0x24020002, 0x10620023, +0x1601021, 0xa001819, 0x8fbf0028, 0x30a6000f, +0x28c20007, 0x1040000f, 0x28c20003, 0x1440001c, +0x24020005, 0x8d820000, 0x8d830024, 0x1802021, +0xafad0010, 0xafa8001c, 0xafa90020, 0xafaa0024, +0xafa20014, 0xe00181b, 0xafa30018, 0xa001817, +0x405821, 0xa001815, 0x24020005, 0x1443000c, +0x24020005, 0x1802021, 0xafa80010, 0xafa90014, +0xafaa0018, 0x8c860000, 0x8c870024, 0xe0018c4, +0x1a02821, 0xa001817, 0x405821, 0x240200ff, +0xad420000, 0x240bffff, 0x1601021, 0x8fbf0028, +0x3e00008, 0x27bd0030, 0x27bdffc0, 0x8f8c001c, +0x97ae005e, 0xafb00038, 0x808021, 0x8fab0050, +0x8faf0064, 0x30a5ffff, 0x30c6ffff, 0xafbf003c, +0x9183018f, 0x9588000a, 0x95890182, 0x918a018c, +0x9182018d, 0x30f9ffff, 0x97b80062, 0x304d00ff, +0x31902, 0x24020001, 0x621004, 0x3108ffff, +0x15aa0005, 0x3129ffff, 0x15280031, 0x24020011, +0xa001865, 0x24020080, 0x2442ffff, 0x1a26824, +0x31c20001, 0x1040000f, 0x2f020011, 0x1040000d, +0x3c020800, 0x24426a50, 0x181880, 0x621821, +0x8c620000, 0x400008, 0x0, 0x8d640010, +0xa00184c, 0x8d6b0014, 0x8d64000c, 0xa00184c, +0x8d6b0014, 0x8d64000c, 0x8d6b0010, 0x8d820228, +0x2723ffee, 0x24420001, 0x10820003, 0x3063ffff, +0xa001865, 0x2402000f, 0xd10c0, 0x4d1023, +0x21080, 0x244201a0, 0x1825021, 0x8d440014, +0x164102b, 0x10400009, 0x3821, 0x1631821, +0x2462ffff, 0x4b102b, 0x14400005, 0x24020013, +0x83102b, 0x50400005, 0x30a24000, 0x24020012, +0xade20000, 0xa0018c0, 0x2402ffff, 0x50400028, +0x24050001, 0xa5430012, 0x8fa20054, 0xad420018, +0x24020005, 0x10c2000f, 0x28c20006, 0x10400005, +0x24020004, 0x10c20008, 0x24050001, 0xa001884, +0x91420007, 0x24020006, 0x10c20009, 0x24050001, +0xa001884, 0x91420007, 0x24070040, 0xa001883, +0x24050003, 0x24070020, 0xa001883, 0x24050002, +0x24070060, 0x24050004, 0x91420007, 0xe21025, +0xa1420007, 0x31c20008, 0x50400009, 0x35ce0010, +0x8f82001c, 0x8c430228, 0x24630001, 0xac430228, +0x9043018d, 0x24630001, 0xa043018d, 0x35ce0010, +0x8f83001c, 0x90620219, 0x30420008, 0x50400006, +0x95420010, 0x90620219, 0x35ce0002, 0x304200f7, +0xa0620219, 0x95420010, 0x91440007, 0x93490120, +0xafa20010, 0x9543000a, 0x24020014, 0xafa20018, +0xafa5001c, 0xafa30014, 0x8d420000, 0x1603821, +0xafa20020, 0x8d480004, 0x8e050024, 0x3021, +0x3084000f, 0xafa50028, 0x2405ff00, 0x1054024, +0xafa80024, 0x8d43000c, 0x42200, 0x1c42025, +0x1021, 0xe33821, 0xe3282b, 0xc23021, +0xc53021, 0xafa60030, 0xafa70034, 0x9605000a, +0x27260002, 0x30c6ffff, 0x3003821, 0xa92821, +0xe001943, 0x30a5ffff, 0x1021, 0x8fbf003c, +0x8fb00038, 0x3e00008, 0x27bd0040, 0x27bdffc0, +0x97a90052, 0x805021, 0x8f84001c, 0x8fa60058, +0xafbf0038, 0x908301e7, 0x24020001, 0x14620003, +0x97a70056, 0xa00190e, 0x2402000e, 0x31220001, +0x10400037, 0x248801fc, 0x2ce2002d, 0x10400034, +0x2ce2000d, 0x50400002, 0x8ca3000c, 0x8ca30010, +0x8c82022c, 0x24420001, 0x14620032, 0x24020010, +0x2ce20015, 0x1040000c, 0x3021, 0x1001821, +0x24a50018, 0x8ca20000, 0x24a50004, 0x24c60001, +0xac620000, 0x2cc20007, 0x1440fffa, 0x24630004, +0xa00191b, 0x0, 0x24e2ffec, 0x23883, +0x10e0000a, 0x24a50014, 0x1002021, 0xa01821, +0x8c620000, 0x24630004, 0x24c60001, 0xac820000, +0xc7102b, 0x1440fffa, 0x24840004, 0xc01821, +0x2c620007, 0x10400020, 0x24c60001, 0x31080, +0x482021, 0x61080, 0x452821, 0x8ca20000, +0x24a50004, 0x24630001, 0xac820000, 0x2c620007, +0x1440fffa, 0x24840004, 0xa00191b, 0x0, +0x8c82022c, 0x8ca3000c, 0x24420001, 0x10620004, +0x24020010, 0xacc20000, 0xa001940, 0x2402ffff, +0x3021, 0x1001821, 0x24a50014, 0x8ca20000, +0x24a50004, 0x24c60001, 0xac620000, 0x2cc20007, +0x1440fffa, 0x24630004, 0x8f83001c, 0x8c62022c, +0x24420001, 0xac62022c, 0x24020001, 0xa06201e7, +0x8f83001c, 0x90620219, 0x30420008, 0x10400005, +0x0, 0x90620219, 0x35290002, 0x304200f7, +0xa0620219, 0x93440120, 0x9545000a, 0x8d460024, +0x1021, 0x1821, 0xafa20030, 0xafa30034, +0x24020006, 0x3821, 0xafa00010, 0xafa00014, +0xafa00018, 0xafa2001c, 0xafa00020, 0xafa00024, +0xa42821, 0x1202021, 0x30a5ffff, 0xafa60028, +0xe001943, 0x3021, 0x1021, 0x8fbf0038, +0x3e00008, 0x27bd0040, 0x27bdfff8, 0x8fad001c, +0x8fae0028, 0x8faf002c, 0xafb00000, 0x8fb00030, +0x8fa80038, 0x8fa9003c, 0x97aa001a, 0x97ac0022, +0x93830020, 0x97ab0026, 0x24620001, 0xa3820020, +0x27420180, 0xa043000a, 0x2403000a, 0xa4440008, +0xa043000b, 0xa445000c, 0xa446000e, 0xa4470010, +0xa44a0012, 0xac4d0014, 0xa44c0018, 0xa44b001a, +0xac4e001c, 0xac4f0020, 0xac500024, 0xac480028, +0xac49002c, 0x8f430128, 0x8fb00000, 0xac430000, +0x3c021000, 0xaf4201b8, 0x3e00008, 0x27bd0008, +0x8f450128, 0x27430180, 0x24025000, 0xa4620008, +0xac650000, 0x93850020, 0x24a20001, 0xa3820020, +0x24020002, 0xa062000b, 0x2402000c, 0xa065000a, +0xa462001a, 0x8c820024, 0xac620024, 0x3c021000, +0x3e00008, 0xaf4201b8, 0x8f83001c, 0x27bdffe8, +0x24020002, 0xafbf0010, 0xa06201e6, 0x8f83001c, +0x24020004, 0xe001987, 0xa0620197, 0x8fbf0010, +0x3e00008, 0x27bd0018, 0x8f450128, 0x27430180, +0x24025085, 0xa4620008, 0x24020002, 0xa062000b, +0x3c021000, 0xac640028, 0xa460001a, 0xac650000, +0x3e00008, 0xaf4201b8, 0x27bdffe0, 0xafbf0018, +0xafb10014, 0xafb00010, 0x8f460148, 0x8f470144, +0x62402, 0x308500ff, 0x8f4201b8, 0x440fffe, +0x30a3003f, 0x2402000c, 0x14620010, 0x0, +0x8f420140, 0x27440180, 0xac820000, 0x8f430144, +0x2402000e, 0xa082000b, 0x30a20040, 0xa4860010, +0x10400004, 0xac830004, 0x24020001, 0xa0019ec, +0xa082000a, 0xa0019ec, 0xa080000a, 0x8f420140, +0x27430180, 0xaf820024, 0xac620000, 0x61202, +0x304200ff, 0xac620004, 0x24020002, 0xa062000b, +0x30c200ff, 0xac620024, 0x24020007, 0xa4640008, +0xac670028, 0x10a20018, 0xa460001a, 0x28a20008, +0x1040000a, 0x2402000f, 0x10a00027, 0x28a20004, +0x14400012, 0x24020001, 0x24020005, 0x10a2000f, +0x24020001, 0xa0019ec, 0xa060000a, 0x10a20011, +0x28a2000f, 0x5440001d, 0xa060000a, 0x28a20085, +0x10400019, 0x28a20083, 0x54400018, 0xa060000a, +0xa0019da, 0x3c020008, 0x24020001, 0xa0019ec, +0xa062000a, 0x3428021, 0x920201e6, 0xa0019e3, +0x24110002, 0x24110002, 0x10f1000c, 0x3c020008, +0x3428021, 0x920201e6, 0x10510009, 0x8fbf0018, +0x8f440140, 0xe0015b0, 0x0, 0xa21101e6, +0xa0019ed, 0x8fbf0018, 0xa060000a, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0x3c021000, 0xaf4201b8, +0x3e00008, 0x27bd0020, 0x10c00007, 0x0, +0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, +0x14c0fffb, 0x24840004, 0x3e00008, 0x0, +0xa001a04, 0xa01021, 0xac860000, 0x0, +0x0, 0x24840004, 0xa01021, 0x1440fffa, +0x24a5ffff, 0x3e00008, 0x0, 0x0 }; +static u32 bce_RXP_b06FwData[(0x0/4) + 1] = { 0x0 }; +static u32 bce_RXP_b06FwRodata[(0x278/4) + 1] = { +0x80040ec, 0x8003fec, 0x8004090, +0x80040a8, 0x80040c0, 0x80040e0, 0x80040ec, +0x80040ec, 0x8003ff4, 0x0, 0x8004b1c, +0x8004b54, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004b8c, 0x8004d50, 0x8004c98, +0x8004cd0, 0x8004d50, 0x8004c20, 0x8004d50, +0x8004d50, 0x8004cd0, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d10, 0x8004d50, 0x8004d10, 0x8004c98, +0x8004d50, 0x8004d50, 0x8004d10, 0x8004d10, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004d50, +0x8004d50, 0x8004d50, 0x8004d50, 0x8004bfc, +0x0, 0x8006110, 0x8006128, 0x8006128, +0x8006128, 0x8006110, 0x8006128, 0x8006128, +0x8006128, 0x8006110, 0x8006128, 0x8006128, +0x8006128, 0x8006110, 0x8006128, 0x8006128, +0x8006128, 0x800611c, 0x0, 0x0 }; +static u32 bce_RXP_b06FwBss[(0x13dc/4) + 1] = { 0x0 }; +static u32 bce_RXP_b06FwSbss[(0x28/4) + 1] = { 0x0 }; +/* static u32 bce_RXP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; */ + +static u32 bce_rv2p_proc1[] = { + 0x00000008, 0xac000001, 0x0000000c, 0x2f800001, 0x00000010, 0x203f0146, + 0x00000010, 0x213f0003, 0x00000010, 0x20bf002b, 0x00000018, 0x8000fffd, + 0x00000010, 0xb1b8b017, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000, + 0x00000000, 0x2c380000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x00000008, 0x02000002, + 0x00000010, 0x91de0000, 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000008, 0x2d800150, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000010, 0x2c620002, + 0x00000018, 0x80000012, 0x0000000b, 0x2fdf0002, 0x0000000c, 0x1f800002, + 0x00000000, 0x2c070000, 0x00000018, 0x8000ffe6, 0x00000008, 0x02000002, + 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000018, 0x80000004, + 0x0000000c, 0x1f800002, 0x00000000, 0x00000000, 0x00000018, 0x8000ffd9, + 0x0000000c, 0x29800002, 0x0000000c, 0x1f800002, 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000005, 0x00000018, 0x8000ffd4, 0x00000008, 0x02240030, + 0x00000018, 0x00040000, 0x00000018, 0x80000016, 0x00000018, 0x80000018, + 0x00000018, 0x8000001c, 0x00000018, 0x8000004d, 0x00000018, 0x8000008d, + 0x00000018, 0x80000010, 0x00000018, 0x8000000f, 0x00000018, 0x8000000e, + 0x00000018, 0x8000000d, 0x00000018, 0x800000c3, 0x00000018, 0x8000000b, + 0x00000018, 0x8000000a, 0x00000018, 0x80000009, 0x00000018, 0x800000fe, + 0x00000018, 0x80000007, 0x00000018, 0x80000006, 0x00000018, 0x80000100, + 0x00000018, 0x80000105, 0x00000018, 0x80000003, 0x00000018, 0x80000099, + 0x00000018, 0x80000123, 0x00000018, 0x80000000, 0x0000000c, 0x1f800001, + 0x00000000, 0x00000000, 0x00000018, 0x8000ffb9, 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000002, + 0x00000018, 0x8000ffb4, 0x00000010, 0xb1a0b012, 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c200000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, + 0x00000010, 0x91d40000, 0x00000008, 0x2d80011c, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x0000000f, 0x47600008, 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, + 0x00000018, 0x80000013, 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002, + 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000010, 0x91d40000, + 0x00000008, 0x2d80011c, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, + 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, + 0x00000000, 0x02620000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x309a0000, + 0x00000000, 0x31040000, 0x00000000, 0x0c961800, 0x00000009, 0x0c99ffff, + 0x00000004, 0xcc993400, 0x00000010, 0xb1963202, 0x00000008, 0x0f800000, + 0x0000000c, 0x29800001, 0x00000010, 0x00220002, 0x0000000c, 0x29520001, + 0x0000000c, 0x29520000, 0x00000008, 0x22000001, 0x0000000c, 0x1f800001, + 0x00000000, 0x2adf0000, 0x00000008, 0x2a000003, 0x00000018, 0x8000ff82, + 0x00000010, 0xb1a0b01d, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, + 0x00000008, 0x2d800150, 0x00000000, 0x00000000, 0x00000010, 0x205f0000, + 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x0000000f, 0x47600008, + 0x00000000, 0x060e0000, 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, + 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, + 0x00000000, 0x0b670000, 0x00000000, 0x0d620000, 0x00000000, 0x0ce71800, + 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400, 0x00000010, 0xb1963220, + 0x00000008, 0x0f800000, 0x00000018, 0x8000001e, 0x0000000f, 0x47600008, + 0x0000000b, 0x2fdf0002, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, + 0x00000010, 0x91d40000, 0x00000008, 0x2d80012c, 0x0000000f, 0x060e0001, + 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, + 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000, + 0x00000000, 0x0d620000, 0x00000000, 0x02630000, 0x0000000f, 0x47620010, + 0x00000000, 0x0ce71800, 0x0000000b, 0x2fdf0002, 0x00000000, 0x311a0000, + 0x00000000, 0x31840000, 0x0000000b, 0xc20000ff, 0x00000002, 0x42040000, + 0x00000001, 0x31620800, 0x0000000f, 0x020e0010, 0x00000002, 0x31620800, + 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400, 0x00000010, 0xb1963202, + 0x00000008, 0x0f800000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x0000000c, 0x61420006, 0x00000008, 0x22000008, 0x00000000, 0x2adf0000, + 0x00000008, 0x2a000004, 0x00000018, 0x8000ff41, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91a0b008, 0x00000010, 0x91d40000, + 0x0000000c, 0x31620018, 0x00000008, 0x2d800001, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x00000008, 0xac000001, 0x00000018, 0x8000000e, + 0x00000000, 0x0380b000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c004000, + 0x00000010, 0x91d40000, 0x00000008, 0x2d800101, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x0000000c, 0x31620018, 0x00000008, 0x2d800001, + 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x0000000b, 0x2fdf0002, + 0x00000000, 0x2c000e00, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000008, 0x2a000007, 0x00000018, 0x8000ff26, 0x00000010, 0xb1a0b016, + 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000, 0x00000000, 0x2c200000, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, + 0x00000008, 0x2d800150, 0x00000000, 0x00000000, 0x00000010, 0x205f0000, + 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, + 0x00000008, 0x07000001, 0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, + 0x00000018, 0x8000000a, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, + 0x0000000c, 0x1f800001, 0x00000010, 0x91de0000, 0x00000018, 0x8000ff10, + 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, + 0x00000008, 0x2d800108, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000010, 0x91de0000, 0x00000000, 0x2adf0000, 0x00000008, 0x2a00000a, + 0x00000018, 0x8000ff06, 0x00000000, 0x82265600, 0x0000000f, 0x47220008, + 0x00000009, 0x070e000f, 0x00000008, 0x070e0008, 0x00000008, 0x02800001, + 0x00000007, 0x02851c00, 0x00000008, 0x82850001, 0x00000000, 0x02840a00, + 0x00000007, 0x42851c00, 0x00000003, 0xc3aa5200, 0x00000000, 0x03b10e00, + 0x00000010, 0x001f0000, 0x0000000f, 0x0f280007, 0x00000007, 0x4b071c00, + 0x00000000, 0x00000000, 0x0000000f, 0x0a960003, 0x00000000, 0x0a955c00, + 0x00000000, 0x4a005a00, 0x00000000, 0x0c960a00, 0x00000009, 0x0c99ffff, + 0x00000008, 0x0d00ffff, 0x00000010, 0xb1963202, 0x00000008, 0x0f800005, + 0x00000010, 0x00220020, 0x00000000, 0x02a70000, 0x00000010, 0xb1850002, + 0x00000008, 0x82850200, 0x00000000, 0x02000000, 0x00000000, 0x03a60000, + 0x00000018, 0x80000053, 0x00000000, 0x072b0000, 0x00000001, 0x878c1c00, + 0x00000000, 0x870e1e00, 0x00000000, 0x860c1e00, 0x00000000, 0x03061e00, + 0x00000010, 0xb18e0003, 0x00000018, 0x8000004c, 0x00000018, 0x8000fffa, + 0x00000010, 0x918c0003, 0x00000010, 0xb1870002, 0x00000018, 0x80000048, + 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x00000000, 0x2a860000, + 0x00000000, 0x230c0000, 0x00000000, 0x2b070000, 0x00000010, 0xb187000e, + 0x00000008, 0x2a000008, 0x00000018, 0x80000040, 0x00000010, 0x91d40000, + 0x00000000, 0x28d18c00, 0x00000000, 0x2a860000, 0x00000000, 0x230c0000, + 0x00000000, 0x2b070000, 0x00000018, 0x8000fff8, 0x00000010, 0x91d40000, + 0x0000000c, 0x29800001, 0x00000000, 0x2aab0000, 0x00000000, 0xa3265600, + 0x00000000, 0x2b000000, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000008, + 0x00000018, 0x8000fec7, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, + 0x0000000c, 0x1f800001, 0x00000008, 0x2a000009, 0x00000018, 0x8000fec2, + 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000000, 0x29420000, 0x00000008, 0x2a000002, 0x00000018, 0x8000febc, + 0x00000018, 0x8000febb, 0x00000010, 0xb1bcb016, 0x0000000b, 0x2fdf0002, + 0x00000000, 0x03d80000, 0x00000000, 0x2c3c0000, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150, + 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000, + 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000008, 0x07000001, + 0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, 0x00000018, 0x8000000a, + 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, 0x0000000c, 0x1f800000, + 0x00000010, 0x91de0000, 0x00000018, 0x8000fea5, 0x00000008, 0x2c8000b0, + 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, + 0x0000000c, 0x29800000, 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000, + 0x00000000, 0x2adf0000, 0x00000008, 0x2a000006, 0x00000018, 0x8000fe9b, + 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, + 0x00000008, 0x2a00000b, 0x00000018, 0x8000fe96, 0x00000008, 0x03050004, + 0x00000006, 0x83040c00, 0x00000008, 0x02850200, 0x00000000, 0x86050c00, + 0x00000001, 0x860c0e00, 0x00000008, 0x02040004, 0x00000000, 0x02041800, + 0x00000000, 0x83871800, 0x00000018, 0x00020000 +}; + +static u32 bce_rv2p_proc2[] = { + 0x00000000, 0x2a000000, + 0x00000010, 0xb1d40000, 0x00000008, 0x02540003, 0x00000018, 0x00040000, + 0x00000018, 0x8000000b, 0x00000018, 0x8000000b, 0x00000018, 0x8000000f, + 0x00000018, 0x8000004c, 0x00000018, 0x800001bd, 0x00000018, 0x800001e5, + 0x00000018, 0x8000019f, 0x00000018, 0x800001fd, 0x00000018, 0x800001a3, + 0x00000018, 0x800001aa, 0x00000018, 0x8000022f, 0x00000018, 0x80000000, + 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, 0x00000018, 0x8000ffed, 0x0000000c, 0x29800001, + 0x00000010, 0x91de0000, 0x00000010, 0x001f0000, 0x00000000, 0x2f80aa00, + 0x00000000, 0x2a000000, 0x00000000, 0x0d610000, 0x00000000, 0x03620000, + 0x00000000, 0x2c400000, 0x00000000, 0x02638c00, 0x00000000, 0x26460000, + 0x00000008, 0x02040012, 0x00000010, 0xb906082c, 0x00000000, 0x0f580000, + 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b660000, + 0x00000000, 0x0c000000, 0x00000000, 0x0b800000, 0x00000008, 0x0cc60012, + 0x00000008, 0x0f800003, 0x00000000, 0x00000000, 0x00000010, 0x009f0000, + 0x00000008, 0x27110012, 0x00000000, 0x66900000, 0x00000008, 0xa31b0012, + 0x00000010, 0xb197320d, 0x00000000, 0x25960000, 0x00000010, 0x001f0000, + 0x00000008, 0x0f800003, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000010, 0x009f0000, 0x00000000, 0x27002200, + 0x00000000, 0x26802000, 0x00000000, 0x231b0000, 0x0000000c, 0x69520001, + 0x00000018, 0x8000fff4, 0x00000010, 0x01130002, 0x00000010, 0xb1980003, + 0x00000010, 0x001f0000, 0x00000008, 0x0f800004, 0x00000008, 0x22000003, + 0x00000008, 0x2c80000c, 0x00000008, 0x2d00000c, 0x00000010, 0x009f0000, + 0x00000000, 0x25960000, 0x0000000c, 0x29800000, 0x00000000, 0x32140000, + 0x00000000, 0x32950000, 0x00000000, 0x33160000, 0x00000000, 0x31e32e00, + 0x00000008, 0x2d800010, 0x00000010, 0x20530000, 0x00000018, 0x8000ffb6, + 0x00000000, 0x23000000, 0x00000000, 0x25e60000, 0x00000008, 0x2200000b, + 0x0000000c, 0x69520000, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000018, 0x8000ffaf, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, + 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, + 0x00000009, 0x076000ff, 0x0000000f, 0x2c0e0007, 0x00000008, 0x2c800000, + 0x00000008, 0x2d000064, 0x00000008, 0x2d80011c, 0x00000009, 0x06420002, + 0x0000000c, 0x61420001, 0x00000000, 0x0f400000, 0x00000000, 0x02d08c00, + 0x00000000, 0x23000000, 0x00000004, 0x826da000, 0x00000000, 0x8304a000, + 0x00000000, 0x22c50c00, 0x00000000, 0x03760000, 0x00000004, 0x83860a00, + 0x00000000, 0x83870c00, 0x00000010, 0x91de0000, 0x00000000, 0x037c0000, + 0x00000000, 0x837b0c00, 0x00000001, 0x83060e00, 0x00000000, 0x83870c00, + 0x00000000, 0x82850e00, 0x00000010, 0xb1860016, 0x0000000f, 0x47610018, + 0x00000000, 0x068e0000, 0x0000000f, 0x47670010, 0x0000000f, 0x47e20010, + 0x00000000, 0x870e1e00, 0x00000010, 0xb70e1a10, 0x00000010, 0x0ce7000e, + 0x00000008, 0x22000009, 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, + 0x00000003, 0xf66c9400, 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, 0x0000000c, 0x29800000, 0x00000000, 0x37ed0000, + 0x0000000c, 0x73e7001a, 0x00000010, 0x20530000, 0x00000008, 0x22000008, + 0x0000000c, 0x61420004, 0x00000000, 0x02f60000, 0x00000004, 0x82840a00, + 0x00000010, 0xb1840a2b, 0x00000010, 0x2d67000a, 0x00000010, 0xb96d0804, + 0x00000004, 0xb6ed0a00, 0x00000000, 0x37ed0000, 0x00000018, 0x80000029, + 0x0000000c, 0x61420000, 0x00000000, 0x37040000, 0x00000000, 0x37850000, + 0x0000000c, 0x33e7001a, 0x00000018, 0x80000024, 0x00000010, 0xb96d0809, + 0x00000004, 0xb6ed0a00, 0x00000000, 0x036d0000, 0x00000004, 0xb76e0c00, + 0x00000010, 0x91ee0c1f, 0x0000000c, 0x73e7001a, 0x00000004, 0xb6ef0c00, + 0x00000000, 0x37ed0000, 0x00000018, 0x8000001b, 0x0000000c, 0x61420000, + 0x00000010, 0xb7ee0a05, 0x00000010, 0xb96f0815, 0x00000003, 0xb76e0800, + 0x00000004, 0xb7ef0a00, 0x00000018, 0x80000015, 0x00000010, 0x0ce7000c, + 0x00000008, 0x22000009, 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, + 0x00000003, 0xf66c9400, 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, + 0x0000000c, 0x21420004, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000008, 0x22000008, 0x0000000c, 0x61420004, 0x00000000, 0x37040000, + 0x00000000, 0x37850000, 0x00000000, 0x036d0000, 0x00000003, 0xb8f10c00, + 0x00000018, 0x80000004, 0x00000000, 0x02840000, 0x00000002, 0x21421800, + 0x0000000c, 0x61420000, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, 0x00000000, 0x23000000, 0x00000010, 0xb1840a40, + 0x00000010, 0x01420002, 0x00000004, 0xb8f10a00, 0x00000003, 0x83760a00, + 0x00000010, 0xb8040c3c, 0x00000010, 0xb7e6080a, 0x00000000, 0x0a640000, + 0x00000000, 0x0ae50000, 0x00000009, 0x0c68ffff, 0x00000009, 0x0b67ffff, + 0x00000000, 0x0be60000, 0x00000000, 0x0c840000, 0x00000010, 0xb197320b, + 0x00000008, 0x0f800002, 0x00000018, 0x80000009, 0x00000000, 0x0a6a0000, + 0x00000000, 0x0aeb0000, 0x00000000, 0x0c000000, 0x00000009, 0x0b6cffff, + 0x00000000, 0x0be90000, 0x00000000, 0x0c840000, 0x00000010, 0xb1973202, + 0x00000008, 0x0f800002, 0x00000010, 0x001f0000, 0x00000000, 0x0c860000, + 0x00000000, 0x06980000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000, + 0x00000010, 0x009f0000, 0x00000010, 0xb1973212, 0x00000000, 0x231b0000, + 0x00000000, 0x28840000, 0x00000000, 0x02043600, 0x00000003, 0x8384a000, + 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, + 0x00000000, 0x66900000, 0x0000000c, 0x29000000, 0x00000000, 0x24c60000, + 0x0000000c, 0x29800000, 0x00000000, 0x06980000, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000010, 0x001f0000, 0x00000008, 0x0f800003, + 0x00000018, 0x8000ffee, 0x00000000, 0x02043600, 0x00000000, 0x231b0000, + 0x00000000, 0x03840000, 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, + 0x00000002, 0x21421800, 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000, + 0x0000000c, 0x29000000, 0x00000000, 0x32140000, 0x00000000, 0x32950000, + 0x00000005, 0x73e72c00, 0x00000005, 0x74683000, 0x00000000, 0x33170000, + 0x00000018, 0x80000146, 0x00000010, 0x91c60005, 0x00000008, 0x07000004, + 0x00000010, 0xb1c41c03, 0x00000010, 0x91840a06, 0x00000000, 0x28840000, + 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000010, 0xb1840a97, 0x0000000c, 0x21420006, + 0x00000010, 0x0ce7001d, 0x0000000f, 0x43680010, 0x00000000, 0x03f30c00, + 0x00000010, 0x91870856, 0x0000000f, 0x46ec0010, 0x00000010, 0xb68d0c54, + 0x00000000, 0x838d0c00, 0x00000000, 0xa3050800, 0x00000001, 0xa3460e00, + 0x00000000, 0x28840000, 0x00000000, 0x02048c00, 0x00000008, 0x22000008, + 0x00000000, 0x03840000, 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, + 0x00000002, 0x21421800, 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, + 0x00000009, 0x2607ffff, 0x00000000, 0x27750c00, 0x00000000, 0x66f40000, + 0x0000000c, 0x29000000, 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, + 0x00000000, 0x03068c00, 0x00000003, 0xf4680c00, 0x00000010, 0x20530000, + 0x00000000, 0x22c58c00, 0x00000018, 0x8000ffe2, 0x00000000, 0x39760000, + 0x00000000, 0x39840000, 0x0000000c, 0x33e70019, 0x00000000, 0x031e0000, + 0x00000009, 0x076000ff, 0x00000010, 0x001f0000, 0x0000000f, 0x0f0e0007, + 0x00000000, 0x83850800, 0x00000000, 0x0a7d0000, 0x00000000, 0x0afe0000, + 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, 0x00000000, 0x0c000000, + 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003, + 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff, + 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010, + 0x00000002, 0x33e70e00, 0x00000000, 0x28f30000, 0x00000010, 0x009f0000, + 0x00000000, 0x02043600, 0x00000008, 0x22000006, 0x00000000, 0x231b0000, + 0x00000000, 0x23ff0000, 0x00000000, 0x241b0000, 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, 0x00000002, 0x21421800, + 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, + 0x00000000, 0x27110000, 0x00000000, 0x26900000, 0x0000000c, 0x29000000, + 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, 0x00000003, 0xf4683600, + 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400, + 0x00000010, 0xb1923605, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000, + 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000, + 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, 0x00000018, 0x8000ffa6, 0x00000000, 0x031e0000, + 0x00000000, 0x83850800, 0x00000009, 0x076000ff, 0x00000010, 0x001f0000, + 0x0000000f, 0x0f0e0007, 0x00000000, 0x0c000000, 0x00000000, 0x0a7d0000, + 0x00000000, 0x0afe0000, 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, + 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003, + 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff, + 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010, + 0x00000002, 0x33e70e00, 0x00000000, 0x39840000, 0x00000003, 0xb9720800, + 0x00000000, 0x28f30000, 0x0000000f, 0x65680010, 0x00000010, 0x009f0000, + 0x00000000, 0x02043600, 0x00000008, 0x22000007, 0x00000000, 0x231b0000, + 0x00000000, 0x23ff0000, 0x00000000, 0x241b0000, 0x00000000, 0x03840000, + 0x00000010, 0x91870a03, 0x00000000, 0x03d00000, 0x00000002, 0x21421800, + 0x00000003, 0x8387a000, 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, + 0x00000000, 0x27110000, 0x00000000, 0x26900000, 0x0000000c, 0x29000000, + 0x00000000, 0x24c60000, 0x0000000c, 0x29800000, 0x00000003, 0xf4683600, + 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400, + 0x00000010, 0xb1923605, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004, + 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000, + 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000, + 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, 0x00000018, 0x8000ff6a, 0x00000010, 0x0ce70005, + 0x00000008, 0x2c80000c, 0x00000008, 0x2d000070, 0x00000008, 0x2d800010, + 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000018, 0x80000121, + 0x00000000, 0x2c1e0000, 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, + 0x00000008, 0x2d800048, 0x00000000, 0x00000000, 0x00000010, 0x91de0000, + 0x00000018, 0x8000fe59, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, 0x00000000, 0x0f008000, 0x00000008, 0x0f800007, + 0x00000018, 0x80000006, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, + 0x00000010, 0x001f0000, 0x0000000f, 0x0f470007, 0x00000008, 0x0f800008, + 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000018, 0x8000fe4b, + 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, + 0x00000000, 0x2a000000, 0x00000009, 0x0261ffff, 0x0000000d, 0x70e10001, + 0x00000018, 0x80000105, 0x00000000, 0x2c400000, 0x00000008, 0x2c8000c4, + 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, 0x00000005, 0x70e10800, + 0x00000010, 0x91de0000, 0x00000018, 0x8000fe3d, 0x0000000c, 0x29800001, + 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, + 0x00000000, 0x02700000, 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, + 0x00000000, 0x2a000000, 0x00000000, 0x0f400000, 0x00000000, 0x2c400000, + 0x0000000c, 0x73e7001b, 0x00000010, 0x0ce7000e, 0x00000000, 0x286d0000, + 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff, 0x00000018, 0x8000006c, + 0x00000008, 0x02000004, 0x00000010, 0x91c40803, 0x0000000c, 0x29800000, + 0x00000010, 0x20530000, 0x00000018, 0x800000e9, 0x00000008, 0x2c8000b8, + 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, 0x00000018, 0x80000005, + 0x00000008, 0x2c8000c4, 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, + 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800048, + 0x00000008, 0x2d000068, 0x00000008, 0x2d800104, 0x00000000, 0x00000000, + 0x00000010, 0x91de0000, 0x00000000, 0x27f60000, 0x00000010, 0xb87a9e04, + 0x00000008, 0x2200000d, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, + 0x00000018, 0x8000fe14, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, + 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000, + 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, + 0x00000010, 0x0e670011, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, + 0x00000009, 0x266dffff, 0x00000004, 0xb8f1a000, 0x00000000, 0x0f400000, + 0x0000000c, 0x73e7001c, 0x00000018, 0x80000043, 0x00000008, 0x02000004, + 0x00000010, 0x91c40802, 0x0000000c, 0x29800000, 0x00000000, 0x2c1e0000, + 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, + 0x00000010, 0x20530000, 0x00000010, 0x91de0000, 0x00000018, 0x8000fdfa, + 0x0000000c, 0x29800001, 0x00000000, 0x03550000, 0x00000000, 0x06460000, + 0x00000000, 0x03d60000, 0x00000000, 0x2a000000, 0x0000000f, 0x0f480007, + 0x00000010, 0xb18c0027, 0x0000000f, 0x47420008, 0x00000009, 0x070e000f, + 0x00000008, 0x070e0008, 0x00000010, 0x001f0000, 0x00000008, 0x09000001, + 0x00000007, 0x09121c00, 0x00000003, 0xcbca9200, 0x00000000, 0x0b97a200, + 0x00000007, 0x4b171c00, 0x0000000f, 0x0a960003, 0x00000000, 0x0a959c00, + 0x00000000, 0x4a009a00, 0x00000008, 0x82120001, 0x00000001, 0x0c170800, + 0x00000000, 0x02180000, 0x00000000, 0x0c971800, 0x00000008, 0x0d00ffff, + 0x00000008, 0x0f800006, 0x0000000c, 0x29000000, 0x00000008, 0x22000001, + 0x00000000, 0x22c50c00, 0x00000010, 0x009f0000, 0x00000010, 0xb197320b, + 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, 0x00000000, 0x02180000, 0x00000010, 0x20530000, + 0x00000000, 0x22c53600, 0x00000010, 0x001f0000, 0x00000008, 0x0f800006, + 0x00000018, 0x8000fff5, 0x00000010, 0x91870002, 0x00000008, 0x2200000a, + 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000, + 0x0000000c, 0x29800000, 0x00000008, 0x0200000a, 0x00000010, 0x91c40804, + 0x00000010, 0x02c20003, 0x00000010, 0x001f0000, 0x00000008, 0x0f800008, + 0x00000010, 0x20530000, 0x00000018, 0x8000fdc5, 0x0000000c, 0x29800001, + 0x00000000, 0x2a000000, 0x00000018, 0x8000fdc2, 0x00000000, 0x06820000, + 0x00000010, 0x001f0000, 0x00000010, 0x0ce70028, 0x00000000, 0x03720000, + 0x00000000, 0xa8760c00, 0x00000000, 0x0cf60000, 0x00000010, 0xb8723224, + 0x00000000, 0x03440000, 0x00000008, 0x22000010, 0x00000000, 0x03ca0000, + 0x0000000f, 0x65680010, 0x00000000, 0x0bcf0000, 0x00000000, 0x27f20000, + 0x00000010, 0xb7ef3203, 0x0000000c, 0x21420004, 0x0000000c, 0x73e70019, + 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x0000000c, 0x29800000, + 0x00000004, 0xb9723200, 0x00000010, 0x20530000, 0x00000000, 0x22060000, + 0x0000000c, 0x61420004, 0x00000000, 0x25070000, 0x00000000, 0x27970000, + 0x00000000, 0x290e0000, 0x00000010, 0x0ce70010, 0x00000010, 0xb873320f, + 0x0000000f, 0x436c0010, 0x00000000, 0x03f30c00, 0x00000000, 0x03f30000, + 0x00000000, 0x83990e00, 0x00000001, 0x83860e00, 0x00000000, 0x83060e00, + 0x00000003, 0xf66c0c00, 0x00000000, 0x39f30e00, 0x00000000, 0x3af50e00, + 0x00000000, 0x7a740000, 0x0000000f, 0x43680010, 0x00000001, 0x83860e00, + 0x00000000, 0x83060e00, 0x00000003, 0xf4680c00, 0x00000000, 0x286d0000, + 0x00000010, 0xb1e9a056, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c54, + 0x00000000, 0x0a6a0000, 0x00000000, 0x0aeb0000, 0x00000009, 0x0b6cffff, + 0x00000000, 0x0c000000, 0x00000000, 0x0be90000, 0x00000003, 0x8cf6a000, + 0x0000000c, 0x09800002, 0x00000010, 0x009f0000, 0x00000010, 0xb8173209, + 0x00000000, 0x35140000, 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, + 0x00000000, 0x34970000, 0x00000004, 0xb8f12e00, 0x00000010, 0x001f0000, + 0x00000008, 0x0f800004, 0x00000018, 0x8000fff7, 0x00000000, 0x03e90000, + 0x00000010, 0xb8f6a01a, 0x00000010, 0x20130019, 0x00000010, 0xb1f10e18, + 0x00000000, 0x83973200, 0x00000000, 0x38700e00, 0x00000000, 0xbb760e00, + 0x00000000, 0x37d00000, 0x0000000c, 0x73e7001a, 0x00000003, 0xb8f1a000, + 0x00000000, 0x32140000, 0x00000000, 0x32950000, 0x00000005, 0x73e72c00, + 0x00000000, 0x33190000, 0x00000005, 0x74680000, 0x00000010, 0x0ce7000d, + 0x00000008, 0x22000009, 0x00000000, 0x07520000, 0x00000000, 0x29000000, + 0x0000000c, 0x73e70019, 0x0000000f, 0x65680010, 0x0000000c, 0x21420004, + 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x0000000c, 0x61420004, + 0x00000000, 0x290e0000, 0x00000018, 0x80000002, 0x00000010, 0x91973206, + 0x00000000, 0x35140000, 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, + 0x00000000, 0x34990000, 0x00000004, 0xb8f13200, 0x00000000, 0x83690c00, + 0x00000010, 0xb1860013, 0x00000000, 0x28e90000, 0x00000008, 0x22000004, + 0x00000000, 0x23ec0000, 0x00000000, 0x03690000, 0x00000010, 0xb8660c07, + 0x00000009, 0x036cffff, 0x00000000, 0x326a0000, 0x00000000, 0x32eb0000, + 0x00000005, 0x73e70c00, 0x00000000, 0x33690000, 0x00000005, 0x74680000, + 0x0000000c, 0x73e7001c, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c12, + 0x00000010, 0xb1d00c11, 0x0000000c, 0x21420005, 0x0000000c, 0x33e7001c, + 0x00000018, 0x8000000e, 0x00000010, 0x2e67000d, 0x00000000, 0x03690000, + 0x00000010, 0xb1f60c0b, 0x00000010, 0xb1d00c0a, 0x00000000, 0x03440000, + 0x00000008, 0x2200000c, 0x00000000, 0x07520000, 0x00000000, 0x29000000, + 0x0000000c, 0x29800000, 0x0000000c, 0x33e7001c, 0x00000010, 0x20530000, + 0x00000000, 0x22060000, 0x00000000, 0x290e0000, 0x00000018, 0x000d0000, + 0x00000000, 0x06820000, 0x00000010, 0x2de7000d, 0x00000010, 0x0ce7000c, + 0x00000000, 0x27f20000, 0x00000010, 0xb96d9e0a, 0x00000000, 0xa86d9e00, + 0x00000009, 0x0361ffff, 0x00000010, 0xb7500c07, 0x00000008, 0x2200000f, + 0x0000000f, 0x65680010, 0x00000000, 0x29000000, 0x0000000c, 0x29800000, + 0x0000000c, 0x33e7001b, 0x00000010, 0x20530000, 0x00000018, 0x000d0000 +}; + +static int bce_TPAT_b06FwReleaseMajor = 0x1; +static int bce_TPAT_b06FwReleaseMinor = 0x0; +static int bce_TPAT_b06FwReleaseFix = 0x0; +static u32 bce_TPAT_b06FwStartAddr = 0x08000860; +static u32 bce_TPAT_b06FwTextAddr = 0x08000800; +static int bce_TPAT_b06FwTextLen = 0x16b0; +static u32 bce_TPAT_b06FwDataAddr = 0x08001ee0; +static int bce_TPAT_b06FwDataLen = 0x0; +static u32 bce_TPAT_b06FwRodataAddr = 0x00000000; +static int bce_TPAT_b06FwRodataLen = 0x0; +static u32 bce_TPAT_b06FwBssAddr = 0x08001f20; +static int bce_TPAT_b06FwBssLen = 0x450; +static u32 bce_TPAT_b06FwSbssAddr = 0x08001ee0; +static int bce_TPAT_b06FwSbssLen = 0x38; +/* static u32 bce_TPAT_b06FwSDataAddr = 0x00000000; */ +/* static int bce_TPAT_b06FwSDataLen = 0x0; */ +static u32 bce_TPAT_b06FwText[(0x16b0/4) + 1] = { +0xa000218, 0x0, 0x0, +0xd, 0x74706174, 0x20332e34, 0x2e380000, +0x3040801, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x10000003, 0x0, +0xd, 0xd, 0x3c020800, 0x24421ee0, +0x3c030800, 0x24632370, 0xac400000, 0x43202b, +0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd2ffc, +0x3a0f021, 0x3c100800, 0x26100860, 0x3c1c0800, +0x279c1ee0, 0xe0005cb, 0x0, 0xd, +0x8f840014, 0x3c038000, 0x8f420178, 0x431024, +0x1440fffd, 0x0, 0x8c850008, 0x24020800, +0xaf420178, 0x97440104, 0x3c020008, 0xaf420140, +0x8f830028, 0x308affff, 0x30630001, 0x10600008, +0x1404821, 0x2543fffe, 0x3069ffff, 0x24020002, +0xa7420146, 0xa7430148, 0xa000249, 0x3c020800, +0xa7400146, 0x3c020800, 0x8c43083c, 0x1460000e, +0x24020f00, 0x8f820028, 0x30430020, 0x3182b, +0x31823, 0x30650009, 0x30420c00, 0x24030400, +0x14430002, 0x34a40001, 0x34a40005, 0xa744014a, +0xa00026b, 0x3c020800, 0x8f830018, 0x14620008, +0x0, 0x8f820028, 0x30420020, 0x2102b, +0x21023, 0x3042000d, 0xa000269, 0x34420005, +0x8f820028, 0x30420020, 0x2102b, 0x21023, +0x30420009, 0x34420001, 0xa742014a, 0x3c020800, +0x8c430820, 0x8f840028, 0x3c020048, 0x621825, +0x30840006, 0x24020002, 0x1082000d, 0x2c820003, +0x50400005, 0x24020004, 0x10800012, 0x3c020001, +0xa00028b, 0x0, 0x10820007, 0x24020006, +0x1482000f, 0x3c020111, 0xa000283, 0x621025, +0xa000282, 0x3c020101, 0x3c020011, 0x621025, +0x24030001, 0xaf421000, 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0xaf401000, 0xaf431000, +0x30420006, 0x1040002a, 0x3c038000, 0x8f421000, +0x431024, 0x1040fffd, 0x0, 0x97441014, +0x8f451020, 0x8f461020, 0x52c02, 0xe00079b, +0x30c6ffff, 0x16000006, 0xa6620000, 0x8f431020, +0x3721021, 0x511021, 0xa000780, 0xac43fffc, +0x8f820014, 0x8f441020, 0x3203fffc, 0x621821, +0xac64fffc, 0x3c040800, 0x24840844, 0x3c050800, +0x24a50840, 0x3c021000, 0xa7500148, 0xa7540144, +0xaf420178, 0x8f630000, 0x2606fffe, 0x2263021, +0xaf830000, 0xe000701, 0x0, 0x2512021, +0xe000676, 0x3084ffff, 0xe000684, 0x2002021, +0x8fbf0024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0028, +0x3084ffff, 0x3882ffff, 0x30c6ffff, 0x52c00, +0xa62825, 0x451021, 0x45282b, 0x451021, +0x3043ffff, 0x21402, 0x621021, 0x3044ffff, +0x21402, 0x821021, 0x3842ffff, 0x3e00008, +0x3042ffff, 0x0 }; +static u32 bce_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 }; +static u32 bce_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 }; +static u32 bce_TPAT_b06FwBss[(0x450/4) + 1] = { 0x0 }; +static u32 bce_TPAT_b06FwSbss[(0x38/4) + 1] = { 0x0 }; +/* static u32 bce_TPAT_b06FwSdata[(0x0/4) + 1] = { 0x0 }; */ + +static int bce_TXP_b06FwReleaseMajor = 0x1; +static int bce_TXP_b06FwReleaseMinor = 0x0; +static int bce_TXP_b06FwReleaseFix = 0x0; +static u32 bce_TXP_b06FwStartAddr = 0x08000064; +static u32 bce_TXP_b06FwTextAddr = 0x08000000; +static int bce_TXP_b06FwTextLen = 0x44d4; +static u32 bce_TXP_b06FwDataAddr = 0x08004520; +static int bce_TXP_b06FwDataLen = 0xd0; +static u32 bce_TXP_b06FwRodataAddr = 0x080044d8; +static int bce_TXP_b06FwRodataLen = 0x30; +static u32 bce_TXP_b06FwBssAddr = 0x08004670; +static int bce_TXP_b06FwBssLen = 0xa20; +static u32 bce_TXP_b06FwSbssAddr = 0x080045f0; +static int bce_TXP_b06FwSbssLen = 0x80; +/* static u32 bce_TXP_b06FwSDataAddr = 0x00000000; */ +/* static int bce_TXP_b06FwSDataLen = 0x0; */ +static u32 bce_TXP_b06FwText[(0x44d4/4) + 1] = { +0xa000019, +0x0, 0x0, 0xd, 0x74787020, +0x332e342e, 0x38000000, 0x3040800, 0xa, +0xe6, 0xea60, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x10000003, 0x0, 0xd, +0xd, 0x3c020800, 0x244245f0, 0x3c030800, +0x24635090, 0xac400000, 0x43202b, 0x1480fffd, +0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x3a0f021, +0x3c100800, 0x26100064, 0x3c1c0800, 0x279c45f0, +0xe00024f, 0x0, 0xd, 0x8f840018, +0x27bdffe8, 0xafb00010, 0x8f460104, 0x8f83000c, +0x8c8500ac, 0xaf430080, 0x948200a8, 0xa7420e10, +0x948300aa, 0xa7430e12, 0x8c8200ac, 0xaf420e18, +0x97430e10, 0xa7430e14, 0x97420e12, 0xc821, +0xa7420e16, 0x8f430e18, 0x6021, 0xc53023, +0xaf430e1c, 0x10c001aa, 0x2d820001, 0x3c0e1000, +0x2418fff8, 0x24100010, 0x240f0f00, 0x93620008, +0x10400009, 0x0, 0x97620010, 0xc2102b, +0x14400005, 0x0, 0x97620010, 0x3042ffff, +0xa000058, 0xaf420e00, 0xaf460e00, 0x8f420000, +0x30420008, 0x1040fffd, 0x0, 0x97420e08, +0x8f450e04, 0x3044ffff, 0x30820001, 0x14400005, +0x0, 0x14a00005, 0x3083a040, 0xa000229, +0x0, 0xd, 0x3083a040, 0x24020040, +0x14620054, 0x3082a000, 0x3c038000, 0x8f420178, +0x431024, 0x1440fffd, 0x308a0036, 0x8f880010, +0x30890008, 0x24020800, 0xaf420178, 0x1001821, +0x9742008a, 0x431023, 0x2442ffff, 0x30421fff, +0x2c420008, 0x1440fffa, 0xa06021, 0x8f82001c, +0xcc3023, 0x24070001, 0x8f83000c, 0x304b00ff, +0x24420001, 0xaf82001c, 0x25024000, 0x106f0005, +0x3422021, 0x93820016, 0x30420007, 0x21240, +0x34470001, 0xb1400, 0x3c030100, 0x431025, +0xac820000, 0x8f83001c, 0xea3825, 0x11200010, +0xac830004, 0xee3825, 0x97430e0a, 0x8f840010, +0x3c028100, 0x621825, 0x2402000e, 0xaf430160, +0x25830006, 0x24840008, 0x30841fff, 0xa742015a, +0xa7430158, 0xaf840010, 0xa0000a7, 0x0, +0x8f830010, 0x25820002, 0xa7420158, 0x24630008, +0x30631fff, 0xaf830010, 0x54c0000f, 0x8f420e14, +0x8f82000c, 0x504f0002, 0x24190001, 0x34e70040, +0x97420e10, 0x97430e12, 0x8f850018, 0x21400, +0x621825, 0xaca300a8, 0x8f840018, 0x8f420e18, +0xac8200ac, 0x8f420e14, 0x8f430e1c, 0xaf420144, +0xaf430148, 0xa34b0152, 0xaf470154, 0xa0001ef, +0xaf4e0178, 0x1040016a, 0x0, 0x93620008, +0x50400008, 0xafa60008, 0x97620010, 0xa2102b, +0x10400003, 0x30820040, 0x10400161, 0x0, +0xafa60008, 0xa7840014, 0xaf850008, 0x93620008, +0x14400060, 0x27ac0008, 0xaf60000c, 0x97820014, +0x30424000, 0x10400002, 0x2403000e, 0x24030016, +0xa363000a, 0x24034007, 0xaf630014, 0x93820016, +0x8f630014, 0x30420007, 0x21240, 0x621825, +0xaf630014, 0x97820014, 0x8f630014, 0x30420010, +0x621825, 0xaf630014, 0x97820014, 0x30420008, +0x5040000f, 0x2821, 0x8f620014, 0x4e1025, +0xaf620014, 0x97430e0a, 0x3c028100, 0x621825, +0x2402000e, 0xaf630004, 0xa3620002, 0x9363000a, +0x3405fffc, 0x24630004, 0xa0000f7, 0xa363000a, +0xaf600004, 0xa3600002, 0x97820014, 0x9363000a, +0x30421f00, 0x21182, 0x24420028, 0x621821, +0xa3630009, 0x97420e0c, 0xa7620010, 0x93630009, +0x24020008, 0x24630002, 0x30630007, 0x431023, +0x30420007, 0xa362000b, 0x93640009, 0x97620010, +0x8f890008, 0x97830014, 0x441021, 0xa21021, +0x30630040, 0x10600007, 0x3045ffff, 0xa9102b, +0x14400005, 0x125102b, 0x3c078000, 0xa00012b, +0x5821, 0x125102b, 0x544000ca, 0x6021, +0x97420e14, 0xa7420e10, 0x97430e16, 0xa7430e12, +0x8f420e1c, 0xaf420e18, 0xaf450e00, 0x8f420000, +0x30420008, 0x1040fffd, 0x0, 0x97420e08, +0xa04821, 0xa7820014, 0x8f430e04, 0x3821, +0x240b0001, 0xaf830008, 0x97620010, 0xa00013d, +0x304dffff, 0x8f890008, 0x97820014, 0x30420040, +0x10400004, 0x1206821, 0x3c078000, 0xa00013d, +0x5821, 0x97630010, 0x8f820008, 0x10430003, +0x3821, 0xa0001e2, 0x6021, 0x240b0001, +0x8d820000, 0x491023, 0x1440000d, 0xad820000, +0x8f620014, 0x34420040, 0xaf620014, 0x97430e10, +0x97420e12, 0x8f840018, 0x31c00, 0x431025, +0xac8200a8, 0x8f830018, 0x8f420e18, 0xac6200ac, +0x93620008, 0x14400041, 0x25260002, 0x8f840010, +0x9743008a, 0x3063ffff, 0xafa30000, 0x8fa20000, +0x441023, 0x2442ffff, 0x30421fff, 0x2c420010, +0x1440fff7, 0x0, 0x8f820010, 0x8f83001c, +0x21082, 0x21080, 0x24424000, 0x3422821, +0x605021, 0x24630001, 0x314200ff, 0x21400, +0xaf83001c, 0x3c033200, 0x431025, 0xaca20000, +0x93630009, 0x9362000a, 0x31c00, 0x431025, +0xaca20004, 0x8f83001c, 0x3c028000, 0xaca0000c, +0x10e00002, 0xaca30008, 0xaca2000c, 0x97820014, +0x30420008, 0x10400002, 0xc04021, 0x25280006, +0x97430e14, 0x93640002, 0x8f450e1c, 0x8f660004, +0x8f670014, 0x3063ffff, 0xa7430144, 0x97420e16, +0xa7420146, 0xaf450148, 0xa34a0152, 0x8f820010, +0x308400ff, 0xa744015a, 0xaf460160, 0xa7480158, +0xaf470154, 0xaf4e0178, 0x501021, 0x30421fff, +0xaf820010, 0xa0001cd, 0x8d820000, 0x93620009, +0x9363000b, 0x8f850010, 0x2463000a, 0x435021, +0x25440007, 0x982024, 0x9743008a, 0x3063ffff, +0xafa30000, 0x8fa20000, 0x451023, 0x2442ffff, +0x30421fff, 0x44102b, 0x1440fff7, 0x0, +0x8f820010, 0x8f84001c, 0x21082, 0x21080, +0x24424000, 0x3422821, 0x804021, 0x24840001, +0xaf84001c, 0x93630009, 0x310200ff, 0x22400, +0x3c024100, 0x24630002, 0x621825, 0x832025, +0xaca40000, 0x8f62000c, 0x471025, 0xaca20004, +0x97430e14, 0x93640002, 0x8f450e1c, 0x8f660004, +0x8f670014, 0x3063ffff, 0xa7430144, 0x97420e16, +0x308400ff, 0xa7420146, 0xaf450148, 0xa3480152, +0x8f830010, 0x25420007, 0x581024, 0xa744015a, +0xaf460160, 0xa7490158, 0xaf470154, 0xaf4e0178, +0x621821, 0x30631fff, 0xaf830010, 0x8d820000, +0x14400005, 0x0, 0x8f620014, 0x2403ffbf, +0x431024, 0xaf620014, 0x8f62000c, 0x4d1021, +0xaf62000c, 0x93630008, 0x14600008, 0x0, +0x11600006, 0x0, 0x8f630014, 0x3c02efff, +0x3442fffe, 0x621824, 0xaf630014, 0xa36b0008, +0x1206021, 0x1580000c, 0x8fa60008, 0x97420e14, +0x97430e16, 0x8f850018, 0x21400, 0x621825, +0xaca300a8, 0x8f840018, 0x8f420e1c, 0xac8200ac, +0xa0001f1, 0x2d820001, 0x14c0fe5c, 0x2d820001, +0x591025, 0x10400059, 0x24020f00, 0x8f83000c, +0x14620024, 0x3c048000, 0x1180000a, 0x3c038000, +0x97420e08, 0x30420040, 0x14400006, 0x0, +0x0, 0xd, 0x0, 0x24000284, +0x3c038000, 0x8f420178, 0x431024, 0x1440fffd, +0x0, 0x97420e10, 0x3c030500, 0x431025, +0xaf42014c, 0x97430e14, 0xa7430144, 0x97420e16, +0xa7420146, 0x8f430e1c, 0x24022000, 0xaf430148, +0x3c031000, 0xa3400152, 0xa740015a, 0xaf400160, +0xa7400158, 0xaf420154, 0xaf430178, 0x8f83000c, +0x3c048000, 0x8f420178, 0x441024, 0x1440fffd, +0x24020f00, 0x10620016, 0x0, 0x97420e14, +0xa7420144, 0x97430e16, 0xa7430146, 0x8f420e1c, +0x3c031000, 0xaf420148, 0xa000246, 0x24020240, +0x97420e14, 0x97430e16, 0x8f840018, 0x21400, +0x621825, 0xac8300a8, 0x8f850018, 0x8f420e1c, +0x6021, 0xaca200ac, 0xa0001f1, 0x2d820001, +0xaf40014c, 0x11800007, 0x0, 0x97420e10, +0xa7420144, 0x97430e12, 0xa7430146, 0xa000243, +0x8f420e18, 0x97420e14, 0xa7420144, 0x97430e16, +0xa7430146, 0x8f420e1c, 0xaf420148, 0x24020040, +0x3c031000, 0xa3400152, 0xa740015a, 0xaf400160, +0xa7400158, 0xaf420154, 0xaf430178, 0x8fb00010, +0x3e00008, 0x27bd0018, 0x27bdffd0, 0x3c1a8000, +0x3c0420ff, 0x3484fffd, 0x3c020008, 0x3421821, +0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020, +0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, +0xaf830018, 0xaf440e00, 0x0, 0x0, +0x0, 0x0, 0x0, 0x3c0200ff, +0x3442fffd, 0x3c036004, 0xaf420e00, 0x8c705000, +0x2402ff7f, 0x2028024, 0x3610380c, 0x3c026000, +0xac705000, 0x8c440438, 0x24030009, 0xaf430008, +0xaf80001c, 0xaf800010, 0x3090ffff, 0x3a102f71, +0xe000819, 0x2610c0b3, 0xe000302, 0x0, +0x16000003, 0x0, 0x3c016000, 0xac20442c, +0xe000830, 0x24160800, 0xe000b90, 0x24140d00, +0x3c020800, 0x24554690, 0x3c130800, 0x24120f00, +0x3c110800, 0x3c104000, 0x8f420000, 0x30420001, +0x1040fffd, 0x0, 0x8f420100, 0x3c038000, +0xaf82000c, 0xaf420020, 0x8f420178, 0x431024, +0x1440fffd, 0x0, 0xaf560178, 0x93430108, +0xa3830016, 0x93820016, 0x30420001, 0x10400008, +0x0, 0x93820016, 0x30420006, 0x21100, +0xe000030, 0x55d821, 0xa0002b0, 0x0, +0x8f82000c, 0x14540005, 0x0, 0xe000030, +0x267b4710, 0xa0002b0, 0x0, 0x14520005, +0x0, 0xe000030, 0x263b4730, 0xa0002b0, +0x0, 0xe00047f, 0x0, 0xaf500138, +0xa000287, 0x0, 0x27bdfff8, 0x3084ffff, +0x24820007, 0x3044fff8, 0x8f850010, 0x9743008a, +0x3063ffff, 0xafa30000, 0x8fa20000, 0x451023, +0x2442ffff, 0x30421fff, 0x44102b, 0x1440fff7, +0x0, 0x8f820010, 0x21082, 0x21080, +0x24424000, 0x3421021, 0x3e00008, 0x27bd0008, +0x3084ffff, 0x8f820010, 0x24840007, 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0x92030063, 0x97820066, 0x431021, +0xa6020012, 0x3043ffff, 0x2402fffc, 0x821024, +0x43102b, 0x10400003, 0x24020006, 0xa000f11, +0xa2000062, 0x96050012, 0x8e040020, 0x24020001, +0x24030008, 0xa2020062, 0x24020051, 0xa6030014, +0xae020050, 0xa6000026, 0x34840048, 0xae040020, +0x24044000, 0xe000f5f, 0xae050054, 0x8f840060, +0x8e030028, 0xae020058, 0xac830018, 0x96050012, +0x8e020028, 0x94830000, 0xa4910006, 0x451021, +0x2442ffff, 0x3063ffbf, 0x34630200, 0xac82001c, +0xa4830000, 0x93850078, 0x24020002, 0x8f840048, +0x51880, 0x651821, 0x318c0, 0x248400ac, +0x832021, 0x24050001, 0xac850000, 0xae05002c, +0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x3e00008, +0x27bd0020, 0x3c020800, 0x24464750, 0x90c30062, +0x804821, 0x10600030, 0x405021, 0x90c20063, +0x8f840070, 0x1040002e, 0x41082, 0x8cc30048, +0x83102b, 0x1440002a, 0x41082, 0x33882, +0x10e0000c, 0x2821, 0xc04021, 0x1203021, +0x8d030058, 0x51080, 0x431021, 0x8c440000, +0x24a50001, 0xa7102b, 0xacc40000, 0x1440fff8, +0x24c60004, 0x25484750, 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0xaca60024, 0x8c8201f4, 0x8c8301f8, +0xaca20028, 0xaca3002c, 0xa000fca, 0xa04821, +0x3c050800, 0x3c040800, 0x24844750, 0x9483000a, +0x8f880060, 0x24a74560, 0x35228002, 0xa4e20002, +0x2463000e, 0xa4a34560, 0x8d02000c, 0xace20004, +0x8c86002c, 0x8d050008, 0xc53023, 0x8d040010, +0x8d050014, 0xc01821, 0x1021, 0xa32821, +0xa3302b, 0x822021, 0x862021, 0xace40008, +0xace5000c, 0xa000fca, 0xe04821, 0x3c060800, +0x3c040800, 0x24844750, 0x9483000a, 0x8f870060, +0x24c54570, 0x35220003, 0xa4a20002, 0x24630012, +0xa000fc1, 0xa4c34570, 0x3c060800, 0x3c040800, +0x24844750, 0x9483000a, 0x8f870060, 0x24c54584, +0x35220005, 0xa4a20002, 0x24630012, 0xa4c34584, +0x8ce2000c, 0xaca2000c, 0x8c83002c, 0x8ce20008, +0xa04821, 0x621823, 0xa000fca, 0xaca30010, +0x4821, 0x3e00008, 0x1201021, 0x3c038000, +0x8f420178, 0x431024, 0x1440fffd, 0x3c020800, +0x24454750, 0x90a30064, 0xa3430150, 0x90a40062, +0x1080001a, 0x403021, 0x8ca2002c, 0x8ca40008, +0x93430980, 0x441023, 0x306300f0, 0x31a00, +0xaf420148, 0xa7430144, 0x8ca20020, 0x34421000, +0xaf420154, 0x94a3003e, 0xa743015a, 0x94a20042, +0xa742015c, 0x94a30046, 0xa743015e, 0x94a2005c, +0xaf420160, 0x94a3005e, 0xaf430164, 0x94a20060, +0xaf420168, 0xa000ff7, 0x24c54750, 0xaf400148, +0xa7400144, 0xa7400146, 0x8ca20020, 0x34421000, +0xaf420154, 0x24c54750, 0x8ca20028, 0xaf42014c, +0x90a30025, 0xa3430152, 0x94a2000a, 0x94a30026, +0x431021, 0x3c031000, 0xa7420158, 0xaf430178, +0x8ca20020, 0x30420008, 0x10400025, 0x0, +0x9382003c, 0x9383006c, 0x24440001, 0x3082007f, +0xa384003c, 0x14430003, 0x30820080, 0x38420080, +0xa382003c, 0x8f820048, 0x9383003c, 0xa0430083, +0x90a40062, 0x10800016, 0x3c038000, 0x8f420178, +0x431024, 0x1440fffd, 0x0, 0x9382003c, +0xa3420150, 0x9343010a, 0x24020080, 0xa3430151, +0x24c34750, 0xa3420152, 0xa7400158, 0x90620064, +0x3c038200, 0x3042007f, 0x431025, 0x24033000, +0xaf42014c, 0x3c021000, 0xaf430154, 0xaf420178, +0x3e00008, 0x0, 0x3c038000, 0x8f420178, +0x431024, 0x1440fffd, 0x3c050800, 0x24a64750, +0x90c30064, 0x8f840048, 0x3063007f, 0x31080, +0x431021, 0x210c0, 0x248400ac, 0x822021, +0x8c830000, 0xaf430148, 0x90c20064, 0xa3420150, +0xa7400144, 0xa7400146, 0x9342010a, 0x24030080, +0xa3420151, 0xa3430152, 0xa7400158, 0x90c30065, +0x24023000, 0x14600014, 0xacc20020, 0x90c20064, +0x3c038100, 0x3042007f, 0x431025, 0xaf42014c, +0x9383003c, 0x9384006c, 0x24630001, 0x3062007f, +0xa383003c, 0x14440003, 0x30620080, 0x38420080, +0xa382003c, 0x8f830048, 0x9382003c, 0xa0620083, +0xa001060, 0x24a24750, 0x9342010a, 0x3c038000, +0x431025, 0xaf42014c, 0x24a24750, 0x8c430020, +0x3c021000, 0xaf430154, 0x3e00008, 0xaf420178, +0x3c038000, 0x8f420178, 0x431024, 0x1440fffd, +0x3c020800, 0x24464750, 0x90c30065, 0x14600015, +0x402821, 0xa7400146, 0xa7400144, 0x8cc20028, +0x24030080, 0xaf42014c, 0xa3430152, 0xa7400158, +0x90c20064, 0xa3420150, 0x90c30064, 0x8f840048, +0x3063007f, 0x31080, 0x431021, 0x210c0, +0x248400ac, 0x822021, 0x8c830000, 0xa0010b9, +0x24021048, 0x24020002, 0x14620039, 0x0, +0x90c30064, 0x8f840048, 0x3063007f, 0x31080, +0x431021, 0x210c0, 0x248400ac, 0x822021, +0x8c830000, 0xaf430148, 0x90c20064, 0xa3420150, +0xa7400144, 0xa7400146, 0x9342010a, 0x24030080, +0xa3420151, 0xa3430152, 0xa7400158, 0x9342010a, +0x3c048000, 0x3c038300, 0x431025, 0x24033000, +0xaf42014c, 0x3c021000, 0xaf430154, 0xaf420178, +0x8f420178, 0x441024, 0x1440fffd, 0x0, +0x24a54750, 0xa7400146, 0xa7400144, 0x8ca20028, +0x24030080, 0xaf42014c, 0xa3430152, 0xa7400158, +0x90a20064, 0xa3420150, 0x90a30064, 0x8f840048, +0x3063007f, 0x31080, 0x431021, 0x210c0, +0x248400ac, 0x822021, 0x8c830000, 0x24021040, +0xaf430148, 0x3c031000, 0xaf420154, 0xaf430178, +0x3e00008, 0x0, 0x3c026000, 0x3e00008, +0xac400808, 0x3c020800, 0x24424750, 0xac400008, +0xa4400026, 0x3e00008, 0x24020001, 0x93830078, +0x3c050800, 0x24a54750, 0xa0a00062, 0x8f840048, +0xaca00008, 0xa4a00026, 0x31080, 0x431021, +0x210c0, 0x248400ac, 0x822021, 0x24030001, +0x24020056, 0xac830000, 0x3e00008, 0xa0a00065, +0x3c020800, 0x24464750, 0x90c30062, 0x10600015, +0x802821, 0x8cc20050, 0x90c30025, 0x94c4001e, +0x21600, 0x31c00, 0x431025, 0x24840002, +0x441025, 0xaca20000, 0x8cc30054, 0x94c20018, +0x31c00, 0x621825, 0xaca30004, 0x8cc40050, +0x24020062, 0x1482000d, 0x24a50008, 0xa0010fa, +0x8cc2004c, 0x90c20025, 0x94c3001e, 0x3c041100, +0xaca00004, 0x21400, 0x24630002, 0x641825, +0x431025, 0xaca20000, 0x24a50008, 0x3e00008, +0xa01021, 0x308500ff, 0x3c038000, 0x8f420178, +0x431024, 0x1440fffd, 0x24041040, 0x3c030800, +0x24634750, 0xa7400144, 0xa7400146, 0xac640020, +0xaf440154, 0x8c620028, 0xaf42014c, 0x8c630028, +0x8f82005c, 0x62102b, 0x10400002, 0x24020001, +0xaf82007c, 0xaf83005c, 0xa3400152, 0x9342010a, +0x30a3007f, 0xa3420151, 0xa7400158, 0xa3450150, +0x8f840048, 0x31080, 0x431021, 0x210c0, +0x248400ac, 0x822021, 0x8c830000, 0x3c021000, +0xaf430148, 0x3e00008, 0xaf420178, 0x308400ff, +0x3082007f, 0x50400004, 0x24020080, 0x2482ffff, +0x3e00008, 0x304200ff, 0x10820005, 0x0, +0x9382006c, 0x2442007f, 0x3e00008, 0x304200ff, +0x9382006c, 0x2442ffff, 0x3e00008, 0x304200ff, +0x0 }; +static u32 bce_TXP_b06FwData[(0xd0/4) + 1] = { +0x0, +0x14, 0x14, 0x14, 0x14, +0x10, 0x30, 0x30, 0x0, +0x0, 0x0, 0x10, 0x8000, +0x0, 0x0, 0x0, 0x8002, +0x0, 0x0, 0x0, 0x3, +0x0, 0x0, 0x0, 0x0, +0x5, 0x0, 0x0, 0x0, +0x0, 0x4, 0x0, 0x0, +0x0, 0x0, 0x6, 0x0, +0x0, 0x0, 0x0, 0x1, +0x0, 0x1, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0 }; +static u32 bce_TXP_b06FwRodata[(0x30/4) + 1] = { +0x8003eb0, 0x8003edc, 0x8003f24, +0x8003f24, 0x8003db0, 0x8003ddc, 0x8003ddc, +0x8003f24, 0x8003f24, 0x8003f24, 0x8003e44, +0x0, 0x0 }; +static u32 bce_TXP_b06FwBss[(0xa20/4) + 1] = { 0x0 }; +static u32 bce_TXP_b06FwSbss[(0x80/4) + 1] = { 0x0 }; +/* static u32 bce_TXP_b06FwSdata[(0x0/4) + 1] = { 0x0 }; */ + +#undef u32 diff --git a/sys/dev/netif/bce/if_bcereg.h b/sys/dev/netif/bce/if_bcereg.h new file mode 100644 index 0000000000..75b300754e --- /dev/null +++ b/sys/dev/netif/bce/if_bcereg.h @@ -0,0 +1,4823 @@ +/*- + * Copyright (c) 2006-2007 Broadcom Corporation + * David Christensen . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Broadcom Corporation nor the name of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written consent. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.13 2007/05/16 23:34:11 davidch Exp $ + * $DragonFly: src/sys/dev/netif/bce/if_bcereg.h,v 1.1 2007/05/26 08:50:49 sephe Exp $ + */ + +#ifndef _BCE_H_DEFINED +#define _BCE_H_DEFINED + +/****************************************************************************/ +/* Debugging macros and definitions. */ +/****************************************************************************/ +#ifdef BCE_DEBUG + +#define BCE_CP_LOAD 0x00000001 +#define BCE_CP_SEND 0x00000002 +#define BCE_CP_RECV 0x00000004 +#define BCE_CP_INTR 0x00000008 +#define BCE_CP_UNLOAD 0x00000010 +#define BCE_CP_RESET 0x00000020 +#define BCE_CP_ALL 0x00FFFFFF + +#define BCE_CP_MASK 0x00FFFFFF + +#define BCE_LEVEL_FATAL 0x00000000 +#define BCE_LEVEL_WARN 0x01000000 +#define BCE_LEVEL_INFO 0x02000000 +#define BCE_LEVEL_VERBOSE 0x03000000 +#define BCE_LEVEL_EXCESSIVE 0x04000000 + +#define BCE_LEVEL_MASK 0xFF000000 + +#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) +#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) +#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) +#define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE) + +#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) +#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) +#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) +#define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE) + +#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) +#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) +#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) +#define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE) + +#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) +#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) +#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) +#define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE) + +#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) +#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) +#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) +#define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE) + +#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) +#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) +#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) +#define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE) + +#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) +#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) +#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) +#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) +#define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE) + +#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) +#define BCE_MSG_LEVEL(lv) \ + ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) +#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) + +/* Print a message based on the logging level and code path. */ +#define DBPRINT(sc, level, format, args...) \ +do { \ + if (BCE_LOG_MSG(level)) \ + if_printf(&sc->arpcom.ac_if, format, ## args); \ +} while (0) + +/* Runs a particular command based on the logging level and code path. */ +#define DBRUN(m, args...) \ +do { \ + if (BCE_LOG_MSG(m)) { \ + args; \ + } \ +} while (0) + +/* Runs a particular command based on the logging level. */ +#define DBRUNLV(level, args...) \ +do { \ + if (BCE_MSG_LEVEL(level)) { \ + args; \ + } \ +} while (0) + +/* Runs a particular command based on the code path. */ +#define DBRUNCP(cp, args...) \ +do { \ + if (BCE_CODE_PATH(cp)) { \ + args; \ + } \ +} while (0) + +/* Runs a particular command based on a condition. */ +#define DBRUNIF(cond, args...) \ +do { \ + if (cond) { \ + args; \ + } \ +} while (0) + +/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ +#define DB_RANDOMFALSE(defects) (krandom() > defects) +#define DB_OR_RANDOMFALSE(defects) || (krandom() > defects) +#define DB_AND_RANDOMFALSE(defects) && (krandom() > ddfects) + +/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ +#define DB_RANDOMTRUE(defects) (krandom() < defects) +#define DB_OR_RANDOMTRUE(defects) || (krandom() < defects) +#define DB_AND_RANDOMTRUE(defects) && (krandom() < defects) + +#else /* !BCE_DEBUG */ + +#define DBPRINT(level, format, args...) +#define DBRUN(m, args...) +#define DBRUNLV(level, args...) +#define DBRUNCP(cp, args...) +#define DBRUNIF(cond, args...) +#define DB_RANDOMFALSE(defects) +#define DB_OR_RANDOMFALSE(percent) +#define DB_AND_RANDOMFALSE(percent) +#define DB_RANDOMTRUE(defects) +#define DB_OR_RANDOMTRUE(percent) +#define DB_AND_RANDOMTRUE(percent) + +#endif /* BCE_DEBUG */ + + +/****************************************************************************/ +/* Device identification definitions. */ +/****************************************************************************/ +#define BRCM_VENDORID 0x14E4 +#define BRCM_DEVICEID_BCM5706 0x164A +#define BRCM_DEVICEID_BCM5706S 0x16AA +#define BRCM_DEVICEID_BCM5708 0x164C +#define BRCM_DEVICEID_BCM5708S 0x16AC + +#define HP_VENDORID 0x103C + +#define PCI_ANY_ID (uint16_t) (~0U) + +/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ + +#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) +#define BCE_CHIP_NUM_5706 0x57060000 +#define BCE_CHIP_NUM_5708 0x57080000 + +#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) +#define BCE_CHIP_REV_Ax 0x00000000 +#define BCE_CHIP_REV_Bx 0x00001000 +#define BCE_CHIP_REV_Cx 0x00002000 + +#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) +#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) + +#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) +#define BCE_CHIP_ID_5706_A0 0x57060000 +#define BCE_CHIP_ID_5706_A1 0x57060010 +#define BCE_CHIP_ID_5706_A2 0x57060020 +#define BCE_CHIP_ID_5706_A3 0x57060030 +#define BCE_CHIP_ID_5708_A0 0x57080000 +#define BCE_CHIP_ID_5708_B0 0x57081000 +#define BCE_CHIP_ID_5708_B1 0x57081010 +#define BCE_CHIP_ID_5708_B2 0x57081020 + +#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) + +/* A serdes chip will have the first bit of the bond id set. */ +#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 + + +/* shorthand one */ +#define BCE_ASICREV(x) ((x) >> 28) +#define BCE_ASICREV_BCM5700 0x06 + +/* chip revisions */ +#define BCE_CHIPREV(x) ((x) >> 24) +#define BCE_CHIPREV_5700_AX 0x70 +#define BCE_CHIPREV_5700_BX 0x71 +#define BCE_CHIPREV_5700_CX 0x72 +#define BCE_CHIPREV_5701_AX 0x00 + +struct bce_type { + uint16_t bce_vid; + uint16_t bce_did; + uint16_t bce_svid; + uint16_t bce_sdid; + const char *bce_name; +}; + +/****************************************************************************/ +/* NVRAM Access */ +/****************************************************************************/ + +/* Buffered flash (Atmel: AT45DB011B) specific information */ +#define SEEPROM_PAGE_BITS 2 +#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) +#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) +#define SEEPROM_PAGE_SIZE 4 +#define SEEPROM_TOTAL_SIZE 65536 + +#define BUFFERED_FLASH_PAGE_BITS 9 +#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) +#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) +#define BUFFERED_FLASH_PAGE_SIZE 264 +#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 + +#define SAIFUN_FLASH_PAGE_BITS 8 +#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) +#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) +#define SAIFUN_FLASH_PAGE_SIZE 256 +#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 + +#define ST_MICRO_FLASH_PAGE_BITS 8 +#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) +#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) +#define ST_MICRO_FLASH_PAGE_SIZE 256 +#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 + +#define NVRAM_TIMEOUT_COUNT 30000 +#define BCE_FLASHDESC_MAX 64 + +#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ + BCE_NVM_CFG1_BUFFER_MODE | \ + BCE_NVM_CFG1_PROTECT_MODE | \ + BCE_NVM_CFG1_FLASH_SIZE) + +#define FLASH_BACKUP_STRAP_MASK (0xf << 26) + +struct flash_spec { + uint32_t strapping; + uint32_t config1; + uint32_t config2; + uint32_t config3; + uint32_t write1; + uint32_t buffered; + uint32_t page_bits; + uint32_t page_size; + uint32_t addr_mask; + uint32_t total_size; + uint8_t *name; +}; + + +/****************************************************************************/ +/* Shared Memory layout */ +/* The BCE bootcode will initialize this data area with port configurtion */ +/* information which can be accessed by the driver. */ +/****************************************************************************/ + +/* + * This value (in milliseconds) determines the frequency of the driver + * issuing the PULSE message code. The firmware monitors this periodic + * pulse to determine when to switch to an OS-absent mode. + */ +#define DRV_PULSE_PERIOD_MS 250 + +/* + * This value (in milliseconds) determines how long the driver should + * wait for an acknowledgement from the firmware before timing out. Once + * the firmware has timed out, the driver will assume there is no firmware + * running and there won't be any firmware-driver synchronization during a + * driver reset. + */ +#define FW_ACK_TIME_OUT_MS 100 + + +#define BCE_DRV_RESET_SIGNATURE 0x00000000 +#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ + +#define BCE_DRV_MB 0x00000004 +#define BCE_DRV_MSG_CODE 0xff000000 +#define BCE_DRV_MSG_CODE_RESET 0x01000000 +#define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 +#define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 +#define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 +#define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 +#define BCE_DRV_MSG_CODE_PULSE 0x06000000 +#define BCE_DRV_MSG_CODE_DIAG 0x07000000 +#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 + +#define BCE_DRV_MSG_DATA 0x00ff0000 +#define BCE_DRV_MSG_DATA_WAIT0 0x00010000 +#define BCE_DRV_MSG_DATA_WAIT1 0x00020000 +#define BCE_DRV_MSG_DATA_WAIT2 0x00030000 +#define BCE_DRV_MSG_DATA_WAIT3 0x00040000 + +#define BCE_DRV_MSG_SEQ 0x0000ffff + +#define BCE_FW_MB 0x00000008 +#define BCE_FW_MSG_ACK 0x0000ffff +#define BCE_FW_MSG_STATUS_MASK 0x00ff0000 +#define BCE_FW_MSG_STATUS_OK 0x00000000 +#define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 + +#define BCE_LINK_STATUS 0x0000000c +#define BCE_LINK_STATUS_INIT_VALUE 0xffffffff +#define BCE_LINK_STATUS_LINK_UP 0x1 +#define BCE_LINK_STATUS_LINK_DOWN 0x0 +#define BCE_LINK_STATUS_SPEED_MASK 0x1e +#define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) +#define BCE_LINK_STATUS_10HALF (1<<1) +#define BCE_LINK_STATUS_10FULL (2<<1) +#define BCE_LINK_STATUS_100HALF (3<<1) +#define BCE_LINK_STATUS_100BASE_T4 (4<<1) +#define BCE_LINK_STATUS_100FULL (5<<1) +#define BCE_LINK_STATUS_1000HALF (6<<1) +#define BCE_LINK_STATUS_1000FULL (7<<1) +#define BCE_LINK_STATUS_2500HALF (8<<1) +#define BCE_LINK_STATUS_2500FULL (9<<1) +#define BCE_LINK_STATUS_AN_ENABLED (1<<5) +#define BCE_LINK_STATUS_AN_COMPLETE (1<<6) +#define BCE_LINK_STATUS_PARALLEL_DET (1<<7) +#define BCE_LINK_STATUS_RESERVED (1<<8) +#define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) +#define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) +#define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) +#define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) +#define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) +#define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) +#define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) +#define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) +#define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) +#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) +#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) +#define BCE_LINK_STATUS_SERDES_LINK (1<<20) +#define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) +#define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) + +#define BCE_DRV_PULSE_MB 0x00000010 +#define BCE_DRV_PULSE_SEQ_MASK 0x00007fff + +/* Indicate to the firmware not to go into the + * OS absent when it is not getting driver pulse. + * This is used for debugging. */ +#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 + +#define BCE_DEV_INFO_SIGNATURE 0x00000020 +#define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 +#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 +#define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 +#define BCE_DEV_INFO_SECONDARY_PORT 0x80 +#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 + +#define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 + +#define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 +#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 +#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 +#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 +#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff + +#define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 +#define BCE_SHARED_HW_CFG_CONFIG 0x0000003c +#define BCE_SHARED_HW_CFG_DESIGN_NIC 0 +#define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 +#define BCE_SHARED_HW_CFG_PHY_COPPER 0 +#define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 +#define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 +#define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 +#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 +#define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 +#define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 +#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 +#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 + +#define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 +#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 + +#define BCE_DEV_INFO_BC_REV 0x0000004c + +#define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 +#define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff + +#define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 +#define BCE_PORT_HW_CFG_CONFIG 0x00000058 +#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 +#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 + +#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 +#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c +#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 +#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 +#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 +#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c + +#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 + +#define BCE_DEV_INFO_FORMAT_REV 0x000000c4 +#define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 +#define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) + +#define BCE_SHARED_FEATURE 0x000000c8 +#define BCE_SHARED_FEATURE_MASK 0xffffffff + +#define BCE_PORT_FEATURE 0x000000d8 +#define BCE_PORT2_FEATURE 0x00000014c +#define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 +#define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 +#define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 +#define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 +#define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf +#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 +#define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 +#define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 +#define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 +#define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 +#define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 +#define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 +#define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 +#define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 +#define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 +#define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa +#define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb +#define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc +#define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd +#define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe +#define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf + +#define BCE_PORT_FEATURE_WOL 0xdc +#define BCE_PORT2_FEATURE_WOL 0x150 +#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 +#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 +#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 +#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 +#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 +#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 +#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 +#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 +#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 +#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 + +#define BCE_PORT_FEATURE_MBA 0xe0 +#define BCE_PORT2_FEATURE_MBA 0x154 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 +#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 +#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 +#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 +#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 +#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 +#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 +#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 +#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 +#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 + +#define BCE_PORT_FEATURE_IMD 0xe4 +#define BCE_PORT2_FEATURE_IMD 0x158 +#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 +#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 + +#define BCE_PORT_FEATURE_VLAN 0xe8 +#define BCE_PORT2_FEATURE_VLAN 0x15c +#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff +#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 + +#define BCE_BC_STATE_RESET_TYPE 0x000001c0 +#define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 +#define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff +#define BCE_BC_STATE_RESET_TYPE_NONE (BCE_BC_STATE_RESET_TYPE_SIG | \ + 0x00010000) +#define BCE_BC_STATE_RESET_TYPE_PCI (BCE_BC_STATE_RESET_TYPE_SIG | \ + 0x00020000) +#define BCE_BC_STATE_RESET_TYPE_VAUX (BCE_BC_STATE_RESET_TYPE_SIG | \ + 0x00030000) +#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE +#define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_RESET) +#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_UNLOAD) +#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_SHUTDOWN) +#define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_WOL) +#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \ + DRV_MSG_CODE_DIAG) +#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \ + (msg)) + +#define BCE_BC_STATE 0x000001c4 +#define BCE_BC_STATE_ERR_MASK 0x0000ff00 +#define BCE_BC_STATE_SIGN 0x42530000 +#define BCE_BC_STATE_SIGN_MASK 0xffff0000 +#define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) +#define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) +#define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) +#define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) +#define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) +#define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) +#define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) +#define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) +#define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) +#define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) +#define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) +#define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) +#define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) +#define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) +#define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) +#define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) +#define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) +#define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) +#define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) +#define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) +#define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) +#define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) +#define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) +#define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) +#define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) + +#define BCE_BC_STATE_DEBUG_CMD 0x1dc +#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 +#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 +#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff +#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff + +#define HOST_VIEW_SHMEM_BASE 0x167c00 + +/* + * PCI registers defined in the PCI 2.2 spec. + */ +#define BCE_PCI_PCIX_CMD 0x42 + + +/****************************************************************************/ +/* Convenience definitions. */ +/****************************************************************************/ +#define REG_WR(sc, reg, val) \ + bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val) +#define REG_WR16(sc, reg, val) \ + bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val) +#define REG_RD(sc, reg) \ + bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg) + +#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) +#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) + +#define CTX_WR(sc, cid_addr, offset, val) \ + bce_ctx_wr(sc, cid_addr, offset, val) + +#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) +#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) + +#define PCI_SETBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) +#define PCI_CLRBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) + +#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo +#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) +#define BCE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) +#define BCE_ADDR_HI(y) ((uint64_t) (y) >> 32) +#else +#define BCE_ADDR_LO(y) ((uint32_t)y) +#define BCE_ADDR_HI(y) (0) +#endif + + +/* + * The following data structures are generated from RTL code. + * Do not modify any values below this line. + */ + +/****************************************************************************/ +/* Do not modify any of the following data structures, they are generated */ +/* from RTL code. */ +/* */ +/* Begin machine generated definitions. */ +/****************************************************************************/ + +/* + * tx_bd definition + */ +struct tx_bd { + uint32_t tx_bd_haddr_hi; + uint32_t tx_bd_haddr_lo; + uint32_t tx_bd_mss_nbytes; + uint16_t tx_bd_flags; + uint16_t tx_bd_vlan_tag; +#define TX_BD_FLAGS_CONN_FAULT (1<<0) +#define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) +#define TX_BD_FLAGS_IP_CKSUM (1<<2) +#define TX_BD_FLAGS_VLAN_TAG (1<<3) +#define TX_BD_FLAGS_COAL_NOW (1<<4) +#define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) +#define TX_BD_FLAGS_END (1<<6) +#define TX_BD_FLAGS_START (1<<7) +#define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) +#define TX_BD_FLAGS_SW_FLAGS (1<<13) +#define TX_BD_FLAGS_SW_SNAP (1<<14) +#define TX_BD_FLAGS_SW_LSO (1<<15) +}; + + +/* + * rx_bd definition + */ +struct rx_bd { + uint32_t rx_bd_haddr_hi; + uint32_t rx_bd_haddr_lo; + uint32_t rx_bd_len; + uint32_t rx_bd_flags; +#define RX_BD_FLAGS_NOPUSH (1<<0) +#define RX_BD_FLAGS_DUMMY (1<<1) +#define RX_BD_FLAGS_END (1<<2) +#define RX_BD_FLAGS_START (1<<3) +}; + + +/* + * status_block definition + */ +struct status_block { + uint32_t status_attn_bits; +#define STATUS_ATTN_BITS_LINK_STATE (1L<<0) +#define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) +#define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) +#define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) +#define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) +#define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) +#define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) +#define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) +#define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) +#define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) +#define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) +#define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) +#define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) +#define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) +#define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) +#define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) +#define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) +#define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) +#define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) +#define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) +#define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) +#define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) +#define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) +#define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) +#define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) +#define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) +#define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) +#define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) +#define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) + + uint32_t status_attn_bits_ack; +#if BYTE_ORDER == BIG_ENDIAN + uint16_t status_tx_quick_consumer_index0; + uint16_t status_tx_quick_consumer_index1; + uint16_t status_tx_quick_consumer_index2; + uint16_t status_tx_quick_consumer_index3; + uint16_t status_rx_quick_consumer_index0; + uint16_t status_rx_quick_consumer_index1; + uint16_t status_rx_quick_consumer_index2; + uint16_t status_rx_quick_consumer_index3; + uint16_t status_rx_quick_consumer_index4; + uint16_t status_rx_quick_consumer_index5; + uint16_t status_rx_quick_consumer_index6; + uint16_t status_rx_quick_consumer_index7; + uint16_t status_rx_quick_consumer_index8; + uint16_t status_rx_quick_consumer_index9; + uint16_t status_rx_quick_consumer_index10; + uint16_t status_rx_quick_consumer_index11; + uint16_t status_rx_quick_consumer_index12; + uint16_t status_rx_quick_consumer_index13; + uint16_t status_rx_quick_consumer_index14; + uint16_t status_rx_quick_consumer_index15; + uint16_t status_completion_producer_index; + uint16_t status_cmd_consumer_index; + uint16_t status_idx; + uint16_t status_unused; +#else + uint16_t status_tx_quick_consumer_index1; + uint16_t status_tx_quick_consumer_index0; + uint16_t status_tx_quick_consumer_index3; + uint16_t status_tx_quick_consumer_index2; + uint16_t status_rx_quick_consumer_index1; + uint16_t status_rx_quick_consumer_index0; + uint16_t status_rx_quick_consumer_index3; + uint16_t status_rx_quick_consumer_index2; + uint16_t status_rx_quick_consumer_index5; + uint16_t status_rx_quick_consumer_index4; + uint16_t status_rx_quick_consumer_index7; + uint16_t status_rx_quick_consumer_index6; + uint16_t status_rx_quick_consumer_index9; + uint16_t status_rx_quick_consumer_index8; + uint16_t status_rx_quick_consumer_index11; + uint16_t status_rx_quick_consumer_index10; + uint16_t status_rx_quick_consumer_index13; + uint16_t status_rx_quick_consumer_index12; + uint16_t status_rx_quick_consumer_index15; + uint16_t status_rx_quick_consumer_index14; + uint16_t status_cmd_consumer_index; + uint16_t status_completion_producer_index; + uint16_t status_unused; + uint16_t status_idx; +#endif +}; + + +/* + * statistics_block definition + */ +struct statistics_block { + uint32_t stat_IfHCInOctets_hi; + uint32_t stat_IfHCInOctets_lo; + uint32_t stat_IfHCInBadOctets_hi; + uint32_t stat_IfHCInBadOctets_lo; + uint32_t stat_IfHCOutOctets_hi; + uint32_t stat_IfHCOutOctets_lo; + uint32_t stat_IfHCOutBadOctets_hi; + uint32_t stat_IfHCOutBadOctets_lo; + uint32_t stat_IfHCInUcastPkts_hi; + uint32_t stat_IfHCInUcastPkts_lo; + uint32_t stat_IfHCInMulticastPkts_hi; + uint32_t stat_IfHCInMulticastPkts_lo; + uint32_t stat_IfHCInBroadcastPkts_hi; + uint32_t stat_IfHCInBroadcastPkts_lo; + uint32_t stat_IfHCOutUcastPkts_hi; + uint32_t stat_IfHCOutUcastPkts_lo; + uint32_t stat_IfHCOutMulticastPkts_hi; + uint32_t stat_IfHCOutMulticastPkts_lo; + uint32_t stat_IfHCOutBroadcastPkts_hi; + uint32_t stat_IfHCOutBroadcastPkts_lo; + uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + uint32_t stat_Dot3StatsCarrierSenseErrors; + uint32_t stat_Dot3StatsFCSErrors; + uint32_t stat_Dot3StatsAlignmentErrors; + uint32_t stat_Dot3StatsSingleCollisionFrames; + uint32_t stat_Dot3StatsMultipleCollisionFrames; + uint32_t stat_Dot3StatsDeferredTransmissions; + uint32_t stat_Dot3StatsExcessiveCollisions; + uint32_t stat_Dot3StatsLateCollisions; + uint32_t stat_EtherStatsCollisions; + uint32_t stat_EtherStatsFragments; + uint32_t stat_EtherStatsJabbers; + uint32_t stat_EtherStatsUndersizePkts; + uint32_t stat_EtherStatsOverrsizePkts; + uint32_t stat_EtherStatsPktsRx64Octets; + uint32_t stat_EtherStatsPktsRx65Octetsto127Octets; + uint32_t stat_EtherStatsPktsRx128Octetsto255Octets; + uint32_t stat_EtherStatsPktsRx256Octetsto511Octets; + uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets; + uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; + uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; + uint32_t stat_EtherStatsPktsTx64Octets; + uint32_t stat_EtherStatsPktsTx65Octetsto127Octets; + uint32_t stat_EtherStatsPktsTx128Octetsto255Octets; + uint32_t stat_EtherStatsPktsTx256Octetsto511Octets; + uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets; + uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; + uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; + uint32_t stat_XonPauseFramesReceived; + uint32_t stat_XoffPauseFramesReceived; + uint32_t stat_OutXonSent; + uint32_t stat_OutXoffSent; + uint32_t stat_FlowControlDone; + uint32_t stat_MacControlFramesReceived; + uint32_t stat_XoffStateEntered; + uint32_t stat_IfInFramesL2FilterDiscards; + uint32_t stat_IfInRuleCheckerDiscards; + uint32_t stat_IfInFTQDiscards; + uint32_t stat_IfInMBUFDiscards; + uint32_t stat_IfInRuleCheckerP4Hit; + uint32_t stat_CatchupInRuleCheckerDiscards; + uint32_t stat_CatchupInFTQDiscards; + uint32_t stat_CatchupInMBUFDiscards; + uint32_t stat_CatchupInRuleCheckerP4Hit; + uint32_t stat_GenStat00; + uint32_t stat_GenStat01; + uint32_t stat_GenStat02; + uint32_t stat_GenStat03; + uint32_t stat_GenStat04; + uint32_t stat_GenStat05; + uint32_t stat_GenStat06; + uint32_t stat_GenStat07; + uint32_t stat_GenStat08; + uint32_t stat_GenStat09; + uint32_t stat_GenStat10; + uint32_t stat_GenStat11; + uint32_t stat_GenStat12; + uint32_t stat_GenStat13; + uint32_t stat_GenStat14; + uint32_t stat_GenStat15; +}; + + +/* + * l2_fhdr definition + */ +struct l2_fhdr { + uint32_t l2_fhdr_status; +#define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) +#define L2_FHDR_STATUS_RULE_P2 (1<<3) +#define L2_FHDR_STATUS_RULE_P3 (1<<4) +#define L2_FHDR_STATUS_RULE_P4 (1<<5) +#define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) +#define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) +#define L2_FHDR_STATUS_RSS_HASH (1<<8) +#define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) +#define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) +#define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) + +#define L2_FHDR_ERRORS_BAD_CRC (1<<17) +#define L2_FHDR_ERRORS_PHY_DECODE (1<<18) +#define L2_FHDR_ERRORS_ALIGNMENT (1<<19) +#define L2_FHDR_ERRORS_TOO_SHORT (1<<20) +#define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) +#define L2_FHDR_ERRORS_TCP_XSUM (1<<28) +#define L2_FHDR_ERRORS_UDP_XSUM (1<<31) + + uint32_t l2_fhdr_hash; +#if BYTE_ORDER == BIG_ENDIAN + uint16_t l2_fhdr_pkt_len; + uint16_t l2_fhdr_vlan_tag; + uint16_t l2_fhdr_ip_xsum; + uint16_t l2_fhdr_tcp_udp_xsum; +#else + uint16_t l2_fhdr_vlan_tag; + uint16_t l2_fhdr_pkt_len; + uint16_t l2_fhdr_tcp_udp_xsum; + uint16_t l2_fhdr_ip_xsum; +#endif +}; + + +/* + * l2_context definition + */ +#define BCE_L2CTX_TYPE 0x00000000 +#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) +#define BCE_L2CTX_TYPE_TYPE (0xf<<28) +#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28) +#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28) + +#define BCE_L2CTX_TX_HOST_BIDX 0x00000088 +#define BCE_L2CTX_EST_NBD 0x00000088 +#define BCE_L2CTX_CMD_TYPE 0x00000088 +#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24) +#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) +#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) + +#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 +#define BCE_L2CTX_TSCH_BSEQ 0x00000094 +#define BCE_L2CTX_TBDR_BSEQ 0x00000098 +#define BCE_L2CTX_TBDR_BOFF 0x0000009c +#define BCE_L2CTX_TBDR_BIDX 0x0000009c +#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0 +#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4 +#define BCE_L2CTX_TXP_BOFF 0x000000a8 +#define BCE_L2CTX_TXP_BIDX 0x000000a8 +#define BCE_L2CTX_TXP_BSEQ 0x000000ac + + +/* + * l2_bd_chain_context definition + */ +#define BCE_L2CTX_BD_PRE_READ 0x00000000 +#define BCE_L2CTX_CTX_SIZE 0x00000000 +#define BCE_L2CTX_CTX_TYPE 0x00000000 +#define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) +#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) +#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) +#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) + +#define BCE_L2CTX_HOST_BDIDX 0x00000004 +#define BCE_L2CTX_HOST_BSEQ 0x00000008 +#define BCE_L2CTX_NX_BSEQ 0x0000000c +#define BCE_L2CTX_NX_BDHADDR_HI 0x00000010 +#define BCE_L2CTX_NX_BDHADDR_LO 0x00000014 +#define BCE_L2CTX_NX_BDIDX 0x00000018 + + +/* + * pci_config_l definition + * offset: 0000 + */ +#define BCE_PCICFG_MISC_CONFIG 0x00000068 +#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) +#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) +#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) +#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) +#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) +#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) +#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) +#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) +#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) +#define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) +#define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) + +#define BCE_PCICFG_MISC_STATUS 0x0000006c +#define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) +#define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) +#define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) +#define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) +#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) +#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) +#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) +#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) +#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) + +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) +#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) + +#define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 +#define BCE_PCICFG_REG_WINDOW 0x00000080 +#define BCE_PCICFG_INT_ACK_CMD 0x00000084 +#define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) +#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) +#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) +#define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) + +#define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 +#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c +#define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 +#define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 + + +/* + * pci_reg definition + * offset: 0x400 + */ +#define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 +#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) + +#define BCE_PCI_CONFIG_1 0x00000404 +#define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) +#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) +#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) + +#define BCE_PCI_CONFIG_2 0x00000408 +#define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) +#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) +#define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) +#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) +#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) +#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) +#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) +#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) +#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) +#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) +#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) +#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) +#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) +#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) +#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) +#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) + +#define BCE_PCI_CONFIG_3 0x0000040c +#define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) +#define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) +#define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) +#define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) +#define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) +#define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) +#define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) + +#define BCE_PCI_PM_DATA_A 0x00000410 +#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) +#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) +#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) +#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) + +#define BCE_PCI_PM_DATA_B 0x00000414 +#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) +#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) +#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) +#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) + +#define BCE_PCI_SWAP_DIAG0 0x00000418 +#define BCE_PCI_SWAP_DIAG1 0x0000041c +#define BCE_PCI_EXP_ROM_ADDR 0x00000420 +#define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) +#define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) + +#define BCE_PCI_EXP_ROM_DATA 0x00000424 +#define BCE_PCI_VPD_INTF 0x00000428 +#define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) + +#define BCE_PCI_VPD_ADDR_FLAG 0x0000042c +#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) +#define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) + +#define BCE_PCI_VPD_DATA 0x00000430 +#define BCE_PCI_ID_VAL1 0x00000434 +#define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) +#define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) + +#define BCE_PCI_ID_VAL2 0x00000438 +#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) +#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) + +#define BCE_PCI_ID_VAL3 0x0000043c +#define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) +#define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) + +#define BCE_PCI_ID_VAL4 0x00000440 +#define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) +#define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) +#define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) +#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) +#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) +#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) +#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) +#define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) +#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) +#define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) +#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) +#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) +#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) +#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) +#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) + +#define BCE_PCI_ID_VAL5 0x00000444 +#define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) +#define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) +#define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) +#define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) +#define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) +#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) + +#define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 +#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) +#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) +#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) +#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) + +#define BCE_PCI_ID_VAL6 0x0000044c +#define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) +#define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) +#define BCE_PCI_ID_VAL6_BIST (0xffL<<16) + +#define BCE_PCI_MSI_DATA 0x00000450 +#define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) + +#define BCE_PCI_MSI_ADDR_H 0x00000454 +#define BCE_PCI_MSI_ADDR_L 0x00000458 + + +/* + * misc_reg definition + * offset: 0x800 + */ +#define BCE_MISC_COMMAND 0x00000800 +#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) +#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) +#define BCE_MISC_COMMAND_CORE_RESET (1L<<4) +#define BCE_MISC_COMMAND_HARD_RESET (1L<<5) +#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) +#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) + +#define BCE_MISC_CFG 0x00000804 +#define BCE_MISC_CFG_PCI_GRC_TMOUT (1L<<0) +#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) +#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) +#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) +#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) +#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) +#define BCE_MISC_CFG_BIST_EN (1L<<3) +#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) +#define BCE_MISC_CFG_BYPASS_BSCAN (1L<<5) +#define BCE_MISC_CFG_BYPASS_EJTAG (1L<<6) +#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) +#define BCE_MISC_CFG_LEDMODE (0x3L<<8) +#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) +#define BCE_MISC_CFG_LEDMODE_GPHY1 (1L<<8) +#define BCE_MISC_CFG_LEDMODE_GPHY2 (2L<<8) + +#define BCE_MISC_ID 0x00000808 +#define BCE_MISC_ID_BOND_ID (0xfL<<0) +#define BCE_MISC_ID_CHIP_METAL (0xffL<<4) +#define BCE_MISC_ID_CHIP_REV (0xfL<<12) +#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) + +#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c +#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) +#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) +#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) +#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) +#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) + +#define BCE_MISC_ENABLE_SET_BITS 0x00000810 +#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) +#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) +#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) +#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) +#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) +#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) +#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) +#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) +#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) + +#define BCE_MISC_ENABLE_CLR_BITS 0x00000814 +#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) +#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) +#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) +#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) +#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) +#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) +#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) +#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) +#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) + +#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) +#define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) +#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) +#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) +#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) +#define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) +#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) + +#define BCE_MISC_GPIO 0x0000081c +#define BCE_MISC_GPIO_VALUE (0xffL<<0) +#define BCE_MISC_GPIO_SET (0xffL<<8) +#define BCE_MISC_GPIO_CLR (0xffL<<16) +#define BCE_MISC_GPIO_FLOAT (0xffL<<24) + +#define BCE_MISC_GPIO_INT 0x00000820 +#define BCE_MISC_GPIO_INT_INT_STATE (0xfL<<0) +#define BCE_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) +#define BCE_MISC_GPIO_INT_OLD_SET (0xfL<<16) +#define BCE_MISC_GPIO_INT_OLD_CLR (0xfL<<24) + +#define BCE_MISC_CONFIG_LFSR 0x00000824 +#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) + +#define BCE_MISC_LFSR_MASK_BITS 0x00000828 +#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) +#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) +#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) +#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) +#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) +#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) +#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) +#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) +#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) +#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) +#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) +#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) +#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) +#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) +#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) +#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) +#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) +#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) +#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) +#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) +#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) +#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) +#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) +#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) +#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) +#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) +#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) +#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) + +#define BCE_MISC_ARB_REQ0 0x0000082c +#define BCE_MISC_ARB_REQ1 0x00000830 +#define BCE_MISC_ARB_REQ2 0x00000834 +#define BCE_MISC_ARB_REQ3 0x00000838 +#define BCE_MISC_ARB_REQ4 0x0000083c +#define BCE_MISC_ARB_FREE0 0x00000840 +#define BCE_MISC_ARB_FREE1 0x00000844 +#define BCE_MISC_ARB_FREE2 0x00000848 +#define BCE_MISC_ARB_FREE3 0x0000084c +#define BCE_MISC_ARB_FREE4 0x00000850 +#define BCE_MISC_ARB_REQ_STATUS0 0x00000854 +#define BCE_MISC_ARB_REQ_STATUS1 0x00000858 +#define BCE_MISC_ARB_REQ_STATUS2 0x0000085c +#define BCE_MISC_ARB_REQ_STATUS3 0x00000860 +#define BCE_MISC_ARB_REQ_STATUS4 0x00000864 +#define BCE_MISC_ARB_GNT0 0x00000868 +#define BCE_MISC_ARB_GNT0_0 (0x7L<<0) +#define BCE_MISC_ARB_GNT0_1 (0x7L<<4) +#define BCE_MISC_ARB_GNT0_2 (0x7L<<8) +#define BCE_MISC_ARB_GNT0_3 (0x7L<<12) +#define BCE_MISC_ARB_GNT0_4 (0x7L<<16) +#define BCE_MISC_ARB_GNT0_5 (0x7L<<20) +#define BCE_MISC_ARB_GNT0_6 (0x7L<<24) +#define BCE_MISC_ARB_GNT0_7 (0x7L<<28) + +#define BCE_MISC_ARB_GNT1 0x0000086c +#define BCE_MISC_ARB_GNT1_8 (0x7L<<0) +#define BCE_MISC_ARB_GNT1_9 (0x7L<<4) +#define BCE_MISC_ARB_GNT1_10 (0x7L<<8) +#define BCE_MISC_ARB_GNT1_11 (0x7L<<12) +#define BCE_MISC_ARB_GNT1_12 (0x7L<<16) +#define BCE_MISC_ARB_GNT1_13 (0x7L<<20) +#define BCE_MISC_ARB_GNT1_14 (0x7L<<24) +#define BCE_MISC_ARB_GNT1_15 (0x7L<<28) + +#define BCE_MISC_ARB_GNT2 0x00000870 +#define BCE_MISC_ARB_GNT2_16 (0x7L<<0) +#define BCE_MISC_ARB_GNT2_17 (0x7L<<4) +#define BCE_MISC_ARB_GNT2_18 (0x7L<<8) +#define BCE_MISC_ARB_GNT2_19 (0x7L<<12) +#define BCE_MISC_ARB_GNT2_20 (0x7L<<16) +#define BCE_MISC_ARB_GNT2_21 (0x7L<<20) +#define BCE_MISC_ARB_GNT2_22 (0x7L<<24) +#define BCE_MISC_ARB_GNT2_23 (0x7L<<28) + +#define BCE_MISC_ARB_GNT3 0x00000874 +#define BCE_MISC_ARB_GNT3_24 (0x7L<<0) +#define BCE_MISC_ARB_GNT3_25 (0x7L<<4) +#define BCE_MISC_ARB_GNT3_26 (0x7L<<8) +#define BCE_MISC_ARB_GNT3_27 (0x7L<<12) +#define BCE_MISC_ARB_GNT3_28 (0x7L<<16) +#define BCE_MISC_ARB_GNT3_29 (0x7L<<20) +#define BCE_MISC_ARB_GNT3_30 (0x7L<<24) +#define BCE_MISC_ARB_GNT3_31 (0x7L<<28) + +#define BCE_MISC_PRBS_CONTROL 0x00000878 +#define BCE_MISC_PRBS_CONTROL_EN (1L<<0) +#define BCE_MISC_PRBS_CONTROL_RSTB (1L<<1) +#define BCE_MISC_PRBS_CONTROL_INV (1L<<2) +#define BCE_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) +#define BCE_MISC_PRBS_CONTROL_ORDER (0x3L<<4) +#define BCE_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) +#define BCE_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) +#define BCE_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) +#define BCE_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) + +#define BCE_MISC_PRBS_STATUS 0x0000087c +#define BCE_MISC_PRBS_STATUS_LOCK (1L<<0) +#define BCE_MISC_PRBS_STATUS_STKY (1L<<1) +#define BCE_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) +#define BCE_MISC_PRBS_STATUS_STATE (0xfL<<16) + +#define BCE_MISC_SM_ASF_CONTROL 0x00000880 +#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) +#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) +#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) +#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) +#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) +#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) +#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) +#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) +#define BCE_MISC_SM_ASF_CONTROL_RES (0xfL<<8) +#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) +#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) +#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) +#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) +#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) +#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) +#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) +#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) + +#define BCE_MISC_SMB_IN 0x00000884 +#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) +#define BCE_MISC_SMB_IN_RDY (1L<<8) +#define BCE_MISC_SMB_IN_DONE (1L<<9) +#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) +#define BCE_MISC_SMB_IN_STATUS (0x7L<<11) +#define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) +#define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) +#define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) +#define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) +#define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) + +#define BCE_MISC_SMB_OUT 0x00000888 +#define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) +#define BCE_MISC_SMB_OUT_RDY (1L<<8) +#define BCE_MISC_SMB_OUT_START (1L<<9) +#define BCE_MISC_SMB_OUT_LAST (1L<<10) +#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) +#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) +#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) +#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) +#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) +#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) +#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) +#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) +#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) + +#define BCE_MISC_SMB_WATCHDOG 0x0000088c +#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) + +#define BCE_MISC_SMB_HEARTBEAT 0x00000890 +#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) + +#define BCE_MISC_SMB_POLL_ASF 0x00000894 +#define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) + +#define BCE_MISC_SMB_POLL_LEGACY 0x00000898 +#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) + +#define BCE_MISC_SMB_RETRAN 0x0000089c +#define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) + +#define BCE_MISC_SMB_TIMESTAMP 0x000008a0 +#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) + +#define BCE_MISC_PERR_ENA0 0x000008a4 +#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) +#define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) +#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) +#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) +#define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) +#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) +#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) +#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) +#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) +#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) +#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) +#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) +#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) +#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) +#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) +#define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) +#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) +#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) +#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) +#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) +#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) +#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) +#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) +#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) +#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) + +#define BCE_MISC_PERR_ENA1 0x000008a8 +#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) +#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) +#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) +#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) +#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) +#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) +#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) +#define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) +#define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) +#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) +#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) +#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) +#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) +#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) +#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) +#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) +#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) +#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) +#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) +#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) +#define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) +#define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) +#define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) +#define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) +#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) +#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) +#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) +#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) +#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) +#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) +#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) +#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) + +#define BCE_MISC_PERR_ENA2 0x000008ac +#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) +#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) +#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) +#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) +#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) +#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) +#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) +#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) +#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) + +#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 +#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) +#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) + +#define BCE_MISC_VREG_CONTROL 0x000008b4 +#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) +#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) + +#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 +#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) + +#define BCE_MISC_UNUSED0 0x000008bc + + +/* + * nvm_reg definition + * offset: 0x6400 + */ +#define BCE_NVM_COMMAND 0x00006400 +#define BCE_NVM_COMMAND_RST (1L<<0) +#define BCE_NVM_COMMAND_DONE (1L<<3) +#define BCE_NVM_COMMAND_DOIT (1L<<4) +#define BCE_NVM_COMMAND_WR (1L<<5) +#define BCE_NVM_COMMAND_ERASE (1L<<6) +#define BCE_NVM_COMMAND_FIRST (1L<<7) +#define BCE_NVM_COMMAND_LAST (1L<<8) +#define BCE_NVM_COMMAND_WREN (1L<<16) +#define BCE_NVM_COMMAND_WRDI (1L<<17) +#define BCE_NVM_COMMAND_EWSR (1L<<18) +#define BCE_NVM_COMMAND_WRSR (1L<<19) + +#define BCE_NVM_STATUS 0x00006404 +#define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0) +#define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4) +#define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) + +#define BCE_NVM_WRITE 0x00006408 +#define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) +#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) +#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) +#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) +#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) +#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) +#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) +#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) + +#define BCE_NVM_ADDR 0x0000640c +#define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) +#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) +#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) +#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) +#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) +#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) +#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) +#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) + +#define BCE_NVM_READ 0x00006410 +#define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) +#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) +#define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) +#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) +#define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) +#define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) +#define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0) +#define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0) + +#define BCE_NVM_CFG1 0x00006414 +#define BCE_NVM_CFG1_FLASH_MODE (1L<<0) +#define BCE_NVM_CFG1_BUFFER_MODE (1L<<1) +#define BCE_NVM_CFG1_PASS_MODE (1L<<2) +#define BCE_NVM_CFG1_BITBANG_MODE (1L<<3) +#define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4) +#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) +#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) +#define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) +#define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) +#define BCE_NVM_CFG1_PROTECT_MODE (1L<<24) +#define BCE_NVM_CFG1_FLASH_SIZE (1L<<25) +#define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31) + +#define BCE_NVM_CFG2 0x00006418 +#define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0) +#define BCE_NVM_CFG2_DUMMY (0xffL<<8) +#define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16) + +#define BCE_NVM_CFG3 0x0000641c +#define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) +#define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8) +#define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) +#define BCE_NVM_CFG3_READ_CMD (0xffL<<24) + +#define BCE_NVM_SW_ARB 0x00006420 +#define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) +#define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) +#define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) +#define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) +#define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) +#define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) +#define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) +#define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) +#define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8) +#define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9) +#define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10) +#define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11) +#define BCE_NVM_SW_ARB_REQ0 (1L<<12) +#define BCE_NVM_SW_ARB_REQ1 (1L<<13) +#define BCE_NVM_SW_ARB_REQ2 (1L<<14) +#define BCE_NVM_SW_ARB_REQ3 (1L<<15) + +#define BCE_NVM_ACCESS_ENABLE 0x00006424 +#define BCE_NVM_ACCESS_ENABLE_EN (1L<<0) +#define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1) + +#define BCE_NVM_WRITE1 0x00006428 +#define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0) +#define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8) +#define BCE_NVM_WRITE1_SR_DATA (0xffL<<16) + + + +/* + * dma_reg definition + * offset: 0xc00 + */ +#define BCE_DMA_COMMAND 0x00000c00 +#define BCE_DMA_COMMAND_ENABLE (1L<<0) + +#define BCE_DMA_STATUS 0x00000c04 +#define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) +#define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) +#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) +#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) +#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) +#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) +#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) +#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) +#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) +#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) +#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) + +#define BCE_DMA_CONFIG 0x00000c08 +#define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) +#define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) +#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) +#define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) +#define BCE_DMA_CONFIG_ONE_DMA (1L<<6) +#define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) +#define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) +#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) +#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) +#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) +#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) +#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) +#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) +#define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) +#define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) +#define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) +#define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) +#define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) +#define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) + +#define BCE_DMA_BLACKOUT 0x00000c0c +#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) +#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) +#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) + +#define BCE_DMA_RCHAN_STAT 0x00000c30 +#define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) +#define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) +#define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) +#define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) +#define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) +#define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) +#define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) +#define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) +#define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) + +#define BCE_DMA_WCHAN_STAT 0x00000c34 +#define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) +#define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) +#define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) +#define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) +#define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) +#define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) +#define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) +#define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) +#define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) + +#define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 +#define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) +#define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) +#define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) +#define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) +#define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) +#define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) +#define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) +#define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) + +#define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c +#define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) +#define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) +#define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) +#define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) +#define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) +#define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) +#define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) +#define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) + +#define BCE_DMA_RCHAN_STAT_00 0x00000c40 +#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) + +#define BCE_DMA_RCHAN_STAT_01 0x00000c44 +#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) + +#define BCE_DMA_RCHAN_STAT_02 0x00000c48 +#define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) +#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) +#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) +#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) + +#define BCE_DMA_RCHAN_STAT_10 0x00000c4c +#define BCE_DMA_RCHAN_STAT_11 0x00000c50 +#define BCE_DMA_RCHAN_STAT_12 0x00000c54 +#define BCE_DMA_RCHAN_STAT_20 0x00000c58 +#define BCE_DMA_RCHAN_STAT_21 0x00000c5c +#define BCE_DMA_RCHAN_STAT_22 0x00000c60 +#define BCE_DMA_RCHAN_STAT_30 0x00000c64 +#define BCE_DMA_RCHAN_STAT_31 0x00000c68 +#define BCE_DMA_RCHAN_STAT_32 0x00000c6c +#define BCE_DMA_RCHAN_STAT_40 0x00000c70 +#define BCE_DMA_RCHAN_STAT_41 0x00000c74 +#define BCE_DMA_RCHAN_STAT_42 0x00000c78 +#define BCE_DMA_RCHAN_STAT_50 0x00000c7c +#define BCE_DMA_RCHAN_STAT_51 0x00000c80 +#define BCE_DMA_RCHAN_STAT_52 0x00000c84 +#define BCE_DMA_RCHAN_STAT_60 0x00000c88 +#define BCE_DMA_RCHAN_STAT_61 0x00000c8c +#define BCE_DMA_RCHAN_STAT_62 0x00000c90 +#define BCE_DMA_RCHAN_STAT_70 0x00000c94 +#define BCE_DMA_RCHAN_STAT_71 0x00000c98 +#define BCE_DMA_RCHAN_STAT_72 0x00000c9c +#define BCE_DMA_WCHAN_STAT_00 0x00000ca0 +#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) + +#define BCE_DMA_WCHAN_STAT_01 0x00000ca4 +#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) + +#define BCE_DMA_WCHAN_STAT_02 0x00000ca8 +#define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) +#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) +#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) +#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) + +#define BCE_DMA_WCHAN_STAT_10 0x00000cac +#define BCE_DMA_WCHAN_STAT_11 0x00000cb0 +#define BCE_DMA_WCHAN_STAT_12 0x00000cb4 +#define BCE_DMA_WCHAN_STAT_20 0x00000cb8 +#define BCE_DMA_WCHAN_STAT_21 0x00000cbc +#define BCE_DMA_WCHAN_STAT_22 0x00000cc0 +#define BCE_DMA_WCHAN_STAT_30 0x00000cc4 +#define BCE_DMA_WCHAN_STAT_31 0x00000cc8 +#define BCE_DMA_WCHAN_STAT_32 0x00000ccc +#define BCE_DMA_WCHAN_STAT_40 0x00000cd0 +#define BCE_DMA_WCHAN_STAT_41 0x00000cd4 +#define BCE_DMA_WCHAN_STAT_42 0x00000cd8 +#define BCE_DMA_WCHAN_STAT_50 0x00000cdc +#define BCE_DMA_WCHAN_STAT_51 0x00000ce0 +#define BCE_DMA_WCHAN_STAT_52 0x00000ce4 +#define BCE_DMA_WCHAN_STAT_60 0x00000ce8 +#define BCE_DMA_WCHAN_STAT_61 0x00000cec +#define BCE_DMA_WCHAN_STAT_62 0x00000cf0 +#define BCE_DMA_WCHAN_STAT_70 0x00000cf4 +#define BCE_DMA_WCHAN_STAT_71 0x00000cf8 +#define BCE_DMA_WCHAN_STAT_72 0x00000cfc +#define BCE_DMA_ARB_STAT_00 0x00000d00 +#define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) +#define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) +#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) + +#define BCE_DMA_ARB_STAT_01 0x00000d04 +#define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) +#define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) +#define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) +#define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) +#define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) +#define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) +#define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) +#define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) + +#define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 +#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) +#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) +#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) +#define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) +#define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) + +#define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 +#define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 +#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) +#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) +#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) +#define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) +#define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) + +#define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c +#define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 +#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) +#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) +#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) +#define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) +#define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) + +#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 + + +/* + * context_reg definition + * offset: 0x1000 + */ +#define BCE_CTX_COMMAND 0x00001000 +#define BCE_CTX_COMMAND_ENABLED (1L<<0) + +#define BCE_CTX_STATUS 0x00001004 +#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) +#define BCE_CTX_STATUS_READ_STAT (1L<<16) +#define BCE_CTX_STATUS_WRITE_STAT (1L<<17) +#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) +#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) + +#define BCE_CTX_VIRT_ADDR 0x00001008 +#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) + +#define BCE_CTX_PAGE_TBL 0x0000100c +#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) + +#define BCE_CTX_DATA_ADR 0x00001010 +#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) + +#define BCE_CTX_DATA 0x00001014 +#define BCE_CTX_LOCK 0x00001018 +#define BCE_CTX_LOCK_TYPE (0x7L<<0) +#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) +#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) +#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) +#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) +#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) +#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) +#define BCE_CTX_LOCK_GRANTED (1L<<26) +#define BCE_CTX_LOCK_MODE (0x7L<<27) +#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) +#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) +#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) +#define BCE_CTX_LOCK_STATUS (1L<<30) +#define BCE_CTX_LOCK_REQ (1L<<31) + +#define BCE_CTX_ACCESS_STATUS 0x00001040 +#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) +#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) +#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) +#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) +#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) + +#define BCE_CTX_DBG_LOCK_STATUS 0x00001044 +#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) +#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) + +#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 +#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) +#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) +#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) + +#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 +#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 +#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c +#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 +#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 +#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 +#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c +#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 + + +/* + * emac_reg definition + * offset: 0x1400 + */ +#define BCE_EMAC_MODE 0x00001400 +#define BCE_EMAC_MODE_RESET (1L<<0) +#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) +#define BCE_EMAC_MODE_PORT (0x3L<<2) +#define BCE_EMAC_MODE_PORT_NONE (0L<<2) +#define BCE_EMAC_MODE_PORT_MII (1L<<2) +#define BCE_EMAC_MODE_PORT_GMII (2L<<2) +#define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) +#define BCE_EMAC_MODE_MAC_LOOP (1L<<4) +#define BCE_EMAC_MODE_25G (1L<<5) +#define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) +#define BCE_EMAC_MODE_TX_BURST (1L<<8) +#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) +#define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) +#define BCE_EMAC_MODE_FORCE_LINK (1L<<11) +#define BCE_EMAC_MODE_MPKT (1L<<18) +#define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) +#define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) + +#define BCE_EMAC_STATUS 0x00001404 +#define BCE_EMAC_STATUS_LINK (1L<<11) +#define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) +#define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) +#define BCE_EMAC_STATUS_MI_INT (1L<<23) +#define BCE_EMAC_STATUS_AP_ERROR (1L<<24) +#define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) + +#define BCE_EMAC_ATTENTION_ENA 0x00001408 +#define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) +#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) +#define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) +#define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) + +#define BCE_EMAC_LED 0x0000140c +#define BCE_EMAC_LED_OVERRIDE (1L<<0) +#define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) +#define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) +#define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) +#define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) +#define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) +#define BCE_EMAC_LED_TRAFFIC (1L<<6) +#define BCE_EMAC_LED_1000MB (1L<<7) +#define BCE_EMAC_LED_100MB (1L<<8) +#define BCE_EMAC_LED_10MB (1L<<9) +#define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) +#define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) +#define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) + +#define BCE_EMAC_MAC_MATCH0 0x00001410 +#define BCE_EMAC_MAC_MATCH1 0x00001414 +#define BCE_EMAC_MAC_MATCH2 0x00001418 +#define BCE_EMAC_MAC_MATCH3 0x0000141c +#define BCE_EMAC_MAC_MATCH4 0x00001420 +#define BCE_EMAC_MAC_MATCH5 0x00001424 +#define BCE_EMAC_MAC_MATCH6 0x00001428 +#define BCE_EMAC_MAC_MATCH7 0x0000142c +#define BCE_EMAC_MAC_MATCH8 0x00001430 +#define BCE_EMAC_MAC_MATCH9 0x00001434 +#define BCE_EMAC_MAC_MATCH10 0x00001438 +#define BCE_EMAC_MAC_MATCH11 0x0000143c +#define BCE_EMAC_MAC_MATCH12 0x00001440 +#define BCE_EMAC_MAC_MATCH13 0x00001444 +#define BCE_EMAC_MAC_MATCH14 0x00001448 +#define BCE_EMAC_MAC_MATCH15 0x0000144c +#define BCE_EMAC_MAC_MATCH16 0x00001450 +#define BCE_EMAC_MAC_MATCH17 0x00001454 +#define BCE_EMAC_MAC_MATCH18 0x00001458 +#define BCE_EMAC_MAC_MATCH19 0x0000145c +#define BCE_EMAC_MAC_MATCH20 0x00001460 +#define BCE_EMAC_MAC_MATCH21 0x00001464 +#define BCE_EMAC_MAC_MATCH22 0x00001468 +#define BCE_EMAC_MAC_MATCH23 0x0000146c +#define BCE_EMAC_MAC_MATCH24 0x00001470 +#define BCE_EMAC_MAC_MATCH25 0x00001474 +#define BCE_EMAC_MAC_MATCH26 0x00001478 +#define BCE_EMAC_MAC_MATCH27 0x0000147c +#define BCE_EMAC_MAC_MATCH28 0x00001480 +#define BCE_EMAC_MAC_MATCH29 0x00001484 +#define BCE_EMAC_MAC_MATCH30 0x00001488 +#define BCE_EMAC_MAC_MATCH31 0x0000148c +#define BCE_EMAC_BACKOFF_SEED 0x00001498 +#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) + +#define BCE_EMAC_RX_MTU_SIZE 0x0000149c +#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) +#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) + +#define BCE_EMAC_SERDES_CNTL 0x000014a4 +#define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) +#define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) +#define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) +#define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) +#define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) +#define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) +#define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) +#define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) +#define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) +#define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) +#define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) +#define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) +#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) +#define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) +#define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) +#define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) + +#define BCE_EMAC_SERDES_STATUS 0x000014a8 +#define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) +#define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) + +#define BCE_EMAC_MDIO_COMM 0x000014ac +#define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) +#define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) +#define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) +#define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) +#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) +#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) +#define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) +#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) +#define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) +#define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) +#define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) + +#define BCE_EMAC_MDIO_STATUS 0x000014b0 +#define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) +#define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) + +#define BCE_EMAC_MDIO_MODE 0x000014b4 +#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) +#define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) +#define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) +#define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) +#define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) +#define BCE_EMAC_MDIO_MODE_MDC (1L<<11) +#define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) +#define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) + +#define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 +#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) + +#define BCE_EMAC_TX_MODE 0x000014bc +#define BCE_EMAC_TX_MODE_RESET (1L<<0) +#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) +#define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) +#define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) +#define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) +#define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) + +#define BCE_EMAC_TX_STATUS 0x000014c0 +#define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) +#define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) +#define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) +#define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) +#define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) + +#define BCE_EMAC_TX_LENGTHS 0x000014c4 +#define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) +#define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) +#define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) + +#define BCE_EMAC_RX_MODE 0x000014c8 +#define BCE_EMAC_RX_MODE_RESET (1L<<0) +#define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) +#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) +#define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) +#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) +#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) +#define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) +#define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) +#define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) +#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) +#define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) +#define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) + +#define BCE_EMAC_RX_STATUS 0x000014cc +#define BCE_EMAC_RX_STATUS_FFED (1L<<0) +#define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) +#define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) + +#define BCE_EMAC_MULTICAST_HASH0 0x000014d0 +#define BCE_EMAC_MULTICAST_HASH1 0x000014d4 +#define BCE_EMAC_MULTICAST_HASH2 0x000014d8 +#define BCE_EMAC_MULTICAST_HASH3 0x000014dc +#define BCE_EMAC_MULTICAST_HASH4 0x000014e0 +#define BCE_EMAC_MULTICAST_HASH5 0x000014e4 +#define BCE_EMAC_MULTICAST_HASH6 0x000014e8 +#define BCE_EMAC_MULTICAST_HASH7 0x000014ec +#define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 +#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 +#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 +#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c +#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 +#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 +#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 +#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c +#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 +#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 +#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 +#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c +#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 +#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 +#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 +#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c +#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 +#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 +#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 +#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c +#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 +#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 +#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 +#define BCE_EMAC_RXMAC_DEBUG0 0x0000155c +#define BCE_EMAC_RXMAC_DEBUG1 0x00001560 +#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) +#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) +#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) +#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) +#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) +#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) +#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) +#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) +#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) + +#define BCE_EMAC_RXMAC_DEBUG2 0x00001564 +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) +#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) +#define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) +#define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) +#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) +#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) +#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) +#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) +#define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) + +#define BCE_EMAC_RXMAC_DEBUG3 0x00001568 +#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) +#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) + +#define BCE_EMAC_RXMAC_DEBUG4 0x0000156c +#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) +#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) +#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) +#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) +#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) +#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) +#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) +#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) +#define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) + +#define BCE_EMAC_RXMAC_DEBUG5 0x00001570 +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) +#define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) +#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) +#define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) +#define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) +#define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) +#define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) +#define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) +#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) +#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) +#define BCE_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) + +#define BCE_EMAC_RX_STAT_AC0 0x00001580 +#define BCE_EMAC_RX_STAT_AC1 0x00001584 +#define BCE_EMAC_RX_STAT_AC2 0x00001588 +#define BCE_EMAC_RX_STAT_AC3 0x0000158c +#define BCE_EMAC_RX_STAT_AC4 0x00001590 +#define BCE_EMAC_RX_STAT_AC5 0x00001594 +#define BCE_EMAC_RX_STAT_AC6 0x00001598 +#define BCE_EMAC_RX_STAT_AC7 0x0000159c +#define BCE_EMAC_RX_STAT_AC8 0x000015a0 +#define BCE_EMAC_RX_STAT_AC9 0x000015a4 +#define BCE_EMAC_RX_STAT_AC10 0x000015a8 +#define BCE_EMAC_RX_STAT_AC11 0x000015ac +#define BCE_EMAC_RX_STAT_AC12 0x000015b0 +#define BCE_EMAC_RX_STAT_AC13 0x000015b4 +#define BCE_EMAC_RX_STAT_AC14 0x000015b8 +#define BCE_EMAC_RX_STAT_AC15 0x000015bc +#define BCE_EMAC_RX_STAT_AC16 0x000015c0 +#define BCE_EMAC_RX_STAT_AC17 0x000015c4 +#define BCE_EMAC_RX_STAT_AC18 0x000015c8 +#define BCE_EMAC_RX_STAT_AC19 0x000015cc +#define BCE_EMAC_RX_STAT_AC20 0x000015d0 +#define BCE_EMAC_RX_STAT_AC21 0x000015d4 +#define BCE_EMAC_RX_STAT_AC22 0x000015d8 +#define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc +#define BCE_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 +#define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 +#define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 +#define BCE_EMAC_TX_STAT_OUTXONSENT 0x0000160c +#define BCE_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 +#define BCE_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 +#define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 +#define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c +#define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 +#define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 +#define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 +#define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c +#define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 +#define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 +#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 +#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c +#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 +#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 +#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 +#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c +#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 +#define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 +#define BCE_EMAC_TXMAC_DEBUG0 0x00001658 +#define BCE_EMAC_TXMAC_DEBUG1 0x0000165c +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) +#define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) +#define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) +#define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) +#define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) +#define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) +#define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) +#define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) +#define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) +#define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) +#define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) + +#define BCE_EMAC_TXMAC_DEBUG2 0x00001660 +#define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) +#define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) +#define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) +#define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) + +#define BCE_EMAC_TXMAC_DEBUG3 0x00001664 +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) +#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) +#define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) +#define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) +#define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) +#define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) + +#define BCE_EMAC_TXMAC_DEBUG4 0x00001668 +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) +#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) +#define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) +#define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) +#define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) +#define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) +#define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) +#define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) +#define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) +#define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) +#define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) +#define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) +#define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) +#define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31) + +#define BCE_EMAC_TX_STAT_AC0 0x00001680 +#define BCE_EMAC_TX_STAT_AC1 0x00001684 +#define BCE_EMAC_TX_STAT_AC2 0x00001688 +#define BCE_EMAC_TX_STAT_AC3 0x0000168c +#define BCE_EMAC_TX_STAT_AC4 0x00001690 +#define BCE_EMAC_TX_STAT_AC5 0x00001694 +#define BCE_EMAC_TX_STAT_AC6 0x00001698 +#define BCE_EMAC_TX_STAT_AC7 0x0000169c +#define BCE_EMAC_TX_STAT_AC8 0x000016a0 +#define BCE_EMAC_TX_STAT_AC9 0x000016a4 +#define BCE_EMAC_TX_STAT_AC10 0x000016a8 +#define BCE_EMAC_TX_STAT_AC11 0x000016ac +#define BCE_EMAC_TX_STAT_AC12 0x000016b0 +#define BCE_EMAC_TX_STAT_AC13 0x000016b4 +#define BCE_EMAC_TX_STAT_AC14 0x000016b8 +#define BCE_EMAC_TX_STAT_AC15 0x000016bc +#define BCE_EMAC_TX_STAT_AC16 0x000016c0 +#define BCE_EMAC_TX_STAT_AC17 0x000016c4 +#define BCE_EMAC_TX_STAT_AC18 0x000016c8 +#define BCE_EMAC_TX_STAT_AC19 0x000016cc +#define BCE_EMAC_TX_STAT_AC20 0x000016d0 +#define BCE_EMAC_TX_STAT_AC21 0x000016d4 +#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 + + +/* + * rpm_reg definition + * offset: 0x1800 + */ +#define BCE_RPM_COMMAND 0x00001800 +#define BCE_RPM_COMMAND_ENABLED (1L<<0) +#define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4) + +#define BCE_RPM_STATUS 0x00001804 +#define BCE_RPM_STATUS_MBUF_WAIT (1L<<0) +#define BCE_RPM_STATUS_FREE_WAIT (1L<<1) + +#define BCE_RPM_CONFIG 0x00001808 +#define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) +#define BCE_RPM_CONFIG_ACPI_ENA (1L<<1) +#define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2) +#define BCE_RPM_CONFIG_MP_KEEP (1L<<3) +#define BCE_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) +#define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31) + +#define BCE_RPM_VLAN_MATCH0 0x00001810 +#define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) + +#define BCE_RPM_VLAN_MATCH1 0x00001814 +#define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) + +#define BCE_RPM_VLAN_MATCH2 0x00001818 +#define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) + +#define BCE_RPM_VLAN_MATCH3 0x0000181c +#define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) + +#define BCE_RPM_SORT_USER0 0x00001820 +#define BCE_RPM_SORT_USER0_PM_EN (0xffffL<<0) +#define BCE_RPM_SORT_USER0_BC_EN (1L<<16) +#define BCE_RPM_SORT_USER0_MC_EN (1L<<17) +#define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18) +#define BCE_RPM_SORT_USER0_PROM_EN (1L<<19) +#define BCE_RPM_SORT_USER0_VLAN_EN (0xfL<<20) +#define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24) +#define BCE_RPM_SORT_USER0_ENA (1L<<31) + +#define BCE_RPM_SORT_USER1 0x00001824 +#define BCE_RPM_SORT_USER1_PM_EN (0xffffL<<0) +#define BCE_RPM_SORT_USER1_BC_EN (1L<<16) +#define BCE_RPM_SORT_USER1_MC_EN (1L<<17) +#define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18) +#define BCE_RPM_SORT_USER1_PROM_EN (1L<<19) +#define BCE_RPM_SORT_USER1_VLAN_EN (0xfL<<20) +#define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24) +#define BCE_RPM_SORT_USER1_ENA (1L<<31) + +#define BCE_RPM_SORT_USER2 0x00001828 +#define BCE_RPM_SORT_USER2_PM_EN (0xffffL<<0) +#define BCE_RPM_SORT_USER2_BC_EN (1L<<16) +#define BCE_RPM_SORT_USER2_MC_EN (1L<<17) +#define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18) +#define BCE_RPM_SORT_USER2_PROM_EN (1L<<19) +#define BCE_RPM_SORT_USER2_VLAN_EN (0xfL<<20) +#define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24) +#define BCE_RPM_SORT_USER2_ENA (1L<<31) + +#define BCE_RPM_SORT_USER3 0x0000182c +#define BCE_RPM_SORT_USER3_PM_EN (0xffffL<<0) +#define BCE_RPM_SORT_USER3_BC_EN (1L<<16) +#define BCE_RPM_SORT_USER3_MC_EN (1L<<17) +#define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18) +#define BCE_RPM_SORT_USER3_PROM_EN (1L<<19) +#define BCE_RPM_SORT_USER3_VLAN_EN (0xfL<<20) +#define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24) +#define BCE_RPM_SORT_USER3_ENA (1L<<31) + +#define BCE_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 +#define BCE_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 +#define BCE_RPM_STAT_IFINFTQDISCARDS 0x00001848 +#define BCE_RPM_STAT_IFINMBUFDISCARD 0x0000184c +#define BCE_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 +#define BCE_RPM_STAT_AC0 0x00001880 +#define BCE_RPM_STAT_AC1 0x00001884 +#define BCE_RPM_STAT_AC2 0x00001888 +#define BCE_RPM_STAT_AC3 0x0000188c +#define BCE_RPM_STAT_AC4 0x00001890 +#define BCE_RPM_RC_CNTL_0 0x00001900 +#define BCE_RPM_RC_CNTL_0_OFFSET (0xffL<<0) +#define BCE_RPM_RC_CNTL_0_CLASS (0x7L<<8) +#define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11) +#define BCE_RPM_RC_CNTL_0_P4 (1L<<12) +#define BCE_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) +#define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) +#define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) +#define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) +#define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) +#define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) +#define BCE_RPM_RC_CNTL_0_COMP (0x3L<<16) +#define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) +#define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) +#define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) +#define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16) +#define BCE_RPM_RC_CNTL_0_SBIT (1L<<19) +#define BCE_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) +#define BCE_RPM_RC_CNTL_0_MAP (1L<<24) +#define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25) +#define BCE_RPM_RC_CNTL_0_MASK (1L<<26) +#define BCE_RPM_RC_CNTL_0_P1 (1L<<27) +#define BCE_RPM_RC_CNTL_0_P2 (1L<<28) +#define BCE_RPM_RC_CNTL_0_P3 (1L<<29) +#define BCE_RPM_RC_CNTL_0_NBIT (1L<<30) + +#define BCE_RPM_RC_VALUE_MASK_0 0x00001904 +#define BCE_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) +#define BCE_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) + +#define BCE_RPM_RC_CNTL_1 0x00001908 +#define BCE_RPM_RC_CNTL_1_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_1_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_1 0x0000190c +#define BCE_RPM_RC_CNTL_2 0x00001910 +#define BCE_RPM_RC_CNTL_2_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_2_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_2 0x00001914 +#define BCE_RPM_RC_CNTL_3 0x00001918 +#define BCE_RPM_RC_CNTL_3_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_3_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_3 0x0000191c +#define BCE_RPM_RC_CNTL_4 0x00001920 +#define BCE_RPM_RC_CNTL_4_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_4_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_4 0x00001924 +#define BCE_RPM_RC_CNTL_5 0x00001928 +#define BCE_RPM_RC_CNTL_5_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_5_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_5 0x0000192c +#define BCE_RPM_RC_CNTL_6 0x00001930 +#define BCE_RPM_RC_CNTL_6_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_6_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_6 0x00001934 +#define BCE_RPM_RC_CNTL_7 0x00001938 +#define BCE_RPM_RC_CNTL_7_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_7_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_7 0x0000193c +#define BCE_RPM_RC_CNTL_8 0x00001940 +#define BCE_RPM_RC_CNTL_8_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_8_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_8 0x00001944 +#define BCE_RPM_RC_CNTL_9 0x00001948 +#define BCE_RPM_RC_CNTL_9_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_9_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_9 0x0000194c +#define BCE_RPM_RC_CNTL_10 0x00001950 +#define BCE_RPM_RC_CNTL_10_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_10_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_10 0x00001954 +#define BCE_RPM_RC_CNTL_11 0x00001958 +#define BCE_RPM_RC_CNTL_11_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_11_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_11 0x0000195c +#define BCE_RPM_RC_CNTL_12 0x00001960 +#define BCE_RPM_RC_CNTL_12_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_12_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_12 0x00001964 +#define BCE_RPM_RC_CNTL_13 0x00001968 +#define BCE_RPM_RC_CNTL_13_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_13_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_13 0x0000196c +#define BCE_RPM_RC_CNTL_14 0x00001970 +#define BCE_RPM_RC_CNTL_14_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_14_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_14 0x00001974 +#define BCE_RPM_RC_CNTL_15 0x00001978 +#define BCE_RPM_RC_CNTL_15_A (0x3ffffL<<0) +#define BCE_RPM_RC_CNTL_15_B (0xfffL<<19) + +#define BCE_RPM_RC_VALUE_MASK_15 0x0000197c +#define BCE_RPM_RC_CONFIG 0x00001980 +#define BCE_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) +#define BCE_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) + +#define BCE_RPM_DEBUG0 0x00001984 +#define BCE_RPM_DEBUG0_FM_BCNT (0xffffL<<0) +#define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) +#define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) +#define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) +#define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) +#define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) +#define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) +#define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22) +#define BCE_RPM_DEBUG0_FM_STARTED (1L<<23) +#define BCE_RPM_DEBUG0_DONE (1L<<24) +#define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25) +#define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) +#define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) +#define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28) +#define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) + +#define BCE_RPM_DEBUG1 0x00001988 +#define BCE_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) +#define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) +#define BCE_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) +#define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) +#define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) +#define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) +#define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) + +#define BCE_RPM_DEBUG2 0x0000198c +#define BCE_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) +#define BCE_RPM_DEBUG2_IP_BCNT (0xffL<<16) +#define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) +#define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) +#define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) +#define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) +#define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) +#define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29) +#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) +#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) + +#define BCE_RPM_DEBUG3 0x00001990 +#define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) +#define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) +#define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) +#define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) +#define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) +#define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) +#define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) +#define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) +#define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) +#define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) +#define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) +#define BCE_RPM_DEBUG3_DROP_NXT (1L<<23) +#define BCE_RPM_DEBUG3_FTQ_FSM (0x3L<<24) +#define BCE_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) +#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) +#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) +#define BCE_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) +#define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) +#define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29) +#define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) +#define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) +#define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30) +#define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) +#define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) +#define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) + +#define BCE_RPM_DEBUG4 0x00001994 +#define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) +#define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) +#define BCE_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) +#define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) + +#define BCE_RPM_DEBUG5 0x00001998 +#define BCE_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) +#define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) +#define BCE_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) +#define BCE_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) +#define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) +#define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) +#define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) +#define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) +#define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) +#define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) +#define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) +#define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) +#define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) +#define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) +#define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) +#define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31) + +#define BCE_RPM_DEBUG6 0x0000199c +#define BCE_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) +#define BCE_RPM_DEBUG6_VEC (0xffffL<<16) + +#define BCE_RPM_DEBUG7 0x000019a0 +#define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) + +#define BCE_RPM_DEBUG8 0x000019a4 +#define BCE_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) +#define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) +#define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) +#define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) +#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) +#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) +#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) +#define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) +#define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) +#define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) +#define BCE_RPM_DEBUG8_EOF_DET (1L<<12) +#define BCE_RPM_DEBUG8_SOF_DET (1L<<13) +#define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14) +#define BCE_RPM_DEBUG8_ALL_DONE (1L<<15) +#define BCE_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) +#define BCE_RPM_DEBUG8_BYTE_CTR (0xffL<<24) + +#define BCE_RPM_DEBUG9 0x000019a8 +#define BCE_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) +#define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) +#define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) +#define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) +#define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) +#define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) +#define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) + +#define BCE_RPM_ACPI_DBG_BUF_W00 0x000019c0 +#define BCE_RPM_ACPI_DBG_BUF_W01 0x000019c4 +#define BCE_RPM_ACPI_DBG_BUF_W02 0x000019c8 +#define BCE_RPM_ACPI_DBG_BUF_W03 0x000019cc +#define BCE_RPM_ACPI_DBG_BUF_W10 0x000019d0 +#define BCE_RPM_ACPI_DBG_BUF_W11 0x000019d4 +#define BCE_RPM_ACPI_DBG_BUF_W12 0x000019d8 +#define BCE_RPM_ACPI_DBG_BUF_W13 0x000019dc +#define BCE_RPM_ACPI_DBG_BUF_W20 0x000019e0 +#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4 +#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8 +#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec +#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0 +#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4 +#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8 +#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc + + +/* + * rbuf_reg definition + * offset: 0x200000 + */ +#define BCE_RBUF_COMMAND 0x00200000 +#define BCE_RBUF_COMMAND_ENABLED (1L<<0) +#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1) +#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2) +#define BCE_RBUF_COMMAND_OVER_FREE (1L<<4) +#define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5) + +#define BCE_RBUF_STATUS1 0x00200004 +#define BCE_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) + +#define BCE_RBUF_STATUS2 0x00200008 +#define BCE_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) +#define BCE_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) + +#define BCE_RBUF_CONFIG 0x0020000c +#define BCE_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) +#define BCE_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) + +#define BCE_RBUF_FW_BUF_ALLOC 0x00200010 +#define BCE_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) + +#define BCE_RBUF_FW_BUF_FREE 0x00200014 +#define BCE_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) +#define BCE_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) +#define BCE_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) + +#define BCE_RBUF_FW_BUF_SEL 0x00200018 +#define BCE_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) +#define BCE_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) +#define BCE_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) + +#define BCE_RBUF_CONFIG2 0x0020001c +#define BCE_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) +#define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) + +#define BCE_RBUF_CONFIG3 0x00200020 +#define BCE_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) +#define BCE_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) + +#define BCE_RBUF_PKT_DATA 0x00208000 +#define BCE_RBUF_CLIST_DATA 0x00210000 +#define BCE_RBUF_BUF_DATA 0x00220000 + + +/* + * rv2p_reg definition + * offset: 0x2800 + */ +#define BCE_RV2P_COMMAND 0x00002800 +#define BCE_RV2P_COMMAND_ENABLED (1L<<0) +#define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1) +#define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2) +#define BCE_RV2P_COMMAND_ABORT0 (1L<<4) +#define BCE_RV2P_COMMAND_ABORT1 (1L<<5) +#define BCE_RV2P_COMMAND_ABORT2 (1L<<6) +#define BCE_RV2P_COMMAND_ABORT3 (1L<<7) +#define BCE_RV2P_COMMAND_ABORT4 (1L<<8) +#define BCE_RV2P_COMMAND_ABORT5 (1L<<9) +#define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16) +#define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17) +#define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18) + +#define BCE_RV2P_STATUS 0x00002804 +#define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0) +#define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) +#define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) +#define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) +#define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) +#define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) +#define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) + +#define BCE_RV2P_CONFIG 0x00002808 +#define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0) +#define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1) +#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) +#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) +#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) +#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) +#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) +#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) +#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) +#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) +#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) +#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) +#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) +#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) +#define BCE_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) +#define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) + +#define BCE_RV2P_GEN_BFR_ADDR_0 0x00002810 +#define BCE_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) + +#define BCE_RV2P_GEN_BFR_ADDR_1 0x00002814 +#define BCE_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) + +#define BCE_RV2P_GEN_BFR_ADDR_2 0x00002818 +#define BCE_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) + +#define BCE_RV2P_GEN_BFR_ADDR_3 0x0000281c +#define BCE_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) + +#define BCE_RV2P_INSTR_HIGH 0x00002830 +#define BCE_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) + +#define BCE_RV2P_INSTR_LOW 0x00002834 +#define BCE_RV2P_PROC1_ADDR_CMD 0x00002838 +#define BCE_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) +#define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) + +#define BCE_RV2P_PROC2_ADDR_CMD 0x0000283c +#define BCE_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) +#define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) + +#define BCE_RV2P_PROC1_GRC_DEBUG 0x00002840 +#define BCE_RV2P_PROC2_GRC_DEBUG 0x00002844 +#define BCE_RV2P_GRC_PROC_DEBUG 0x00002848 +#define BCE_RV2P_DEBUG_VECT_PEEK 0x0000284c +#define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_RV2P_PFTQ_DATA 0x00002b40 +#define BCE_RV2P_PFTQ_CMD 0x00002b78 +#define BCE_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10) +#define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) +#define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26) +#define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) +#define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_RV2P_PFTQ_CMD_POP (1L<<30) +#define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31) + +#define BCE_RV2P_PFTQ_CTL 0x00002b7c +#define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0) +#define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) +#define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_RV2P_TFTQ_DATA 0x00002b80 +#define BCE_RV2P_TFTQ_CMD 0x00002bb8 +#define BCE_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10) +#define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) +#define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26) +#define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) +#define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_RV2P_TFTQ_CMD_POP (1L<<30) +#define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31) + +#define BCE_RV2P_TFTQ_CTL 0x00002bbc +#define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0) +#define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) +#define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_RV2P_MFTQ_DATA 0x00002bc0 +#define BCE_RV2P_MFTQ_CMD 0x00002bf8 +#define BCE_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10) +#define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) +#define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26) +#define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) +#define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_RV2P_MFTQ_CMD_POP (1L<<30) +#define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31) + +#define BCE_RV2P_MFTQ_CTL 0x00002bfc +#define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0) +#define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) +#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * mq_reg definition + * offset: 0x3c00 + */ +#define BCE_MQ_COMMAND 0x00003c00 +#define BCE_MQ_COMMAND_ENABLED (1L<<0) +#define BCE_MQ_COMMAND_OVERFLOW (1L<<4) +#define BCE_MQ_COMMAND_WR_ERROR (1L<<5) +#define BCE_MQ_COMMAND_RD_ERROR (1L<<6) + +#define BCE_MQ_STATUS 0x00003c04 +#define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) +#define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) +#define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18) + +#define BCE_MQ_CONFIG 0x00003c08 +#define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0) +#define BCE_MQ_CONFIG_HALT_DIS (1L<<1) +#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) +#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) +#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) +#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) +#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) +#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) +#define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) +#define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) + +#define BCE_MQ_ENQUEUE1 0x00003c0c +#define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2) +#define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8) +#define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) +#define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28) + +#define BCE_MQ_ENQUEUE2 0x00003c10 +#define BCE_MQ_BAD_WR_ADDR 0x00003c14 +#define BCE_MQ_BAD_RD_ADDR 0x00003c18 +#define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c +#define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) + +#define BCE_MQ_KNL_WIND_END 0x00003c20 +#define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) + +#define BCE_MQ_KNL_WRITE_MASK1 0x00003c24 +#define BCE_MQ_KNL_TX_MASK1 0x00003c28 +#define BCE_MQ_KNL_CMD_MASK1 0x00003c2c +#define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 +#define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34 +#define BCE_MQ_KNL_WRITE_MASK2 0x00003c38 +#define BCE_MQ_KNL_TX_MASK2 0x00003c3c +#define BCE_MQ_KNL_CMD_MASK2 0x00003c40 +#define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 +#define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48 +#define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c +#define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50 +#define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54 +#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 +#define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c +#define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 +#define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64 +#define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68 +#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c +#define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 +#define BCE_MQ_MEM_WR_ADDR 0x00003c74 +#define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) + +#define BCE_MQ_MEM_WR_DATA0 0x00003c78 +#define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) + +#define BCE_MQ_MEM_WR_DATA1 0x00003c7c +#define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) + +#define BCE_MQ_MEM_WR_DATA2 0x00003c80 +#define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) + +#define BCE_MQ_MEM_RD_ADDR 0x00003c84 +#define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) + +#define BCE_MQ_MEM_RD_DATA0 0x00003c88 +#define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) + +#define BCE_MQ_MEM_RD_DATA1 0x00003c8c +#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) + +#define BCE_MQ_MEM_RD_DATA2 0x00003c90 +#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) + + + +/* + * tbdr_reg definition + * offset: 0x5000 + */ +#define BCE_TBDR_COMMAND 0x00005000 +#define BCE_TBDR_COMMAND_ENABLE (1L<<0) +#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1) +#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4) + +#define BCE_TBDR_STATUS 0x00005004 +#define BCE_TBDR_STATUS_DMA_WAIT (1L<<0) +#define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1) +#define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) +#define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) +#define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) +#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) +#define BCE_TBDR_STATUS_BURST_CNT (1L<<6) + +#define BCE_TBDR_CONFIG 0x00005008 +#define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0) +#define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8) +#define BCE_TBDR_CONFIG_PRIORITY (1L<<9) +#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) +#define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) +#define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) + +#define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c +#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_TBDR_FTQ_DATA 0x000053c0 +#define BCE_TBDR_FTQ_CMD 0x000053f8 +#define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_TBDR_FTQ_CMD_POP (1L<<30) +#define BCE_TBDR_FTQ_CMD_BUSY (1L<<31) + +#define BCE_TBDR_FTQ_CTL 0x000053fc +#define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * tdma_reg definition + * offset: 0x5c00 + */ +#define BCE_TDMA_COMMAND 0x00005c00 +#define BCE_TDMA_COMMAND_ENABLED (1L<<0) +#define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4) +#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) + +#define BCE_TDMA_STATUS 0x00005c04 +#define BCE_TDMA_STATUS_DMA_WAIT (1L<<0) +#define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) +#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) +#define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3) +#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) +#define BCE_TDMA_STATUS_BURST_CNT (1L<<17) + +#define BCE_TDMA_CONFIG 0x00005c08 +#define BCE_TDMA_CONFIG_ONE_DMA (1L<<0) +#define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1) +#define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) +#define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) +#define BCE_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) +#define BCE_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) +#define BCE_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) +#define BCE_TDMA_CONFIG_LINE_SZ (0xfL<<8) +#define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8) +#define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8) +#define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8) +#define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8) +#define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15) +#define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16) +#define BCE_TDMA_CONFIG_FIFO_CMP (0xfL<<20) + +#define BCE_TDMA_PAYLOAD_PROD 0x00005c0c +#define BCE_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) + +#define BCE_TDMA_DBG_WATCHDOG 0x00005c10 +#define BCE_TDMA_DBG_TRIGGER 0x00005c14 +#define BCE_TDMA_DMAD_FSM 0x00005c80 +#define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0) +#define BCE_TDMA_DMAD_FSM_PUSH (0xfL<<4) +#define BCE_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) +#define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12) +#define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16) +#define BCE_TDMA_DMAD_FSM_DMAD (0x7L<<20) +#define BCE_TDMA_DMAD_FSM_BD (0xfL<<24) + +#define BCE_TDMA_DMAD_STATUS 0x00005c84 +#define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) +#define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) +#define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) +#define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) + +#define BCE_TDMA_DR_INTF_FSM 0x00005c88 +#define BCE_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) +#define BCE_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) +#define BCE_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) +#define BCE_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) +#define BCE_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) + +#define BCE_TDMA_DR_INTF_STATUS 0x00005c8c +#define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) +#define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) +#define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) +#define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) +#define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) + +#define BCE_TDMA_FTQ_DATA 0x00005fc0 +#define BCE_TDMA_FTQ_CMD 0x00005ff8 +#define BCE_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_TDMA_FTQ_CMD_POP (1L<<30) +#define BCE_TDMA_FTQ_CMD_BUSY (1L<<31) + +#define BCE_TDMA_FTQ_CTL 0x00005ffc +#define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + + + +/* + * hc_reg definition + * offset: 0x6800 + */ +#define BCE_HC_COMMAND 0x00006800 +#define BCE_HC_COMMAND_ENABLE (1L<<0) +#define BCE_HC_COMMAND_SKIP_ABORT (1L<<4) +#define BCE_HC_COMMAND_COAL_NOW (1L<<16) +#define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) +#define BCE_HC_COMMAND_STATS_NOW (1L<<18) +#define BCE_HC_COMMAND_FORCE_INT (0x3L<<19) +#define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19) +#define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19) +#define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19) +#define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19) +#define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21) + +#define BCE_HC_STATUS 0x00006804 +#define BCE_HC_STATUS_MASTER_ABORT (1L<<0) +#define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1) +#define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) +#define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) +#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) +#define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) +#define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) +#define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) +#define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) +#define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) + +#define BCE_HC_CONFIG 0x00006808 +#define BCE_HC_CONFIG_COLLECT_STATS (1L<<0) +#define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1) +#define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2) +#define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3) +#define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4) +#define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) +#define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6) +#define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) + +#define BCE_HC_ATTN_BITS_ENABLE 0x0000680c +#define BCE_HC_STATUS_ADDR_L 0x00006810 +#define BCE_HC_STATUS_ADDR_H 0x00006814 +#define BCE_HC_STATISTICS_ADDR_L 0x00006818 +#define BCE_HC_STATISTICS_ADDR_H 0x0000681c +#define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820 +#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) +#define BCE_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) + +#define BCE_HC_COMP_PROD_TRIP 0x00006824 +#define BCE_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) +#define BCE_HC_COMP_PROD_TRIP_INT (0xffL<<16) + +#define BCE_HC_RX_QUICK_CONS_TRIP 0x00006828 +#define BCE_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) +#define BCE_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) + +#define BCE_HC_RX_TICKS 0x0000682c +#define BCE_HC_RX_TICKS_VALUE (0x3ffL<<0) +#define BCE_HC_RX_TICKS_INT (0x3ffL<<16) + +#define BCE_HC_TX_TICKS 0x00006830 +#define BCE_HC_TX_TICKS_VALUE (0x3ffL<<0) +#define BCE_HC_TX_TICKS_INT (0x3ffL<<16) + +#define BCE_HC_COM_TICKS 0x00006834 +#define BCE_HC_COM_TICKS_VALUE (0x3ffL<<0) +#define BCE_HC_COM_TICKS_INT (0x3ffL<<16) + +#define BCE_HC_CMD_TICKS 0x00006838 +#define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0) +#define BCE_HC_CMD_TICKS_INT (0x3ffL<<16) + +#define BCE_HC_PERIODIC_TICKS 0x0000683c +#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) + +#define BCE_HC_STAT_COLLECT_TICKS 0x00006840 +#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) + +#define BCE_HC_STATS_TICKS 0x00006844 +#define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) + +#define BCE_HC_STAT_MEM_DATA 0x0000684c +#define BCE_HC_STAT_GEN_SEL_0 0x00006850 +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT \ + (88L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT \ + (89L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT \ + (93L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT\ + (94L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) +#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) + +#define BCE_HC_STAT_GEN_SEL_1 0x00006854 +#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) +#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) +#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) +#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) + +#define BCE_HC_STAT_GEN_SEL_2 0x00006858 +#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) +#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) +#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) +#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) + +#define BCE_HC_STAT_GEN_SEL_3 0x0000685c +#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) +#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) +#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) +#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) + +#define BCE_HC_STAT_GEN_STAT0 0x00006888 +#define BCE_HC_STAT_GEN_STAT1 0x0000688c +#define BCE_HC_STAT_GEN_STAT2 0x00006890 +#define BCE_HC_STAT_GEN_STAT3 0x00006894 +#define BCE_HC_STAT_GEN_STAT4 0x00006898 +#define BCE_HC_STAT_GEN_STAT5 0x0000689c +#define BCE_HC_STAT_GEN_STAT6 0x000068a0 +#define BCE_HC_STAT_GEN_STAT7 0x000068a4 +#define BCE_HC_STAT_GEN_STAT8 0x000068a8 +#define BCE_HC_STAT_GEN_STAT9 0x000068ac +#define BCE_HC_STAT_GEN_STAT10 0x000068b0 +#define BCE_HC_STAT_GEN_STAT11 0x000068b4 +#define BCE_HC_STAT_GEN_STAT12 0x000068b8 +#define BCE_HC_STAT_GEN_STAT13 0x000068bc +#define BCE_HC_STAT_GEN_STAT14 0x000068c0 +#define BCE_HC_STAT_GEN_STAT15 0x000068c4 +#define BCE_HC_STAT_GEN_STAT_AC0 0x000068c8 +#define BCE_HC_STAT_GEN_STAT_AC1 0x000068cc +#define BCE_HC_STAT_GEN_STAT_AC2 0x000068d0 +#define BCE_HC_STAT_GEN_STAT_AC3 0x000068d4 +#define BCE_HC_STAT_GEN_STAT_AC4 0x000068d8 +#define BCE_HC_STAT_GEN_STAT_AC5 0x000068dc +#define BCE_HC_STAT_GEN_STAT_AC6 0x000068e0 +#define BCE_HC_STAT_GEN_STAT_AC7 0x000068e4 +#define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8 +#define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec +#define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0 +#define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4 +#define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8 +#define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc +#define BCE_HC_STAT_GEN_STAT_AC14 0x00006900 +#define BCE_HC_STAT_GEN_STAT_AC15 0x00006904 +#define BCE_HC_VIS 0x00006908 +#define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) +#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) +#define BCE_HC_VIS_DMA_STAT_STATE (0xfL<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) +#define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) +#define BCE_HC_VIS_DMA_MSI_STATE (0x7L<<12) +#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) +#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) +#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) +#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) + +#define BCE_HC_VIS_1 0x0000690c +#define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4) +#define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) +#define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) +#define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5) +#define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) +#define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) +#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) +#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) +#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) +#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) +#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) +#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) +#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) +#define BCE_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) +#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) +#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) +#define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23) +#define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) +#define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) +#define BCE_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) +#define BCE_HC_VIS_1_INT_B (1L<<27) + +#define BCE_HC_DEBUG_VECT_PEEK 0x00006910 +#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + + + +/* + * txp_reg definition + * offset: 0x40000 + */ +#define BCE_TXP_CPU_MODE 0x00045000 +#define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0) +#define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1) +#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10) +#define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BCE_TXP_CPU_STATE 0x00045004 +#define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0) +#define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BCE_TXP_CPU_EVENT_MASK 0x00045008 +#define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BCE_TXP_CPU_PROGRAM_COUNTER 0x0004501c +#define BCE_TXP_CPU_INSTRUCTION 0x00045020 +#define BCE_TXP_CPU_DATA_ACCESS 0x00045024 +#define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028 +#define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c +#define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 +#define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034 +#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BCE_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 +#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 +#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BCE_TXP_CPU_REG_FILE 0x00045200 +#define BCE_TXP_FTQ_DATA 0x000453c0 +#define BCE_TXP_FTQ_CMD 0x000453f8 +#define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_TXP_FTQ_CMD_POP (1L<<30) +#define BCE_TXP_FTQ_CMD_BUSY (1L<<31) + +#define BCE_TXP_FTQ_CTL 0x000453fc +#define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_TXP_SCRATCH 0x00060000 + + +/* + * tpat_reg definition + * offset: 0x80000 + */ +#define BCE_TPAT_CPU_MODE 0x00085000 +#define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0) +#define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1) +#define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) +#define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10) +#define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BCE_TPAT_CPU_STATE 0x00085004 +#define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0) +#define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) +#define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12) +#define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BCE_TPAT_CPU_EVENT_MASK 0x00085008 +#define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BCE_TPAT_CPU_PROGRAM_COUNTER 0x0008501c +#define BCE_TPAT_CPU_INSTRUCTION 0x00085020 +#define BCE_TPAT_CPU_DATA_ACCESS 0x00085024 +#define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 +#define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c +#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 +#define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034 +#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BCE_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 +#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 +#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BCE_TPAT_CPU_REG_FILE 0x00085200 +#define BCE_TPAT_FTQ_DATA 0x000853c0 +#define BCE_TPAT_FTQ_CMD 0x000853f8 +#define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_TPAT_FTQ_CMD_POP (1L<<30) +#define BCE_TPAT_FTQ_CMD_BUSY (1L<<31) + +#define BCE_TPAT_FTQ_CTL 0x000853fc +#define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_TPAT_SCRATCH 0x000a0000 + + +/* + * rxp_reg definition + * offset: 0xc0000 + */ +#define BCE_RXP_CPU_MODE 0x000c5000 +#define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0) +#define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1) +#define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10) +#define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BCE_RXP_CPU_STATE 0x000c5004 +#define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0) +#define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12) +#define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BCE_RXP_CPU_EVENT_MASK 0x000c5008 +#define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BCE_RXP_CPU_PROGRAM_COUNTER 0x000c501c +#define BCE_RXP_CPU_INSTRUCTION 0x000c5020 +#define BCE_RXP_CPU_DATA_ACCESS 0x000c5024 +#define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 +#define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c +#define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 +#define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034 +#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BCE_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 +#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 +#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BCE_RXP_CPU_REG_FILE 0x000c5200 +#define BCE_RXP_CFTQ_DATA 0x000c5380 +#define BCE_RXP_CFTQ_CMD 0x000c53b8 +#define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10) +#define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25) +#define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26) +#define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28) +#define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_RXP_CFTQ_CMD_POP (1L<<30) +#define BCE_RXP_CFTQ_CMD_BUSY (1L<<31) + +#define BCE_RXP_CFTQ_CTL 0x000c53bc +#define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0) +#define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1) +#define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_RXP_FTQ_DATA 0x000c53c0 +#define BCE_RXP_FTQ_CMD 0x000c53f8 +#define BCE_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_RXP_FTQ_CMD_POP (1L<<30) +#define BCE_RXP_FTQ_CMD_BUSY (1L<<31) + +#define BCE_RXP_FTQ_CTL 0x000c53fc +#define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_RXP_SCRATCH 0x000e0000 + + +/* + * com_reg definition + * offset: 0x100000 + */ +#define BCE_COM_CPU_MODE 0x00105000 +#define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0) +#define BCE_COM_CPU_MODE_STEP_ENA (1L<<1) +#define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6) +#define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10) +#define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BCE_COM_CPU_STATE 0x00105004 +#define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0) +#define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10) +#define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12) +#define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BCE_COM_CPU_EVENT_MASK 0x00105008 +#define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BCE_COM_CPU_PROGRAM_COUNTER 0x0010501c +#define BCE_COM_CPU_INSTRUCTION 0x00105020 +#define BCE_COM_CPU_DATA_ACCESS 0x00105024 +#define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028 +#define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c +#define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 +#define BCE_COM_CPU_HW_BREAKPOINT 0x00105034 +#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BCE_COM_CPU_DEBUG_VECT_PEEK 0x00105038 +#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_COM_CPU_LAST_BRANCH_ADDR 0x00105048 +#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BCE_COM_CPU_REG_FILE 0x00105200 +#define BCE_COM_COMXQ_FTQ_DATA 0x00105340 +#define BCE_COM_COMXQ_FTQ_CMD 0x00105378 +#define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30) +#define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) + +#define BCE_COM_COMXQ_FTQ_CTL 0x0010537c +#define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_COM_COMTQ_FTQ_DATA 0x00105380 +#define BCE_COM_COMTQ_FTQ_CMD 0x001053b8 +#define BCE_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30) +#define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) + +#define BCE_COM_COMTQ_FTQ_CTL 0x001053bc +#define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_COM_COMQ_FTQ_DATA 0x001053c0 +#define BCE_COM_COMQ_FTQ_CMD 0x001053f8 +#define BCE_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30) +#define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31) + +#define BCE_COM_COMQ_FTQ_CTL 0x001053fc +#define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_COM_SCRATCH 0x00120000 + + +/* + * cp_reg definition + * offset: 0x180000 + */ +#define BCE_CP_CPU_MODE 0x00185000 +#define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0) +#define BCE_CP_CPU_MODE_STEP_ENA (1L<<1) +#define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10) +#define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BCE_CP_CPU_STATE 0x00185004 +#define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0) +#define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12) +#define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BCE_CP_CPU_EVENT_MASK 0x00185008 +#define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BCE_CP_CPU_PROGRAM_COUNTER 0x0018501c +#define BCE_CP_CPU_INSTRUCTION 0x00185020 +#define BCE_CP_CPU_DATA_ACCESS 0x00185024 +#define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028 +#define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c +#define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 +#define BCE_CP_CPU_HW_BREAKPOINT 0x00185034 +#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BCE_CP_CPU_DEBUG_VECT_PEEK 0x00185038 +#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_CP_CPU_LAST_BRANCH_ADDR 0x00185048 +#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BCE_CP_CPU_REG_FILE 0x00185200 +#define BCE_CP_CPQ_FTQ_DATA 0x001853c0 +#define BCE_CP_CPQ_FTQ_CMD 0x001853f8 +#define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30) +#define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31) + +#define BCE_CP_CPQ_FTQ_CTL 0x001853fc +#define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_CP_SCRATCH 0x001a0000 + + +/* + * mcp_reg definition + * offset: 0x140000 + */ +#define BCE_MCP_CPU_MODE 0x00145000 +#define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0) +#define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1) +#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) +#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) +#define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6) +#define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) +#define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10) +#define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) +#define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) +#define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) +#define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) + +#define BCE_MCP_CPU_STATE 0x00145004 +#define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0) +#define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) +#define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) +#define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) +#define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) +#define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) +#define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) +#define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) +#define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10) +#define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) +#define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12) +#define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) +#define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) +#define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31) + +#define BCE_MCP_CPU_EVENT_MASK 0x00145008 +#define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) +#define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) +#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) +#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) +#define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) +#define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) +#define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) +#define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) +#define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) +#define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) +#define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) + +#define BCE_MCP_CPU_PROGRAM_COUNTER 0x0014501c +#define BCE_MCP_CPU_INSTRUCTION 0x00145020 +#define BCE_MCP_CPU_DATA_ACCESS 0x00145024 +#define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028 +#define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c +#define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 +#define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034 +#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) +#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) + +#define BCE_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 +#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) +#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) +#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) +#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) +#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) +#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) + +#define BCE_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 +#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) +#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) +#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) +#define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) + +#define BCE_MCP_CPU_REG_FILE 0x00145200 +#define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0 +#define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8 +#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) +#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) +#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) +#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) +#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) +#define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) +#define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) +#define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) +#define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) +#define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30) +#define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) + +#define BCE_MCP_MCPQ_FTQ_CTL 0x001453fc +#define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) +#define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) +#define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) +#define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) +#define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) + +#define BCE_MCP_ROM 0x00150000 +#define BCE_MCP_SCRATCH 0x00160000 + +#define BCE_SHM_HDR_SIGNATURE BCE_MCP_SCRATCH +#define BCE_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 +#define BCE_SHM_HDR_SIGNATURE_SIG 0x53530000 +#define BCE_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff +#define BCE_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 + +#define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4 +#define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8 + +/****************************************************************************/ +/* End machine generated definitions. */ +/****************************************************************************/ + +#define NUM_MC_HASH_REGISTERS 8 + + +/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ +#define PHY_BCM5706_PHY_ID 0x00206160 + +#define PHY_ID(id) ((id) & 0xfffffff0) +#define PHY_REV_ID(id) ((id) & 0xf) + +/* 5708 Serdes PHY registers */ + +#define BCM5708S_UP1 0xb + +#define BCM5708S_UP1_2G5 0x1 + +#define BCM5708S_BLK_ADDR 0x1f + +#define BCM5708S_BLK_ADDR_DIG 0x0000 +#define BCM5708S_BLK_ADDR_DIG3 0x0002 +#define BCM5708S_BLK_ADDR_TX_MISC 0x0005 + +/* Digital Block */ +#define BCM5708S_1000X_CTL1 0x10 + +#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 +#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 + +#define BCM5708S_1000X_CTL2 0x11 + +#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 + +#define BCM5708S_1000X_STAT1 0x14 + +#define BCM5708S_1000X_STAT1_SGMII 0x0001 +#define BCM5708S_1000X_STAT1_LINK 0x0002 +#define BCM5708S_1000X_STAT1_FD 0x0004 +#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 +#define BCM5708S_1000X_STAT1_SPEED_10 0x0000 +#define BCM5708S_1000X_STAT1_SPEED_100 0x0008 +#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 +#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 +#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 +#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 + +/* Digital3 Block */ +#define BCM5708S_DIG_3_0 0x10 + +#define BCM5708S_DIG_3_0_USE_IEEE 0x0001 + +/* Tx/Misc Block */ +#define BCM5708S_TX_ACTL1 0x15 + +#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 + +#define BCM5708S_TX_ACTL3 0x17 + +#define RX_COPY_THRESH 92 + +#define DMA_READ_CHANS 5 +#define DMA_WRITE_CHANS 3 + +/* Use the natural page size of the host CPU. */ +/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */ +#define BCM_PAGE_BITS PAGE_SHIFT +#define BCM_PAGE_SIZE PAGE_SIZE + +#define TX_PAGES 2 +#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) +#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) +#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) +#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) +#define MAX_TX_BD (TOTAL_TX_BD - 1) +#define BCE_TX_SPARE_SPACE 5 + +#define RX_PAGES 2 +#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) +#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) +#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) +#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) +#define MAX_RX_BD (TOTAL_RX_BD - 1) + +#define NEXT_TX_BD(x) \ + (((x) & USABLE_TX_BD_PER_PAGE) == (USABLE_TX_BD_PER_PAGE - 1)) ? \ + (x) + 2 : (x) + 1 + +#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) + +#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8) +#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) + +#define NEXT_RX_BD(x) \ + (((x) & USABLE_RX_BD_PER_PAGE) == (USABLE_RX_BD_PER_PAGE - 1)) ? \ + (x) + 2 : (x) + 1 + +#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) + +#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8) +#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) + +/* Context size. */ +#define CTX_SHIFT 7 +#define CTX_SIZE (1 << CTX_SHIFT) +#define CTX_MASK (CTX_SIZE - 1) +#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) +#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) + +#define PHY_CTX_SHIFT 6 +#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) +#define PHY_CTX_MASK (PHY_CTX_SIZE - 1) +#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) +#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) + +#define MB_KERNEL_CTX_SHIFT 8 +#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) +#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) +#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) + +#define MAX_CID_CNT 0x4000 +#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) +#define INVALID_CID_ADDR 0xffffffff + +#define TX_CID 16 +#define RX_CID 0 + +#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) +#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) + +/****************************************************************************/ +/* BCE Processor Firmwware Load Definitions */ +/****************************************************************************/ + +struct cpu_reg { + uint32_t mode; + uint32_t mode_value_halt; + uint32_t mode_value_sstep; + + uint32_t state; + uint32_t state_value_clear; + + uint32_t gpr0; + uint32_t evmask; + uint32_t pc; + uint32_t inst; + uint32_t bp; + + uint32_t spad_base; + + uint32_t mips_view_base; +}; + +struct fw_info { + uint32_t ver_major; + uint32_t ver_minor; + uint32_t ver_fix; + + uint32_t start_addr; + + /* Text section. */ + uint32_t text_addr; + uint32_t text_len; + uint32_t text_index; + uint32_t *text; + + /* Data section. */ + uint32_t data_addr; + uint32_t data_len; + uint32_t data_index; + uint32_t *data; + + /* SBSS section. */ + uint32_t sbss_addr; + uint32_t sbss_len; + uint32_t sbss_index; + uint32_t *sbss; + + /* BSS section. */ + uint32_t bss_addr; + uint32_t bss_len; + uint32_t bss_index; + uint32_t *bss; + + /* Read-only section. */ + uint32_t rodata_addr; + uint32_t rodata_len; + uint32_t rodata_index; + uint32_t *rodata; +}; + +#define RV2P_PROC1 0 +#define RV2P_PROC2 1 + +#define BCE_MIREG(x) ((x & 0x1F) << 16) +#define BCE_MIPHY(x) ((x & 0x1F) << 21) +#define BCE_PHY_TIMEOUT 50 + +#define BCE_NVRAM_SIZE 0x200 +#define BCE_NVRAM_MAGIC 0x669955aa +#define BCE_CRC32_RESIDUAL 0xdebb20e3 + +#define BCE_TX_TIMEOUT 5 + +#define BCE_MAX_SEGMENTS 32 +#define BCE_DMA_ALIGN 8 +#define BCE_DMA_BOUNDARY 0 + +/* The BCM5708 has a problem with addresses greater that 40bits. */ +/* Handle the sizing issue in an architecture agnostic fashion. */ +#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) +#define BCE_BUS_SPACE_MAXADDR BUS_SPACE_MAXADDR +#else +#define BCE_BUS_SPACE_MAXADDR 0xFFFFFFFFFF +#endif + +/* + * XXX Checksum offload involving IP fragments seems to cause problems on + * transmit. Disable it for now, hopefully there will be a more elegant + * solution later. + */ +#ifdef BCE_IP_CSUM +#define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) +#else +#define BCE_IF_HWASSIST (CSUM_TCP | CSUM_UDP) +#endif + +/* NOTE: This hardware also can do VLAN csum offload */ +#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | \ + IFCAP_VLAN_HWTAGGING | \ + IFCAP_HWCSUM | \ + IFCAP_JUMBO_MTU) + +#define BCE_MIN_MTU 60 +#define BCE_MIN_ETHER_MTU 64 + +#define BCE_MAX_STD_MTU 1500 +#define BCE_MAX_STD_ETHER_MTU 1518 +#define BCE_MAX_STD_ETHER_MTU_VLAN 1522 + +#define BCE_MAX_JUMBO_MTU 9000 +#define BCE_MAX_JUMBO_ETHER_MTU 9018 +#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022 + +#if 0 +#define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + EVL_ENCAPLEN /* 9022 */ +#endif + +/****************************************************************************/ +/* BCE Device State Data Structure */ +/****************************************************************************/ + +#define BCE_STATUS_BLK_SZ sizeof(struct status_block) +#define BCE_STATS_BLK_SZ sizeof(struct statistics_block) +#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE +#define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE + +struct bce_softc { + struct arpcom arpcom; + device_t bce_dev; + struct resource *bce_res_mem; /* Device resource handle */ + bus_space_tag_t bce_btag; /* Device bus tag */ + bus_space_handle_t bce_bhandle; /* Device bus handle */ + struct resource *bce_res_irq; /* IRQ Resource Handle */ + void *bce_intrhand; /* Interrupt handler */ + + /* ASIC Chip ID. */ + uint32_t bce_chipid; + + /* General controller flags. */ + uint32_t bce_flags; +#define BCE_PCIX_FLAG 0x01 +#define BCE_PCI_32BIT_FLAG 0x02 +#define BCE_ONE_TDMA_FLAG 0x04 /* Deprecated */ +#define BCE_NO_WOL_FLAG 0x08 +#define BCE_USING_DAC_FLAG 0x10 +#define BCE_USING_MSI_FLAG 0x20 +#define BCE_MFW_ENABLE_FLAG 0x40 /* Management F/W is enabled */ + + /* PHY specific flags. */ + uint32_t bce_phy_flags; +#define BCE_PHY_SERDES_FLAG 0x001 +#define BCE_PHY_CRC_FIX_FLAG 0x002 +#define BCE_PHY_PARALLEL_DETECT_FLAG 0x004 +#define BCE_PHY_2_5G_CAPABLE_FLAG 0x008 +#define BCE_PHY_INT_MODE_MASK_FLAG 0x300 +#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 +#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x200 + + bus_addr_t max_bus_addr; + uint16_t bus_speed_mhz; /* PCI bus speed */ + const struct flash_spec *bce_flash_info;/* Flash NVRAM settings */ + uint32_t bce_flash_size; /* Flash NVRAM size */ + uint32_t bce_shmem_base; /* Shared Memory base address */ + + /* Tracks the version of bootcode firmware. */ + uint32_t bce_fw_ver; + + /* + * Tracks the state of the firmware. 0 = Running while any + * other value indicates that the firmware is not responding. + */ + uint16_t bce_fw_timed_out; + + /* + * An incrementing sequence used to coordinate messages passed + * from the driver to the firmware. + */ + uint16_t bce_fw_wr_seq; + + /* + * An incrementing sequence used to let the firmware know that + * the driver is still operating. Without the pulse, management + * firmware such as IPMI or UMP will operate in OS absent state. + */ + uint16_t bce_fw_drv_pulse_wr_seq; + + u_char eaddr[6]; /* Ethernet MAC address. */ + + /* + * These setting are used by the host coalescing (HC) block to + * to control how often the status block, statistics block and + * interrupts are generated. + */ + uint16_t bce_tx_quick_cons_trip_int; + uint16_t bce_tx_quick_cons_trip; + uint16_t bce_rx_quick_cons_trip_int; + uint16_t bce_rx_quick_cons_trip; + uint16_t bce_comp_prod_trip_int; + uint16_t bce_comp_prod_trip; + uint16_t bce_tx_ticks_int; + uint16_t bce_tx_ticks; + uint16_t bce_rx_ticks_int; + uint16_t bce_rx_ticks; + uint16_t bce_com_ticks_int; + uint16_t bce_com_ticks; + uint16_t bce_cmd_ticks_int; + uint16_t bce_cmd_ticks; + uint32_t bce_stats_ticks; + + /* The address of the integrated PHY on the MII bus. */ + int bce_phy_addr; + + /* The device handle for the MII bus child device. */ + device_t bce_miibus; + + /* Driver maintained TX chain pointers and byte counter. */ + uint16_t rx_prod; + uint16_t rx_cons; + uint32_t rx_prod_bseq; /* Counts the bytes used. */ + uint16_t tx_prod; + uint16_t tx_cons; + uint32_t tx_prod_bseq; /* Counts the bytes used. */ + + int bce_link; + struct callout bce_stat_ch; + + /* Frame size and mbuf allocation size for RX frames. */ + uint32_t max_frame_size; + int mbuf_alloc_size; + + /* Receive mode settings (i.e promiscuous, multicast, etc.). */ + uint32_t rx_mode; + + /* Bus tag for the bce controller. */ + bus_dma_tag_t parent_tag; + + /* H/W maintained TX buffer descriptor chain structure. */ + bus_dma_tag_t tx_bd_chain_tag; + bus_dmamap_t tx_bd_chain_map[TX_PAGES]; + struct tx_bd *tx_bd_chain[TX_PAGES]; + bus_addr_t tx_bd_chain_paddr[TX_PAGES]; + + /* H/W maintained RX buffer descriptor chain structure. */ + bus_dma_tag_t rx_bd_chain_tag; + bus_dmamap_t rx_bd_chain_map[RX_PAGES]; + struct rx_bd *rx_bd_chain[RX_PAGES]; + bus_addr_t rx_bd_chain_paddr[RX_PAGES]; + + /* H/W maintained status block. */ + bus_dma_tag_t status_tag; + bus_dmamap_t status_map; + struct status_block *status_block; /* virtual address */ + bus_addr_t status_block_paddr; /* Physical address */ + + /* Driver maintained status block values. */ + uint16_t last_status_idx; + uint16_t hw_rx_cons; + uint16_t hw_tx_cons; + + /* H/W maintained statistics block. */ + bus_dma_tag_t stats_tag; + bus_dmamap_t stats_map; + struct statistics_block *stats_block; /* Virtual address */ + bus_addr_t stats_block_paddr; /* Physical address */ + + /* Bus tag for RX/TX mbufs. */ + bus_dma_tag_t rx_mbuf_tag; + bus_dma_tag_t tx_mbuf_tag; + + /* S/W maintained mbuf TX chain structure. */ + bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; + struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; + + /* S/W maintained mbuf RX chain structure. */ + bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; + struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; + + /* Track the number of rx_bd and tx_bd's in use. */ + uint16_t free_rx_bd; + uint16_t max_rx_bd; + uint16_t used_tx_bd; + uint16_t max_tx_bd; + + int bce_if_flags; + struct sysctl_ctx_list bce_sysctl_ctx; + struct sysctl_oid *bce_sysctl_tree; + + /* Provides access to hardware statistics through sysctl. */ + uint64_t stat_IfHCInOctets; + uint64_t stat_IfHCInBadOctets; + uint64_t stat_IfHCOutOctets; + uint64_t stat_IfHCOutBadOctets; + uint64_t stat_IfHCInUcastPkts; + uint64_t stat_IfHCInMulticastPkts; + uint64_t stat_IfHCInBroadcastPkts; + uint64_t stat_IfHCOutUcastPkts; + uint64_t stat_IfHCOutMulticastPkts; + uint64_t stat_IfHCOutBroadcastPkts; + + uint32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; + uint32_t stat_Dot3StatsCarrierSenseErrors; + uint32_t stat_Dot3StatsFCSErrors; + uint32_t stat_Dot3StatsAlignmentErrors; + uint32_t stat_Dot3StatsSingleCollisionFrames; + uint32_t stat_Dot3StatsMultipleCollisionFrames; + uint32_t stat_Dot3StatsDeferredTransmissions; + uint32_t stat_Dot3StatsExcessiveCollisions; + uint32_t stat_Dot3StatsLateCollisions; + uint32_t stat_EtherStatsCollisions; + uint32_t stat_EtherStatsFragments; + uint32_t stat_EtherStatsJabbers; + uint32_t stat_EtherStatsUndersizePkts; + uint32_t stat_EtherStatsOverrsizePkts; + uint32_t stat_EtherStatsPktsRx64Octets; + uint32_t stat_EtherStatsPktsRx65Octetsto127Octets; + uint32_t stat_EtherStatsPktsRx128Octetsto255Octets; + uint32_t stat_EtherStatsPktsRx256Octetsto511Octets; + uint32_t stat_EtherStatsPktsRx512Octetsto1023Octets; + uint32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; + uint32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; + uint32_t stat_EtherStatsPktsTx64Octets; + uint32_t stat_EtherStatsPktsTx65Octetsto127Octets; + uint32_t stat_EtherStatsPktsTx128Octetsto255Octets; + uint32_t stat_EtherStatsPktsTx256Octetsto511Octets; + uint32_t stat_EtherStatsPktsTx512Octetsto1023Octets; + uint32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; + uint32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; + uint32_t stat_XonPauseFramesReceived; + uint32_t stat_XoffPauseFramesReceived; + uint32_t stat_OutXonSent; + uint32_t stat_OutXoffSent; + uint32_t stat_FlowControlDone; + uint32_t stat_MacControlFramesReceived; + uint32_t stat_XoffStateEntered; + uint32_t stat_IfInFramesL2FilterDiscards; + uint32_t stat_IfInRuleCheckerDiscards; + uint32_t stat_IfInFTQDiscards; + uint32_t stat_IfInMBUFDiscards; + uint32_t stat_IfInRuleCheckerP4Hit; + uint32_t stat_CatchupInRuleCheckerDiscards; + uint32_t stat_CatchupInFTQDiscards; + uint32_t stat_CatchupInMBUFDiscards; + uint32_t stat_CatchupInRuleCheckerP4Hit; + + /* Provides access to certain firmware statistics. */ + uint32_t com_no_buffers; + +#ifdef BCE_DEBUG + /* Track the number of enqueued mbufs. */ + int tx_mbuf_alloc; + int rx_mbuf_alloc; + + /* Track how many and what type of interrupts are generated. */ + uint32_t interrupts_generated; + uint32_t interrupts_handled; + uint32_t rx_interrupts; + uint32_t tx_interrupts; + + uint32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ + uint32_t rx_empty_count; + uint32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ + uint32_t tx_full_count; /* Number of times the TX chain was full. */ + uint32_t mbuf_alloc_failed; /* Mbuf allocation failure counter. */ + uint32_t l2fhdr_status_errors; + uint32_t unexpected_attentions; + uint32_t lost_status_block_updates; +#endif +}; + +struct bce_dmamap_arg { + int bce_maxsegs; + bus_dma_segment_t *bce_segs; +}; + +#endif /* #ifndef _BCE_H_DEFINED */ diff --git a/sys/dev/netif/mii_layer/brgphy.c b/sys/dev/netif/mii_layer/brgphy.c index c81310d9c6..9e3cd95022 100644 --- a/sys/dev/netif/mii_layer/brgphy.c +++ b/sys/dev/netif/mii_layer/brgphy.c @@ -32,7 +32,7 @@ * THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ - * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.17 2007/05/07 04:54:32 sephe Exp $ + * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.18 2007/05/26 08:50:49 sephe Exp $ */ /* @@ -519,6 +519,10 @@ brgphy_reset(struct mii_softc *sc) PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & ~BRGPHY_PHY_EXTCTL_3_LED); } + } else if (strncmp(ifp->if_xname, "bce", 3) == 0) { + brgphy_ber_bug(sc); + brgphy_jumbo_settings(sc, ifp->if_mtu); + brgphy_eth_wirespeed(sc); } }