From: Matthew Dillon Date: Sat, 25 Sep 2010 20:17:31 +0000 (-0700) Subject: docs - Adjust swapcache.8 X-Git-Tag: v2.9.0~74^2~46 X-Git-Url: https://gitweb.dragonflybsd.org/dragonfly.git/commitdiff_plain/955b4283c05a07883e5a746ab0061be4b0946553 docs - Adjust swapcache.8 * Clarify the lack of clarity on read-disturb effects. Expand the write endurance section a bit incorporating the results from long-term testing on pkgbox64. --- diff --git a/share/man/man8/swapcache.8 b/share/man/man8/swapcache.8 index f6680db5ef..10a7e67d3a 100644 --- a/share/man/man8/swapcache.8 +++ b/share/man/man8/swapcache.8 @@ -457,11 +457,19 @@ write clustering it does. The theoretical limit for the Intel X25V is 400TB (10,000 erase cycles per MLC cell, 40GB drive), but the firmware doesn't do perfect static wear leveling so the actual durability is less. +In tests over several hundred days we have validated a write endurance +greater than 200TB on the 40G Intel X25V using +.Nm . .Pp In contrast, most filesystems directly stored on a SSD have fairly severe write amplification effects and will have durabilities ranging closer to the vendor-specified limit. +.Pp Power-on hours, power cycles, and read operations do not really affect wear. +There is something called read-disturb but it is unclear what sort of +ratio would be needed. Since the data is cached in ram and thus not +re-read at a high rate there is no expectation of a practical effect. +For all intents and purposes only write operations effect wear. .Pp SSD's with MLC-based flash technology are high-density, low-cost solutions with limited write durability.