From: Sascha Wildner Date: Mon, 5 Aug 2013 19:37:54 +0000 (+0200) Subject: kernel: Move some header files to the drivers that only need them. X-Git-Tag: v3.7.0~641 X-Git-Url: https://gitweb.dragonflybsd.org/dragonfly.git/commitdiff_plain/db75f6aaab2a5310c8cb1bfd6314f9f8567adcbb kernel: Move some header files to the drivers that only need them. --- diff --git a/sys/dev/netif/fe/if_fe.c b/sys/dev/netif/fe/if_fe.c index f845085488..4a2dbeda5a 100644 --- a/sys/dev/netif/fe/if_fe.c +++ b/sys/dev/netif/fe/if_fe.c @@ -96,7 +96,7 @@ #include -#include +#include "mb86960.h" #include "if_fereg.h" #include "if_fevar.h" diff --git a/sys/dev/netif/fe/if_fe_isa.c b/sys/dev/netif/fe/if_fe_isa.c index 5a9b5501d3..b447e4bf19 100644 --- a/sys/dev/netif/fe/if_fe_isa.c +++ b/sys/dev/netif/fe/if_fe_isa.c @@ -44,7 +44,7 @@ #include #include -#include +#include "mb86960.h" #include "if_fereg.h" #include "if_fevar.h" diff --git a/sys/dev/netif/fe/if_fe_pccard.c b/sys/dev/netif/fe/if_fe_pccard.c index 05df49534c..9760fd8729 100644 --- a/sys/dev/netif/fe/if_fe_pccard.c +++ b/sys/dev/netif/fe/if_fe_pccard.c @@ -41,7 +41,7 @@ #include #include -#include +#include "mb86960.h" #include "if_fereg.h" #include "if_fevar.h" diff --git a/sys/platform/pc32/isa/ic/mb86960.h b/sys/dev/netif/fe/mb86960.h similarity index 99% rename from sys/platform/pc32/isa/ic/mb86960.h rename to sys/dev/netif/fe/mb86960.h index 29bcb8a206..5c35fcfdfa 100644 --- a/sys/platform/pc32/isa/ic/mb86960.h +++ b/sys/dev/netif/fe/mb86960.h @@ -20,7 +20,6 @@ * SUCH DAMAGE. * * $FreeBSD: src/sys/i386/isa/ic/mb86960.h,v 1.2.8.1 2000/08/03 01:01:25 peter Exp $ - * $DragonFly: src/sys/platform/pc32/isa/ic/mb86960.h,v 1.2 2003/06/17 04:28:37 dillon Exp $ */ /* diff --git a/sys/platform/pc32/isa/ic/cd1400.h b/sys/dev/serial/cy/cd1400.h similarity index 99% rename from sys/platform/pc32/isa/ic/cd1400.h rename to sys/dev/serial/cy/cd1400.h index ae0c2ff853..d257b25410 100644 --- a/sys/platform/pc32/isa/ic/cd1400.h +++ b/sys/dev/serial/cy/cd1400.h @@ -28,7 +28,6 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD: src/sys/i386/isa/ic/cd1400.h,v 1.6 1999/08/28 00:45:12 peter Exp $ - * $DragonFly: src/sys/platform/pc32/isa/ic/cd1400.h,v 1.2 2003/06/17 04:28:37 dillon Exp $ */ /* diff --git a/sys/dev/serial/cy/cy.c b/sys/dev/serial/cy/cy.c index 7451991cc2..574733dd8c 100644 --- a/sys/dev/serial/cy/cy.c +++ b/sys/dev/serial/cy/cy.c @@ -86,7 +86,7 @@ #include #include "cyreg.h" -#include +#include "cd1400.h" #define disable_intr() com_lock() #define enable_intr() com_unlock() diff --git a/sys/platform/pc64/isa/ic/sc26198.h b/sys/dev/serial/stl/sc26198.h similarity index 99% rename from sys/platform/pc64/isa/ic/sc26198.h rename to sys/dev/serial/stl/sc26198.h index fe236c7e18..d0597344a3 100644 --- a/sys/platform/pc64/isa/ic/sc26198.h +++ b/sys/dev/serial/stl/sc26198.h @@ -34,7 +34,6 @@ * SUCH DAMAGE. * * $FreeBSD: src/sys/i386/isa/ic/sc26198.h,v 1.1.2.1 2001/08/30 12:29:55 murray Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ic/sc26198.h,v 1.1 2008/08/29 17:07:21 dillon Exp $ */ /*****************************************************************************/ diff --git a/sys/platform/pc32/isa/ic/scd1400.h b/sys/dev/serial/stl/scd1400.h similarity index 98% rename from sys/platform/pc32/isa/ic/scd1400.h rename to sys/dev/serial/stl/scd1400.h index df1f44cddd..4d6a470980 100644 --- a/sys/platform/pc32/isa/ic/scd1400.h +++ b/sys/dev/serial/stl/scd1400.h @@ -34,7 +34,6 @@ * SUCH DAMAGE. * * $FreeBSD: src/sys/i386/isa/ic/scd1400.h,v 1.5 1999/08/28 00:45:15 peter Exp $ - * $DragonFly: src/sys/platform/pc32/isa/ic/scd1400.h,v 1.2 2003/06/17 04:28:37 dillon Exp $ */ /*****************************************************************************/ diff --git a/sys/dev/serial/stl/stallion.c b/sys/dev/serial/stl/stallion.c index c46aa662d1..5d97dc17f3 100644 --- a/sys/dev/serial/stl/stallion.c +++ b/sys/dev/serial/stl/stallion.c @@ -52,8 +52,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/sys/platform/pc32/isa/ic/sc26198.h b/sys/platform/pc32/isa/ic/sc26198.h deleted file mode 100644 index 9b9fecd6e2..0000000000 --- a/sys/platform/pc32/isa/ic/sc26198.h +++ /dev/null @@ -1,547 +0,0 @@ -/*****************************************************************************/ - -/* - * sc26198.h -- SC26198 UART hardware info. - * - * Copyright (c) 1995-1998 Greg Ungerer (gerg@stallion.oz.au). - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Greg Ungerer. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/sc26198.h,v 1.1.2.1 2001/08/30 12:29:55 murray Exp $ - * $DragonFly: src/sys/platform/pc32/isa/ic/sc26198.h,v 1.2 2003/06/17 04:28:37 dillon Exp $ - */ - -/*****************************************************************************/ -#ifndef _SC26198_H -#define _SC26198_H -/*****************************************************************************/ - -/* - * Define the number of async ports per sc26198 uart device. - */ -#define SC26198_PORTS 8 - -/* - * Baud rate timing clocks. All derived from a master 14.7456 MHz clock. - */ -#define SC26198_MASTERCLOCK 14745600L -#define SC26198_DCLK (SC26198_MASTERCLOCK) -#define SC26198_CCLK (SC26198_MASTERCLOCK / 2) -#define SC26198_BCLK (SC26198_MASTERCLOCK / 4) - -/* - * Define internal FIFO sizes for the 26198 ports. - */ -#define SC26198_TXFIFOSIZE 16 -#define SC26198_RXFIFOSIZE 16 - -/*****************************************************************************/ - -/* - * Global register definitions. These registers are global to each 26198 - * device, not specific ports on it. - */ -#define TSTR 0x0d -#define GCCR 0x0f -#define ICR 0x1b -#define WDTRCR 0x1d -#define IVR 0x1f -#define BRGTRUA 0x84 -#define GPOSR 0x87 -#define GPOC 0x8b -#define UCIR 0x8c -#define CIR 0x8c -#define BRGTRUB 0x8d -#define GRXFIFO 0x8e -#define GTXFIFO 0x8e -#define GCCR2 0x8f -#define BRGTRLA 0x94 -#define GPOR 0x97 -#define GPOD 0x9b -#define BRGTCR 0x9c -#define GICR 0x9c -#define BRGTRLB 0x9d -#define GIBCR 0x9d -#define GITR 0x9f - -/* - * Per port channel registers. These are the register offsets within - * the port address space, so need to have the port address (0 to 7) - * inserted in bit positions 4:6. - */ -#define MR0 0x00 -#define MR1 0x01 -#define IOPCR 0x02 -#define BCRBRK 0x03 -#define BCRCOS 0x04 -#define BCRX 0x06 -#define BCRA 0x07 -#define XONCR 0x08 -#define XOFFCR 0x09 -#define ARCR 0x0a -#define RXCSR 0x0c -#define TXCSR 0x0e -#define MR2 0x80 -#define SR 0x81 -#define SCCR 0x81 -#define ISR 0x82 -#define IMR 0x82 -#define TXFIFO 0x83 -#define RXFIFO 0x83 -#define IPR 0x84 -#define IOPIOR 0x85 -#define XISR 0x86 - -/* - * For any given port calculate the address to use to access a specified - * register. This is only used for unusual access... - */ -#define SC26198_PORTREG(port,reg) ((((port) & 0x07) << 4) | (reg)) - -/*****************************************************************************/ - -/* - * Global configuration control register bit definitions. - */ -#define GCCR_NOACK 0x00 -#define GCCR_IVRACK 0x02 -#define GCCR_IVRCHANACK 0x04 -#define GCCR_IVRTYPCHANACK 0x06 -#define GCCR_ASYNCCYCLE 0x00 -#define GCCR_SYNCCYCLE 0x40 - -/*****************************************************************************/ - -/* - * Mode register 0 bit definitions. - */ -#define MR0_ADDRNONE 0x00 -#define MR0_AUTOWAKE 0x01 -#define MR0_AUTODOZE 0x02 -#define MR0_AUTOWAKEDOZE 0x03 -#define MR0_SWFNONE 0x00 -#define MR0_SWFTX 0x04 -#define MR0_SWFRX 0x08 -#define MR0_SWFRXTX 0x0c -#define MR0_TXMASK 0x30 -#define MR0_TXEMPTY 0x00 -#define MR0_TXHIGH 0x10 -#define MR0_TXHALF 0x20 -#define MR0_TXRDY 0x00 -#define MR0_ADDRNT 0x00 -#define MR0_ADDRT 0x40 -#define MR0_SWFNT 0x00 -#define MR0_SWFT 0x80 - -/* - * Mode register 1 bit definitions. - */ -#define MR1_CS5 0x00 -#define MR1_CS6 0x01 -#define MR1_CS7 0x02 -#define MR1_CS8 0x03 -#define MR1_PAREVEN 0x00 -#define MR1_PARODD 0x04 -#define MR1_PARENB 0x00 -#define MR1_PARFORCE 0x08 -#define MR1_PARNONE 0x10 -#define MR1_PARSPECIAL 0x18 -#define MR1_ERRCHAR 0x00 -#define MR1_ERRBLOCK 0x20 -#define MR1_ISRUNMASKED 0x00 -#define MR1_ISRMASKED 0x40 -#define MR1_AUTORTS 0x80 - -/* - * Mode register 2 bit definitions. - */ -#define MR2_STOP1 0x00 -#define MR2_STOP15 0x01 -#define MR2_STOP2 0x02 -#define MR2_STOP916 0x03 -#define MR2_RXFIFORDY 0x00 -#define MR2_RXFIFOHALF 0x04 -#define MR2_RXFIFOHIGH 0x08 -#define MR2_RXFIFOFULL 0x0c -#define MR2_AUTOCTS 0x10 -#define MR2_TXRTS 0x20 -#define MR2_MODENORM 0x00 -#define MR2_MODEAUTOECHO 0x40 -#define MR2_MODELOOP 0x80 -#define MR2_MODEREMECHO 0xc0 - -/*****************************************************************************/ - -/* - * Baud Rate Generator (BRG) selector values. - */ -#define BRG_50 0x00 -#define BRG_75 0x01 -#define BRG_150 0x02 -#define BRG_200 0x03 -#define BRG_300 0x04 -#define BRG_450 0x05 -#define BRG_600 0x06 -#define BRG_900 0x07 -#define BRG_1200 0x08 -#define BRG_1800 0x09 -#define BRG_2400 0x0a -#define BRG_3600 0x0b -#define BRG_4800 0x0c -#define BRG_7200 0x0d -#define BRG_9600 0x0e -#define BRG_14400 0x0f -#define BRG_19200 0x10 -#define BRG_28200 0x11 -#define BRG_38400 0x12 -#define BRG_57600 0x13 -#define BRG_115200 0x14 -#define BRG_230400 0x15 -#define BRG_GIN0 0x16 -#define BRG_GIN1 0x17 -#define BRG_CT0 0x18 -#define BRG_CT1 0x19 -#define BRG_RX2TX316 0x1b -#define BRG_RX2TX31 0x1c - -/*****************************************************************************/ - -/* - * Command register command definitions. - */ -#define CR_NULL 0x04 -#define CR_ADDRNORMAL 0x0c -#define CR_RXRESET 0x14 -#define CR_TXRESET 0x1c -#define CR_CLEARRXERR 0x24 -#define CR_BREAKRESET 0x2c -#define CR_TXSTARTBREAK 0x34 -#define CR_TXSTOPBREAK 0x3c -#define CR_RTSON 0x44 -#define CR_RTSOFF 0x4c -#define CR_ADDRINIT 0x5c -#define CR_RXERRBLOCK 0x6c -#define CR_TXSENDXON 0x84 -#define CR_TXSENDXOFF 0x8c -#define CR_GANGXONSET 0x94 -#define CR_GANGXOFFSET 0x9c -#define CR_GANGXONINIT 0xa4 -#define CR_GANGXOFFINIT 0xac -#define CR_HOSTXON 0xb4 -#define CR_HOSTXOFF 0xbc -#define CR_CANCELXOFF 0xc4 -#define CR_ADDRRESET 0xdc -#define CR_RESETALLPORTS 0xf4 -#define CR_RESETALL 0xfc - -#define CR_RXENABLE 0x01 -#define CR_TXENABLE 0x02 - -/*****************************************************************************/ - -/* - * Channel status register. - */ -#define SR_RXRDY 0x01 -#define SR_RXFULL 0x02 -#define SR_TXRDY 0x04 -#define SR_TXEMPTY 0x08 -#define SR_RXOVERRUN 0x10 -#define SR_RXPARITY 0x20 -#define SR_RXFRAMING 0x40 -#define SR_RXBREAK 0x80 - -#define SR_RXERRS (SR_RXPARITY | SR_RXFRAMING | SR_RXOVERRUN) - -/*****************************************************************************/ - -/* - * Interrupt status register and interrupt mask register bit definitions. - */ -#define IR_TXRDY 0x01 -#define IR_RXRDY 0x02 -#define IR_RXBREAK 0x04 -#define IR_XONXOFF 0x10 -#define IR_ADDRRECOG 0x20 -#define IR_RXWATCHDOG 0x40 -#define IR_IOPORT 0x80 - -/*****************************************************************************/ - -/* - * Interrupt vector register field definitions. - */ -#define IVR_CHANMASK 0x07 -#define IVR_TYPEMASK 0x18 -#define IVR_CONSTMASK 0xc0 - -#define IVR_RXDATA 0x10 -#define IVR_RXBADDATA 0x18 -#define IVR_TXDATA 0x08 -#define IVR_OTHER 0x00 - -/*****************************************************************************/ - -/* - * BRG timer control register bit definitions. - */ -#define BRGCTCR_DISABCLK0 0x00 -#define BRGCTCR_ENABCLK0 0x08 -#define BRGCTCR_DISABCLK1 0x00 -#define BRGCTCR_ENABCLK1 0x80 - -#define BRGCTCR_0SCLK16 0x00 -#define BRGCTCR_0SCLK32 0x01 -#define BRGCTCR_0SCLK64 0x02 -#define BRGCTCR_0SCLK128 0x03 -#define BRGCTCR_0X1 0x04 -#define BRGCTCR_0X12 0x05 -#define BRGCTCR_0IO1A 0x06 -#define BRGCTCR_0GIN0 0x07 - -#define BRGCTCR_1SCLK16 0x00 -#define BRGCTCR_1SCLK32 0x10 -#define BRGCTCR_1SCLK64 0x20 -#define BRGCTCR_1SCLK128 0x30 -#define BRGCTCR_1X1 0x40 -#define BRGCTCR_1X12 0x50 -#define BRGCTCR_1IO1B 0x60 -#define BRGCTCR_1GIN1 0x70 - -/*****************************************************************************/ - -/* - * Watch dog timer enable register. - */ -#define WDTRCR_ENABALL 0xff - -/*****************************************************************************/ - -/* - * XON/XOFF interrupt status register. - */ -#define XISR_TXCHARMASK 0x03 -#define XISR_TXCHARNORMAL 0x00 -#define XISR_TXWAIT 0x01 -#define XISR_TXXOFFPEND 0x02 -#define XISR_TXXONPEND 0x03 - -#define XISR_TXFLOWMASK 0x0c -#define XISR_TXNORMAL 0x00 -#define XISR_TXSTOPPEND 0x04 -#define XISR_TXSTARTED 0x08 -#define XISR_TXSTOPPED 0x0c - -#define XISR_RXFLOWMASK 0x30 -#define XISR_RXFLOWNONE 0x00 -#define XISR_RXXONSENT 0x10 -#define XISR_RXXOFFSENT 0x20 - -#define XISR_RXXONGOT 0x40 -#define XISR_RXXOFFGOT 0x80 - -/*****************************************************************************/ - -/* - * Current interrupt register. - */ -#define CIR_TYPEMASK 0xc0 -#define CIR_TYPEOTHER 0x00 -#define CIR_TYPETX 0x40 -#define CIR_TYPERXGOOD 0x80 -#define CIR_TYPERXBAD 0xc0 - -#define CIR_RXDATA 0x80 -#define CIR_RXBADDATA 0x40 -#define CIR_TXDATA 0x40 - -#define CIR_CHANMASK 0x07 -#define CIR_CNTMASK 0x38 - -#define CIR_SUBTYPEMASK 0x38 -#define CIR_SUBNONE 0x00 -#define CIR_SUBCOS 0x08 -#define CIR_SUBADDR 0x10 -#define CIR_SUBXONXOFF 0x18 -#define CIR_SUBBREAK 0x28 - -/*****************************************************************************/ - -/* - * Global interrupting channel register. - */ -#define GICR_CHANMASK 0x07 - -/*****************************************************************************/ - -/* - * Global interrupting byte count register. - */ -#define GICR_COUNTMASK 0x0f - -/*****************************************************************************/ - -/* - * Global interrupting type register. - */ -#define GITR_RXMASK 0xc0 -#define GITR_RXNONE 0x00 -#define GITR_RXBADDATA 0x80 -#define GITR_RXGOODDATA 0xc0 -#define GITR_TXDATA 0x20 - -#define GITR_SUBTYPEMASK 0x07 -#define GITR_SUBNONE 0x00 -#define GITR_SUBCOS 0x01 -#define GITR_SUBADDR 0x02 -#define GITR_SUBXONXOFF 0x03 -#define GITR_SUBBREAK 0x05 - -/*****************************************************************************/ - -/* - * Input port change register. - */ -#define IPR_CTS 0x01 -#define IPR_DTR 0x02 -#define IPR_RTS 0x04 -#define IPR_DCD 0x08 -#define IPR_CTSCHANGE 0x10 -#define IPR_DTRCHANGE 0x20 -#define IPR_RTSCHANGE 0x40 -#define IPR_DCDCHANGE 0x80 - -#define IPR_CHANGEMASK 0xf0 - -/*****************************************************************************/ - -/* - * IO port interrupt and output register. - */ -#define IOPR_CTS 0x01 -#define IOPR_DTR 0x02 -#define IOPR_RTS 0x04 -#define IOPR_DCD 0x08 -#define IOPR_CTSCOS 0x10 -#define IOPR_DTRCOS 0x20 -#define IOPR_RTSCOS 0x40 -#define IOPR_DCDCOS 0x80 - -/*****************************************************************************/ - -/* - * IO port configuration register. - */ -#define IOPCR_SETCTS 0x00 -#define IOPCR_SETDTR 0x04 -#define IOPCR_SETRTS 0x10 -#define IOPCR_SETDCD 0x00 - -#define IOPCR_SETSIGS (IOPCR_SETRTS | IOPCR_SETRTS | IOPCR_SETDTR | IOPCR_SETDCD) - -/*****************************************************************************/ - -/* - * General purpose output select register. - */ -#define GPORS_TXC1XA 0x08 -#define GPORS_TXC16XA 0x09 -#define GPORS_RXC16XA 0x0a -#define GPORS_TXC16XB 0x0b -#define GPORS_GPOR3 0x0c -#define GPORS_GPOR2 0x0d -#define GPORS_GPOR1 0x0e -#define GPORS_GPOR0 0x0f - -/*****************************************************************************/ - -/* - * General purpose output register. - */ -#define GPOR_0 0x01 -#define GPOR_1 0x02 -#define GPOR_2 0x04 -#define GPOR_3 0x08 - -/*****************************************************************************/ - -/* - * General purpose output clock register. - */ -#define GPORC_0NONE 0x00 -#define GPORC_0GIN0 0x01 -#define GPORC_0GIN1 0x02 -#define GPORC_0IO3A 0x02 - -#define GPORC_1NONE 0x00 -#define GPORC_1GIN0 0x04 -#define GPORC_1GIN1 0x08 -#define GPORC_1IO3C 0x0c - -#define GPORC_2NONE 0x00 -#define GPORC_2GIN0 0x10 -#define GPORC_2GIN1 0x20 -#define GPORC_2IO3E 0x20 - -#define GPORC_3NONE 0x00 -#define GPORC_3GIN0 0x40 -#define GPORC_3GIN1 0x80 -#define GPORC_3IO3G 0xc0 - -/*****************************************************************************/ - -/* - * General purpose output data register. - */ -#define GPOD_0MASK 0x03 -#define GPOD_0SET1 0x00 -#define GPOD_0SET0 0x01 -#define GPOD_0SETR0 0x02 -#define GPOD_0SETIO3B 0x03 - -#define GPOD_1MASK 0x0c -#define GPOD_1SET1 0x00 -#define GPOD_1SET0 0x04 -#define GPOD_1SETR0 0x08 -#define GPOD_1SETIO3D 0x0c - -#define GPOD_2MASK 0x30 -#define GPOD_2SET1 0x00 -#define GPOD_2SET0 0x10 -#define GPOD_2SETR0 0x20 -#define GPOD_2SETIO3F 0x30 - -#define GPOD_3MASK 0xc0 -#define GPOD_3SET1 0x00 -#define GPOD_3SET0 0x40 -#define GPOD_3SETR0 0x80 -#define GPOD_3SETIO3H 0xc0 - -/*****************************************************************************/ -#endif diff --git a/sys/platform/pc64/isa/ic/cd1400.h b/sys/platform/pc64/isa/ic/cd1400.h deleted file mode 100644 index ffa7236a55..0000000000 --- a/sys/platform/pc64/isa/ic/cd1400.h +++ /dev/null @@ -1,204 +0,0 @@ -/*- - * cyclades cyclom-y serial driver - * Andrew Herbert , 17 August 1993 - * - * Copyright (c) 1993 Andrew Herbert. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name Andrew Herbert may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/cd1400.h,v 1.6 1999/08/28 00:45:12 peter Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ic/cd1400.h,v 1.1 2008/08/29 17:07:21 dillon Exp $ - */ - -/* - * Definitions for Cirrus Logic CD1400 serial/parallel chips. - */ - -#define CD1400_NO_OF_CHANNELS 4 /* 4 serial channels per chip */ -#define CD1400_RX_FIFO_SIZE 12 -#define CD1400_TX_FIFO_SIZE 12 - -/* - * Global registers. - */ -#define CD1400_GFRCR 0x40 /* global firmware revision code */ -#define CD1400_CAR 0x68 /* channel access */ -#define CD1400_CAR_CHAN (3<<0) /* channel select */ -#define CD1400_GCR 0x4B /* global configuration */ -#define CD1400_GCR_PARALLEL (1<<7) /* channel 0 is parallel */ -#define CD1400_SVRR 0x67 /* service request */ -#define CD1400_SVRR_MDMCH (1<<2) -#define CD1400_SVRR_TXRDY (1<<1) -#define CD1400_SVRR_RXRDY (1<<0) -#define CD1400_RICR 0x44 /* receive interrupting channel */ -#define CD1400_TICR 0x45 /* transmit interrupting channel */ -#define CD1400_MICR 0x46 /* modem interrupting channel */ -#define CD1400_RIR 0x6B /* receive interrupt status */ -#define CD1400_RIR_RDIREQ (1<<7) /* rx service required */ -#define CD1400_RIR_RBUSY (1<<6) /* rx service in progress */ -#define CD1400_RIR_CHAN (3<<0) /* channel select */ -#define CD1400_TIR 0x6A /* transmit interrupt status */ -#define CD1400_TIR_RDIREQ (1<<7) /* tx service required */ -#define CD1400_TIR_RBUSY (1<<6) /* tx service in progress */ -#define CD1400_TIR_CHAN (3<<0) /* channel select */ -#define CD1400_MIR 0x69 /* modem interrupt status */ -#define CD1400_MIR_RDIREQ (1<<7) /* modem service required */ -#define CD1400_MIR_RBUSY (1<<6) /* modem service in progress */ -#define CD1400_MIR_CHAN (3<<0) /* channel select */ -#define CD1400_PPR 0x7E /* prescaler period */ -#define CD1400_PPR_PRESCALER 512 - -/* - * Virtual registers. - */ -#define CD1400_RIVR 0x43 /* receive interrupt vector */ -#define CD1400_RIVR_EXCEPTION (1<<2) /* receive exception bit */ -#define CD1400_TIVR 0x42 /* transmit interrupt vector */ -#define CD1400_MIVR 0x41 /* modem interrupt vector */ -#define CD1400_TDR 0x63 /* transmit data */ -#define CD1400_RDSR 0x62 /* receive data/status */ -#define CD1400_RDSR_TIMEOUT (1<<7) /* rx timeout */ -#define CD1400_RDSR_SPECIAL_SHIFT 4 /* rx special char shift */ -#define CD1400_RDSR_SPECIAL (7<<4) /* rx special char */ -#define CD1400_RDSR_BREAK (1<<3) /* rx break */ -#define CD1400_RDSR_PE (1<<2) /* rx parity error */ -#define CD1400_RDSR_FE (1<<1) /* rx framing error */ -#define CD1400_RDSR_OE (1<<0) /* rx overrun error */ -#define CD1400_MISR 0x4C /* modem interrupt status */ -#define CD1400_MISR_DSRd (1<<7) /* DSR delta */ -#define CD1400_MISR_CTSd (1<<6) /* CTS delta */ -#define CD1400_MISR_RId (1<<5) /* RI delta */ -#define CD1400_MISR_CDd (1<<4) /* CD delta */ -#define CD1400_EOSRR 0x60 /* end of service request */ - -/* - * Channel registers. - */ -#define CD1400_LIVR 0x18 /* local interrupt vector */ -#define CD1400_CCR 0x05 /* channel control */ -#define CD1400_CCR_CMDRESET (1<<7) /* enables following: */ -#define CD1400_CCR_FTF (1<<1) /* flush tx fifo */ -#define CD1400_CCR_FULLRESET (1<<0) /* full reset */ -#define CD1400_CCR_CHANRESET 0 /* current channel */ -#define CD1400_CCR_CMDCORCHG (1<<6) /* enables following: */ -#define CD1400_CCR_COR3 (1<<3) /* COR3 changed */ -#define CD1400_CCR_COR2 (1<<2) /* COR2 changed */ -#define CD1400_CCR_COR1 (1<<1) /* COR1 changed */ -#define CD1400_CCR_CMDSENDSC (1<<5) /* enables following: */ -#define CD1400_CCR_SC (7<<0) /* special char 1-4 */ -#define CD1400_CCR_CMDCHANCTL (1<<4) /* enables following: */ -#define CD1400_CCR_XMTEN (1<<3) /* tx enable */ -#define CD1400_CCR_XMTDIS (1<<2) /* tx disable */ -#define CD1400_CCR_RCVEN (1<<1) /* rx enable */ -#define CD1400_CCR_RCVDIS (1<<0) /* rx disable */ -#define CD1400_SRER 0x06 /* service request enable */ -#define CD1400_SRER_MDMCH (1<<7) /* modem change */ -#define CD1400_SRER_RXDATA (1<<4) /* rx data */ -#define CD1400_SRER_TXRDY (1<<2) /* tx fifo empty */ -#define CD1400_SRER_TXMPTY (1<<1) /* tx shift reg empty */ -#define CD1400_SRER_NNDT (1<<0) /* no new data */ -#define CD1400_COR1 0x08 /* channel option 1 */ -#define CD1400_COR1_PARODD (1<<7) -#define CD1400_COR1_PARNORMAL (2<<5) -#define CD1400_COR1_PARFORCE (1<<5) /* odd/even = force 1/0 */ -#define CD1400_COR1_PARNONE (0<<5) -#define CD1400_COR1_NOINPCK (1<<4) -#define CD1400_COR1_STOP2 (2<<2) -#define CD1400_COR1_STOP15 (1<<2) /* 1.5 stop bits */ -#define CD1400_COR1_STOP1 (0<<2) -#define CD1400_COR1_CS8 (3<<0) -#define CD1400_COR1_CS7 (2<<0) -#define CD1400_COR1_CS6 (1<<0) -#define CD1400_COR1_CS5 (0<<0) -#define CD1400_COR2 0x09 /* channel option 2 */ -#define CD1400_COR2_IXANY (1<<7) /* implied XON mode */ -#define CD1400_COR2_IXOFF (1<<6) /* in-band tx flow control */ -#define CD1400_COR2_ETC (1<<5) /* embedded tx command */ -#define CD1400_ETC_CMD 0x00 /* start an ETC */ -#define CD1400_ETC_SENDBREAK 0x81 -#define CD1400_ETC_INSERTDELAY 0x82 -#define CD1400_ETC_STOPBREAK 0x83 -#define CD1400_COR2_LLM (1<<4) /* local loopback mode */ -#define CD1400_COR2_RLM (1<<3) /* remote loopback mode */ -#define CD1400_COR2_RTSAO (1<<2) /* RTS auto output */ -#define CD1400_COR2_CCTS_OFLOW (1<<1) /* CTS auto enable */ -#define CD1400_COR2_CDSR_OFLOW (1<<0) /* DSR auto enable */ -#define CD1400_COR3 0x0A /* channel option 3 */ -#define CD1400_COR3_SCDRNG (1<<7) /* special char detect range */ -#define CD1400_COR3_SCD34 (1<<6) /* special char detect 3-4 */ -#define CD1400_COR3_FTC (1<<5) /* flow control transparency */ -#define CD1400_COR3_SCD12 (1<<4) /* special char detect 1-2 */ -#define CD1400_COR3_RXTH (15<<0) /* rx fifo threshold */ -#define CD1400_COR4 0x1E /* channel option 4 */ -#define CD1400_COR4_IGNCR (1<<7) -#define CD1400_COR4_ICRNL (1<<6) -#define CD1400_COR4_INLCR (1<<5) -#define CD1400_COR4_IGNBRK (1<<4) -#define CD1400_COR4_NOBRKINT (1<<3) -#define CD1400_COR4_PFO_ESC (4<<0) /* parity/framing/overrun... */ -#define CD1400_COR4_PFO_NUL (3<<0) -#define CD1400_COR4_PFO_DISCARD (2<<0) -#define CD1400_COR4_PFO_GOOD (1<<0) -#define CD1400_COR4_PFO_EXCEPTION (0<<0) -#define CD1400_COR5 0x1F /* channel option 5 */ -#define CD1400_COR5_ISTRIP (1<<7) -#define CD1400_COR5_LNEXT (1<<6) -#define CD1400_COR5_CMOE (1<<5) /* char matching on error */ -#define CD1400_COR5_EBD (1<<2) /* end of break detected */ -#define CD1400_COR5_ONLCR (1<<1) -#define CD1400_COR5_OCRNL (1<<0) -#define CD1400_CCSR 0x0B /* channel control status */ -#define CD1400_RDCR 0x0E /* received data count */ -#define CD1400_SCHR1 0x1A /* special character 1 */ -#define CD1400_SCHR2 0x1B /* special character 2 */ -#define CD1400_SCHR3 0x1C /* special character 3 */ -#define CD1400_SCHR4 0x1D /* special character 4 */ -#define CD1400_SCRL 0x22 /* special character range, low */ -#define CD1400_SCRH 0x23 /* special character range, high */ -#define CD1400_LNC 0x24 /* lnext character */ -#define CD1400_MCOR1 0x15 /* modem change option 1 */ -#define CD1400_MCOR1_DSRzd (1<<7) /* DSR one-to-zero delta */ -#define CD1400_MCOR1_CTSzd (1<<6) -#define CD1400_MCOR1_RIzd (1<<5) -#define CD1400_MCOR1_CDzd (1<<4) -#define CD1400_MCOR1_DTRth (15<<0) /* dtrflow threshold */ -#define CD1400_MCOR2 0x16 /* modem change option 2 */ -#define CD1400_MCOR2_DSRod (1<<7) /* DSR zero-to-one delta */ -#define CD1400_MCOR2_CTSod (1<<6) -#define CD1400_MCOR2_RIod (1<<5) -#define CD1400_MCOR2_CDod (1<<4) -#define CD1400_RTPR 0x21 /* receive timeout period */ -#define CD1400_MSVR1 0x6C /* modem signal value 1 */ -#define CD1400_MSVR1_RTS (1<<0) /* RTS line (r/w) */ -#define CD1400_MSVR2 0x6D /* modem signal value 2 */ -#define CD1400_MSVR2_DSR (1<<7) /* !DSR line (r) */ -#define CD1400_MSVR2_CTS (1<<6) /* !CTS line (r) */ -#define CD1400_MSVR2_RI (1<<5) /* !RI line (r) */ -#define CD1400_MSVR2_CD (1<<4) /* !CD line (r) */ -#define CD1400_MSVR2_DTR (1<<1) /* DTR line (r/w) */ -#define CD1400_PSVR 0x6F /* printer signal value */ -#define CD1400_RBPR 0x78 /* receive baud rate period */ -#define CD1400_RCOR 0x7C /* receive clock option */ -#define CD1400_TBPR 0x72 /* transmit baud rate period */ -#define CD1400_TCOR 0x76 /* transmit clock option */ diff --git a/sys/platform/pc64/isa/ic/mb86960.h b/sys/platform/pc64/isa/ic/mb86960.h deleted file mode 100644 index 6f7cb0ce84..0000000000 --- a/sys/platform/pc64/isa/ic/mb86960.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 - * - * This software may be used, modified, copied, distributed, and sold, in - * both source and binary form provided that the above copyright, these - * terms and the following disclaimer are retained. The name of the author - * and/or the contributor may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/mb86960.h,v 1.2.8.1 2000/08/03 01:01:25 peter Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ic/mb86960.h,v 1.1 2008/08/29 17:07:21 dillon Exp $ - */ - -/* - * Registers of Fujitsu MB86960A/MB86965A series Ethernet controllers. - * Written and contributed by M.S. - */ - -/* - * Notes on register naming: - * - * Fujitsu documents for MB86960A/MB86965A uses no mnemorable names - * for their registers. They defined only three names for 32 - * registers and appended numbers to distinguish registers of - * same name. Surprisingly, the numbers represent I/O address - * offsets of the registers from the base addresses, and their - * names correspond to the "bank" the registers are allocated. - * All this means that, for example, to say "read DLCR8" has no more - * than to say "read a register at offset 8 on bank DLCR." - * - * The following definitions may look silly, but that's what Fujitsu - * did, and it is necessary to know these names to read Fujitsu - * documents.. - */ - -/* Data Link Control Registrs, on invaliant port addresses. */ -#define FE_DLCR0 0 -#define FE_DLCR1 1 -#define FE_DLCR2 2 -#define FE_DLCR3 3 -#define FE_DLCR4 4 -#define FE_DLCR5 5 -#define FE_DLCR6 6 -#define FE_DLCR7 7 - -/* More DLCRs, on register bank #0. */ -#define FE_DLCR8 8 -#define FE_DLCR9 9 -#define FE_DLCR10 10 -#define FE_DLCR11 11 -#define FE_DLCR12 12 -#define FE_DLCR13 13 -#define FE_DLCR14 14 -#define FE_DLCR15 15 - -/* Malticast Address Registers. On register bank #1. */ -#define FE_MAR8 8 -#define FE_MAR9 9 -#define FE_MAR10 10 -#define FE_MAR11 11 -#define FE_MAR12 12 -#define FE_MAR13 13 -#define FE_MAR14 14 -#define FE_MAR15 15 - -/* Buffer Memory Port Registers. On register back #2. */ -#define FE_BMPR8 8 -#define FE_BMPR9 9 -#define FE_BMPR10 10 -#define FE_BMPR11 11 -#define FE_BMPR12 12 -#define FE_BMPR13 13 -#define FE_BMPR14 14 -#define FE_BMPR15 15 - -/* More BMPRs, only on 86965, accessible only when JLI mode. */ -#define FE_BMPR16 16 -#define FE_BMPR17 17 -#define FE_BMPR18 18 -#define FE_BMPR19 19 - -/* - * Definitions of registers. - * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't - * know the official names for each flags and fields. The following - * names are assigned by me (the author of this file,) since I cannot - * mnemorize hexadecimal constants for all of these functions. - * Comments? - * - * I've got documents from Fujitsu web site, recently. However, it's - * too late. Names for some fields (bits) are kept different from - * those used in the Fujitsu documents... - */ - -/* DLCR0 -- transmitter status */ -#define FE_D0_BUSERR 0x01 /* Bus write error? */ -#define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */ -#define FE_D0_COLLID 0x04 /* Collision on last transmission */ -#define FE_D0_JABBER 0x08 /* Jabber */ -#define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */ -#define FE_D0_PKTRCD 0x20 /* Last packet looped back correctly */ -#define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */ -#define FE_D0_TXDONE 0x80 /* Transmission complete */ - -/* DLCR1 -- receiver status */ -#define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */ -#define FE_D1_CRCERR 0x02 /* CRC error on last packet */ -#define FE_D1_ALGERR 0x04 /* Alignment error on last packet */ -#define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */ -#define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */ -#define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */ -#define FE_D1_BUSERR 0x40 /* Bus read error */ -#define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */ - -/* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */ -#define FE_D2_BUSERR FE_D0_BUSERR -#define FE_D2_COLL16 FE_D0_COLL16 -#define FE_D2_COLLID FE_D0_COLLID -#define FE_D2_JABBER FE_D0_JABBER -#define FE_D2_TXDONE FE_D0_TXDONE - -#define FE_D2_RESERVED 0x70 - -/* DLCR3 -- receiver interrupt control; same layout as DLCR1 */ -#define FE_D3_OVRFLO FE_D1_OVRFLO -#define FE_D3_CRCERR FE_D1_CRCERR -#define FE_D3_ALGERR FE_D1_ALGERR -#define FE_D3_SRTPKT FE_D1_SRTPKT -#define FE_D3_RMTRST FE_D1_RMTRST -#define FE_D3_DMAEOP FE_D1_DMAEOP -#define FE_D3_BUSERR FE_D1_BUSERR -#define FE_D3_PKTRDY FE_D1_PKTRDY - -/* DLCR4 -- transmitter operation mode */ -#define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */ -#define FE_D4_LBC 0x02 /* Loop back test control */ -#define FE_D4_CNTRL 0x04 /* - tied to CNTRL pin of the chip */ -#define FE_D4_TEST1 0x08 /* Test output #1 */ -#define FE_D4_COL 0xF0 /* Collision counter */ - -#define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */ -#define FE_D4_LBC_DISABLE 0x02 /* Normal operation */ - -#define FE_D4_COL_SHIFT 4 - -/* DLCR5 -- receiver operation mode */ -#define FE_D5_AFM0 0x01 /* Receive packets for other stations */ -#define FE_D5_AFM1 0x02 /* Receive packets for this station */ -#define FE_D5_RMTRST 0x04 /* Enable remote reset operation */ -#define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */ -#define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */ -#define FE_D5_BADPKT 0x20 /* Accept packets with error */ -#define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */ -#define FE_D5_TEST2 0x80 /* Test output #2 */ - -/* DLCR6 -- hardware configuration #0 */ -#define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */ -#define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */ -#define FE_D6_BBW 0x10 /* Buffer SRAM bus width */ -#define FE_D6_SBW 0x20 /* System bus width */ -#define FE_D6_SRAM 0x40 /* Buffer SRAM access time */ -#define FE_D6_DLC 0x80 /* Disable DLC (recever/transmitter) */ - -#define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */ -#define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */ -#define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */ -#define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */ - -#define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */ -#define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */ -#define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */ -#define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */ - -#define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */ -#define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */ - -#define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */ -#define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */ - -#define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */ -#define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */ - -#define FE_D6_DLC_ENABLE 0x00 /* Normal operation */ -#define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */ - -/* DLC7 -- hardware configuration #1 */ -#define FE_D7_BYTSWP 0x01 /* Host byte order control */ -#define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */ -#define FE_D7_RBS 0x0C /* Register bank select */ -#define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */ -#define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */ -#define FE_D7_IDENT 0xC0 /* Chip identification */ - -#define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */ -#define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */ - -#define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */ -#define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */ -#define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */ - -#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */ -#define FE_D7_POWER_UP 0x20 /* Normal operation */ - -#define FE_D7_IDENT_TDK 0x00 /* TDK chips? */ -#define FE_D7_IDENT_NICE 0x80 /* Fujitsu NICE (86960) */ -#define FE_D7_IDENT_EC 0xC0 /* Fujitsu EtherCoupler (86965) */ - -/* DLCR8 thru DLCR13 are for Ethernet station address. */ - -/* DLCR14 and DLCR15 are for TDR. (TDR is used for cable diagnostic.) */ - -/* MAR8 thru MAR15 are for Multicast address filter. */ - -/* BMPR8 and BMPR9 are for packet data. */ - -/* BMPR10 -- transmitter start trigger */ -#define FE_B10_START 0x80 /* Start transmitter */ -#define FE_B10_COUNT 0x7F /* Packet count */ - -/* BMPR11 -- 16 collisions control */ -#define FE_B11_CTRL 0x01 /* Skip or resend errored packets */ -#define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */ -#define FE_B11_MODE2 0x04 /* Automatic restart enable */ - -#define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */ -#define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */ - -/* BMPR12 -- DMA enable */ -#define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */ -#define FE_B12_RXDMA 0x02 /* Enable receiver DMA */ - -/* BMPR13 -- DMA control */ -#define FE_B13_BSTCTL 0x03 /* DMA burst mode control */ -#define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */ -#define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */ -#define FE_B13_LNKTST 0x20 /* Link test enable */ -#define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */ -#define FE_B13_IOUNLK 0x80 /* Change I/O base address, on JLI mode */ - -#define FE_B13_BSTCTL_1 0x00 -#define FE_B13_BSTCTL_4 0x01 -#define FE_B13_BSTCTL_8 0x02 -#define FE_B13_BSTCLT_12 0x03 - -#define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */ -#define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */ - -#define FE_B13_PORT_AUTO 0x00 /* Auto detected */ -#define FE_B13_PORT_TP 0x08 /* Force TP */ -#define FE_B13_PORT_AUI 0x18 /* Force AUI */ - -/* BMPR14 -- More receiver control and more transmission interrupts */ -#define FE_B14_FILTER 0x01 /* Filter out self-originated packets */ -#define FE_B14_SQE 0x02 /* SQE interrupt enable */ -#define FE_B14_SKIP 0x04 /* Skip a received packet */ -#define FE_B14_RJAB 0x20 /* RJAB interrupt enable */ -#define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */ -#define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */ - -/* BMPR15 -- More transmitter status; basically same layout as BMPR14 */ -#define FE_B15_SQE FE_B14_SQE -#define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */ -#define FE_B15_RMTPRT 0x10 /* ??? */ -#define FE_B15_RAJB FE_B14_RJAB -#define FE_B15_LLD FE_B14_LLD -#define FE_B15_RLD FE_B14_RLD - -/* BMPR16 -- EEPROM control */ -#define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */ -#define FE_B16_SELECT 0x20 /* EEPROM chip select */ -#define FE_B16_CLOCK 0x40 /* EEPROM shift clock */ -#define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */ - -/* BMPR17 -- EEPROM data */ -#define FE_B17_DATA 0x80 /* EEPROM data bit */ - -/* BMPR18 -- cycle I/O address setting in JLI mode */ - -/* BMPR19 -- ISA interface configuration in JLI mode */ -#define FE_B19_IRQ 0xC0 -#define FE_B19_IRQ_SHIFT 6 - -#define FE_B19_ROM 0x38 -#define FE_B19_ROM_SHIFT 3 - -#define FE_B19_ADDR 0x07 -#define FE_B19_ADDR_SHIFT 0 - -/* - * An extra I/O port address to reset 86965. This location is called - * "ID ROM area" by Fujitsu document. - */ - -/* - * Flags in Receive Packet Header... Basically same layout as DLCR1. - */ -#define FE_RPH_OVRFLO FE_D1_OVRFLO -#define FE_RPH_CRCERR FE_D1_CRCERR -#define FE_RPH_ALGERR FE_D1_ALGERR -#define FE_RPH_SRTPKT FE_D1_SRTPKT -#define FE_RPH_RMTRST FE_D1_RMTRST -#define FE_RPH_GOOD 0x20 /* Good packet follows */ - -/* - * EEPROM specification (of JLI mode). - */ - -/* Number of bytes in an EEPROM accessible through 86965. */ -#define FE_EEPROM_SIZE 32 - -/* Offset for JLI config; automatically copied into BMPR19 at startup. */ -#define FE_EEPROM_CONF 0 - -/* - * Some 8696x specific constants. - */ - -/* Length (in bytes) of a Multicast Address Filter. */ -#define FE_FILTER_LEN 8 - -/* How many packets we can put in the transmission buffer on NIC memory. */ -#define FE_QUEUEING_MAX 127 - -/* Length (in bytes) of a "packet length" word in transmission buffer. */ -#define FE_DATA_LEN_LEN 2 - -/* Special Multicast Address Filter value. */ -#define FE_FILTER_NOTHING { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } -#define FE_FILTER_ALL { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF } diff --git a/sys/platform/pc64/isa/ic/scd1400.h b/sys/platform/pc64/isa/ic/scd1400.h deleted file mode 100644 index 3517fbf201..0000000000 --- a/sys/platform/pc64/isa/ic/scd1400.h +++ /dev/null @@ -1,313 +0,0 @@ -/*****************************************************************************/ - -/* - * cd1400.h -- cd1400 UART hardware info. - * - * Copyright (c) 1995 Greg Ungerer (gerg@stallion.oz.au). - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Greg Ungerer. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/scd1400.h,v 1.5 1999/08/28 00:45:15 peter Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ic/scd1400.h,v 1.1 2008/08/29 17:07:21 dillon Exp $ - */ - -/*****************************************************************************/ -#ifndef _CD1400_H -#define _CD1400_H -/*****************************************************************************/ - -/* - * Define the number of async ports per cd1400 uart chip. - */ -#define CD1400_PORTS 4 - -/* - * Define the cd1400 uarts internal FIFO sizes. - */ -#define CD1400_TXFIFOSIZE 12 -#define CD1400_RXFIFOSIZE 12 - -/* - * Local RX FIFO thresh hold level. Also define the RTS thresh hold - * based on the RX thresh hold. - */ -#define FIFO_RXTHRESHOLD 6 -#define FIFO_RTSTHRESHOLD 7 - -/*****************************************************************************/ - -/* - * Define the cd1400 register addresses. These are all the valid - * registers with the cd1400. Some are global, some virtual, some - * per port. - */ -#define GFRCR 0x40 -#define CAR 0x68 -#define GCR 0x4b -#define SVRR 0x67 -#define RICR 0x44 -#define TICR 0x45 -#define MICR 0x46 -#define RIR 0x6b -#define TIR 0x6a -#define MIR 0x69 -#define PPR 0x7e - -#define RIVR 0x43 -#define TIVR 0x42 -#define MIVR 0x41 -#define TDR 0x63 -#define RDSR 0x62 -#define MISR 0x4c -#define EOSRR 0x60 - -#define LIVR 0x18 -#define CCR 0x05 -#define SRER 0x06 -#define COR1 0x08 -#define COR2 0x09 -#define COR3 0x0a -#define COR4 0x1e -#define COR5 0x1f -#define CCSR 0x0b -#define RDCR 0x0e -#define SCHR1 0x1a -#define SCHR2 0x1b -#define SCHR3 0x1c -#define SCHR4 0x1d -#define SCRL 0x22 -#define SCRH 0x23 -#define LNC 0x24 -#define MCOR1 0x15 -#define MCOR2 0x16 -#define RTPR 0x21 -#define MSVR1 0x6c -#define MSVR2 0x6d -#define PSVR 0x6f -#define RBPR 0x78 -#define RCOR 0x7c -#define TBPR 0x72 -#define TCOR 0x76 - -/*****************************************************************************/ - -/* - * Define the set of baud rate clock divisors. - */ -#define CD1400_CLK0 8 -#define CD1400_CLK1 32 -#define CD1400_CLK2 128 -#define CD1400_CLK3 512 -#define CD1400_CLK4 2048 - -#define CD1400_NUMCLKS 5 - -/*****************************************************************************/ - -/* - * Define the clock pre-scalar value to be a 5 ms clock. This should be - * OK for now. It would probably be better to make it 10 ms, but we - * can't fit that divisor into 8 bits! - */ -#define PPR_SCALAR 244 - -/*****************************************************************************/ - -/* - * Define values used to set character size options. - */ -#define COR1_CHL5 0x00 -#define COR1_CHL6 0x01 -#define COR1_CHL7 0x02 -#define COR1_CHL8 0x03 - -/* - * Define values used to set the number of stop bits. - */ -#define COR1_STOP1 0x00 -#define COR1_STOP15 0x04 -#define COR1_STOP2 0x08 - -/* - * Define values used to set the parity scheme in use. - */ -#define COR1_PARNONE 0x00 -#define COR1_PARFORCE 0x20 -#define COR1_PARENB 0x40 -#define COR1_PARIGNORE 0x10 - -#define COR1_PARODD 0x80 -#define COR1_PAREVEN 0x00 - -#define COR2_IXM 0x80 -#define COR2_TXIBE 0x40 -#define COR2_ETC 0x20 -#define COR2_LLM 0x10 -#define COR2_RLM 0x08 -#define COR2_RTSAO 0x04 -#define COR2_CTSAE 0x02 - -#define COR3_SCDRNG 0x80 -#define COR3_SCD34 0x40 -#define COR3_FCT 0x20 -#define COR3_SCD12 0x10 - -/* - * Define the bit values of COR4. - */ -#define COR4_BRKINT 0x08 -#define COR4_IGNBRK 0x18 - -/* - * Define the bit values of COR5. - */ -#define COR5_ISTRIP 0x80 - -/*****************************************************************************/ - -/* - * Define the modem control register values. - * Note that the actual hardware is a little different to the conventional - * pin names on the cd1400. - */ -#define MSVR1_DTR 0x01 -#define MSVR1_DSR 0x10 -#define MSVR1_RI 0x20 -#define MSVR1_CTS 0x40 -#define MSVR1_DCD 0x80 - -#define MSVR2_RTS 0x02 -#define MSVR2_DSR 0x10 -#define MSVR2_RI 0x20 -#define MSVR2_CTS 0x40 -#define MSVR2_DCD 0x80 - -#define MCOR1_DCD 0x80 -#define MCOR1_CTS 0x40 -#define MCOR1_RI 0x20 -#define MCOR1_DSR 0x10 - -#define MCOR2_DCD 0x80 -#define MCOR2_CTS 0x40 -#define MCOR2_RI 0x20 -#define MCOR2_DSR 0x10 - -/*****************************************************************************/ - -/* - * Define the bits used with the service (interrupt) enable register. - */ -#define SRER_NNDT 0x01 -#define SRER_TXEMPTY 0x02 -#define SRER_TXDATA 0x04 -#define SRER_RXDATA 0x10 -#define SRER_MODEM 0x80 - -/*****************************************************************************/ - -/* - * Define operational commands for the command register. - */ -#define CCR_RESET 0x80 -#define CCR_CORCHANGE 0x4e -#define CCR_SENDCH 0x20 -#define CCR_CHANCTRL 0x10 - -#define CCR_TXENABLE (CCR_CHANCTRL | 0x08) -#define CCR_TXDISABLE (CCR_CHANCTRL | 0x04) -#define CCR_RXENABLE (CCR_CHANCTRL | 0x02) -#define CCR_RXDISABLE (CCR_CHANCTRL | 0x01) - -#define CCR_SENDSCHR1 (CCR_SENDCH | 0x01) -#define CCR_SENDSCHR2 (CCR_SENDCH | 0x02) -#define CCR_SENDSCHR3 (CCR_SENDCH | 0x03) -#define CCR_SENDSCHR4 (CCR_SENDCH | 0x04) - -#define CCR_RESETCHAN (CCR_RESET | 0x00) -#define CCR_RESETFULL (CCR_RESET | 0x01) -#define CCR_TXFLUSHFIFO (CCR_RESET | 0x02) - -#define CCR_MAXWAIT 10000 - -/*****************************************************************************/ - -/* - * Define the valid acknowledgement types (for hw ack cycle). - */ -#define ACK_TYPMASK 0x07 -#define ACK_TYPTX 0x02 -#define ACK_TYPMDM 0x01 -#define ACK_TYPRXGOOD 0x03 -#define ACK_TYPRXBAD 0x07 - -#define SVRR_RX 0x01 -#define SVRR_TX 0x02 -#define SVRR_MDM 0x04 - -#define ST_OVERRUN 0x01 -#define ST_FRAMING 0x02 -#define ST_PARITY 0x04 -#define ST_BREAK 0x08 -#define ST_SCHAR1 0x10 -#define ST_SCHAR2 0x20 -#define ST_SCHAR3 0x30 -#define ST_SCHAR4 0x40 -#define ST_RANGE 0x70 -#define ST_SCHARMASK 0x70 -#define ST_TIMEOUT 0x80 - -#define MISR_DCD 0x80 -#define MISR_CTS 0x40 -#define MISR_RI 0x20 -#define MISR_DSR 0x10 - -/*****************************************************************************/ - -/* - * Defines for the CCSR status register. - */ -#define CCSR_RXENABLED 0x80 -#define CCSR_RXFLOWON 0x40 -#define CCSR_RXFLOWOFF 0x20 -#define CCSR_TXENABLED 0x08 -#define CCSR_TXFLOWON 0x04 -#define CCSR_TXFLOWOFF 0x02 - -/*****************************************************************************/ - -/* - * Define the embedded commands. - */ -#define ETC_CMD 0x00 -#define ETC_STARTBREAK 0x81 -#define ETC_DELAY 0x82 -#define ETC_STOPBREAK 0x83 - -/*****************************************************************************/ -#endif