From: Sepherosa Ziehau <sephe@dragonflybsd.org>
Date: Sat, 6 Oct 2012 15:03:22 +0000 (+0800)
Subject: igb: Cache align msix, rx and tx data
X-Git-Tag: v3.2.0~13
X-Git-Url: https://gitweb.dragonflybsd.org/dragonfly.git/commitdiff_plain/ff230ec8e08911c0ec9fcd292c2feaab0f7f1241

igb: Cache align msix, rx and tx data
---

diff --git a/sys/dev/netif/igb/if_igb.h b/sys/dev/netif/igb/if_igb.h
index 539f62352a..1e5c96da4e 100644
--- a/sys/dev/netif/igb/if_igb.h
+++ b/sys/dev/netif/igb/if_igb.h
@@ -237,7 +237,7 @@ struct igb_tx_ring {
 
 	u_long			no_desc_avail;
 	u_long			tx_packets;
-};
+} __cachealign;
 
 /*
  * Receive ring: one per queue
@@ -266,7 +266,7 @@ struct igb_rx_ring {
 
 	/* Soft stats */
 	u_long			rx_packets;
-};
+} __cachealign;
 
 struct igb_msix_data {
 	struct lwkt_serialize	*msix_serialize;
@@ -287,7 +287,7 @@ struct igb_msix_data {
 	u_int			msix_vector;
 	int			msix_rate;
 	char			msix_rate_desc[32];
-};
+} __cachealign;
 
 struct igb_softc {
 	struct arpcom		arpcom;