igb: Cache align msix, rx and tx data
[dragonfly.git] / sys / dev / netif / igb / if_igb.h
2012-10-06 Sepherosa Ziehauigb: Cache align msix, rx and tx data
2012-10-06 Sepherosa Ziehauigb: Change polling(4) support to ifpoll support
2012-10-01 John MarinoMerge branch 'vendor/GCC47'
2012-09-29 John MarinoMerge branch 'vendor/MPC'
2012-08-29 Sepherosa Ziehauigb: Set default RX descriptor count to 512
2012-08-14 Sepherosa Ziehauigb: Remove unused field
2012-08-02 Sepherosa Ziehauigb: Add TSO support
2012-07-11 Peter AvalosMerge branch 'vendor/OPENPAM'
2012-07-11 Peter AvalosMerge branch 'vendor/XZ'
2012-07-11 Peter AvalosMerge branch 'vendor/TNFTP'
2012-07-11 Peter AvalosMerge branch 'vendor/LIBARCHIVE'
2012-07-11 Peter AvalosMerge branch 'vendor/TCPDUMP'
2012-07-11 Peter AvalosMerge branch 'vendor/LIBPCAP'
2012-07-04 Peter AvalosMerge branch 'vendor/FILE'
2012-06-30 Sepherosa Ziehauigb: Reduce MSI/legacy interrupt rate limit to 6000
2012-06-30 Sepherosa Ziehauigb: Make sure EITR interval is within range
2012-06-30 Sepherosa Ziehauigb: Add MSI-X support
2012-06-16 Sepherosa Ziehauigb: Allow used RX rings less than allocated ones
2012-06-13 Sepherosa Ziehauigb: Enable multiple RX rings and integrate it w/ Drago...
2012-06-12 Sepherosa Ziehauigb: Split RX and TX serializer
2012-06-12 Sepherosa Ziehauigb: Move RX/TX descriptor count into ring struct
2012-06-12 Sepherosa Ziehauigb: Remove unused field
2012-06-11 Sepherosa Ziehauigb: Split RX/TX ring count
2012-06-04 Sepherosa Ziehauigb: Use extended interrupt mode whenever possible
2012-05-31 Sepherosa Ziehauigb: Optimize TX path
2012-05-20 Sepherosa Ziehauigb: Import Intel igb-2.2.3