From 47f0be7a9a496e817472be35d786fc8355265767 Mon Sep 17 00:00:00 2001 From: Sascha Wildner Date: Thu, 22 Dec 2011 23:15:21 +0100 Subject: [PATCH] kernel: Remove some more old headers. They all got useless with the recent ISA-only driver removal. --- sys/platform/pc32/isa/ic/am7990.h | 110 ---------- sys/platform/pc32/isa/ic/cd180.h | 199 ------------------ sys/platform/pc32/isa/ic/i82586.h | 332 ------------------------------ sys/platform/pc32/isa/ic/lemac.h | 178 ---------------- sys/platform/pc64/isa/ascreg.h | 98 --------- sys/platform/pc64/isa/ic/am7990.h | 110 ---------- sys/platform/pc64/isa/ic/cd180.h | 199 ------------------ sys/platform/pc64/isa/ic/i82586.h | 332 ------------------------------ sys/platform/pc64/isa/ic/lemac.h | 178 ---------------- 9 files changed, 1736 deletions(-) delete mode 100644 sys/platform/pc32/isa/ic/am7990.h delete mode 100644 sys/platform/pc32/isa/ic/cd180.h delete mode 100644 sys/platform/pc32/isa/ic/i82586.h delete mode 100644 sys/platform/pc32/isa/ic/lemac.h delete mode 100644 sys/platform/pc64/isa/ascreg.h delete mode 100644 sys/platform/pc64/isa/ic/am7990.h delete mode 100644 sys/platform/pc64/isa/ic/cd180.h delete mode 100644 sys/platform/pc64/isa/ic/i82586.h delete mode 100644 sys/platform/pc64/isa/ic/lemac.h diff --git a/sys/platform/pc32/isa/ic/am7990.h b/sys/platform/pc32/isa/ic/am7990.h deleted file mode 100644 index 2a97104bbb..0000000000 --- a/sys/platform/pc32/isa/ic/am7990.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * AMD 7990 (LANCE) definitions - * - * $FreeBSD: src/sys/i386/isa/ic/am7990.h,v 1.3.6.1 2000/08/03 01:01:25 peter Exp $ - * $DragonFly: src/sys/platform/pc32/isa/ic/am7990.h,v 1.2 2003/06/17 04:28:37 dillon Exp $ - */ - -#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN -#define LN_BITFIELD2(a, b) b, a -#define LN_BITFIELD3(a, b, c) c, b, a -#define LN_BITFIELD4(a, b, c, d) d, c, b, a -#else -#define LN_BITFIELD2(a, b) a, b -#define LN_BITFIELD3(a, b, c) a, b, c -#define LN_BITFIELD4(a, b, c, d) a, b, c, d -#endif - -#define LN_ADDR_LO(addr) ((addr) & 0xFFFF) -#define LN_ADDR_HI(addr) (((addr) >> 16) & 0xFF) - -typedef struct { - unsigned short r_addr_lo; - unsigned int LN_BITFIELD3(r_addr_hi : 8, - : 5, - r_log2_size : 3); -} ln_ring_t; - -#define LN_MC_MASK 0x3F /* Only 6 bits of the CRC */ - -typedef struct { - unsigned short ln_mode; -#define LN_MODE_RXD 0x0001 /* ( W) Receiver Disabled */ -#define LN_MODE_TXD 0x0002 /* ( W) Transmitter Disabled */ -#define LN_MODE_LOOP 0x0004 /* ( W) Enable Loopback */ -#define LN_MODE_NOTXCRC 0x0008 /* ( W) Don't Calculate TX CRCs */ -#define LN_MODE_FRCCOLL 0x0010 /* ( W) Force Collision */ -#define LN_MODE_NORETRY 0x0020 /* ( W) No Transmit Retries */ -#define LN_MODE_INTLOOP 0x0040 /* ( W) Internal Loopback */ -#define LN_MODE_PROMISC 0x8000 /* ( W) Promiscious Mode */ - unsigned short ln_physaddr[3]; - unsigned short ln_multi_mask[4]; - ln_ring_t ln_rxring; - ln_ring_t ln_txring; -} ln_initb_t; - -typedef struct { - unsigned short d_addr_lo; - unsigned char d_addr_hi; - unsigned char d_flag; -#define LN_DFLAG_EOP 0x0001 /* (RW) End Of Packet */ -#define LN_DFLAG_SOP 0x0002 /* (RW) Start Of Packet */ -#define LN_DFLAG_RxBUFERROR 0x0004 /* (R ) Receive - Buffer Error */ -#define LN_DFLAG_TxDEFERRED 0x0004 /* (R ) Transmit - Initially Deferred */ -#define LN_DFLAG_RxBADCRC 0x0008 /* (R ) Receive - Bad Checksum */ -#define LN_DFLAG_TxONECOLL 0x0008 /* (R ) Transmit - Single Collision */ -#define LN_DFLAG_RxOVERFLOW 0x0010 /* (R ) Receive - Overflow Error */ -#define LN_DFLAG_TxMULTCOLL 0x0010 /* (R ) Transmit - Multiple Collisions */ -#define LN_DFLAG_RxFRAMING 0x0020 /* (R ) Receive - Framing Error */ -#define LN_DFLAG_RxERRSUM 0x0040 /* (R ) Receive - Error Summary */ -#define LN_DFLAG_TxERRSUM 0x0040 /* (R ) Transmit - Error Summary */ -#define LN_DFLAG_OWNER 0x0080 /* (RW) Owner (1=Am7990, 0=host) */ - signed short d_buflen; /* ( W) Two's complement */ - unsigned short d_status; -#define LN_DSTS_RxLENMASK 0x0FFF /* (R ) Recieve Length */ -#define LN_DSTS_TxTDRMASK 0x03FF /* (R ) Transmit - Time Domain Reflectometer */ -#define LN_DSTS_TxEXCCOLL 0x0400 /* (R ) Transmit - Excessive Collisions */ -#define LN_DSTS_TxCARRLOSS 0x0800 /* (R ) Transmit - Carrier Loss */ -#define LN_DSTS_TxLATECOLL 0x1000 /* (R ) Transmit - Late Collision */ -#define LN_DSTS_TxUNDERFLOW 0x4000 /* (R ) Transmit - Underflow */ -#define LN_DSTS_TxBUFERROR 0x8000 /* (R ) Transmit - Buffer Error */ -} ln_desc_t; - - - - -#define LN_CSR0 0x0000 - -#define LN_CSR0_INIT 0x0001 /* (RS) Initialize Am 7990 */ -#define LN_CSR0_START 0x0002 /* (RS) Start Am7990 */ -#define LN_CSR0_STOP 0x0004 /* (RS) Reset Am7990 */ -#define LN_CSR0_TXDEMAND 0x0008 /* (RS) Transmit On Demand */ -#define LN_CSR0_TXON 0x0010 /* (R ) Transmitter Enabled */ -#define LN_CSR0_RXON 0x0020 /* (R ) Receiver Enabled */ -#define LN_CSR0_ENABINTR 0x0040 /* (RW) Interrupt Enabled */ -#define LN_CSR0_PENDINTR 0x0080 /* (R ) Interrupt Pending */ -#define LN_CSR0_INITDONE 0x0100 /* (RC) Initialization Done */ -#define LN_CSR0_TXINT 0x0200 /* (RC) Transmit Interrupt */ -#define LN_CSR0_RXINT 0x0400 /* (RC) Receive Interrupt */ -#define LN_CSR0_MEMERROR 0x0800 /* (RC) Memory Error */ -#define LN_CSR0_MISS 0x1000 /* (RC) No Available Receive Buffers */ -#define LN_CSR0_CERR 0x2000 /* (RC) SQE failed */ -#define LN_CSR0_BABL 0x4000 /* (RC) Transmit Babble */ -#define LN_CSR0_ERRSUM 0x8000 /* (R ) Error Summary (last 4) */ -#define LN_CSR0_CLEAR 0x7F00 /* Clear Status Bit */ - -/* - * CSR1 -- Init Block Address (Low 16 Bits -- Must be Word Aligned) - * CSR2 -- Init Block Address (High 8 Bits) - */ -#define LN_CSR1 0x0001 -#define LN_CSR2 0x0002 - -/* - * CSR3 -- Hardware Control - */ - -#define LN_CSR3 0x0003 -#define LN_CSR3_BCON 0x0001 /* (RW) BM/HOLD Control */ -#define LN_CSR3_ALE 0x0002 /* (RW) ALE Control */ -#define LN_CSR3_BSWP 0x0004 /* (RW) Byte Swap */ diff --git a/sys/platform/pc32/isa/ic/cd180.h b/sys/platform/pc32/isa/ic/cd180.h deleted file mode 100644 index 38df583bb5..0000000000 --- a/sys/platform/pc32/isa/ic/cd180.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. - * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/cd180.h,v 1.2.12.1 2000/08/03 01:01:25 peter Exp $ - * $DragonFly: src/sys/platform/pc32/isa/ic/cd180.h,v 1.2 2003/06/17 04:28:37 dillon Exp $ - */ - -/* - * Cirrus Logic CD180 registers - */ - -/* Global registers */ -#define CD180_GIVR 0x40 /* Global Interrupt Verctor Register */ -#define CD180_GICR 0x41 /* Global Interrupting Channel Register */ -#define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */ -#define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */ -#define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */ -#define CD180_CAR 0x64 /* Channel Access Register */ -#define CD180_GFRCR 0x6B /* Global Firmware Revision Code Register */ -#define CD180_PPRH 0x70 /* Prescaler Period Register MSB */ -#define CD180_PPRL 0x71 /* Prescaler Period Register LSB */ -#define CD180_RDR 0x78 /* Receiver Data Register */ -#define CD180_RCSR 0x7A /* Receiver Character Status Register */ -#define CD180_TDR 0x7B /* Transmit Data Register */ -#define CD180_EOIR 0x7F /* End of Interrupt Register */ - -/* Channel Registers */ -#define CD180_CCR 0x01 /* Channel Command Register */ -#define CD180_IER 0x02 /* Interrupt Enable Register */ -#define CD180_COR1 0x03 /* Channel Option Register 1 */ -#define CD180_COR2 0x04 /* Channel Option Register 1 */ -#define CD180_COR3 0x05 /* Channel Option Register 1 */ -#define CD180_CCSR 0x06 /* Channel Control STatus Register */ -#define CD180_RDCR 0x07 /* Receive Data Count Register */ -#define CD180_SCHR1 0x09 /* Special Character Register 1 */ -#define CD180_SCHR2 0x0A /* Special Character Register 2 */ -#define CD180_SCHR3 0x0B /* Special Character Register 3 */ -#define CD180_SCHR4 0x0C /* Special Character Register 4 */ -#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */ -#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */ -#define CD180_MCR 0x12 /* Modem Change Register */ -#define CD180_RTPR 0x18 /* Receive Timeout Period Register */ -#define CD180_MSVR 0x28 /* Modem Signal Value Register */ -#define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register MSB */ -#define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register LSB */ -#define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register MSB */ -#define CD180_TBPRL 0x3A /* Transmit Baud Rate Period Register LSB */ - -/** Register descritpions **/ - -/* Global Interrupt Vector Register */ -#define GIVR_IT_MSCI 0x01 /* Modem Signal Change Interrupt */ -#define GIVR_IT_TDI 0x02 /* Transmit Data Interrupt */ -#define GIVR_IT_RGDI 0x03 /* Receive Good Data Interrupt */ -#define GIVR_IT_REI 0x07 /* Receive Exception Interrupt */ - -/* Global Interrupt Channel Register */ -#define GICR_CHAN 0x1C /* Channel Number Mask */ -#define GICR_LSH 2 /* Channel Number Shift */ - -/* Channel Address Register */ -#define CAR_CHAN 0x07 /* Channel Number Mask */ -#define CAR_A7 0x08 /* Addres bit 7 (unused) */ - -/* Receive Character Status Register */ -#define RCSR_OE 0x01 /* Overrun Error */ -#define RCSR_FE 0x02 /* Frame Error */ -#define RCSR_PE 0x04 /* Parity Error */ -#define RCSR_Break 0x08 /* Break detected */ -#define RCSR_Timeout 0x80 /* Rx Timeout */ -#define RCSR_SCMASK 0x70 /* Special Character Detected Mask */ -#define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */ -#define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */ -#define RCSR_SC3 0x30 /* Special Char 3 */ -#define RCSR_SC4 0x40 /* Special Char 4 */ - -/* Channel Command Register */ -#define CCR_ResetChan 0x80 /* Reset Channel */ -#define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */ -#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */ -#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */ -#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */ -#define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */ -#define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */ -#define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */ -#define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */ -#define CCR_RCVRDIS 0x11 /* Receiver Disable */ -#define CCR_RCVREN 0x12 /* Receiver Enable */ -#define CCR_XMTRDIS 0x14 /* Transmitter Disable */ -#define CCR_XMTREN 0x18 /* Transmitter Enable */ - -/* Interrupt Enable Register */ -#define IER_DSR 0x80 /* Enable interrupt on DSR change */ -#define IER_CD 0x40 /* Enable interrupt on CD change */ -#define IER_CTS 0x20 /* Enable interrupt on CTS change */ -#define IER_RxData 0x10 /* Enable interrupt on Receive Data */ -#define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */ -#define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */ -#define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/ -#define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */ - -/* Channel Option Register 1 */ -#define COR1_ODDP 0x80 /* Odd Parity */ -#define COR1_ParMMASK 0x60 /* Parity Mode mask */ -#define COR1_NOPAR 0x02 /* No Parity */ -#define COR1_FORCEPAR 0x20 /* Force Parity */ -#define COR1_NORMPAR 0x40 /* Normal Parity */ -#define COR1_Ignore 0x10 /* Ignore Parity on RX */ -#define COR1_StopMASK 0x0C /* Stop Bits mode mask */ -#define COR1_1SB 0x00 /* 1 Stop Bit */ -#define COR1_15SB 0x04 /* 1.5 Stop Bits */ -#define COR1_2SB 0x08 /* 2 Stop Bits */ -#define COR1_CHLMASK 0x03 /* Character Length mask */ -#define COR1_5BITS 0x00 /* 5 bits */ -#define COR1_6BITS 0x01 /* 6 bits */ -#define COR1_7BITS 0x02 /* 7 bits */ -#define COR1_8BITS 0x03 /* 8 bits */ - -/* Channel Option Register 2 */ -#define COR2_IXM 0x80 /* Implied XON mode */ -#define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */ -#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */ -#define COR2_LLM 0x10 /* Local Loopback Mode */ -#define COR2_RLM 0x08 /* Remote Loopback Mode */ -#define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */ -#define COR2_CtsAE 0x02 /* CTS Automatic Enable */ -#define COR2_DsrAE 0x01 /* DSR Automatic Enable */ - -/* Channel Option Register 3 */ -#define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */ -#define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */ -#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */ -#define COR3_SCDE 0x10 /* Special Character Detection Enable */ -#define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */ - -/* Channel Control Status Register */ -#define CCSR_RxEn 0x80 /* Revceiver Enabled */ -#define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */ -#define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */ -#define CCSR_TxEn 0x08 /* Transmitter Enabled */ -#define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */ -#define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */ - -/* Modem Change Option Register 1 */ -#define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */ -#define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */ -#define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */ -#define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */ - -/* Modem Change Option Register 2 */ -#define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */ -#define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */ -#define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */ - -/* Modem Change Register */ -#define MCR_DSRchg 0x80 /* DSR Changed */ -#define MCR_CDchg 0x40 /* CD Changed */ -#define MCR_CTSchg 0x20 /* CTS Changed */ - -/* Modem Signal Value Register */ -#define MSVR_DSR 0x80 /* Current state of DSR input */ -#define MSVR_CD 0x40 /* Current state of DSR input */ -#define MSVR_CTS 0x20 /* Current state of CTS input */ -#define MSVR_DTR 0x02 /* Current state of DTR output */ -#define MSVR_RTS 0x01 /* Current state of RTS output */ - -/* Escape characters */ -#define CD180_C_ESC 0x00 /* Escape character */ -#define CD180_C_SBRK 0x81 /* Start sending BREAK */ -#define CD180_C_DELAY 0x82 /* Delay output */ -#define CD180_C_EBRK 0x83 /* Stop sending BREAK */ - -/* Miscellaneous */ -#define CD180_NCHAN 8 /* 8 channels per chip */ -#define CD180_CTICKS 16 /* 16 ticks for character processing */ -#define CD180_NFIFO 8 /* 8 bytes in FIFO */ diff --git a/sys/platform/pc32/isa/ic/i82586.h b/sys/platform/pc32/isa/ic/i82586.h deleted file mode 100644 index 9b254202bb..0000000000 --- a/sys/platform/pc32/isa/ic/i82586.h +++ /dev/null @@ -1,332 +0,0 @@ -/*- - * Copyright (c) 1992, University of Vermont and State Agricultural College. - * Copyright (c) 1992, Garrett A. Wollman. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * Vermont and State Agricultural College and Garrett A. Wollman. - * 4. Neither the name of the University nor the name of the author - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHOR BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/i82586.h,v 1.9 1999/08/28 00:45:14 peter Exp $ - */ - -/* - * Intel 82586 Ethernet chip - * Register, bit, and structure definitions. - * - * Written by GAW with reference to the Clarkson Packet Driver code for this - * chip written by Russ Nelson and others. - */ - -struct ie_en_addr { - u_char data[6]; -}; - -/* - * This is the master configuration block. It tells the hardware where all - * the rest of the stuff is. - */ -struct ie_sys_conf_ptr { - u_short mbz; /* must be zero */ - u_char ie_bus_use; /* true if 8-bit only */ - u_char mbz2[5]; /* must be zero */ - caddr_t ie_iscp_ptr; /* 24-bit physaddr of ISCP */ -}; - -/* - * Note that this is wired in hardware; the SCP is always located here, no - * matter what. - */ -#define IE_SCP_ADDR 0xfffff4 - -/* - * The tells the hardware where all the rest of the stuff is, too. - * FIXME: some of these should be re-commented after we figure out their - * REAL function. - */ -struct ie_int_sys_conf_ptr { - u_char ie_busy; /* zeroed after init */ - u_char mbz; - u_short ie_scb_offset; /* 16-bit physaddr of next struct */ - caddr_t ie_base; /* 24-bit physaddr for all 16-bit vars */ -}; - -/* - * This FINALLY tells the hardware what to do and where to put it. - */ -struct ie_sys_ctl_block { - u_short ie_status; /* status word */ - u_short ie_command; /* command word */ - u_short ie_command_list; /* 16-pointer to command block list */ - u_short ie_recv_list; /* 16-pointer to receive frame list */ - u_short ie_err_crc; /* CRC errors */ - u_short ie_err_align; /* Alignment errors */ - u_short ie_err_resource; /* Resource errors */ - u_short ie_err_overrun; /* Overrun errors */ -}; - -/* Command values */ -#define IE_RU_COMMAND 0x0070 /* mask for RU command */ -#define IE_RU_NOP 0 /* for completeness */ -#define IE_RU_START 0x0010 /* start receive unit command */ -#define IE_RU_ENABLE 0x0020 /* enable receiver command */ -#define IE_RU_DISABLE 0x0030 /* disable receiver command */ -#define IE_RU_ABORT 0x0040 /* abort current receive operation */ - -#define IE_CU_COMMAND 0x0700 /* mask for CU command */ -#define IE_CU_NOP 0 /* included for completeness */ -#define IE_CU_START 0x0100 /* do-command command */ -#define IE_CU_RESUME 0x0200 /* resume a suspended cmd list */ -#define IE_CU_STOP 0x0300 /* SUSPEND was already taken */ -#define IE_CU_ABORT 0x0400 /* abort current command */ - -#define IE_ACK_COMMAND 0xf000 /* mask for ACK command */ -#define IE_ACK_CX 0x8000 /* ack IE_ST_DONE */ -#define IE_ACK_FR 0x4000 /* ack IE_ST_RECV */ -#define IE_ACK_CNA 0x2000 /* ack IE_ST_ALLDONE */ -#define IE_ACK_RNR 0x1000 /* ack IE_ST_RNR */ - -#define IE_ACTION_COMMAND(x) (((x) & IE_CU_COMMAND) == IE_CU_START) - /* is this command an action command? */ - -/* Status values */ -#define IE_ST_WHENCE 0xf000 /* mask for cause of interrupt */ -#define IE_ST_DONE 0x8000 /* command with I bit completed */ -#define IE_ST_RECV 0x4000 /* frame received */ -#define IE_ST_ALLDONE 0x2000 /* all commands completed */ -#define IE_ST_RNR 0x1000 /* receive not ready */ - -#define IE_CU_STATUS 0x700 /* mask for command unit status */ -#define IE_CU_ACTIVE 0x200 /* command unit is active */ -#define IE_CU_SUSPEND 0x100 /* command unit is suspended */ - -#define IE_RU_STATUS 0x70 /* mask for receiver unit status */ -#define IE_RU_SUSPEND 0x10 /* receiver is suspended */ -#define IE_RU_NOSPACE 0x20 /* receiver has no resources */ -#define IE_RU_READY 0x40 /* reveiver is ready */ - -/* - * This is filled in partially by the chip, partially by us. - */ -struct ie_recv_frame_desc { - u_short ie_fd_status; /* status for this frame */ - u_short ie_fd_last; /* end of frame list flag */ - u_short ie_fd_next; /* 16-pointer to next RFD */ - u_short ie_fd_buf_desc; /* 16-pointer to list of buffer desc's */ - struct ie_en_addr dest; /* destination ether */ - struct ie_en_addr src; /* source ether */ - u_short ie_length; /* 802 length/Ether type */ - u_short mbz; /* must be zero */ -}; - -#define IE_FD_LAST 0x8000 /* last rfd in list */ -#define IE_FD_SUSP 0x4000 /* suspend RU after receipt */ - -#define IE_FD_COMPLETE 0x8000 /* frame is complete */ -#define IE_FD_BUSY 0x4000 /* frame is busy */ -#define IE_FD_OK 0x2000 /* frame is bad */ -#define IE_FD_RNR 0x0200 /* receiver out of resources here */ - -/* - * linked list of buffers... - */ -struct ie_recv_buf_desc { - u_short ie_rbd_actual; /* status for this buffer */ - u_short ie_rbd_next; /* 16-pointer to next RBD */ - caddr_t ie_rbd_buffer; /* 24-pointer to buffer for this RBD */ - u_short ie_rbd_length; /* length of the buffer */ - u_short mbz; /* must be zero */ -}; - -#define IE_RBD_LAST 0x8000 /* last buffer */ -#define IE_RBD_USED 0x4000 /* this buffer has data */ -/* - * All commands share this in common. - */ -struct ie_cmd_common { - u_short ie_cmd_status; /* status of this command */ - u_short ie_cmd_cmd; /* command word */ - u_short ie_cmd_link; /* link to next command */ -}; - -#define IE_STAT_COMPL 0x8000 /* command is completed */ -#define IE_STAT_BUSY 0x4000 /* command is running now */ -#define IE_STAT_OK 0x2000 /* command completed successfully */ - -#define IE_CMD_NOP 0x0000 /* NOP */ -#define IE_CMD_IASETUP 0x0001 /* initial address setup */ -#define IE_CMD_CONFIG 0x0002 /* configure command */ -#define IE_CMD_MCAST 0x0003 /* multicast setup command */ -#define IE_CMD_XMIT 0x0004 /* transmit command */ -#define IE_CMD_TDR 0x0005 /* time-domain reflectometer command */ -#define IE_CMD_DUMP 0x0006 /* dump command */ -#define IE_CMD_DIAGNOSE 0x0007 /* diagnostics command */ - -#define IE_CMD_LAST 0x8000 /* this is the last command in the list */ -#define IE_CMD_SUSPEND 0x4000 /* suspend CU after this command */ -#define IE_CMD_INTR 0x2000 /* post an interrupt after completion */ - -/* - * This is the command to transmit a frame. - */ -struct ie_xmit_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_xmit_status com.ie_cmd_status - - u_short ie_xmit_desc; /* 16-pointer to buffer descriptor */ - struct ie_en_addr ie_xmit_addr; /* destination address */ - - u_short ie_xmit_length; /* 802.3 length/Ether type field */ -}; - -#define IE_XS_MAXCOLL 0x000f /* number of collisions during transmit */ -#define IE_XS_EXCMAX 0x0020 /* exceeded maximum number of collisions */ -#define IE_XS_SQE 0x0040 /* SQE positive */ -#define IE_XS_DEFERRED 0x0080 /* transmission deferred */ -#define IE_XS_UNDERRUN 0x0100 /* DMA underrun */ -#define IE_XS_LOSTCTS 0x0200 /* Lost CTS */ -#define IE_XS_NOCARRIER 0x0400 /* No Carrier */ -#define IE_XS_LATECOLL 0x0800 /* Late collision */ - -/* - * This is a buffer descriptor for a frame to be transmitted. - */ - -struct ie_xmit_buf { - u_short ie_xmit_flags; /* see below */ - u_short ie_xmit_next; /* 16-pointer to next desc. */ - caddr_t ie_xmit_buf; /* 24-pointer to the actual buffer */ -}; - -#define IE_XMIT_LAST 0x8000 /* this TBD is the last one */ -/* The rest of the `flags' word is actually the length. */ - -/* - * Multicast setup command. - */ - -#define MAXMCAST 50 /* must fit in transmit buffer */ - -struct ie_mcast_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_mcast_status com.ie_cmd_status - - u_short ie_mcast_bytes; /* size (in bytes) of multicast addresses */ - struct ie_en_addr ie_mcast_addrs[MAXMCAST + 1]; /* space for them */ -}; - -/* - * Time Domain Reflectometer command. - */ - -struct ie_tdr_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_tdr_status com.ie_cmd_status - - u_short ie_tdr_time; /* error bits and time */ -}; - -#define IE_TDR_SUCCESS 0x8000 /* TDR succeeded without error */ -#define IE_TDR_XCVR 0x4000 /* detected a transceiver problem */ -#define IE_TDR_OPEN 0x2000 /* detected an open */ -#define IE_TDR_SHORT 0x1000 /* TDR detected a short */ -#define IE_TDR_TIME 0x07ff /* mask for reflection time */ - -/* - * Initial Address Setup command - */ -struct ie_iasetup_cmd { - struct ie_cmd_common com; -#define ie_iasetup_status com.ie_cmd_status - - struct ie_en_addr ie_address; -}; - -/* - * Configuration command - */ -struct ie_config_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_config_status com.ie_cmd_status - - u_char ie_config_count; /* byte count (0x0c) */ - u_char ie_fifo; /* fifo (8) */ - u_char ie_save_bad; /* save bad frames (0x40) */ - u_char ie_addr_len; /* address length (0x2e) (AL-LOC == 1) */ - u_char ie_priority; /* priority and backoff (0x0) */ - u_char ie_ifs; /* inter-frame spacing (0x60) */ - u_char ie_slot_low; /* slot time, LSB (0x0) */ - u_char ie_slot_high; /* slot time, MSN, and retries (0xf2) */ - u_char ie_promisc; /* 1 if promiscuous, else 0 */ - u_char ie_crs_cdt; /* CSMA/CD parameters (0x0) */ - u_char ie_min_len; /* min frame length (0x40) */ - u_char ie_junk; /* stuff for 82596 (0xff) */ -}; - -/* - * Here are a few useful functions. We could have done these as macros, - * but since we have the inline facility, it makes sense to use that - * instead. - */ -static __inline void -ie_setup_config(volatile struct ie_config_cmd *cmd, - int promiscuous, int manchester) { - cmd->ie_config_count = 0x0c; - cmd->ie_fifo = 8; - cmd->ie_save_bad = 0x40; - cmd->ie_addr_len = 0x2e; - cmd->ie_priority = 0; - cmd->ie_ifs = 0x60; - cmd->ie_slot_low = 0; - cmd->ie_slot_high = 0xf2; - cmd->ie_promisc = (!!promiscuous) | manchester << 2; - cmd->ie_crs_cdt = 0; - cmd->ie_min_len = 64; - cmd->ie_junk = 0xff; -} - -static __inline void * -Align(void *ptr) { - uintptr_t l = (uintptr_t)ptr; - l = (l + 3) & ~3L; - return (void *)l; -} - -static __inline volatile void * -Alignvol(volatile void *ptr) { - uintptr_t l = (uintptr_t)ptr; - l = (l + 3) & ~3L; - return (volatile void *)l; -} - -static __inline void -ie_ack(volatile struct ie_sys_ctl_block *scb, - u_int mask, int unit, - void (*ca)(int)) { - scb->ie_command = scb->ie_status & mask; - (*ca)(unit); -} diff --git a/sys/platform/pc32/isa/ic/lemac.h b/sys/platform/pc32/isa/ic/lemac.h deleted file mode 100644 index c76959d5c0..0000000000 --- a/sys/platform/pc32/isa/ic/lemac.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/lemac.h,v 1.5 1999/08/28 00:45:14 peter Exp $ - * $DragonFly: src/sys/platform/pc32/isa/ic/lemac.h,v 1.2 2003/06/17 04:28:37 dillon Exp $ - */ -#ifndef _LEMAC_H_ -#define _LEMAC_H_ - -/* - * This is list of registers used on a DEC EtherWORKS III card. - * Each board occupies a 32 byte register space. This can be - * in either EISA or ISA space. Currently we only support ISA - * space. - */ - -#define LEMAC_REG_CS 0x00 /* Control and Status */ -#define LEMAC_REG_CTL 0x01 /* Control */ -#define LEMAC_REG_IC 0x02 /* Interrupt Control */ -#define LEMAC_REG_TS 0x03 /* Transmit Status */ -#define LEMAC_REG_RSVD1 0x04 /* Reserved (not used) */ -#define LEMAC_REG_RSVD2 0x05 /* Reserved (not used) */ -#define LEMAC_REG_FMQ 0x06 /* Free Memory Queue */ -#define LEMAC_REG_FMC 0x07 /* Free Memory Queue Count */ -#define LEMAC_REG_RQ 0x08 /* Receive Queue */ -#define LEMAC_REG_RQC 0x09 /* Receive Queue Count */ -#define LEMAC_REG_TQ 0x0A /* Transmit Queue */ -#define LEMAC_REG_TQC 0x0B /* Transmit Queue Count */ -#define LEMAC_REG_TDQ 0x0C /* Transmit Done Queue */ -#define LEMAC_REG_TDC 0x0D /* Transmit Done Queue Count */ -#define LEMAC_REG_PI1 0x0E /* Page Index #1 */ -#define LEMAC_REG_PI2 0x0F /* Page Index #2 */ -#define LEMAC_REG_DAT 0x10 /* Data */ -#define LEMAC_REG_IOP 0x11 /* I/O Page */ -#define LEMAC_REG_IOB 0x12 /* I/O Base */ -#define LEMAC_REG_MPN 0x13 /* Memory Page */ -#define LEMAC_REG_MBR 0x14 /* Memory Base */ -#define LEMAC_REG_APD 0x15 /* Address PROM */ -#define LEMAC_REG_EE1 0x16 /* EEPROM Data #1 */ -#define LEMAC_REG_EE2 0x17 /* EEPROM Data #2 */ -#define LEMAC_REG_PA0 0x18 /* Physical Address (Byte 0) */ -#define LEMAC_REG_PA1 0x19 /* Physical Address (Byte 1) */ -#define LEMAC_REG_PA2 0x1A /* Physical Address (Byte 2) */ -#define LEMAC_REG_PA3 0x1B /* Physical Address (Byte 3) */ -#define LEMAC_REG_PA4 0x1C /* Physical Address (Byte 4) */ -#define LEMAC_REG_PA5 0x1D /* Physical Address (Byte 5) */ -#define LEMAC_REG_CNF 0x1E /* Configuration Management */ -#define LEMAC_IOSPACE 0x20 /* LEMAC uses 32 bytes of IOSPACE */ - - -#define LEMAC_REG_EID0 0x80 /* EISA Identification 0 */ -#define LEMAC_REG_EID1 0x81 /* EISA Identification 1 */ -#define LEMAC_REG_EID2 0x82 /* EISA Identification 2 */ -#define LEMAC_REG_EID3 0x83 /* EISA Identification 3 */ -#define LEMAC_REG_EIC 0x84 /* EISA Control */ - -/* Control Page (Page 0) Definitions */ - -#define LEMAC_MCTBL_BITS 9 -#define LEMAC_MCTBL_OFF 512 -#define LEMAC_MCTBL_SIZE (1 << (LEMAC_MCTBL_BITS - 3)) -#define LEMAC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian) */ - -/* EEPROM Definitions */ - -#define LEMAC_EEP_CKSUM 0 /* The valid checksum is 0 */ -#define LEMAC_EEP_SIZE 32 /* EEPROM is 32 bytes */ -#define LEMAC_EEP_DELAY 2000 /* 2ms = 2000us */ -#define LEMAC_EEP_PRDNM 8 /* Product Name Offset */ -#define LEMAC_EEP_PRDNMSZ 8 /* Product Name Size */ -#define LEMAC_EEP_SWFLAGS 16 /* Software Options Offset */ -#define LEMAC_EEP_SETUP 23 /* Setup Options Offset */ - -#define LEMAC_EEP_SW_SQE 0x10 /* Enable TX_SQE on Transmits */ -#define LEMAC_EEP_SW_LAB 0x08 /* Enable TX_LAB on Transmits */ -#define LEMAC_EEP_ST_DRAM 0x02 /* Enable extra DRAM */ - -#define LEMAC_ADP_ROMSZ 32 /* Size of Address PROM */ - -/* Receive Status Definitions */ - -#define LEMAC_RX_PLL 0x01 /* Phase Lock Lost */ -#define LEMAC_RX_CRC 0x02 /* CRC Error */ -#define LEMAC_RX_DBE 0x04 /* Dribble Bit Error */ -#define LEMAC_RX_MCM 0x08 /* Multicast Match */ -#define LEMAC_RX_IAM 0x10 /* Individual Address Match */ -#define LEMAC_RX_OK 0x80 /* No Errors */ - -/* Transmit Status Definitions (not valid if TXD == 0) */ - -#define LEMAC_TS_RTRYMSK 0x0F /* Retries of last TX PDU */ -#define LEMAC_TS_ECL 0x10 /* Excessive collision of ... */ -#define LEMAC_TS_LCL 0x20 /* Late collision of ... */ -#define LEMAC_TS_ID 0x40 /* Initially Deferred ... */ - -/* Transmit Control Definitions */ - -#define LEMAC_TX_ISA 0x01 /* Insert Source Address (no) */ -#define LEMAC_TX_IFC 0x02 /* Insert Frame Check (yes) */ -#define LEMAC_TX_PAD 0x04 /* Zero PAD to mininum length (yes) */ -#define LEMAC_TX_LAB 0x08 /* Less Agressive Backoff (no) */ -#define LEMAC_TX_QMD 0x10 /* Q-Mode (yes) */ -#define LEMAC_TX_STP 0x20 /* Stop on Error (yes) */ -#define LEMAC_TX_SQE 0x40 /* SQE Enable (yes) */ - -#define LEMAC_TX_FLAGS (LEMAC_TX_IFC|LEMAC_TX_PAD|LEMAC_TX_QMD|\ - LEMAC_TX_STP|LEMAC_TX_SQE) -#define LEMAC_TX_HDRSZ 4 /* Size of TX header */ - -/* Transmit Done Queue Status Definitions */ - -#define LEMAC_TDQ_COL 0x03 /* Collision Mask */ -#define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */ -#define LEMAC_TDQ_ONECOL 0x01 /* One Collision */ -#define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */ -#define LEMAC_TDQ_EXCCOL 0x03 /* Excesive Collisions */ -#define LEMAC_TDQ_ID 0x04 /* Initially Deferred */ -#define LEMAC_TDQ_LCL 0x08 /* Late Collision (will TX_STP) */ - -/* Control / Status Definitions */ - -#define LEMAC_CS_RXD 0x01 /* Receiver Disabled */ -#define LEMAC_CS_TXD 0x02 /* Transmitter Disabled */ -#define LEMAC_CS_RNE 0x04 /* Receive Queue Not Empty */ -#define LEMAC_CS_TNE 0x08 /* Transmit Done Queue Not Empty */ -#define LEMAC_CS_MBZ4 0x10 /* MBZ */ -#define LEMAC_CS_MCE 0x20 /* Multicast Enable */ -#define LEMAC_CS_PME 0x40 /* Promiscuous Mode Enable */ -#define LEMAC_CS_RA 0x80 /* Runt Accept */ - -/* Control Definitions */ - -#define LEMAC_CTL_LED 0x02 /* LED state (inverted) */ - -/* Interrupt Control Definitions */ - -#define LEMAC_IC_RXD 0x01 /* Enable RXD Interrupt */ -#define LEMAC_IC_TXD 0x02 /* Enable TXD Interrupt */ -#define LEMAC_IC_RNE 0x04 /* Enable RNE Interrupt */ -#define LEMAC_IC_TNE 0x08 /* Enable TNE Interrupt */ -#define LEMAC_IC_ALL 0x0F /* Enable RXD,TXD,RNE,TNE */ -#define LEMAC_IC_IRQMSK 0x60 /* Interrupt Select */ -#define LEMAC_IC_IRQ5 0x00 /* Select IRQ 5 */ -#define LEMAC_IC_IRQ10 0x20 /* Select IRQ 10 */ -#define LEMAC_IC_IRQ11 0x40 /* Select IRQ 11 */ -#define LEMAC_IC_IRQ15 0x60 /* Select IRQ 15 */ -#define LEMAC_IC_IE 0x80 /* Interrupt Enable */ - -/* I/O Page Definitions */ - -#define LEMAC_IOP_EEINIT 0xC0 /* Perform a board init/reset */ -#define LEMAC_IOP_EEREAD 0xE0 /* Start a read from EEPROM */ - -/* Configuration / Management Definitions */ - -#define LEMAC_CNF_DRAM 0x02 /* Extra on-board DRAM is available */ - -#endif /* _LEMAC_H_ */ diff --git a/sys/platform/pc64/isa/ascreg.h b/sys/platform/pc64/isa/ascreg.h deleted file mode 100644 index 199ad7c3e6..0000000000 --- a/sys/platform/pc64/isa/ascreg.h +++ /dev/null @@ -1,98 +0,0 @@ -/* ascreg.h - port and bit definitions for the GI-1904 interface - * - * Copyright (c) 1995 Gunther Schadow. All rights reserved. - * Copyright (c) 1995 Luigi Rizzo. All rights reserved. - * Copyright (c) 2008 The DragonFly Project. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Gunther Schadow. - * and Luigi Rizzo - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * $FreeBSD: src/sys/i386/isa/ascreg.h,v 1.5 1999/08/28 00:44:37 peter Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ascreg.h,v 1.1 2008/08/29 17:07:19 dillon Exp $ - */ - - /*** Registers (base=3EB): ************/ -#define ASC_CFG (scu->base) - /*** ASC_CFG 3EB: configuration register. Write only, mirror in RAM - *** 7 6 5 4 3 2 1 0 - *** - - I_5 I_3 I10 D_3 - D_1 - ***/ - /*** #define ASC_CNF_MASK 0x3D */ /* was 0x5a */ -#define ASC_CNF_DMA1 0x01 /* was (~0x02 & ASC_CNF_MASK) */ -#define ASC_CNF_DMA3 0x04 /* was (~0x08 & ASC_CNF_MASK) */ -#define ASC_CNF_IRQ3 0x10 /* was (~0x10 & ASC_CNF_MASK) */ -#define ASC_CNF_IRQ5 0x20 /* was (~0x40 & ASC_CNF_MASK) */ -#define ASC_CNF_IRQ10 0x08 /* was (~0x40 & ASC_CNF_MASK) */ - - /*** ASC_STAT 3EC: command/status; rw, mirror in ram - *** 7 6 5 4 3 2 1 0 - *** BSY - - - - - - - - *** [<-- Resolution -->] 13h,10h,0eh,0ch,09h, 07h, 04h, 02h - ***/ -#define ASC_STAT (scu->base + 1) - -#define ASC_RDY_FLAG 0x80 -#define ASC_RES_MASK 0x3f -#define ASC_RES_800 0x13 -#define ASC_RES_700 0x10 -#define ASC_RES_600 0x0e -#define ASC_RES_500 0x0c -#define ASC_RES_400 0x09 /* 0x00 */ -#define ASC_RES_300 0x07 /* 0x04 */ -#define ASC_RES_200 0x04 /* 0x20 */ -#define ASC_RES_100 0x02 /* 0x24 */ - - /*** ASC_CMD 3EC: command/status; rw, mirror in ram - *** W: 7 6 5 4 3 2 1 0 - *** . - - . . . . . - *** b0: 1: light on & get resolution, 0: light off - *** b1: 0: load scan len (sub_16, with b4=1, b7=1) - *** b2: 1/0 : dma stuff - *** b3: 0/1 : dma stuff - *** b4: 1 : load scan len (sub_16, with b1=0, b7=1) - *** b5: ? - *** b6: ? - *** b7: ? : set at beginning of sub_16 - ***/ -#define ASC_CMD (scu->base + 1) - -#define ASC_LIGHT_ON 0x01 -#define ASC_SET_B2 0x04 -#define ASC_OPERATE 0x91 /* from linux driver... */ -#define ASC_STANDBY 0x05 /* from linux driver... */ - - /*** ASC_LEN_L, ASC_LEN_H 3ED, 3EE: transfer length, lsb first ***/ -#define ASC_LEN_L ((scu->base)+2) -#define ASC_LEN_H ((scu->base)+3) - - /*** 3EE ASC_PROBE (must read ASC_PROBE_VALUE) ***/ -#define ASC_PROBE ((scu->base)+3) -#define ASC_PROBE_VALUE 0xA5 - - /*** ASC_BOH 3EF: always write 0 at the moment, read some values ? ***/ -#define ASC_BOH ((scu->base)+4) diff --git a/sys/platform/pc64/isa/ic/am7990.h b/sys/platform/pc64/isa/ic/am7990.h deleted file mode 100644 index 798f627784..0000000000 --- a/sys/platform/pc64/isa/ic/am7990.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * AMD 7990 (LANCE) definitions - * - * $FreeBSD: src/sys/i386/isa/ic/am7990.h,v 1.3.6.1 2000/08/03 01:01:25 peter Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ic/am7990.h,v 1.1 2008/08/29 17:07:21 dillon Exp $ - */ - -#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN -#define LN_BITFIELD2(a, b) b, a -#define LN_BITFIELD3(a, b, c) c, b, a -#define LN_BITFIELD4(a, b, c, d) d, c, b, a -#else -#define LN_BITFIELD2(a, b) a, b -#define LN_BITFIELD3(a, b, c) a, b, c -#define LN_BITFIELD4(a, b, c, d) a, b, c, d -#endif - -#define LN_ADDR_LO(addr) ((addr) & 0xFFFF) -#define LN_ADDR_HI(addr) (((addr) >> 16) & 0xFF) - -typedef struct { - unsigned short r_addr_lo; - unsigned int LN_BITFIELD3(r_addr_hi : 8, - : 5, - r_log2_size : 3); -} ln_ring_t; - -#define LN_MC_MASK 0x3F /* Only 6 bits of the CRC */ - -typedef struct { - unsigned short ln_mode; -#define LN_MODE_RXD 0x0001 /* ( W) Receiver Disabled */ -#define LN_MODE_TXD 0x0002 /* ( W) Transmitter Disabled */ -#define LN_MODE_LOOP 0x0004 /* ( W) Enable Loopback */ -#define LN_MODE_NOTXCRC 0x0008 /* ( W) Don't Calculate TX CRCs */ -#define LN_MODE_FRCCOLL 0x0010 /* ( W) Force Collision */ -#define LN_MODE_NORETRY 0x0020 /* ( W) No Transmit Retries */ -#define LN_MODE_INTLOOP 0x0040 /* ( W) Internal Loopback */ -#define LN_MODE_PROMISC 0x8000 /* ( W) Promiscious Mode */ - unsigned short ln_physaddr[3]; - unsigned short ln_multi_mask[4]; - ln_ring_t ln_rxring; - ln_ring_t ln_txring; -} ln_initb_t; - -typedef struct { - unsigned short d_addr_lo; - unsigned char d_addr_hi; - unsigned char d_flag; -#define LN_DFLAG_EOP 0x0001 /* (RW) End Of Packet */ -#define LN_DFLAG_SOP 0x0002 /* (RW) Start Of Packet */ -#define LN_DFLAG_RxBUFERROR 0x0004 /* (R ) Receive - Buffer Error */ -#define LN_DFLAG_TxDEFERRED 0x0004 /* (R ) Transmit - Initially Deferred */ -#define LN_DFLAG_RxBADCRC 0x0008 /* (R ) Receive - Bad Checksum */ -#define LN_DFLAG_TxONECOLL 0x0008 /* (R ) Transmit - Single Collision */ -#define LN_DFLAG_RxOVERFLOW 0x0010 /* (R ) Receive - Overflow Error */ -#define LN_DFLAG_TxMULTCOLL 0x0010 /* (R ) Transmit - Multiple Collisions */ -#define LN_DFLAG_RxFRAMING 0x0020 /* (R ) Receive - Framing Error */ -#define LN_DFLAG_RxERRSUM 0x0040 /* (R ) Receive - Error Summary */ -#define LN_DFLAG_TxERRSUM 0x0040 /* (R ) Transmit - Error Summary */ -#define LN_DFLAG_OWNER 0x0080 /* (RW) Owner (1=Am7990, 0=host) */ - signed short d_buflen; /* ( W) Two's complement */ - unsigned short d_status; -#define LN_DSTS_RxLENMASK 0x0FFF /* (R ) Recieve Length */ -#define LN_DSTS_TxTDRMASK 0x03FF /* (R ) Transmit - Time Domain Reflectometer */ -#define LN_DSTS_TxEXCCOLL 0x0400 /* (R ) Transmit - Excessive Collisions */ -#define LN_DSTS_TxCARRLOSS 0x0800 /* (R ) Transmit - Carrier Loss */ -#define LN_DSTS_TxLATECOLL 0x1000 /* (R ) Transmit - Late Collision */ -#define LN_DSTS_TxUNDERFLOW 0x4000 /* (R ) Transmit - Underflow */ -#define LN_DSTS_TxBUFERROR 0x8000 /* (R ) Transmit - Buffer Error */ -} ln_desc_t; - - - - -#define LN_CSR0 0x0000 - -#define LN_CSR0_INIT 0x0001 /* (RS) Initialize Am 7990 */ -#define LN_CSR0_START 0x0002 /* (RS) Start Am7990 */ -#define LN_CSR0_STOP 0x0004 /* (RS) Reset Am7990 */ -#define LN_CSR0_TXDEMAND 0x0008 /* (RS) Transmit On Demand */ -#define LN_CSR0_TXON 0x0010 /* (R ) Transmitter Enabled */ -#define LN_CSR0_RXON 0x0020 /* (R ) Receiver Enabled */ -#define LN_CSR0_ENABINTR 0x0040 /* (RW) Interrupt Enabled */ -#define LN_CSR0_PENDINTR 0x0080 /* (R ) Interrupt Pending */ -#define LN_CSR0_INITDONE 0x0100 /* (RC) Initialization Done */ -#define LN_CSR0_TXINT 0x0200 /* (RC) Transmit Interrupt */ -#define LN_CSR0_RXINT 0x0400 /* (RC) Receive Interrupt */ -#define LN_CSR0_MEMERROR 0x0800 /* (RC) Memory Error */ -#define LN_CSR0_MISS 0x1000 /* (RC) No Available Receive Buffers */ -#define LN_CSR0_CERR 0x2000 /* (RC) SQE failed */ -#define LN_CSR0_BABL 0x4000 /* (RC) Transmit Babble */ -#define LN_CSR0_ERRSUM 0x8000 /* (R ) Error Summary (last 4) */ -#define LN_CSR0_CLEAR 0x7F00 /* Clear Status Bit */ - -/* - * CSR1 -- Init Block Address (Low 16 Bits -- Must be Word Aligned) - * CSR2 -- Init Block Address (High 8 Bits) - */ -#define LN_CSR1 0x0001 -#define LN_CSR2 0x0002 - -/* - * CSR3 -- Hardware Control - */ - -#define LN_CSR3 0x0003 -#define LN_CSR3_BCON 0x0001 /* (RW) BM/HOLD Control */ -#define LN_CSR3_ALE 0x0002 /* (RW) ALE Control */ -#define LN_CSR3_BSWP 0x0004 /* (RW) Byte Swap */ diff --git a/sys/platform/pc64/isa/ic/cd180.h b/sys/platform/pc64/isa/ic/cd180.h deleted file mode 100644 index 05ad5b18b7..0000000000 --- a/sys/platform/pc64/isa/ic/cd180.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia. - * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/cd180.h,v 1.2.12.1 2000/08/03 01:01:25 peter Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ic/cd180.h,v 1.1 2008/08/29 17:07:21 dillon Exp $ - */ - -/* - * Cirrus Logic CD180 registers - */ - -/* Global registers */ -#define CD180_GIVR 0x40 /* Global Interrupt Verctor Register */ -#define CD180_GICR 0x41 /* Global Interrupting Channel Register */ -#define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */ -#define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */ -#define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */ -#define CD180_CAR 0x64 /* Channel Access Register */ -#define CD180_GFRCR 0x6B /* Global Firmware Revision Code Register */ -#define CD180_PPRH 0x70 /* Prescaler Period Register MSB */ -#define CD180_PPRL 0x71 /* Prescaler Period Register LSB */ -#define CD180_RDR 0x78 /* Receiver Data Register */ -#define CD180_RCSR 0x7A /* Receiver Character Status Register */ -#define CD180_TDR 0x7B /* Transmit Data Register */ -#define CD180_EOIR 0x7F /* End of Interrupt Register */ - -/* Channel Registers */ -#define CD180_CCR 0x01 /* Channel Command Register */ -#define CD180_IER 0x02 /* Interrupt Enable Register */ -#define CD180_COR1 0x03 /* Channel Option Register 1 */ -#define CD180_COR2 0x04 /* Channel Option Register 1 */ -#define CD180_COR3 0x05 /* Channel Option Register 1 */ -#define CD180_CCSR 0x06 /* Channel Control STatus Register */ -#define CD180_RDCR 0x07 /* Receive Data Count Register */ -#define CD180_SCHR1 0x09 /* Special Character Register 1 */ -#define CD180_SCHR2 0x0A /* Special Character Register 2 */ -#define CD180_SCHR3 0x0B /* Special Character Register 3 */ -#define CD180_SCHR4 0x0C /* Special Character Register 4 */ -#define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */ -#define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */ -#define CD180_MCR 0x12 /* Modem Change Register */ -#define CD180_RTPR 0x18 /* Receive Timeout Period Register */ -#define CD180_MSVR 0x28 /* Modem Signal Value Register */ -#define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register MSB */ -#define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register LSB */ -#define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register MSB */ -#define CD180_TBPRL 0x3A /* Transmit Baud Rate Period Register LSB */ - -/** Register descritpions **/ - -/* Global Interrupt Vector Register */ -#define GIVR_IT_MSCI 0x01 /* Modem Signal Change Interrupt */ -#define GIVR_IT_TDI 0x02 /* Transmit Data Interrupt */ -#define GIVR_IT_RGDI 0x03 /* Receive Good Data Interrupt */ -#define GIVR_IT_REI 0x07 /* Receive Exception Interrupt */ - -/* Global Interrupt Channel Register */ -#define GICR_CHAN 0x1C /* Channel Number Mask */ -#define GICR_LSH 2 /* Channel Number Shift */ - -/* Channel Address Register */ -#define CAR_CHAN 0x07 /* Channel Number Mask */ -#define CAR_A7 0x08 /* Addres bit 7 (unused) */ - -/* Receive Character Status Register */ -#define RCSR_OE 0x01 /* Overrun Error */ -#define RCSR_FE 0x02 /* Frame Error */ -#define RCSR_PE 0x04 /* Parity Error */ -#define RCSR_Break 0x08 /* Break detected */ -#define RCSR_Timeout 0x80 /* Rx Timeout */ -#define RCSR_SCMASK 0x70 /* Special Character Detected Mask */ -#define RCSR_SC1 0x10 /* Special Char 1 (or 1 & 3 seq matched) */ -#define RCSR_SC2 0x20 /* Special Char 2 (or 2 & 4 seq matched) */ -#define RCSR_SC3 0x30 /* Special Char 3 */ -#define RCSR_SC4 0x40 /* Special Char 4 */ - -/* Channel Command Register */ -#define CCR_ResetChan 0x80 /* Reset Channel */ -#define CCR_HWRESET 0x81 /* Hardware Reset (all channels) */ -#define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */ -#define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */ -#define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */ -#define CCR_SENDSPCH1 0x21 /* Send Special Character 1 */ -#define CCR_SENDSPCH2 0x22 /* Send Special Character 2 */ -#define CCR_SENDSPCH3 0x23 /* Send Special Character 3 */ -#define CCR_SENDSPCH4 0x24 /* Send Special Character 4 */ -#define CCR_RCVRDIS 0x11 /* Receiver Disable */ -#define CCR_RCVREN 0x12 /* Receiver Enable */ -#define CCR_XMTRDIS 0x14 /* Transmitter Disable */ -#define CCR_XMTREN 0x18 /* Transmitter Enable */ - -/* Interrupt Enable Register */ -#define IER_DSR 0x80 /* Enable interrupt on DSR change */ -#define IER_CD 0x40 /* Enable interrupt on CD change */ -#define IER_CTS 0x20 /* Enable interrupt on CTS change */ -#define IER_RxData 0x10 /* Enable interrupt on Receive Data */ -#define IER_RxSC 0x08 /* Enable interrupt on Receive Spec. Char */ -#define IER_TxRdy 0x04 /* Enable interrupt on TX FIFO empty */ -#define IER_TxMpty 0x02 /* Enable interrupt on TX completely empty*/ -#define IER_RET 0x01 /* Enable interrupt on RX Except. Timeout */ - -/* Channel Option Register 1 */ -#define COR1_ODDP 0x80 /* Odd Parity */ -#define COR1_ParMMASK 0x60 /* Parity Mode mask */ -#define COR1_NOPAR 0x02 /* No Parity */ -#define COR1_FORCEPAR 0x20 /* Force Parity */ -#define COR1_NORMPAR 0x40 /* Normal Parity */ -#define COR1_Ignore 0x10 /* Ignore Parity on RX */ -#define COR1_StopMASK 0x0C /* Stop Bits mode mask */ -#define COR1_1SB 0x00 /* 1 Stop Bit */ -#define COR1_15SB 0x04 /* 1.5 Stop Bits */ -#define COR1_2SB 0x08 /* 2 Stop Bits */ -#define COR1_CHLMASK 0x03 /* Character Length mask */ -#define COR1_5BITS 0x00 /* 5 bits */ -#define COR1_6BITS 0x01 /* 6 bits */ -#define COR1_7BITS 0x02 /* 7 bits */ -#define COR1_8BITS 0x03 /* 8 bits */ - -/* Channel Option Register 2 */ -#define COR2_IXM 0x80 /* Implied XON mode */ -#define COR2_TxIBE 0x40 /* Enable In-Band XON/XOFF Flow Control */ -#define COR2_ETC 0x20 /* Embedded Tx Commands Enable */ -#define COR2_LLM 0x10 /* Local Loopback Mode */ -#define COR2_RLM 0x08 /* Remote Loopback Mode */ -#define COR2_RtsAO 0x04 /* RTS Automatic Output Enable */ -#define COR2_CtsAE 0x02 /* CTS Automatic Enable */ -#define COR2_DsrAE 0x01 /* DSR Automatic Enable */ - -/* Channel Option Register 3 */ -#define COR3_XonCH 0x80 /* XON is a double seq (1 & 3) */ -#define COR3_XoffCH 0x40 /* XOFF is a double seq (1 & 3) */ -#define COR3_FCT 0x20 /* Flow-Control Transparency Mode */ -#define COR3_SCDE 0x10 /* Special Character Detection Enable */ -#define COR3_RxTHMASK 0x0F /* RX FIFO Threshold value (1-8) */ - -/* Channel Control Status Register */ -#define CCSR_RxEn 0x80 /* Revceiver Enabled */ -#define CCSR_RxFloff 0x40 /* Receive Flow Off (XOFF sent) */ -#define CCSR_RxFlon 0x20 /* Receive Flow On (XON sent) */ -#define CCSR_TxEn 0x08 /* Transmitter Enabled */ -#define CCSR_TxFloff 0x04 /* Transmit Flow Off (got XOFF) */ -#define CCSR_TxFlon 0x02 /* Transmit Flow On (got XON) */ - -/* Modem Change Option Register 1 */ -#define MCOR1_DSRzd 0x80 /* Detect 0->1 transition of DSR */ -#define MCOR1_CDzd 0x40 /* Detect 0->1 transition of CD */ -#define MCOR1_CTSzd 0x20 /* Detect 0->1 transition of CTS */ -#define MCOR1_DTRthMASK 0x0F /* Automatic DTR FC Threshold (1-8) chars */ - -/* Modem Change Option Register 2 */ -#define MCOR2_DSRod 0x80 /* Detect 1->0 transition of DSR */ -#define MCOR2_CDod 0x40 /* Detect 1->0 transition of CD */ -#define MCOR2_CTSod 0x20 /* Detect 1->0 transition of CTS */ - -/* Modem Change Register */ -#define MCR_DSRchg 0x80 /* DSR Changed */ -#define MCR_CDchg 0x40 /* CD Changed */ -#define MCR_CTSchg 0x20 /* CTS Changed */ - -/* Modem Signal Value Register */ -#define MSVR_DSR 0x80 /* Current state of DSR input */ -#define MSVR_CD 0x40 /* Current state of DSR input */ -#define MSVR_CTS 0x20 /* Current state of CTS input */ -#define MSVR_DTR 0x02 /* Current state of DTR output */ -#define MSVR_RTS 0x01 /* Current state of RTS output */ - -/* Escape characters */ -#define CD180_C_ESC 0x00 /* Escape character */ -#define CD180_C_SBRK 0x81 /* Start sending BREAK */ -#define CD180_C_DELAY 0x82 /* Delay output */ -#define CD180_C_EBRK 0x83 /* Stop sending BREAK */ - -/* Miscellaneous */ -#define CD180_NCHAN 8 /* 8 channels per chip */ -#define CD180_CTICKS 16 /* 16 ticks for character processing */ -#define CD180_NFIFO 8 /* 8 bytes in FIFO */ diff --git a/sys/platform/pc64/isa/ic/i82586.h b/sys/platform/pc64/isa/ic/i82586.h deleted file mode 100644 index 9b254202bb..0000000000 --- a/sys/platform/pc64/isa/ic/i82586.h +++ /dev/null @@ -1,332 +0,0 @@ -/*- - * Copyright (c) 1992, University of Vermont and State Agricultural College. - * Copyright (c) 1992, Garrett A. Wollman. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * Vermont and State Agricultural College and Garrett A. Wollman. - * 4. Neither the name of the University nor the name of the author - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OR AUTHOR BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/i82586.h,v 1.9 1999/08/28 00:45:14 peter Exp $ - */ - -/* - * Intel 82586 Ethernet chip - * Register, bit, and structure definitions. - * - * Written by GAW with reference to the Clarkson Packet Driver code for this - * chip written by Russ Nelson and others. - */ - -struct ie_en_addr { - u_char data[6]; -}; - -/* - * This is the master configuration block. It tells the hardware where all - * the rest of the stuff is. - */ -struct ie_sys_conf_ptr { - u_short mbz; /* must be zero */ - u_char ie_bus_use; /* true if 8-bit only */ - u_char mbz2[5]; /* must be zero */ - caddr_t ie_iscp_ptr; /* 24-bit physaddr of ISCP */ -}; - -/* - * Note that this is wired in hardware; the SCP is always located here, no - * matter what. - */ -#define IE_SCP_ADDR 0xfffff4 - -/* - * The tells the hardware where all the rest of the stuff is, too. - * FIXME: some of these should be re-commented after we figure out their - * REAL function. - */ -struct ie_int_sys_conf_ptr { - u_char ie_busy; /* zeroed after init */ - u_char mbz; - u_short ie_scb_offset; /* 16-bit physaddr of next struct */ - caddr_t ie_base; /* 24-bit physaddr for all 16-bit vars */ -}; - -/* - * This FINALLY tells the hardware what to do and where to put it. - */ -struct ie_sys_ctl_block { - u_short ie_status; /* status word */ - u_short ie_command; /* command word */ - u_short ie_command_list; /* 16-pointer to command block list */ - u_short ie_recv_list; /* 16-pointer to receive frame list */ - u_short ie_err_crc; /* CRC errors */ - u_short ie_err_align; /* Alignment errors */ - u_short ie_err_resource; /* Resource errors */ - u_short ie_err_overrun; /* Overrun errors */ -}; - -/* Command values */ -#define IE_RU_COMMAND 0x0070 /* mask for RU command */ -#define IE_RU_NOP 0 /* for completeness */ -#define IE_RU_START 0x0010 /* start receive unit command */ -#define IE_RU_ENABLE 0x0020 /* enable receiver command */ -#define IE_RU_DISABLE 0x0030 /* disable receiver command */ -#define IE_RU_ABORT 0x0040 /* abort current receive operation */ - -#define IE_CU_COMMAND 0x0700 /* mask for CU command */ -#define IE_CU_NOP 0 /* included for completeness */ -#define IE_CU_START 0x0100 /* do-command command */ -#define IE_CU_RESUME 0x0200 /* resume a suspended cmd list */ -#define IE_CU_STOP 0x0300 /* SUSPEND was already taken */ -#define IE_CU_ABORT 0x0400 /* abort current command */ - -#define IE_ACK_COMMAND 0xf000 /* mask for ACK command */ -#define IE_ACK_CX 0x8000 /* ack IE_ST_DONE */ -#define IE_ACK_FR 0x4000 /* ack IE_ST_RECV */ -#define IE_ACK_CNA 0x2000 /* ack IE_ST_ALLDONE */ -#define IE_ACK_RNR 0x1000 /* ack IE_ST_RNR */ - -#define IE_ACTION_COMMAND(x) (((x) & IE_CU_COMMAND) == IE_CU_START) - /* is this command an action command? */ - -/* Status values */ -#define IE_ST_WHENCE 0xf000 /* mask for cause of interrupt */ -#define IE_ST_DONE 0x8000 /* command with I bit completed */ -#define IE_ST_RECV 0x4000 /* frame received */ -#define IE_ST_ALLDONE 0x2000 /* all commands completed */ -#define IE_ST_RNR 0x1000 /* receive not ready */ - -#define IE_CU_STATUS 0x700 /* mask for command unit status */ -#define IE_CU_ACTIVE 0x200 /* command unit is active */ -#define IE_CU_SUSPEND 0x100 /* command unit is suspended */ - -#define IE_RU_STATUS 0x70 /* mask for receiver unit status */ -#define IE_RU_SUSPEND 0x10 /* receiver is suspended */ -#define IE_RU_NOSPACE 0x20 /* receiver has no resources */ -#define IE_RU_READY 0x40 /* reveiver is ready */ - -/* - * This is filled in partially by the chip, partially by us. - */ -struct ie_recv_frame_desc { - u_short ie_fd_status; /* status for this frame */ - u_short ie_fd_last; /* end of frame list flag */ - u_short ie_fd_next; /* 16-pointer to next RFD */ - u_short ie_fd_buf_desc; /* 16-pointer to list of buffer desc's */ - struct ie_en_addr dest; /* destination ether */ - struct ie_en_addr src; /* source ether */ - u_short ie_length; /* 802 length/Ether type */ - u_short mbz; /* must be zero */ -}; - -#define IE_FD_LAST 0x8000 /* last rfd in list */ -#define IE_FD_SUSP 0x4000 /* suspend RU after receipt */ - -#define IE_FD_COMPLETE 0x8000 /* frame is complete */ -#define IE_FD_BUSY 0x4000 /* frame is busy */ -#define IE_FD_OK 0x2000 /* frame is bad */ -#define IE_FD_RNR 0x0200 /* receiver out of resources here */ - -/* - * linked list of buffers... - */ -struct ie_recv_buf_desc { - u_short ie_rbd_actual; /* status for this buffer */ - u_short ie_rbd_next; /* 16-pointer to next RBD */ - caddr_t ie_rbd_buffer; /* 24-pointer to buffer for this RBD */ - u_short ie_rbd_length; /* length of the buffer */ - u_short mbz; /* must be zero */ -}; - -#define IE_RBD_LAST 0x8000 /* last buffer */ -#define IE_RBD_USED 0x4000 /* this buffer has data */ -/* - * All commands share this in common. - */ -struct ie_cmd_common { - u_short ie_cmd_status; /* status of this command */ - u_short ie_cmd_cmd; /* command word */ - u_short ie_cmd_link; /* link to next command */ -}; - -#define IE_STAT_COMPL 0x8000 /* command is completed */ -#define IE_STAT_BUSY 0x4000 /* command is running now */ -#define IE_STAT_OK 0x2000 /* command completed successfully */ - -#define IE_CMD_NOP 0x0000 /* NOP */ -#define IE_CMD_IASETUP 0x0001 /* initial address setup */ -#define IE_CMD_CONFIG 0x0002 /* configure command */ -#define IE_CMD_MCAST 0x0003 /* multicast setup command */ -#define IE_CMD_XMIT 0x0004 /* transmit command */ -#define IE_CMD_TDR 0x0005 /* time-domain reflectometer command */ -#define IE_CMD_DUMP 0x0006 /* dump command */ -#define IE_CMD_DIAGNOSE 0x0007 /* diagnostics command */ - -#define IE_CMD_LAST 0x8000 /* this is the last command in the list */ -#define IE_CMD_SUSPEND 0x4000 /* suspend CU after this command */ -#define IE_CMD_INTR 0x2000 /* post an interrupt after completion */ - -/* - * This is the command to transmit a frame. - */ -struct ie_xmit_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_xmit_status com.ie_cmd_status - - u_short ie_xmit_desc; /* 16-pointer to buffer descriptor */ - struct ie_en_addr ie_xmit_addr; /* destination address */ - - u_short ie_xmit_length; /* 802.3 length/Ether type field */ -}; - -#define IE_XS_MAXCOLL 0x000f /* number of collisions during transmit */ -#define IE_XS_EXCMAX 0x0020 /* exceeded maximum number of collisions */ -#define IE_XS_SQE 0x0040 /* SQE positive */ -#define IE_XS_DEFERRED 0x0080 /* transmission deferred */ -#define IE_XS_UNDERRUN 0x0100 /* DMA underrun */ -#define IE_XS_LOSTCTS 0x0200 /* Lost CTS */ -#define IE_XS_NOCARRIER 0x0400 /* No Carrier */ -#define IE_XS_LATECOLL 0x0800 /* Late collision */ - -/* - * This is a buffer descriptor for a frame to be transmitted. - */ - -struct ie_xmit_buf { - u_short ie_xmit_flags; /* see below */ - u_short ie_xmit_next; /* 16-pointer to next desc. */ - caddr_t ie_xmit_buf; /* 24-pointer to the actual buffer */ -}; - -#define IE_XMIT_LAST 0x8000 /* this TBD is the last one */ -/* The rest of the `flags' word is actually the length. */ - -/* - * Multicast setup command. - */ - -#define MAXMCAST 50 /* must fit in transmit buffer */ - -struct ie_mcast_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_mcast_status com.ie_cmd_status - - u_short ie_mcast_bytes; /* size (in bytes) of multicast addresses */ - struct ie_en_addr ie_mcast_addrs[MAXMCAST + 1]; /* space for them */ -}; - -/* - * Time Domain Reflectometer command. - */ - -struct ie_tdr_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_tdr_status com.ie_cmd_status - - u_short ie_tdr_time; /* error bits and time */ -}; - -#define IE_TDR_SUCCESS 0x8000 /* TDR succeeded without error */ -#define IE_TDR_XCVR 0x4000 /* detected a transceiver problem */ -#define IE_TDR_OPEN 0x2000 /* detected an open */ -#define IE_TDR_SHORT 0x1000 /* TDR detected a short */ -#define IE_TDR_TIME 0x07ff /* mask for reflection time */ - -/* - * Initial Address Setup command - */ -struct ie_iasetup_cmd { - struct ie_cmd_common com; -#define ie_iasetup_status com.ie_cmd_status - - struct ie_en_addr ie_address; -}; - -/* - * Configuration command - */ -struct ie_config_cmd { - struct ie_cmd_common com; /* common part */ -#define ie_config_status com.ie_cmd_status - - u_char ie_config_count; /* byte count (0x0c) */ - u_char ie_fifo; /* fifo (8) */ - u_char ie_save_bad; /* save bad frames (0x40) */ - u_char ie_addr_len; /* address length (0x2e) (AL-LOC == 1) */ - u_char ie_priority; /* priority and backoff (0x0) */ - u_char ie_ifs; /* inter-frame spacing (0x60) */ - u_char ie_slot_low; /* slot time, LSB (0x0) */ - u_char ie_slot_high; /* slot time, MSN, and retries (0xf2) */ - u_char ie_promisc; /* 1 if promiscuous, else 0 */ - u_char ie_crs_cdt; /* CSMA/CD parameters (0x0) */ - u_char ie_min_len; /* min frame length (0x40) */ - u_char ie_junk; /* stuff for 82596 (0xff) */ -}; - -/* - * Here are a few useful functions. We could have done these as macros, - * but since we have the inline facility, it makes sense to use that - * instead. - */ -static __inline void -ie_setup_config(volatile struct ie_config_cmd *cmd, - int promiscuous, int manchester) { - cmd->ie_config_count = 0x0c; - cmd->ie_fifo = 8; - cmd->ie_save_bad = 0x40; - cmd->ie_addr_len = 0x2e; - cmd->ie_priority = 0; - cmd->ie_ifs = 0x60; - cmd->ie_slot_low = 0; - cmd->ie_slot_high = 0xf2; - cmd->ie_promisc = (!!promiscuous) | manchester << 2; - cmd->ie_crs_cdt = 0; - cmd->ie_min_len = 64; - cmd->ie_junk = 0xff; -} - -static __inline void * -Align(void *ptr) { - uintptr_t l = (uintptr_t)ptr; - l = (l + 3) & ~3L; - return (void *)l; -} - -static __inline volatile void * -Alignvol(volatile void *ptr) { - uintptr_t l = (uintptr_t)ptr; - l = (l + 3) & ~3L; - return (volatile void *)l; -} - -static __inline void -ie_ack(volatile struct ie_sys_ctl_block *scb, - u_int mask, int unit, - void (*ca)(int)) { - scb->ie_command = scb->ie_status & mask; - (*ca)(unit); -} diff --git a/sys/platform/pc64/isa/ic/lemac.h b/sys/platform/pc64/isa/ic/lemac.h deleted file mode 100644 index 20925e3e9d..0000000000 --- a/sys/platform/pc64/isa/ic/lemac.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com) - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/i386/isa/ic/lemac.h,v 1.5 1999/08/28 00:45:14 peter Exp $ - * $DragonFly: src/sys/platform/pc64/isa/ic/lemac.h,v 1.1 2008/08/29 17:07:21 dillon Exp $ - */ -#ifndef _LEMAC_H_ -#define _LEMAC_H_ - -/* - * This is list of registers used on a DEC EtherWORKS III card. - * Each board occupies a 32 byte register space. This can be - * in either EISA or ISA space. Currently we only support ISA - * space. - */ - -#define LEMAC_REG_CS 0x00 /* Control and Status */ -#define LEMAC_REG_CTL 0x01 /* Control */ -#define LEMAC_REG_IC 0x02 /* Interrupt Control */ -#define LEMAC_REG_TS 0x03 /* Transmit Status */ -#define LEMAC_REG_RSVD1 0x04 /* Reserved (not used) */ -#define LEMAC_REG_RSVD2 0x05 /* Reserved (not used) */ -#define LEMAC_REG_FMQ 0x06 /* Free Memory Queue */ -#define LEMAC_REG_FMC 0x07 /* Free Memory Queue Count */ -#define LEMAC_REG_RQ 0x08 /* Receive Queue */ -#define LEMAC_REG_RQC 0x09 /* Receive Queue Count */ -#define LEMAC_REG_TQ 0x0A /* Transmit Queue */ -#define LEMAC_REG_TQC 0x0B /* Transmit Queue Count */ -#define LEMAC_REG_TDQ 0x0C /* Transmit Done Queue */ -#define LEMAC_REG_TDC 0x0D /* Transmit Done Queue Count */ -#define LEMAC_REG_PI1 0x0E /* Page Index #1 */ -#define LEMAC_REG_PI2 0x0F /* Page Index #2 */ -#define LEMAC_REG_DAT 0x10 /* Data */ -#define LEMAC_REG_IOP 0x11 /* I/O Page */ -#define LEMAC_REG_IOB 0x12 /* I/O Base */ -#define LEMAC_REG_MPN 0x13 /* Memory Page */ -#define LEMAC_REG_MBR 0x14 /* Memory Base */ -#define LEMAC_REG_APD 0x15 /* Address PROM */ -#define LEMAC_REG_EE1 0x16 /* EEPROM Data #1 */ -#define LEMAC_REG_EE2 0x17 /* EEPROM Data #2 */ -#define LEMAC_REG_PA0 0x18 /* Physical Address (Byte 0) */ -#define LEMAC_REG_PA1 0x19 /* Physical Address (Byte 1) */ -#define LEMAC_REG_PA2 0x1A /* Physical Address (Byte 2) */ -#define LEMAC_REG_PA3 0x1B /* Physical Address (Byte 3) */ -#define LEMAC_REG_PA4 0x1C /* Physical Address (Byte 4) */ -#define LEMAC_REG_PA5 0x1D /* Physical Address (Byte 5) */ -#define LEMAC_REG_CNF 0x1E /* Configuration Management */ -#define LEMAC_IOSPACE 0x20 /* LEMAC uses 32 bytes of IOSPACE */ - - -#define LEMAC_REG_EID0 0x80 /* EISA Identification 0 */ -#define LEMAC_REG_EID1 0x81 /* EISA Identification 1 */ -#define LEMAC_REG_EID2 0x82 /* EISA Identification 2 */ -#define LEMAC_REG_EID3 0x83 /* EISA Identification 3 */ -#define LEMAC_REG_EIC 0x84 /* EISA Control */ - -/* Control Page (Page 0) Definitions */ - -#define LEMAC_MCTBL_BITS 9 -#define LEMAC_MCTBL_OFF 512 -#define LEMAC_MCTBL_SIZE (1 << (LEMAC_MCTBL_BITS - 3)) -#define LEMAC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian) */ - -/* EEPROM Definitions */ - -#define LEMAC_EEP_CKSUM 0 /* The valid checksum is 0 */ -#define LEMAC_EEP_SIZE 32 /* EEPROM is 32 bytes */ -#define LEMAC_EEP_DELAY 2000 /* 2ms = 2000us */ -#define LEMAC_EEP_PRDNM 8 /* Product Name Offset */ -#define LEMAC_EEP_PRDNMSZ 8 /* Product Name Size */ -#define LEMAC_EEP_SWFLAGS 16 /* Software Options Offset */ -#define LEMAC_EEP_SETUP 23 /* Setup Options Offset */ - -#define LEMAC_EEP_SW_SQE 0x10 /* Enable TX_SQE on Transmits */ -#define LEMAC_EEP_SW_LAB 0x08 /* Enable TX_LAB on Transmits */ -#define LEMAC_EEP_ST_DRAM 0x02 /* Enable extra DRAM */ - -#define LEMAC_ADP_ROMSZ 32 /* Size of Address PROM */ - -/* Receive Status Definitions */ - -#define LEMAC_RX_PLL 0x01 /* Phase Lock Lost */ -#define LEMAC_RX_CRC 0x02 /* CRC Error */ -#define LEMAC_RX_DBE 0x04 /* Dribble Bit Error */ -#define LEMAC_RX_MCM 0x08 /* Multicast Match */ -#define LEMAC_RX_IAM 0x10 /* Individual Address Match */ -#define LEMAC_RX_OK 0x80 /* No Errors */ - -/* Transmit Status Definitions (not valid if TXD == 0) */ - -#define LEMAC_TS_RTRYMSK 0x0F /* Retries of last TX PDU */ -#define LEMAC_TS_ECL 0x10 /* Excessive collision of ... */ -#define LEMAC_TS_LCL 0x20 /* Late collision of ... */ -#define LEMAC_TS_ID 0x40 /* Initially Deferred ... */ - -/* Transmit Control Definitions */ - -#define LEMAC_TX_ISA 0x01 /* Insert Source Address (no) */ -#define LEMAC_TX_IFC 0x02 /* Insert Frame Check (yes) */ -#define LEMAC_TX_PAD 0x04 /* Zero PAD to mininum length (yes) */ -#define LEMAC_TX_LAB 0x08 /* Less Agressive Backoff (no) */ -#define LEMAC_TX_QMD 0x10 /* Q-Mode (yes) */ -#define LEMAC_TX_STP 0x20 /* Stop on Error (yes) */ -#define LEMAC_TX_SQE 0x40 /* SQE Enable (yes) */ - -#define LEMAC_TX_FLAGS (LEMAC_TX_IFC|LEMAC_TX_PAD|LEMAC_TX_QMD|\ - LEMAC_TX_STP|LEMAC_TX_SQE) -#define LEMAC_TX_HDRSZ 4 /* Size of TX header */ - -/* Transmit Done Queue Status Definitions */ - -#define LEMAC_TDQ_COL 0x03 /* Collision Mask */ -#define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */ -#define LEMAC_TDQ_ONECOL 0x01 /* One Collision */ -#define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */ -#define LEMAC_TDQ_EXCCOL 0x03 /* Excesive Collisions */ -#define LEMAC_TDQ_ID 0x04 /* Initially Deferred */ -#define LEMAC_TDQ_LCL 0x08 /* Late Collision (will TX_STP) */ - -/* Control / Status Definitions */ - -#define LEMAC_CS_RXD 0x01 /* Receiver Disabled */ -#define LEMAC_CS_TXD 0x02 /* Transmitter Disabled */ -#define LEMAC_CS_RNE 0x04 /* Receive Queue Not Empty */ -#define LEMAC_CS_TNE 0x08 /* Transmit Done Queue Not Empty */ -#define LEMAC_CS_MBZ4 0x10 /* MBZ */ -#define LEMAC_CS_MCE 0x20 /* Multicast Enable */ -#define LEMAC_CS_PME 0x40 /* Promiscuous Mode Enable */ -#define LEMAC_CS_RA 0x80 /* Runt Accept */ - -/* Control Definitions */ - -#define LEMAC_CTL_LED 0x02 /* LED state (inverted) */ - -/* Interrupt Control Definitions */ - -#define LEMAC_IC_RXD 0x01 /* Enable RXD Interrupt */ -#define LEMAC_IC_TXD 0x02 /* Enable TXD Interrupt */ -#define LEMAC_IC_RNE 0x04 /* Enable RNE Interrupt */ -#define LEMAC_IC_TNE 0x08 /* Enable TNE Interrupt */ -#define LEMAC_IC_ALL 0x0F /* Enable RXD,TXD,RNE,TNE */ -#define LEMAC_IC_IRQMSK 0x60 /* Interrupt Select */ -#define LEMAC_IC_IRQ5 0x00 /* Select IRQ 5 */ -#define LEMAC_IC_IRQ10 0x20 /* Select IRQ 10 */ -#define LEMAC_IC_IRQ11 0x40 /* Select IRQ 11 */ -#define LEMAC_IC_IRQ15 0x60 /* Select IRQ 15 */ -#define LEMAC_IC_IE 0x80 /* Interrupt Enable */ - -/* I/O Page Definitions */ - -#define LEMAC_IOP_EEINIT 0xC0 /* Perform a board init/reset */ -#define LEMAC_IOP_EEREAD 0xE0 /* Start a read from EEPROM */ - -/* Configuration / Management Definitions */ - -#define LEMAC_CNF_DRAM 0x02 /* Extra on-board DRAM is available */ - -#endif /* _LEMAC_H_ */ -- 2.41.0