From 4b8649cbf100e49aff14f2ea48295a0156fa85ab Mon Sep 17 00:00:00 2001 From: Matthew Dillon Date: Fri, 15 Aug 2014 22:55:43 -0700 Subject: [PATCH] ath - incremental update ar9300 from FreeBSD * Update to fbsd 61ad4c7509a280c218a389f91026136cec60708e (Aug 11 2014). * Minor adjustments to the ar9300 hal, plus sysctl support for forced cold reset. --- .../dev/ath/ath_hal/ar9300/ar9300_attach.c | 2 ++ .../dev/ath/ath_hal/ar9300/ar9300_interrupts.c | 15 +++++++++++++++ sys/contrib/dev/ath/ath_hal/ar9300/ar9300_power.c | 4 ++++ sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c | 5 +++++ sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c | 14 +++++++++++++- sys/dev/netif/ath/ath_hal/ah_devid.h | 1 + 6 files changed, 40 insertions(+), 1 deletion(-) diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c index 46833ef749..9cc99ec701 100644 --- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c +++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c @@ -4113,6 +4113,8 @@ ar9300_probe(uint16_t vendorid, uint16_t devid) return "Qualcomm Atheros QCA955x"; case AR9300_DEVID_QCA9565: /* Aphrodite */ return "Qualcomm Atheros AR9565"; + case AR9300_DEVID_AR1111_PCIE: + return "Atheros AR1111"; default: return AH_NULL; } diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c index 51ee3cdf87..acc14b34e2 100644 --- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c +++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c @@ -142,6 +142,21 @@ ar9300_get_pending_interrupts( sync_en_def = AR9340_INTR_SYNC_DEFAULT; } + /* Store away the async and sync cause registers */ + /* XXX Do this before the filtering done below */ +#ifdef AH_INTERRUPT_DEBUGGING + ah->ah_intrstate[0] = OS_REG_READ(ah, AR_ISR); + ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0); + ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1); + ah->ah_intrstate[3] = OS_REG_READ(ah, AR_ISR_S2); + ah->ah_intrstate[4] = OS_REG_READ(ah, AR_ISR_S3); + ah->ah_intrstate[5] = OS_REG_READ(ah, AR_ISR_S4); + ah->ah_intrstate[6] = OS_REG_READ(ah, AR_ISR_S5); + + /* XXX double reading? */ + ah->ah_syncstate = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)); +#endif + sync_cause = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)) & (sync_en_def | AR_INTR_SYNC_MASK_GPIO); diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_power.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_power.c index 0fe4d6323e..c97a5f5bd1 100644 --- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_power.c +++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_power.c @@ -673,6 +673,8 @@ ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip) set_chip ? "set chip " : ""); #endif + OS_MARK(ah, AH_MARK_CHIP_POWER, mode); + switch (mode) { case HAL_PM_AWAKE: if (set_chip) @@ -725,8 +727,10 @@ ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip) default: HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: unknown power mode %u\n", __func__, mode); + OS_MARK(ah, AH_MARK_CHIP_POWER_DONE, -1); return AH_FALSE; } + OS_MARK(ah, AH_MARK_CHIP_POWER_DONE, status); return status; } diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c index e13c00bb57..c919d3ce06 100644 --- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c +++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c @@ -113,6 +113,8 @@ ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout) #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ #define AH_TIME_QUANTUM 100 /* usec */ + OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP); + if (timeout == 0) { timeout = AH_RX_STOP_DMA_TIMEOUT; } @@ -157,6 +159,9 @@ ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout) OS_REG_WRITE(ah, AR_MACMISC, org_value); + OS_MARK(ah, AH_MARK_RX_CTL, + status ? AH_MARK_RX_CTL_DMA_STOP_OK : AH_MARK_RX_CTL_DMA_STOP_ERR); + return status; #undef AH_RX_STOP_DMA_TIMEOUT #undef AH_TIME_QUANTUM diff --git a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c index a52f01e227..1090c9c59a 100644 --- a/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c +++ b/sys/contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c @@ -1987,13 +1987,25 @@ HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *chan) { struct ath_hal_9300 *ahp = AH9300(ah); + int type = HAL_RESET_WARM; OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); /* * Warm reset is optimistic. + * + * If the TX/RX DMA engines aren't shut down (eg, they're + * wedged) then we're better off doing a full cold reset + * to try and shake that condition. */ - if (!ar9300_set_reset_reg(ah, HAL_RESET_WARM)) { + if (ahp->ah_chip_full_sleep || + (ah->ah_config.ah_force_full_reset == 1) || + OS_REG_READ(ah, AR_Q_TXE) || + (OS_REG_READ(ah, AR_CR) & AR_CR_RXE)) { + type = HAL_RESET_COLD; + } + + if (!ar9300_set_reset_reg(ah, type)) { return AH_FALSE; } diff --git a/sys/dev/netif/ath/ath_hal/ah_devid.h b/sys/dev/netif/ath/ath_hal/ah_devid.h index 43d994dcd3..1e4d473072 100644 --- a/sys/dev/netif/ath/ath_hal/ah_devid.h +++ b/sys/dev/netif/ath/ath_hal/ah_devid.h @@ -92,6 +92,7 @@ #define AR9300_DEVID_AR946X_PCIE 0x0034 #define AR9300_DEVID_AR9330 0x0035 #define AR9300_DEVID_QCA9565 0x0036 +#define AR9300_DEVID_AR1111_PCIE 0x0037 #define AR9300_DEVID_QCA955X 0x0039 #define AR_SUBVENDOR_ID_NOG 0x0e11 /* No 11G subvendor ID */ -- 2.41.0