From 5d8e0f49ad2ab6201288c8b4f5ebb966f27e5779 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Fran=C3=A7ois=20Tigeot?= Date: Wed, 6 Apr 2016 08:40:48 +0200 Subject: [PATCH] drm/i915: Fix Baytrail hangs with deeper C-states Submitted-by: Daniel Bilik --- sys/dev/drm/i915/intel_pm.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/sys/dev/drm/i915/intel_pm.c b/sys/dev/drm/i915/intel_pm.c index c327210709..fe6e458b74 100644 --- a/sys/dev/drm/i915/intel_pm.c +++ b/sys/dev/drm/i915/intel_pm.c @@ -3991,6 +3991,13 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) break; } + if (IS_VALLEYVIEW(dev_priv)) { + ei_up = 64000; + ei_down = 64000; + threshold_up = 90; + threshold_down = 70; + } + I915_WRITE(GEN6_RP_UP_EI, GT_INTERVAL_FROM_US(dev_priv, ei_up)); I915_WRITE(GEN6_RP_UP_THRESHOLD, @@ -4084,9 +4091,21 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) val &= ~1; if (val != dev_priv->rps.cur_freq) { + u32 ctrl; + + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + ctrl = I915_READ(GEN6_RC_CONTROL); + I915_WRITE(GEN6_RC_CONTROL, 0); + vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); if (!IS_CHERRYVIEW(dev_priv)) gen6_set_rps_thresholds(dev_priv, val); + + I915_WRITE(GEN6_RC_CONTROL, ctrl); + POSTING_READ(GEN6_RC_CONTROL); + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); @@ -4109,11 +4128,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) if (dev_priv->rps.cur_freq <= val) return; - /* Wake up the media well, as that takes a lot less - * power than the Render well. */ - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); valleyview_set_rps(dev_priv->dev, val); - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); } void gen6_rps_busy(struct drm_i915_private *dev_priv) -- 2.41.0