From 9561b8dbeeba70799df48f59ecefc49b4d5ef4f9 Mon Sep 17 00:00:00 2001 From: Markus Pfeiffer Date: Sat, 18 May 2013 14:56:47 +0000 Subject: [PATCH] fix MXCSR default value XEN fails to initialise its vcpus to behave like actual cpus. One instance of this is that the MXCSR is not setup to the default value documented in as documented in AMD64 Architecture Programmer's Manual Volume 1: Application Programming, Section Section 4.3.2 --- sys/platform/pc64/x86_64/npx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sys/platform/pc64/x86_64/npx.c b/sys/platform/pc64/x86_64/npx.c index 9361d32b47..1c8243ad06 100644 --- a/sys/platform/pc64/x86_64/npx.c +++ b/sys/platform/pc64/x86_64/npx.c @@ -84,6 +84,7 @@ typedef u_char bool_t; #ifndef CPU_DISABLE_SSE static void fpu_clean_state(void); +#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) #endif static struct krate badfprate = { 1 }; @@ -99,6 +100,7 @@ npxinit(u_short control) { /*64-Byte alignment required for xsave*/ static union savefpu dummy __aligned(64); + u_int mxcsr; /* * fninit has the same h/w bugs as fnsave. Use the detoxified @@ -109,6 +111,10 @@ npxinit(u_short control) crit_enter(); stop_emulating(); fldcw(&control); + + mxcsr = __INITIAL_MXCSR__; + ldmxcsr(mxcsr); + fpusave(curthread->td_savefpu); mdcpu->gd_npxthread = NULL; start_emulating(); -- 2.41.0