From b3a9cafb3b93ad7c35efca8d0a7a3b06b0e9f61c Mon Sep 17 00:00:00 2001 From: Sepherosa Ziehau Date: Tue, 15 May 2012 13:48:54 +0800 Subject: [PATCH] pci: Update several bits for PCI Express 2.0 --- sys/bus/pci/pci.c | 21 ++++++--------------- sys/bus/pci/pcireg.h | 3 +++ 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/sys/bus/pci/pci.c b/sys/bus/pci/pci.c index 1f88becdf4..7776803240 100644 --- a/sys/bus/pci/pci.c +++ b/sys/bus/pci/pci.c @@ -734,12 +734,6 @@ pcie_slotimpl(const pcicfgregs *cfg) const struct pcicfg_expr *expr = &cfg->expr; uint16_t port_type; - /* - * Only version 1 can be parsed currently - */ - if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) - return 0; - /* * - Slot implemented bit is meaningful iff current port is * root port or down stream port. @@ -777,12 +771,6 @@ pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg) expr->expr_ptr = ptr; expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2); - /* - * Only version 1 can be parsed currently - */ - if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) - return; - /* * Read slot capabilities. Slot capabilities exists iff * current port's slot is implemented @@ -2393,8 +2381,6 @@ pci_print_verbose_expr(const pcicfgregs *cfg) kprintf("\tPCI Express ver.%d cap=0x%04x", expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap); - if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) - goto back; port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE; @@ -2420,6 +2406,12 @@ pci_print_verbose_expr(const pcicfgregs *cfg) case PCIE_PCI2PCIE_BRIDGE: port_name = "PCI2PCIE"; break; + case PCIE_ROOT_END_POINT: + port_name = "ROOTDEV"; + break; + case PCIE_ROOT_EVT_COLL: + port_name = "ROOTEVTC"; + break; default: port_name = NULL; break; @@ -2436,7 +2428,6 @@ pci_print_verbose_expr(const pcicfgregs *cfg) if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP) kprintf("[HOTPLUG]"); } -back: kprintf("\n"); } diff --git a/sys/bus/pci/pcireg.h b/sys/bus/pci/pcireg.h index 85aadc5240..cd4e734dee 100644 --- a/sys/bus/pci/pcireg.h +++ b/sys/bus/pci/pcireg.h @@ -630,6 +630,7 @@ typedef u_int32_t pcireg_t; /* ~typical configuration space */ #define PCIER_CAPABILITY 0x2 #define PCIEM_CAP_VER_MASK 0x000f /* Version */ #define PCIEM_CAP_VER_1 0x0001 +#define PCIEM_CAP_VER_2 0x0002 #define PCIEM_CAP_PORT_TYPE 0x00f0 /* Port type mask */ #define PCIEM_CAP_SLOT_IMPL 0x0100 /* Slot implemented, * valid only for root port and @@ -643,6 +644,8 @@ typedef u_int32_t pcireg_t; /* ~typical configuration space */ #define PCIE_DOWN_STREAM_PORT 0x0060 /* Switch downstream port */ #define PCIE_PCIE2PCI_BRIDGE 0x0070 /* PCI Express to PCI/PCI-X bridge */ #define PCIE_PCI2PCIE_BRIDGE 0x0080 /* PCI/PCI-X to PCI Express bridge */ +#define PCIE_ROOT_END_POINT 0x0090 /* Root Complex Integrated Endpoint */ +#define PCIE_ROOT_EVT_COLL 0x00a0 /* Root Complex Event Collector */ /* PCI Express device control, 16bits */ #define PCIER_DEVCTRL 0x08 -- 2.41.0