2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <sys/cpuset.h>
128 #include <vm/vm_param.h>
129 #include <vm/vm_kern.h>
130 #include <vm/vm_page.h>
131 #include <vm/vm_map.h>
132 #include <vm/vm_object.h>
133 #include <vm/vm_extern.h>
134 #include <vm/vm_pageout.h>
135 #include <vm/vm_pager.h>
136 #include <vm/vm_phys.h>
137 #include <vm/vm_radix.h>
138 #include <vm/vm_reserv.h>
143 #include <machine/intr_machdep.h>
144 #include <x86/apicvar.h>
146 #include <machine/cpu.h>
147 #include <machine/cputypes.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
150 #include <machine/specialreg.h>
152 #include <machine/smp.h>
156 #include <machine/xbox.h>
159 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
160 #define CPU_ENABLE_SSE
163 #ifndef PMAP_SHPGPERPROC
164 #define PMAP_SHPGPERPROC 200
167 #if !defined(DIAGNOSTIC)
168 #ifdef __GNUC_GNU_INLINE__
169 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
171 #define PMAP_INLINE extern inline
178 #define PV_STAT(x) do { x ; } while (0)
180 #define PV_STAT(x) do { } while (0)
183 #define pa_index(pa) ((pa) >> PDRSHIFT)
184 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
187 * Get PDEs and PTEs for user/kernel address space
189 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
190 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
192 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
193 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
194 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
195 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
196 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
198 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
199 atomic_clear_int((u_int *)(pte), PG_W))
200 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
202 struct pmap kernel_pmap_store;
203 LIST_HEAD(pmaplist, pmap);
204 static struct pmaplist allpmaps;
205 static struct mtx allpmaps_lock;
207 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
208 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
209 int pgeflag = 0; /* PG_G or-in */
210 int pseflag = 0; /* PG_PS or-in */
212 static int nkpt = NKPT;
213 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
214 extern u_int32_t KERNend;
215 extern u_int32_t KPTphys;
217 #if defined(PAE) || defined(PAE_TABLES)
219 static uma_zone_t pdptzone;
222 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
224 static int pat_works = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
226 "Is page attribute table fully functional?");
228 static int pg_ps_enabled = 1;
229 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
230 &pg_ps_enabled, 0, "Are large page mappings enabled?");
232 #define PAT_INDEX_SIZE 8
233 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
235 static struct rwlock_padalign pvh_global_lock;
238 * Data for the pv entry allocation mechanism
240 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
241 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
242 static struct md_page *pv_table;
243 static int shpgperproc = PMAP_SHPGPERPROC;
245 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
246 int pv_maxchunks; /* How many chunks we have KVA for */
247 vm_offset_t pv_vafree; /* freelist stored in the PTE */
250 * All those kernel PT submaps that BSD is so fond of
259 static struct sysmaps sysmaps_pcpu[MAXCPU];
261 static pd_entry_t *KPTD;
264 struct msgbuf *msgbufp = 0;
269 static caddr_t crashdumpmap;
271 static pt_entry_t *PMAP1 = 0, *PMAP2;
272 static pt_entry_t *PADDR1 = 0, *PADDR2;
275 static int PMAP1changedcpu;
276 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
278 "Number of times pmap_pte_quick changed CPU with same PMAP1");
280 static int PMAP1changed;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
283 "Number of times pmap_pte_quick changed PMAP1");
284 static int PMAP1unchanged;
285 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
287 "Number of times pmap_pte_quick didn't change PMAP1");
288 static struct mtx PMAP2mutex;
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
293 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
294 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
295 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
309 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
310 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
311 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
312 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
313 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
314 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
315 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
318 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
319 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
320 struct spglist *free);
321 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
322 struct spglist *free);
323 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
324 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
325 struct spglist *free);
326 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
328 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
329 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
331 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
333 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
335 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
337 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
338 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
339 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
340 static void pmap_pte_release(pt_entry_t *pte);
341 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
342 #if defined(PAE) || defined(PAE_TABLES)
343 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
346 static void pmap_set_pg(void);
348 static __inline void pagezero(void *page);
350 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
351 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
354 * If you get an error here, then you set KVA_PAGES wrong! See the
355 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
356 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
358 CTASSERT(KERNBASE % (1 << 24) == 0);
361 * Bootstrap the system enough to run with virtual memory.
363 * On the i386 this is called after mapping has already been enabled
364 * and just syncs the pmap module with what has already been done.
365 * [We can't call it easily with mapping off since the kernel is not
366 * mapped with PA == VA, hence we would have to relocate every address
367 * from the linked base (virtual) address "KERNBASE" to the actual
368 * (physical) address starting relative to 0]
371 pmap_bootstrap(vm_paddr_t firstaddr)
374 pt_entry_t *pte, *unused;
375 struct sysmaps *sysmaps;
379 * Add a physical memory segment (vm_phys_seg) corresponding to the
380 * preallocated kernel page table pages so that vm_page structures
381 * representing these pages will be created. The vm_page structures
382 * are required for promotion of the corresponding kernel virtual
383 * addresses to superpage mappings.
385 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
388 * Initialize the first available kernel virtual address. However,
389 * using "firstaddr" may waste a few pages of the kernel virtual
390 * address space, because locore may not have mapped every physical
391 * page that it allocated. Preferably, locore would provide a first
392 * unused virtual address in addition to "firstaddr".
394 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
396 virtual_end = VM_MAX_KERNEL_ADDRESS;
399 * Initialize the kernel pmap (which is statically allocated).
401 PMAP_LOCK_INIT(kernel_pmap);
402 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
403 #if defined(PAE) || defined(PAE_TABLES)
404 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
406 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
407 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
410 * Initialize the global pv list lock.
412 rw_init(&pvh_global_lock, "pmap pv global");
414 LIST_INIT(&allpmaps);
417 * Request a spin mutex so that changes to allpmaps cannot be
418 * preempted by smp_rendezvous_cpus(). Otherwise,
419 * pmap_update_pde_kernel() could access allpmaps while it is
422 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
423 mtx_lock_spin(&allpmaps_lock);
424 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
425 mtx_unlock_spin(&allpmaps_lock);
428 * Reserve some special page table entries/VA space for temporary
431 #define SYSMAP(c, p, v, n) \
432 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
438 * CMAP1/CMAP2 are used for zeroing and copying pages.
439 * CMAP3 is used for the idle process page zeroing.
441 for (i = 0; i < MAXCPU; i++) {
442 sysmaps = &sysmaps_pcpu[i];
443 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
444 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
445 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
447 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
452 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
455 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
457 SYSMAP(caddr_t, unused, ptvmmap, 1)
460 * msgbufp is used to map the system message buffer.
462 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
465 * KPTmap is used by pmap_kextract().
467 * KPTmap is first initialized by locore. However, that initial
468 * KPTmap can only support NKPT page table pages. Here, a larger
469 * KPTmap is created that can support KVA_PAGES page table pages.
471 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
473 for (i = 0; i < NKPT; i++)
474 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
477 * Adjust the start of the KPTD and KPTmap so that the implementation
478 * of pmap_kextract() and pmap_growkernel() can be made simpler.
481 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
484 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
487 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
488 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
490 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
495 * Leave in place an identity mapping (virt == phys) for the low 1 MB
496 * physical memory region that is used by the ACPI wakeup code. This
497 * mapping must not have PG_G set.
500 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
501 * an early stadium, we cannot yet neatly map video memory ... :-(
502 * Better fixes are very welcome! */
503 if (!arch_i386_is_xbox)
505 for (i = 1; i < NKPT; i++)
508 /* Initialize the PAT MSR if present. */
511 /* Turn on PG_G on kernel page(s) */
521 int pat_table[PAT_INDEX_SIZE];
526 /* Set default PAT index table. */
527 for (i = 0; i < PAT_INDEX_SIZE; i++)
529 pat_table[PAT_WRITE_BACK] = 0;
530 pat_table[PAT_WRITE_THROUGH] = 1;
531 pat_table[PAT_UNCACHEABLE] = 3;
532 pat_table[PAT_WRITE_COMBINING] = 3;
533 pat_table[PAT_WRITE_PROTECTED] = 3;
534 pat_table[PAT_UNCACHED] = 3;
536 /* Bail if this CPU doesn't implement PAT. */
537 if ((cpu_feature & CPUID_PAT) == 0) {
538 for (i = 0; i < PAT_INDEX_SIZE; i++)
539 pat_index[i] = pat_table[i];
545 * Due to some Intel errata, we can only safely use the lower 4
548 * Intel Pentium III Processor Specification Update
549 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
552 * Intel Pentium IV Processor Specification Update
553 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
555 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
556 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
559 /* Initialize default PAT entries. */
560 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
561 PAT_VALUE(1, PAT_WRITE_THROUGH) |
562 PAT_VALUE(2, PAT_UNCACHED) |
563 PAT_VALUE(3, PAT_UNCACHEABLE) |
564 PAT_VALUE(4, PAT_WRITE_BACK) |
565 PAT_VALUE(5, PAT_WRITE_THROUGH) |
566 PAT_VALUE(6, PAT_UNCACHED) |
567 PAT_VALUE(7, PAT_UNCACHEABLE);
571 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
572 * Program 5 and 6 as WP and WC.
573 * Leave 4 and 7 as WB and UC.
575 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
576 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
577 PAT_VALUE(6, PAT_WRITE_COMBINING);
578 pat_table[PAT_UNCACHED] = 2;
579 pat_table[PAT_WRITE_PROTECTED] = 5;
580 pat_table[PAT_WRITE_COMBINING] = 6;
583 * Just replace PAT Index 2 with WC instead of UC-.
585 pat_msr &= ~PAT_MASK(2);
586 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
587 pat_table[PAT_WRITE_COMBINING] = 2;
592 load_cr4(cr4 & ~CR4_PGE);
594 /* Disable caches (CD = 1, NW = 0). */
596 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
598 /* Flushes caches and TLBs. */
602 /* Update PAT and index table. */
603 wrmsr(MSR_PAT, pat_msr);
604 for (i = 0; i < PAT_INDEX_SIZE; i++)
605 pat_index[i] = pat_table[i];
607 /* Flush caches and TLBs again. */
611 /* Restore caches and PGE. */
617 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
623 vm_offset_t va, endva;
628 endva = KERNBASE + KERNend;
631 va = KERNBASE + KERNLOAD;
633 pdir_pde(PTD, va) |= pgeflag;
634 invltlb(); /* Play it safe, invltlb() every time */
638 va = (vm_offset_t)btext;
643 invltlb(); /* Play it safe, invltlb() every time */
650 * Initialize a vm_page's machine-dependent fields.
653 pmap_page_init(vm_page_t m)
656 TAILQ_INIT(&m->md.pv_list);
657 m->md.pat_mode = PAT_WRITE_BACK;
660 #if defined(PAE) || defined(PAE_TABLES)
662 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
665 /* Inform UMA that this allocator uses kernel_map/object. */
666 *flags = UMA_SLAB_KERNEL;
667 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
668 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
673 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
675 * - Must deal with pages in order to ensure that none of the PG_* bits
676 * are ever set, PG_V in particular.
677 * - Assumes we can write to ptes without pte_store() atomic ops, even
678 * on PAE systems. This should be ok.
679 * - Assumes nothing will ever test these addresses for 0 to indicate
680 * no mapping instead of correctly checking PG_V.
681 * - Assumes a vm_offset_t will fit in a pte (true for i386).
682 * Because PG_V is never set, there can be no mappings to invalidate.
685 pmap_ptelist_alloc(vm_offset_t *head)
692 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
696 panic("pmap_ptelist_alloc: va with PG_V set!");
702 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
707 panic("pmap_ptelist_free: freeing va with PG_V set!");
709 *pte = *head; /* virtual! PG_V is 0 though */
714 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
720 for (i = npages - 1; i >= 0; i--) {
721 va = (vm_offset_t)base + i * PAGE_SIZE;
722 pmap_ptelist_free(head, va);
728 * Initialize the pmap module.
729 * Called by vm_init, to initialize any structures that the pmap
730 * system needs to map virtual memory.
740 * Initialize the vm page array entries for the kernel pmap's
743 for (i = 0; i < NKPT; i++) {
744 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
745 KASSERT(mpte >= vm_page_array &&
746 mpte < &vm_page_array[vm_page_array_size],
747 ("pmap_init: page table page is out of range"));
748 mpte->pindex = i + KPTDI;
749 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
753 * Initialize the address space (zone) for the pv entries. Set a
754 * high water mark so that the system can recover from excessive
755 * numbers of pv entries.
757 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
758 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
759 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
760 pv_entry_max = roundup(pv_entry_max, _NPCPV);
761 pv_entry_high_water = 9 * (pv_entry_max / 10);
764 * If the kernel is running on a virtual machine, then it must assume
765 * that MCA is enabled by the hypervisor. Moreover, the kernel must
766 * be prepared for the hypervisor changing the vendor and family that
767 * are reported by CPUID. Consequently, the workaround for AMD Family
768 * 10h Erratum 383 is enabled if the processor's feature set does not
769 * include at least one feature that is only supported by older Intel
770 * or newer AMD processors.
772 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
773 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
774 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
776 workaround_erratum383 = 1;
779 * Are large page mappings supported and enabled?
781 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
784 else if (pg_ps_enabled) {
785 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
786 ("pmap_init: can't assign to pagesizes[1]"));
787 pagesizes[1] = NBPDR;
791 * Calculate the size of the pv head table for superpages.
792 * Handle the possibility that "vm_phys_segs[...].end" is zero.
794 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
795 PAGE_SIZE) / NBPDR + 1;
798 * Allocate memory for the pv head table for superpages.
800 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
802 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
804 for (i = 0; i < pv_npg; i++)
805 TAILQ_INIT(&pv_table[i].pv_list);
807 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
808 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
809 if (pv_chunkbase == NULL)
810 panic("pmap_init: not enough kvm for pv chunks");
811 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
812 #if defined(PAE) || defined(PAE_TABLES)
813 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
814 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
815 UMA_ZONE_VM | UMA_ZONE_NOFREE);
816 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
821 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
822 "Max number of PV entries");
823 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
824 "Page share factor per proc");
826 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
827 "2/4MB page mapping counters");
829 static u_long pmap_pde_demotions;
830 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
831 &pmap_pde_demotions, 0, "2/4MB page demotions");
833 static u_long pmap_pde_mappings;
834 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
835 &pmap_pde_mappings, 0, "2/4MB page mappings");
837 static u_long pmap_pde_p_failures;
838 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
839 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
841 static u_long pmap_pde_promotions;
842 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
843 &pmap_pde_promotions, 0, "2/4MB page promotions");
845 /***************************************************
846 * Low level helper routines.....
847 ***************************************************/
850 * Determine the appropriate bits to set in a PTE or PDE for a specified
854 pmap_cache_bits(int mode, boolean_t is_pde)
856 int cache_bits, pat_flag, pat_idx;
858 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
859 panic("Unknown caching mode %d\n", mode);
861 /* The PAT bit is different for PTE's and PDE's. */
862 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
864 /* Map the caching mode to a PAT index. */
865 pat_idx = pat_index[mode];
867 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
870 cache_bits |= pat_flag;
872 cache_bits |= PG_NC_PCD;
874 cache_bits |= PG_NC_PWT;
879 * The caller is responsible for maintaining TLB consistency.
882 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
886 boolean_t PTD_updated;
889 mtx_lock_spin(&allpmaps_lock);
890 LIST_FOREACH(pmap, &allpmaps, pm_list) {
891 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
894 pde = pmap_pde(pmap, va);
895 pde_store(pde, newpde);
897 mtx_unlock_spin(&allpmaps_lock);
899 ("pmap_kenter_pde: current page table is not in allpmaps"));
903 * After changing the page size for the specified virtual address in the page
904 * table, flush the corresponding entries from the processor's TLB. Only the
905 * calling processor's TLB is affected.
907 * The calling thread must be pinned to a processor.
910 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
914 if ((newpde & PG_PS) == 0)
915 /* Demotion: flush a specific 2MB page mapping. */
917 else if ((newpde & PG_G) == 0)
919 * Promotion: flush every 4KB page mapping from the TLB
920 * because there are too many to flush individually.
925 * Promotion: flush every 4KB page mapping from the TLB,
926 * including any global (PG_G) mappings.
929 load_cr4(cr4 & ~CR4_PGE);
931 * Although preemption at this point could be detrimental to
932 * performance, it would not lead to an error. PG_G is simply
933 * ignored if CR4.PGE is clear. Moreover, in case this block
934 * is re-entered, the load_cr4() either above or below will
935 * modify CR4.PGE flushing the TLB.
937 load_cr4(cr4 | CR4_PGE);
942 * For SMP, these functions have to use the IPI mechanism for coherence.
944 * N.B.: Before calling any of the following TLB invalidation functions,
945 * the calling processor must ensure that all stores updating a non-
946 * kernel page table are globally performed. Otherwise, another
947 * processor could cache an old, pre-update entry without being
948 * invalidated. This can happen one of two ways: (1) The pmap becomes
949 * active on another processor after its pm_active field is checked by
950 * one of the following functions but before a store updating the page
951 * table is globally performed. (2) The pmap becomes active on another
952 * processor before its pm_active field is checked but due to
953 * speculative loads one of the following functions stills reads the
954 * pmap as inactive on the other processor.
956 * The kernel page table is exempt because its pm_active field is
957 * immutable. The kernel page table is always active on every
961 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
967 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
971 cpuid = PCPU_GET(cpuid);
972 other_cpus = all_cpus;
973 CPU_CLR(cpuid, &other_cpus);
974 if (CPU_ISSET(cpuid, &pmap->pm_active))
976 CPU_AND(&other_cpus, &pmap->pm_active);
977 if (!CPU_EMPTY(&other_cpus))
978 smp_masked_invlpg(other_cpus, va);
984 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
991 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
992 for (addr = sva; addr < eva; addr += PAGE_SIZE)
994 smp_invlpg_range(sva, eva);
996 cpuid = PCPU_GET(cpuid);
997 other_cpus = all_cpus;
998 CPU_CLR(cpuid, &other_cpus);
999 if (CPU_ISSET(cpuid, &pmap->pm_active))
1000 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1002 CPU_AND(&other_cpus, &pmap->pm_active);
1003 if (!CPU_EMPTY(&other_cpus))
1004 smp_masked_invlpg_range(other_cpus, sva, eva);
1010 pmap_invalidate_all(pmap_t pmap)
1012 cpuset_t other_cpus;
1016 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1020 cpuid = PCPU_GET(cpuid);
1021 other_cpus = all_cpus;
1022 CPU_CLR(cpuid, &other_cpus);
1023 if (CPU_ISSET(cpuid, &pmap->pm_active))
1025 CPU_AND(&other_cpus, &pmap->pm_active);
1026 if (!CPU_EMPTY(&other_cpus))
1027 smp_masked_invltlb(other_cpus);
1033 pmap_invalidate_cache(void)
1043 cpuset_t invalidate; /* processors that invalidate their TLB */
1047 u_int store; /* processor that updates the PDE */
1051 pmap_update_pde_kernel(void *arg)
1053 struct pde_action *act = arg;
1057 if (act->store == PCPU_GET(cpuid)) {
1060 * Elsewhere, this operation requires allpmaps_lock for
1061 * synchronization. Here, it does not because it is being
1062 * performed in the context of an all_cpus rendezvous.
1064 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1065 pde = pmap_pde(pmap, act->va);
1066 pde_store(pde, act->newpde);
1072 pmap_update_pde_user(void *arg)
1074 struct pde_action *act = arg;
1076 if (act->store == PCPU_GET(cpuid))
1077 pde_store(act->pde, act->newpde);
1081 pmap_update_pde_teardown(void *arg)
1083 struct pde_action *act = arg;
1085 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1086 pmap_update_pde_invalidate(act->va, act->newpde);
1090 * Change the page size for the specified virtual address in a way that
1091 * prevents any possibility of the TLB ever having two entries that map the
1092 * same virtual address using different page sizes. This is the recommended
1093 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1094 * machine check exception for a TLB state that is improperly diagnosed as a
1098 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1100 struct pde_action act;
1101 cpuset_t active, other_cpus;
1105 cpuid = PCPU_GET(cpuid);
1106 other_cpus = all_cpus;
1107 CPU_CLR(cpuid, &other_cpus);
1108 if (pmap == kernel_pmap)
1111 active = pmap->pm_active;
1112 if (CPU_OVERLAP(&active, &other_cpus)) {
1114 act.invalidate = active;
1117 act.newpde = newpde;
1118 CPU_SET(cpuid, &active);
1119 smp_rendezvous_cpus(active,
1120 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1121 pmap_update_pde_kernel : pmap_update_pde_user,
1122 pmap_update_pde_teardown, &act);
1124 if (pmap == kernel_pmap)
1125 pmap_kenter_pde(va, newpde);
1127 pde_store(pde, newpde);
1128 if (CPU_ISSET(cpuid, &active))
1129 pmap_update_pde_invalidate(va, newpde);
1135 * Normal, non-SMP, 486+ invalidation functions.
1136 * We inline these within pmap.c for speed.
1139 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1142 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1147 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1151 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1152 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1157 pmap_invalidate_all(pmap_t pmap)
1160 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1165 pmap_invalidate_cache(void)
1172 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1175 if (pmap == kernel_pmap)
1176 pmap_kenter_pde(va, newpde);
1178 pde_store(pde, newpde);
1179 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1180 pmap_update_pde_invalidate(va, newpde);
1184 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1187 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1191 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1193 KASSERT((sva & PAGE_MASK) == 0,
1194 ("pmap_invalidate_cache_range: sva not page-aligned"));
1195 KASSERT((eva & PAGE_MASK) == 0,
1196 ("pmap_invalidate_cache_range: eva not page-aligned"));
1199 if ((cpu_feature & CPUID_SS) != 0 && !force)
1200 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1201 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1202 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1206 * XXX: Some CPUs fault, hang, or trash the local APIC
1207 * registers if we use CLFLUSH on the local APIC
1208 * range. The local APIC is always uncached, so we
1209 * don't need to flush for that range anyway.
1211 if (pmap_kextract(sva) == lapic_paddr)
1215 * Otherwise, do per-cache line flush. Use the mfence
1216 * instruction to insure that previous stores are
1217 * included in the write-back. The processor
1218 * propagates flush to other processors in the cache
1222 for (; sva < eva; sva += cpu_clflush_line_size)
1228 * No targeted cache flush methods are supported by CPU,
1229 * or the supplied range is bigger than 2MB.
1230 * Globally invalidate cache.
1232 pmap_invalidate_cache();
1237 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1241 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1242 (cpu_feature & CPUID_CLFSH) == 0) {
1243 pmap_invalidate_cache();
1245 for (i = 0; i < count; i++)
1246 pmap_flush_page(pages[i]);
1251 * Are we current address space or kernel?
1254 pmap_is_current(pmap_t pmap)
1257 return (pmap == kernel_pmap || pmap ==
1258 vmspace_pmap(curthread->td_proc->p_vmspace));
1262 * If the given pmap is not the current or kernel pmap, the returned pte must
1263 * be released by passing it to pmap_pte_release().
1266 pmap_pte(pmap_t pmap, vm_offset_t va)
1271 pde = pmap_pde(pmap, va);
1275 /* are we current address space or kernel? */
1276 if (pmap_is_current(pmap))
1277 return (vtopte(va));
1278 mtx_lock(&PMAP2mutex);
1279 newpf = *pde & PG_FRAME;
1280 if ((*PMAP2 & PG_FRAME) != newpf) {
1281 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1282 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1284 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1290 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1293 static __inline void
1294 pmap_pte_release(pt_entry_t *pte)
1297 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1298 mtx_unlock(&PMAP2mutex);
1302 * NB: The sequence of updating a page table followed by accesses to the
1303 * corresponding pages is subject to the situation described in the "AMD64
1304 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1305 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1306 * right after modifying the PTE bits is crucial.
1308 static __inline void
1309 invlcaddr(void *caddr)
1312 invlpg((u_int)caddr);
1316 * Super fast pmap_pte routine best used when scanning
1317 * the pv lists. This eliminates many coarse-grained
1318 * invltlb calls. Note that many of the pv list
1319 * scans are across different pmaps. It is very wasteful
1320 * to do an entire invltlb for checking a single mapping.
1322 * If the given pmap is not the current pmap, pvh_global_lock
1323 * must be held and curthread pinned to a CPU.
1326 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1331 pde = pmap_pde(pmap, va);
1335 /* are we current address space or kernel? */
1336 if (pmap_is_current(pmap))
1337 return (vtopte(va));
1338 rw_assert(&pvh_global_lock, RA_WLOCKED);
1339 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1340 newpf = *pde & PG_FRAME;
1341 if ((*PMAP1 & PG_FRAME) != newpf) {
1342 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1344 PMAP1cpu = PCPU_GET(cpuid);
1350 if (PMAP1cpu != PCPU_GET(cpuid)) {
1351 PMAP1cpu = PCPU_GET(cpuid);
1357 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1363 * Routine: pmap_extract
1365 * Extract the physical page address associated
1366 * with the given map/virtual_address pair.
1369 pmap_extract(pmap_t pmap, vm_offset_t va)
1377 pde = pmap->pm_pdir[va >> PDRSHIFT];
1379 if ((pde & PG_PS) != 0)
1380 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1382 pte = pmap_pte(pmap, va);
1383 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1384 pmap_pte_release(pte);
1392 * Routine: pmap_extract_and_hold
1394 * Atomically extract and hold the physical page
1395 * with the given pmap and virtual address pair
1396 * if that mapping permits the given protection.
1399 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1402 pt_entry_t pte, *ptep;
1410 pde = *pmap_pde(pmap, va);
1413 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1414 if (vm_page_pa_tryrelock(pmap, (pde &
1415 PG_PS_FRAME) | (va & PDRMASK), &pa))
1417 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1422 ptep = pmap_pte(pmap, va);
1424 pmap_pte_release(ptep);
1426 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1427 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1430 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1440 /***************************************************
1441 * Low level mapping routines.....
1442 ***************************************************/
1445 * Add a wired page to the kva.
1446 * Note: not SMP coherent.
1448 * This function may be used before pmap_bootstrap() is called.
1451 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1456 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1459 static __inline void
1460 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1465 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1469 * Remove a page from the kernel pagetables.
1470 * Note: not SMP coherent.
1472 * This function may be used before pmap_bootstrap() is called.
1475 pmap_kremove(vm_offset_t va)
1484 * Used to map a range of physical addresses into kernel
1485 * virtual address space.
1487 * The value passed in '*virt' is a suggested virtual address for
1488 * the mapping. Architectures which can support a direct-mapped
1489 * physical to virtual region can return the appropriate address
1490 * within that region, leaving '*virt' unchanged. Other
1491 * architectures should map the pages starting at '*virt' and
1492 * update '*virt' with the first usable address after the mapped
1496 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1498 vm_offset_t va, sva;
1499 vm_paddr_t superpage_offset;
1504 * Does the physical address range's size and alignment permit at
1505 * least one superpage mapping to be created?
1507 superpage_offset = start & PDRMASK;
1508 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1510 * Increase the starting virtual address so that its alignment
1511 * does not preclude the use of superpage mappings.
1513 if ((va & PDRMASK) < superpage_offset)
1514 va = (va & ~PDRMASK) + superpage_offset;
1515 else if ((va & PDRMASK) > superpage_offset)
1516 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1519 while (start < end) {
1520 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1522 KASSERT((va & PDRMASK) == 0,
1523 ("pmap_map: misaligned va %#x", va));
1524 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1525 pmap_kenter_pde(va, newpde);
1529 pmap_kenter(va, start);
1534 pmap_invalidate_range(kernel_pmap, sva, va);
1541 * Add a list of wired pages to the kva
1542 * this routine is only used for temporary
1543 * kernel mappings that do not need to have
1544 * page modification or references recorded.
1545 * Note that old mappings are simply written
1546 * over. The page *must* be wired.
1547 * Note: SMP coherent. Uses a ranged shootdown IPI.
1550 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1552 pt_entry_t *endpte, oldpte, pa, *pte;
1557 endpte = pte + count;
1558 while (pte < endpte) {
1560 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1561 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1563 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1567 if (__predict_false((oldpte & PG_V) != 0))
1568 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1573 * This routine tears out page mappings from the
1574 * kernel -- it is meant only for temporary mappings.
1575 * Note: SMP coherent. Uses a ranged shootdown IPI.
1578 pmap_qremove(vm_offset_t sva, int count)
1583 while (count-- > 0) {
1587 pmap_invalidate_range(kernel_pmap, sva, va);
1590 /***************************************************
1591 * Page table page management routines.....
1592 ***************************************************/
1593 static __inline void
1594 pmap_free_zero_pages(struct spglist *free)
1598 while ((m = SLIST_FIRST(free)) != NULL) {
1599 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1600 /* Preserve the page's PG_ZERO setting. */
1601 vm_page_free_toq(m);
1606 * Schedule the specified unused page table page to be freed. Specifically,
1607 * add the page to the specified list of pages that will be released to the
1608 * physical memory manager after the TLB has been updated.
1610 static __inline void
1611 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1612 boolean_t set_PG_ZERO)
1616 m->flags |= PG_ZERO;
1618 m->flags &= ~PG_ZERO;
1619 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1623 * Inserts the specified page table page into the specified pmap's collection
1624 * of idle page table pages. Each of a pmap's page table pages is responsible
1625 * for mapping a distinct range of virtual addresses. The pmap's collection is
1626 * ordered by this virtual address range.
1629 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1632 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1633 return (vm_radix_insert(&pmap->pm_root, mpte));
1637 * Looks for a page table page mapping the specified virtual address in the
1638 * specified pmap's collection of idle page table pages. Returns NULL if there
1639 * is no page table page corresponding to the specified virtual address.
1641 static __inline vm_page_t
1642 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1645 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1646 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1650 * Removes the specified page table page from the specified pmap's collection
1651 * of idle page table pages. The specified page table page must be a member of
1652 * the pmap's collection.
1654 static __inline void
1655 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1658 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1659 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1663 * Decrements a page table page's wire count, which is used to record the
1664 * number of valid page table entries within the page. If the wire count
1665 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1666 * page table page was unmapped and FALSE otherwise.
1668 static inline boolean_t
1669 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1673 if (m->wire_count == 0) {
1674 _pmap_unwire_ptp(pmap, m, free);
1681 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1686 * unmap the page table page
1688 pmap->pm_pdir[m->pindex] = 0;
1689 --pmap->pm_stats.resident_count;
1692 * This is a release store so that the ordinary store unmapping
1693 * the page table page is globally performed before TLB shoot-
1696 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1699 * Do an invltlb to make the invalidated mapping
1700 * take effect immediately.
1702 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1703 pmap_invalidate_page(pmap, pteva);
1706 * Put page on a list so that it is released after
1707 * *ALL* TLB shootdown is done
1709 pmap_add_delayed_free_list(m, free, TRUE);
1713 * After removing a page table entry, this routine is used to
1714 * conditionally free the page, and manage the hold/wire counts.
1717 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1722 if (va >= VM_MAXUSER_ADDRESS)
1724 ptepde = *pmap_pde(pmap, va);
1725 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1726 return (pmap_unwire_ptp(pmap, mpte, free));
1730 * Initialize the pmap for the swapper process.
1733 pmap_pinit0(pmap_t pmap)
1736 PMAP_LOCK_INIT(pmap);
1738 * Since the page table directory is shared with the kernel pmap,
1739 * which is already included in the list "allpmaps", this pmap does
1740 * not need to be inserted into that list.
1742 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1743 #if defined(PAE) || defined(PAE_TABLES)
1744 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1746 pmap->pm_root.rt_root = 0;
1747 CPU_ZERO(&pmap->pm_active);
1748 PCPU_SET(curpmap, pmap);
1749 TAILQ_INIT(&pmap->pm_pvchunk);
1750 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1754 * Initialize a preallocated and zeroed pmap structure,
1755 * such as one in a vmspace structure.
1758 pmap_pinit(pmap_t pmap)
1760 vm_page_t m, ptdpg[NPGPTD];
1765 * No need to allocate page table space yet but we do need a valid
1766 * page directory table.
1768 if (pmap->pm_pdir == NULL) {
1769 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1770 if (pmap->pm_pdir == NULL)
1772 #if defined(PAE) || defined(PAE_TABLES)
1773 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1774 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1775 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1776 ("pmap_pinit: pdpt misaligned"));
1777 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1778 ("pmap_pinit: pdpt above 4g"));
1780 pmap->pm_root.rt_root = 0;
1782 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1783 ("pmap_pinit: pmap has reserved page table page(s)"));
1786 * allocate the page directory page(s)
1788 for (i = 0; i < NPGPTD;) {
1789 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1790 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1798 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1800 for (i = 0; i < NPGPTD; i++)
1801 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1802 pagezero(pmap->pm_pdir + (i * NPDEPG));
1804 mtx_lock_spin(&allpmaps_lock);
1805 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1806 /* Copy the kernel page table directory entries. */
1807 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1808 mtx_unlock_spin(&allpmaps_lock);
1810 /* install self-referential address mapping entry(s) */
1811 for (i = 0; i < NPGPTD; i++) {
1812 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1813 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1814 #if defined(PAE) || defined(PAE_TABLES)
1815 pmap->pm_pdpt[i] = pa | PG_V;
1819 CPU_ZERO(&pmap->pm_active);
1820 TAILQ_INIT(&pmap->pm_pvchunk);
1821 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1827 * this routine is called if the page table page is not
1831 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1837 * Allocate a page table page.
1839 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1840 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1841 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1843 rw_wunlock(&pvh_global_lock);
1845 rw_wlock(&pvh_global_lock);
1850 * Indicate the need to retry. While waiting, the page table
1851 * page may have been allocated.
1855 if ((m->flags & PG_ZERO) == 0)
1859 * Map the pagetable page into the process address space, if
1860 * it isn't already there.
1863 pmap->pm_stats.resident_count++;
1865 ptepa = VM_PAGE_TO_PHYS(m);
1866 pmap->pm_pdir[ptepindex] =
1867 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1873 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1880 * Calculate pagetable page index
1882 ptepindex = va >> PDRSHIFT;
1885 * Get the page directory entry
1887 ptepa = pmap->pm_pdir[ptepindex];
1890 * This supports switching from a 4MB page to a
1893 if (ptepa & PG_PS) {
1894 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1895 ptepa = pmap->pm_pdir[ptepindex];
1899 * If the page table page is mapped, we just increment the
1900 * hold count, and activate it.
1903 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1907 * Here if the pte page isn't mapped, or if it has
1910 m = _pmap_allocpte(pmap, ptepindex, flags);
1911 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1918 /***************************************************
1919 * Pmap allocation/deallocation routines.
1920 ***************************************************/
1923 * Release any resources held by the given physical map.
1924 * Called when a pmap initialized by pmap_pinit is being released.
1925 * Should only be called if the map contains no valid mappings.
1928 pmap_release(pmap_t pmap)
1930 vm_page_t m, ptdpg[NPGPTD];
1933 KASSERT(pmap->pm_stats.resident_count == 0,
1934 ("pmap_release: pmap resident count %ld != 0",
1935 pmap->pm_stats.resident_count));
1936 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1937 ("pmap_release: pmap has reserved page table page(s)"));
1938 KASSERT(CPU_EMPTY(&pmap->pm_active),
1939 ("releasing active pmap %p", pmap));
1941 mtx_lock_spin(&allpmaps_lock);
1942 LIST_REMOVE(pmap, pm_list);
1943 mtx_unlock_spin(&allpmaps_lock);
1945 for (i = 0; i < NPGPTD; i++)
1946 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
1949 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
1950 sizeof(*pmap->pm_pdir));
1952 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
1954 for (i = 0; i < NPGPTD; i++) {
1956 #if defined(PAE) || defined(PAE_TABLES)
1957 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
1958 ("pmap_release: got wrong ptd page"));
1961 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1962 vm_page_free_zero(m);
1967 kvm_size(SYSCTL_HANDLER_ARGS)
1969 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
1971 return (sysctl_handle_long(oidp, &ksize, 0, req));
1973 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1974 0, 0, kvm_size, "IU", "Size of KVM");
1977 kvm_free(SYSCTL_HANDLER_ARGS)
1979 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1981 return (sysctl_handle_long(oidp, &kfree, 0, req));
1983 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1984 0, 0, kvm_free, "IU", "Amount of KVM free");
1987 * grow the number of kernel page table entries, if needed
1990 pmap_growkernel(vm_offset_t addr)
1992 vm_paddr_t ptppaddr;
1996 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1997 addr = roundup2(addr, NBPDR);
1998 if (addr - 1 >= kernel_map->max_offset)
1999 addr = kernel_map->max_offset;
2000 while (kernel_vm_end < addr) {
2001 if (pdir_pde(PTD, kernel_vm_end)) {
2002 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2003 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2004 kernel_vm_end = kernel_map->max_offset;
2010 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2011 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2014 panic("pmap_growkernel: no memory to grow kernel");
2018 if ((nkpg->flags & PG_ZERO) == 0)
2019 pmap_zero_page(nkpg);
2020 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2021 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2022 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2024 pmap_kenter_pde(kernel_vm_end, newpdir);
2025 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2026 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2027 kernel_vm_end = kernel_map->max_offset;
2034 /***************************************************
2035 * page management routines.
2036 ***************************************************/
2038 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2039 CTASSERT(_NPCM == 11);
2040 CTASSERT(_NPCPV == 336);
2042 static __inline struct pv_chunk *
2043 pv_to_chunk(pv_entry_t pv)
2046 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2049 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2051 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2052 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2054 static const uint32_t pc_freemask[_NPCM] = {
2055 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2056 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2057 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2058 PC_FREE0_9, PC_FREE10
2061 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2062 "Current number of pv entries");
2065 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2067 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2068 "Current number of pv entry chunks");
2069 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2070 "Current number of pv entry chunks allocated");
2071 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2072 "Current number of pv entry chunks frees");
2073 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2074 "Number of times tried to get a chunk page but failed.");
2076 static long pv_entry_frees, pv_entry_allocs;
2077 static int pv_entry_spare;
2079 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2080 "Current number of pv entry frees");
2081 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2082 "Current number of pv entry allocs");
2083 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2084 "Current number of spare pv entries");
2088 * We are in a serious low memory condition. Resort to
2089 * drastic measures to free some pages so we can allocate
2090 * another pv entry chunk.
2093 pmap_pv_reclaim(pmap_t locked_pmap)
2096 struct pv_chunk *pc;
2097 struct md_page *pvh;
2100 pt_entry_t *pte, tpte;
2104 struct spglist free;
2106 int bit, field, freed;
2108 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2112 TAILQ_INIT(&newtail);
2113 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2114 SLIST_EMPTY(&free))) {
2115 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2116 if (pmap != pc->pc_pmap) {
2118 pmap_invalidate_all(pmap);
2119 if (pmap != locked_pmap)
2123 /* Avoid deadlock and lock recursion. */
2124 if (pmap > locked_pmap)
2126 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2128 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2134 * Destroy every non-wired, 4 KB page mapping in the chunk.
2137 for (field = 0; field < _NPCM; field++) {
2138 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2139 inuse != 0; inuse &= ~(1UL << bit)) {
2141 pv = &pc->pc_pventry[field * 32 + bit];
2143 pde = pmap_pde(pmap, va);
2144 if ((*pde & PG_PS) != 0)
2146 pte = pmap_pte(pmap, va);
2148 if ((tpte & PG_W) == 0)
2149 tpte = pte_load_clear(pte);
2150 pmap_pte_release(pte);
2151 if ((tpte & PG_W) != 0)
2154 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2156 if ((tpte & PG_G) != 0)
2157 pmap_invalidate_page(pmap, va);
2158 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2159 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2161 if ((tpte & PG_A) != 0)
2162 vm_page_aflag_set(m, PGA_REFERENCED);
2163 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2164 if (TAILQ_EMPTY(&m->md.pv_list) &&
2165 (m->flags & PG_FICTITIOUS) == 0) {
2166 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2167 if (TAILQ_EMPTY(&pvh->pv_list)) {
2168 vm_page_aflag_clear(m,
2172 pc->pc_map[field] |= 1UL << bit;
2173 pmap_unuse_pt(pmap, va, &free);
2178 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2181 /* Every freed mapping is for a 4 KB page. */
2182 pmap->pm_stats.resident_count -= freed;
2183 PV_STAT(pv_entry_frees += freed);
2184 PV_STAT(pv_entry_spare += freed);
2185 pv_entry_count -= freed;
2186 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2187 for (field = 0; field < _NPCM; field++)
2188 if (pc->pc_map[field] != pc_freemask[field]) {
2189 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2191 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2194 * One freed pv entry in locked_pmap is
2197 if (pmap == locked_pmap)
2201 if (field == _NPCM) {
2202 PV_STAT(pv_entry_spare -= _NPCPV);
2203 PV_STAT(pc_chunk_count--);
2204 PV_STAT(pc_chunk_frees++);
2205 /* Entire chunk is free; return it. */
2206 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2207 pmap_qremove((vm_offset_t)pc, 1);
2208 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2213 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2215 pmap_invalidate_all(pmap);
2216 if (pmap != locked_pmap)
2219 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2220 m_pc = SLIST_FIRST(&free);
2221 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2222 /* Recycle a freed page table page. */
2223 m_pc->wire_count = 1;
2224 atomic_add_int(&vm_cnt.v_wire_count, 1);
2226 pmap_free_zero_pages(&free);
2231 * free the pv_entry back to the free list
2234 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2236 struct pv_chunk *pc;
2237 int idx, field, bit;
2239 rw_assert(&pvh_global_lock, RA_WLOCKED);
2240 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2241 PV_STAT(pv_entry_frees++);
2242 PV_STAT(pv_entry_spare++);
2244 pc = pv_to_chunk(pv);
2245 idx = pv - &pc->pc_pventry[0];
2248 pc->pc_map[field] |= 1ul << bit;
2249 for (idx = 0; idx < _NPCM; idx++)
2250 if (pc->pc_map[idx] != pc_freemask[idx]) {
2252 * 98% of the time, pc is already at the head of the
2253 * list. If it isn't already, move it to the head.
2255 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2257 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2258 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2263 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2268 free_pv_chunk(struct pv_chunk *pc)
2272 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2273 PV_STAT(pv_entry_spare -= _NPCPV);
2274 PV_STAT(pc_chunk_count--);
2275 PV_STAT(pc_chunk_frees++);
2276 /* entire chunk is free, return it */
2277 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2278 pmap_qremove((vm_offset_t)pc, 1);
2279 vm_page_unwire(m, PQ_INACTIVE);
2281 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2285 * get a new pv_entry, allocating a block from the system
2289 get_pv_entry(pmap_t pmap, boolean_t try)
2291 static const struct timeval printinterval = { 60, 0 };
2292 static struct timeval lastprint;
2295 struct pv_chunk *pc;
2298 rw_assert(&pvh_global_lock, RA_WLOCKED);
2299 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2300 PV_STAT(pv_entry_allocs++);
2302 if (pv_entry_count > pv_entry_high_water)
2303 if (ratecheck(&lastprint, &printinterval))
2304 printf("Approaching the limit on PV entries, consider "
2305 "increasing either the vm.pmap.shpgperproc or the "
2306 "vm.pmap.pv_entry_max tunable.\n");
2308 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2310 for (field = 0; field < _NPCM; field++) {
2311 if (pc->pc_map[field]) {
2312 bit = bsfl(pc->pc_map[field]);
2316 if (field < _NPCM) {
2317 pv = &pc->pc_pventry[field * 32 + bit];
2318 pc->pc_map[field] &= ~(1ul << bit);
2319 /* If this was the last item, move it to tail */
2320 for (field = 0; field < _NPCM; field++)
2321 if (pc->pc_map[field] != 0) {
2322 PV_STAT(pv_entry_spare--);
2323 return (pv); /* not full, return */
2325 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2326 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2327 PV_STAT(pv_entry_spare--);
2332 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2333 * global lock. If "pv_vafree" is currently non-empty, it will
2334 * remain non-empty until pmap_ptelist_alloc() completes.
2336 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2337 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2340 PV_STAT(pc_chunk_tryfail++);
2343 m = pmap_pv_reclaim(pmap);
2347 PV_STAT(pc_chunk_count++);
2348 PV_STAT(pc_chunk_allocs++);
2349 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2350 pmap_qenter((vm_offset_t)pc, &m, 1);
2352 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2353 for (field = 1; field < _NPCM; field++)
2354 pc->pc_map[field] = pc_freemask[field];
2355 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2356 pv = &pc->pc_pventry[0];
2357 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2358 PV_STAT(pv_entry_spare += _NPCPV - 1);
2362 static __inline pv_entry_t
2363 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2367 rw_assert(&pvh_global_lock, RA_WLOCKED);
2368 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2369 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2370 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2378 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2380 struct md_page *pvh;
2382 vm_offset_t va_last;
2385 rw_assert(&pvh_global_lock, RA_WLOCKED);
2386 KASSERT((pa & PDRMASK) == 0,
2387 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2390 * Transfer the 4mpage's pv entry for this mapping to the first
2393 pvh = pa_to_pvh(pa);
2394 va = trunc_4mpage(va);
2395 pv = pmap_pvh_remove(pvh, pmap, va);
2396 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2397 m = PHYS_TO_VM_PAGE(pa);
2398 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2399 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2400 va_last = va + NBPDR - PAGE_SIZE;
2403 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2404 ("pmap_pv_demote_pde: page %p is not managed", m));
2406 pmap_insert_entry(pmap, va, m);
2407 } while (va < va_last);
2411 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2413 struct md_page *pvh;
2415 vm_offset_t va_last;
2418 rw_assert(&pvh_global_lock, RA_WLOCKED);
2419 KASSERT((pa & PDRMASK) == 0,
2420 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2423 * Transfer the first page's pv entry for this mapping to the
2424 * 4mpage's pv list. Aside from avoiding the cost of a call
2425 * to get_pv_entry(), a transfer avoids the possibility that
2426 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2427 * removes one of the mappings that is being promoted.
2429 m = PHYS_TO_VM_PAGE(pa);
2430 va = trunc_4mpage(va);
2431 pv = pmap_pvh_remove(&m->md, pmap, va);
2432 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2433 pvh = pa_to_pvh(pa);
2434 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2435 /* Free the remaining NPTEPG - 1 pv entries. */
2436 va_last = va + NBPDR - PAGE_SIZE;
2440 pmap_pvh_free(&m->md, pmap, va);
2441 } while (va < va_last);
2445 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2449 pv = pmap_pvh_remove(pvh, pmap, va);
2450 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2451 free_pv_entry(pmap, pv);
2455 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2457 struct md_page *pvh;
2459 rw_assert(&pvh_global_lock, RA_WLOCKED);
2460 pmap_pvh_free(&m->md, pmap, va);
2461 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2462 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2463 if (TAILQ_EMPTY(&pvh->pv_list))
2464 vm_page_aflag_clear(m, PGA_WRITEABLE);
2469 * Create a pv entry for page at pa for
2473 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2477 rw_assert(&pvh_global_lock, RA_WLOCKED);
2478 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2479 pv = get_pv_entry(pmap, FALSE);
2481 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2485 * Conditionally create a pv entry.
2488 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2492 rw_assert(&pvh_global_lock, RA_WLOCKED);
2493 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2494 if (pv_entry_count < pv_entry_high_water &&
2495 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2497 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2504 * Create the pv entries for each of the pages within a superpage.
2507 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2509 struct md_page *pvh;
2512 rw_assert(&pvh_global_lock, RA_WLOCKED);
2513 if (pv_entry_count < pv_entry_high_water &&
2514 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2516 pvh = pa_to_pvh(pa);
2517 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2524 * Fills a page table page with mappings to consecutive physical pages.
2527 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2531 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2533 newpte += PAGE_SIZE;
2538 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2539 * 2- or 4MB page mapping is invalidated.
2542 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2544 pd_entry_t newpde, oldpde;
2545 pt_entry_t *firstpte, newpte;
2548 struct spglist free;
2550 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2552 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2553 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2554 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2556 pmap_remove_pt_page(pmap, mpte);
2558 KASSERT((oldpde & PG_W) == 0,
2559 ("pmap_demote_pde: page table page for a wired mapping"
2563 * Invalidate the 2- or 4MB page mapping and return
2564 * "failure" if the mapping was never accessed or the
2565 * allocation of the new page table page fails.
2567 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2568 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2569 VM_ALLOC_WIRED)) == NULL) {
2571 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2572 pmap_invalidate_page(pmap, trunc_4mpage(va));
2573 pmap_free_zero_pages(&free);
2574 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2575 " in pmap %p", va, pmap);
2578 if (va < VM_MAXUSER_ADDRESS)
2579 pmap->pm_stats.resident_count++;
2581 mptepa = VM_PAGE_TO_PHYS(mpte);
2584 * If the page mapping is in the kernel's address space, then the
2585 * KPTmap can provide access to the page table page. Otherwise,
2586 * temporarily map the page table page (mpte) into the kernel's
2587 * address space at either PADDR1 or PADDR2.
2590 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2591 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2592 if ((*PMAP1 & PG_FRAME) != mptepa) {
2593 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2595 PMAP1cpu = PCPU_GET(cpuid);
2601 if (PMAP1cpu != PCPU_GET(cpuid)) {
2602 PMAP1cpu = PCPU_GET(cpuid);
2610 mtx_lock(&PMAP2mutex);
2611 if ((*PMAP2 & PG_FRAME) != mptepa) {
2612 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2613 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2617 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2618 KASSERT((oldpde & PG_A) != 0,
2619 ("pmap_demote_pde: oldpde is missing PG_A"));
2620 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2621 ("pmap_demote_pde: oldpde is missing PG_M"));
2622 newpte = oldpde & ~PG_PS;
2623 if ((newpte & PG_PDE_PAT) != 0)
2624 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2627 * If the page table page is new, initialize it.
2629 if (mpte->wire_count == 1) {
2630 mpte->wire_count = NPTEPG;
2631 pmap_fill_ptp(firstpte, newpte);
2633 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2634 ("pmap_demote_pde: firstpte and newpte map different physical"
2638 * If the mapping has changed attributes, update the page table
2641 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2642 pmap_fill_ptp(firstpte, newpte);
2645 * Demote the mapping. This pmap is locked. The old PDE has
2646 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2647 * set. Thus, there is no danger of a race with another
2648 * processor changing the setting of PG_A and/or PG_M between
2649 * the read above and the store below.
2651 if (workaround_erratum383)
2652 pmap_update_pde(pmap, va, pde, newpde);
2653 else if (pmap == kernel_pmap)
2654 pmap_kenter_pde(va, newpde);
2656 pde_store(pde, newpde);
2657 if (firstpte == PADDR2)
2658 mtx_unlock(&PMAP2mutex);
2661 * Invalidate the recursive mapping of the page table page.
2663 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2666 * Demote the pv entry. This depends on the earlier demotion
2667 * of the mapping. Specifically, the (re)creation of a per-
2668 * page pv entry might trigger the execution of pmap_collect(),
2669 * which might reclaim a newly (re)created per-page pv entry
2670 * and destroy the associated mapping. In order to destroy
2671 * the mapping, the PDE must have already changed from mapping
2672 * the 2mpage to referencing the page table page.
2674 if ((oldpde & PG_MANAGED) != 0)
2675 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2677 pmap_pde_demotions++;
2678 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2679 " in pmap %p", va, pmap);
2684 * Removes a 2- or 4MB page mapping from the kernel pmap.
2687 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2693 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2694 mpte = pmap_lookup_pt_page(pmap, va);
2696 panic("pmap_remove_kernel_pde: Missing pt page.");
2698 pmap_remove_pt_page(pmap, mpte);
2699 mptepa = VM_PAGE_TO_PHYS(mpte);
2700 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2703 * Initialize the page table page.
2705 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2708 * Remove the mapping.
2710 if (workaround_erratum383)
2711 pmap_update_pde(pmap, va, pde, newpde);
2713 pmap_kenter_pde(va, newpde);
2716 * Invalidate the recursive mapping of the page table page.
2718 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2722 * pmap_remove_pde: do the things to unmap a superpage in a process
2725 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2726 struct spglist *free)
2728 struct md_page *pvh;
2730 vm_offset_t eva, va;
2733 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2734 KASSERT((sva & PDRMASK) == 0,
2735 ("pmap_remove_pde: sva is not 4mpage aligned"));
2736 oldpde = pte_load_clear(pdq);
2738 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2741 * Machines that don't support invlpg, also don't support
2745 pmap_invalidate_page(kernel_pmap, sva);
2746 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2747 if (oldpde & PG_MANAGED) {
2748 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2749 pmap_pvh_free(pvh, pmap, sva);
2751 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2752 va < eva; va += PAGE_SIZE, m++) {
2753 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2756 vm_page_aflag_set(m, PGA_REFERENCED);
2757 if (TAILQ_EMPTY(&m->md.pv_list) &&
2758 TAILQ_EMPTY(&pvh->pv_list))
2759 vm_page_aflag_clear(m, PGA_WRITEABLE);
2762 if (pmap == kernel_pmap) {
2763 pmap_remove_kernel_pde(pmap, pdq, sva);
2765 mpte = pmap_lookup_pt_page(pmap, sva);
2767 pmap_remove_pt_page(pmap, mpte);
2768 pmap->pm_stats.resident_count--;
2769 KASSERT(mpte->wire_count == NPTEPG,
2770 ("pmap_remove_pde: pte page wire count error"));
2771 mpte->wire_count = 0;
2772 pmap_add_delayed_free_list(mpte, free, FALSE);
2773 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2779 * pmap_remove_pte: do the things to unmap a page in a process
2782 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2783 struct spglist *free)
2788 rw_assert(&pvh_global_lock, RA_WLOCKED);
2789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2790 oldpte = pte_load_clear(ptq);
2791 KASSERT(oldpte != 0,
2792 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2794 pmap->pm_stats.wired_count -= 1;
2796 * Machines that don't support invlpg, also don't support
2800 pmap_invalidate_page(kernel_pmap, va);
2801 pmap->pm_stats.resident_count -= 1;
2802 if (oldpte & PG_MANAGED) {
2803 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2804 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2807 vm_page_aflag_set(m, PGA_REFERENCED);
2808 pmap_remove_entry(pmap, m, va);
2810 return (pmap_unuse_pt(pmap, va, free));
2814 * Remove a single page from a process address space
2817 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2821 rw_assert(&pvh_global_lock, RA_WLOCKED);
2822 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2823 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2824 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2826 pmap_remove_pte(pmap, pte, va, free);
2827 pmap_invalidate_page(pmap, va);
2831 * Remove the given range of addresses from the specified map.
2833 * It is assumed that the start and end are properly
2834 * rounded to the page size.
2837 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2842 struct spglist free;
2846 * Perform an unsynchronized read. This is, however, safe.
2848 if (pmap->pm_stats.resident_count == 0)
2854 rw_wlock(&pvh_global_lock);
2859 * special handling of removing one page. a very
2860 * common operation and easy to short circuit some
2863 if ((sva + PAGE_SIZE == eva) &&
2864 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2865 pmap_remove_page(pmap, sva, &free);
2869 for (; sva < eva; sva = pdnxt) {
2873 * Calculate index for next page table.
2875 pdnxt = (sva + NBPDR) & ~PDRMASK;
2878 if (pmap->pm_stats.resident_count == 0)
2881 pdirindex = sva >> PDRSHIFT;
2882 ptpaddr = pmap->pm_pdir[pdirindex];
2885 * Weed out invalid mappings. Note: we assume that the page
2886 * directory table is always allocated, and in kernel virtual.
2892 * Check for large page.
2894 if ((ptpaddr & PG_PS) != 0) {
2896 * Are we removing the entire large page? If not,
2897 * demote the mapping and fall through.
2899 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2901 * The TLB entry for a PG_G mapping is
2902 * invalidated by pmap_remove_pde().
2904 if ((ptpaddr & PG_G) == 0)
2906 pmap_remove_pde(pmap,
2907 &pmap->pm_pdir[pdirindex], sva, &free);
2909 } else if (!pmap_demote_pde(pmap,
2910 &pmap->pm_pdir[pdirindex], sva)) {
2911 /* The large page mapping was destroyed. */
2917 * Limit our scan to either the end of the va represented
2918 * by the current page table page, or to the end of the
2919 * range being removed.
2924 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2930 * The TLB entry for a PG_G mapping is invalidated
2931 * by pmap_remove_pte().
2933 if ((*pte & PG_G) == 0)
2935 if (pmap_remove_pte(pmap, pte, sva, &free))
2942 pmap_invalidate_all(pmap);
2943 rw_wunlock(&pvh_global_lock);
2945 pmap_free_zero_pages(&free);
2949 * Routine: pmap_remove_all
2951 * Removes this physical page from
2952 * all physical maps in which it resides.
2953 * Reflects back modify bits to the pager.
2956 * Original versions of this routine were very
2957 * inefficient because they iteratively called
2958 * pmap_remove (slow...)
2962 pmap_remove_all(vm_page_t m)
2964 struct md_page *pvh;
2967 pt_entry_t *pte, tpte;
2970 struct spglist free;
2972 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2973 ("pmap_remove_all: page %p is not managed", m));
2975 rw_wlock(&pvh_global_lock);
2977 if ((m->flags & PG_FICTITIOUS) != 0)
2978 goto small_mappings;
2979 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2980 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2984 pde = pmap_pde(pmap, va);
2985 (void)pmap_demote_pde(pmap, pde, va);
2989 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2992 pmap->pm_stats.resident_count--;
2993 pde = pmap_pde(pmap, pv->pv_va);
2994 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
2995 " a 4mpage in page %p's pv list", m));
2996 pte = pmap_pte_quick(pmap, pv->pv_va);
2997 tpte = pte_load_clear(pte);
2998 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3001 pmap->pm_stats.wired_count--;
3003 vm_page_aflag_set(m, PGA_REFERENCED);
3006 * Update the vm_page_t clean and reference bits.
3008 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3010 pmap_unuse_pt(pmap, pv->pv_va, &free);
3011 pmap_invalidate_page(pmap, pv->pv_va);
3012 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3013 free_pv_entry(pmap, pv);
3016 vm_page_aflag_clear(m, PGA_WRITEABLE);
3018 rw_wunlock(&pvh_global_lock);
3019 pmap_free_zero_pages(&free);
3023 * pmap_protect_pde: do the things to protect a 4mpage in a process
3026 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3028 pd_entry_t newpde, oldpde;
3029 vm_offset_t eva, va;
3031 boolean_t anychanged;
3033 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3034 KASSERT((sva & PDRMASK) == 0,
3035 ("pmap_protect_pde: sva is not 4mpage aligned"));
3038 oldpde = newpde = *pde;
3039 if (oldpde & PG_MANAGED) {
3041 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3042 va < eva; va += PAGE_SIZE, m++)
3043 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3046 if ((prot & VM_PROT_WRITE) == 0)
3047 newpde &= ~(PG_RW | PG_M);
3048 #if defined(PAE) || defined(PAE_TABLES)
3049 if ((prot & VM_PROT_EXECUTE) == 0)
3052 if (newpde != oldpde) {
3053 if (!pde_cmpset(pde, oldpde, newpde))
3056 pmap_invalidate_page(pmap, sva);
3060 return (anychanged);
3064 * Set the physical protection on the
3065 * specified range of this map as requested.
3068 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3073 boolean_t anychanged, pv_lists_locked;
3075 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3076 if (prot == VM_PROT_NONE) {
3077 pmap_remove(pmap, sva, eva);
3081 #if defined(PAE) || defined(PAE_TABLES)
3082 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3083 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3086 if (prot & VM_PROT_WRITE)
3090 if (pmap_is_current(pmap))
3091 pv_lists_locked = FALSE;
3093 pv_lists_locked = TRUE;
3095 rw_wlock(&pvh_global_lock);
3101 for (; sva < eva; sva = pdnxt) {
3102 pt_entry_t obits, pbits;
3105 pdnxt = (sva + NBPDR) & ~PDRMASK;
3109 pdirindex = sva >> PDRSHIFT;
3110 ptpaddr = pmap->pm_pdir[pdirindex];
3113 * Weed out invalid mappings. Note: we assume that the page
3114 * directory table is always allocated, and in kernel virtual.
3120 * Check for large page.
3122 if ((ptpaddr & PG_PS) != 0) {
3124 * Are we protecting the entire large page? If not,
3125 * demote the mapping and fall through.
3127 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3129 * The TLB entry for a PG_G mapping is
3130 * invalidated by pmap_protect_pde().
3132 if (pmap_protect_pde(pmap,
3133 &pmap->pm_pdir[pdirindex], sva, prot))
3137 if (!pv_lists_locked) {
3138 pv_lists_locked = TRUE;
3139 if (!rw_try_wlock(&pvh_global_lock)) {
3141 pmap_invalidate_all(
3148 if (!pmap_demote_pde(pmap,
3149 &pmap->pm_pdir[pdirindex], sva)) {
3151 * The large page mapping was
3162 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3168 * Regardless of whether a pte is 32 or 64 bits in
3169 * size, PG_RW, PG_A, and PG_M are among the least
3170 * significant 32 bits.
3172 obits = pbits = *pte;
3173 if ((pbits & PG_V) == 0)
3176 if ((prot & VM_PROT_WRITE) == 0) {
3177 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3178 (PG_MANAGED | PG_M | PG_RW)) {
3179 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3182 pbits &= ~(PG_RW | PG_M);
3184 #if defined(PAE) || defined(PAE_TABLES)
3185 if ((prot & VM_PROT_EXECUTE) == 0)
3189 if (pbits != obits) {
3190 #if defined(PAE) || defined(PAE_TABLES)
3191 if (!atomic_cmpset_64(pte, obits, pbits))
3194 if (!atomic_cmpset_int((u_int *)pte, obits,
3199 pmap_invalidate_page(pmap, sva);
3206 pmap_invalidate_all(pmap);
3207 if (pv_lists_locked) {
3209 rw_wunlock(&pvh_global_lock);
3215 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3216 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3217 * For promotion to occur, two conditions must be met: (1) the 4KB page
3218 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3219 * mappings must have identical characteristics.
3221 * Managed (PG_MANAGED) mappings within the kernel address space are not
3222 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3223 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3227 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3230 pt_entry_t *firstpte, oldpte, pa, *pte;
3231 vm_offset_t oldpteva;
3234 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3237 * Examine the first PTE in the specified PTP. Abort if this PTE is
3238 * either invalid, unused, or does not map the first 4KB physical page
3239 * within a 2- or 4MB page.
3241 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3244 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3245 pmap_pde_p_failures++;
3246 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3247 " in pmap %p", va, pmap);
3250 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3251 pmap_pde_p_failures++;
3252 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3253 " in pmap %p", va, pmap);
3256 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3258 * When PG_M is already clear, PG_RW can be cleared without
3259 * a TLB invalidation.
3261 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3268 * Examine each of the other PTEs in the specified PTP. Abort if this
3269 * PTE maps an unexpected 4KB physical page or does not have identical
3270 * characteristics to the first PTE.
3272 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3273 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3276 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3277 pmap_pde_p_failures++;
3278 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3279 " in pmap %p", va, pmap);
3282 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3284 * When PG_M is already clear, PG_RW can be cleared
3285 * without a TLB invalidation.
3287 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3291 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3293 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3294 " in pmap %p", oldpteva, pmap);
3296 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3297 pmap_pde_p_failures++;
3298 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3299 " in pmap %p", va, pmap);
3306 * Save the page table page in its current state until the PDE
3307 * mapping the superpage is demoted by pmap_demote_pde() or
3308 * destroyed by pmap_remove_pde().
3310 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3311 KASSERT(mpte >= vm_page_array &&
3312 mpte < &vm_page_array[vm_page_array_size],
3313 ("pmap_promote_pde: page table page is out of range"));
3314 KASSERT(mpte->pindex == va >> PDRSHIFT,
3315 ("pmap_promote_pde: page table page's pindex is wrong"));
3316 if (pmap_insert_pt_page(pmap, mpte)) {
3317 pmap_pde_p_failures++;
3319 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3325 * Promote the pv entries.
3327 if ((newpde & PG_MANAGED) != 0)
3328 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3331 * Propagate the PAT index to its proper position.
3333 if ((newpde & PG_PTE_PAT) != 0)
3334 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3337 * Map the superpage.
3339 if (workaround_erratum383)
3340 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3341 else if (pmap == kernel_pmap)
3342 pmap_kenter_pde(va, PG_PS | newpde);
3344 pde_store(pde, PG_PS | newpde);
3346 pmap_pde_promotions++;
3347 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3348 " in pmap %p", va, pmap);
3352 * Insert the given physical page (p) at
3353 * the specified virtual address (v) in the
3354 * target physical map with the protection requested.
3356 * If specified, the page will be wired down, meaning
3357 * that the related pte can not be reclaimed.
3359 * NB: This is the only routine which MAY NOT lazy-evaluate
3360 * or lose information. That is, this routine must actually
3361 * insert this page into the given map NOW.
3364 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3365 u_int flags, int8_t psind)
3369 pt_entry_t newpte, origpte;
3373 boolean_t invlva, wired;
3375 va = trunc_page(va);
3377 wired = (flags & PMAP_ENTER_WIRED) != 0;
3379 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3380 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3381 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3383 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3384 VM_OBJECT_ASSERT_LOCKED(m->object);
3386 rw_wlock(&pvh_global_lock);
3391 * In the case that a page table page is not
3392 * resident, we are creating it here.
3394 if (va < VM_MAXUSER_ADDRESS) {
3395 mpte = pmap_allocpte(pmap, va, flags);
3397 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3398 ("pmap_allocpte failed with sleep allowed"));
3400 rw_wunlock(&pvh_global_lock);
3402 return (KERN_RESOURCE_SHORTAGE);
3406 pde = pmap_pde(pmap, va);
3407 if ((*pde & PG_PS) != 0)
3408 panic("pmap_enter: attempted pmap_enter on 4MB page");
3409 pte = pmap_pte_quick(pmap, va);
3412 * Page Directory table entry not valid, we need a new PT page
3415 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3416 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3419 pa = VM_PAGE_TO_PHYS(m);
3422 opa = origpte & PG_FRAME;
3425 * Mapping has not changed, must be protection or wiring change.
3427 if (origpte && (opa == pa)) {
3429 * Wiring change, just update stats. We don't worry about
3430 * wiring PT pages as they remain resident as long as there
3431 * are valid mappings in them. Hence, if a user page is wired,
3432 * the PT page will be also.
3434 if (wired && ((origpte & PG_W) == 0))
3435 pmap->pm_stats.wired_count++;
3436 else if (!wired && (origpte & PG_W))
3437 pmap->pm_stats.wired_count--;
3440 * Remove extra pte reference
3445 if (origpte & PG_MANAGED) {
3455 * Mapping has changed, invalidate old range and fall through to
3456 * handle validating new mapping.
3460 pmap->pm_stats.wired_count--;
3461 if (origpte & PG_MANAGED) {
3462 om = PHYS_TO_VM_PAGE(opa);
3463 pv = pmap_pvh_remove(&om->md, pmap, va);
3467 KASSERT(mpte->wire_count > 0,
3468 ("pmap_enter: missing reference to page table page,"
3472 pmap->pm_stats.resident_count++;
3475 * Enter on the PV list if part of our managed memory.
3477 if ((m->oflags & VPO_UNMANAGED) == 0) {
3478 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3479 ("pmap_enter: managed mapping within the clean submap"));
3481 pv = get_pv_entry(pmap, FALSE);
3483 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3485 } else if (pv != NULL)
3486 free_pv_entry(pmap, pv);
3489 * Increment counters
3492 pmap->pm_stats.wired_count++;
3496 * Now validate mapping with desired protection/wiring.
3498 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3499 if ((prot & VM_PROT_WRITE) != 0) {
3501 if ((newpte & PG_MANAGED) != 0)
3502 vm_page_aflag_set(m, PGA_WRITEABLE);
3504 #if defined(PAE) || defined(PAE_TABLES)
3505 if ((prot & VM_PROT_EXECUTE) == 0)
3510 if (va < VM_MAXUSER_ADDRESS)
3512 if (pmap == kernel_pmap)
3516 * if the mapping or permission bits are different, we need
3517 * to update the pte.
3519 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3521 if ((flags & VM_PROT_WRITE) != 0)
3523 if (origpte & PG_V) {
3525 origpte = pte_load_store(pte, newpte);
3526 if (origpte & PG_A) {
3527 if (origpte & PG_MANAGED)
3528 vm_page_aflag_set(om, PGA_REFERENCED);
3529 if (opa != VM_PAGE_TO_PHYS(m))
3531 #if defined(PAE) || defined(PAE_TABLES)
3532 if ((origpte & PG_NX) == 0 &&
3533 (newpte & PG_NX) != 0)
3537 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3538 if ((origpte & PG_MANAGED) != 0)
3540 if ((prot & VM_PROT_WRITE) == 0)
3543 if ((origpte & PG_MANAGED) != 0 &&
3544 TAILQ_EMPTY(&om->md.pv_list) &&
3545 ((om->flags & PG_FICTITIOUS) != 0 ||
3546 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3547 vm_page_aflag_clear(om, PGA_WRITEABLE);
3549 pmap_invalidate_page(pmap, va);
3551 pte_store(pte, newpte);
3555 * If both the page table page and the reservation are fully
3556 * populated, then attempt promotion.
3558 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3559 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3560 vm_reserv_level_iffullpop(m) == 0)
3561 pmap_promote_pde(pmap, pde, va);
3564 rw_wunlock(&pvh_global_lock);
3566 return (KERN_SUCCESS);
3570 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3571 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3572 * blocking, (2) a mapping already exists at the specified virtual address, or
3573 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3576 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3578 pd_entry_t *pde, newpde;
3580 rw_assert(&pvh_global_lock, RA_WLOCKED);
3581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3582 pde = pmap_pde(pmap, va);
3584 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3585 " in pmap %p", va, pmap);
3588 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3590 if ((m->oflags & VPO_UNMANAGED) == 0) {
3591 newpde |= PG_MANAGED;
3594 * Abort this mapping if its PV entry could not be created.
3596 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3597 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3598 " in pmap %p", va, pmap);
3602 #if defined(PAE) || defined(PAE_TABLES)
3603 if ((prot & VM_PROT_EXECUTE) == 0)
3606 if (va < VM_MAXUSER_ADDRESS)
3610 * Increment counters.
3612 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3615 * Map the superpage.
3617 pde_store(pde, newpde);
3619 pmap_pde_mappings++;
3620 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3621 " in pmap %p", va, pmap);
3626 * Maps a sequence of resident pages belonging to the same object.
3627 * The sequence begins with the given page m_start. This page is
3628 * mapped at the given virtual address start. Each subsequent page is
3629 * mapped at a virtual address that is offset from start by the same
3630 * amount as the page is offset from m_start within the object. The
3631 * last page in the sequence is the page with the largest offset from
3632 * m_start that can be mapped at a virtual address less than the given
3633 * virtual address end. Not every virtual page between start and end
3634 * is mapped; only those for which a resident page exists with the
3635 * corresponding offset from m_start are mapped.
3638 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3639 vm_page_t m_start, vm_prot_t prot)
3643 vm_pindex_t diff, psize;
3645 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3647 psize = atop(end - start);
3650 rw_wlock(&pvh_global_lock);
3652 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3653 va = start + ptoa(diff);
3654 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3655 m->psind == 1 && pg_ps_enabled &&
3656 pmap_enter_pde(pmap, va, m, prot))
3657 m = &m[NBPDR / PAGE_SIZE - 1];
3659 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3661 m = TAILQ_NEXT(m, listq);
3663 rw_wunlock(&pvh_global_lock);
3668 * this code makes some *MAJOR* assumptions:
3669 * 1. Current pmap & pmap exists.
3672 * 4. No page table pages.
3673 * but is *MUCH* faster than pmap_enter...
3677 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3680 rw_wlock(&pvh_global_lock);
3682 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3683 rw_wunlock(&pvh_global_lock);
3688 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3689 vm_prot_t prot, vm_page_t mpte)
3693 struct spglist free;
3695 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3696 (m->oflags & VPO_UNMANAGED) != 0,
3697 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3698 rw_assert(&pvh_global_lock, RA_WLOCKED);
3699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3702 * In the case that a page table page is not
3703 * resident, we are creating it here.
3705 if (va < VM_MAXUSER_ADDRESS) {
3710 * Calculate pagetable page index
3712 ptepindex = va >> PDRSHIFT;
3713 if (mpte && (mpte->pindex == ptepindex)) {
3717 * Get the page directory entry
3719 ptepa = pmap->pm_pdir[ptepindex];
3722 * If the page table page is mapped, we just increment
3723 * the hold count, and activate it.
3728 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3731 mpte = _pmap_allocpte(pmap, ptepindex,
3732 PMAP_ENTER_NOSLEEP);
3742 * This call to vtopte makes the assumption that we are
3743 * entering the page into the current pmap. In order to support
3744 * quick entry into any pmap, one would likely use pmap_pte_quick.
3745 * But that isn't as quick as vtopte.
3757 * Enter on the PV list if part of our managed memory.
3759 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3760 !pmap_try_insert_pv_entry(pmap, va, m)) {
3763 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3764 pmap_invalidate_page(pmap, va);
3765 pmap_free_zero_pages(&free);
3774 * Increment counters
3776 pmap->pm_stats.resident_count++;
3778 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3779 #if defined(PAE) || defined(PAE_TABLES)
3780 if ((prot & VM_PROT_EXECUTE) == 0)
3785 * Now validate mapping with RO protection
3787 if ((m->oflags & VPO_UNMANAGED) != 0)
3788 pte_store(pte, pa | PG_V | PG_U);
3790 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3795 * Make a temporary mapping for a physical address. This is only intended
3796 * to be used for panic dumps.
3799 pmap_kenter_temporary(vm_paddr_t pa, int i)
3803 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3804 pmap_kenter(va, pa);
3806 return ((void *)crashdumpmap);
3810 * This code maps large physical mmap regions into the
3811 * processor address space. Note that some shortcuts
3812 * are taken, but the code works.
3815 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3816 vm_pindex_t pindex, vm_size_t size)
3819 vm_paddr_t pa, ptepa;
3823 VM_OBJECT_ASSERT_WLOCKED(object);
3824 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3825 ("pmap_object_init_pt: non-device object"));
3827 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3828 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3830 p = vm_page_lookup(object, pindex);
3831 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3832 ("pmap_object_init_pt: invalid page %p", p));
3833 pat_mode = p->md.pat_mode;
3836 * Abort the mapping if the first page is not physically
3837 * aligned to a 2/4MB page boundary.
3839 ptepa = VM_PAGE_TO_PHYS(p);
3840 if (ptepa & (NBPDR - 1))
3844 * Skip the first page. Abort the mapping if the rest of
3845 * the pages are not physically contiguous or have differing
3846 * memory attributes.
3848 p = TAILQ_NEXT(p, listq);
3849 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3851 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3852 ("pmap_object_init_pt: invalid page %p", p));
3853 if (pa != VM_PAGE_TO_PHYS(p) ||
3854 pat_mode != p->md.pat_mode)
3856 p = TAILQ_NEXT(p, listq);
3860 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3861 * "size" is a multiple of 2/4M, adding the PAT setting to
3862 * "pa" will not affect the termination of this loop.
3865 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3866 size; pa += NBPDR) {
3867 pde = pmap_pde(pmap, addr);
3869 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3870 PG_U | PG_RW | PG_V);
3871 pmap->pm_stats.resident_count += NBPDR /
3873 pmap_pde_mappings++;
3875 /* Else continue on if the PDE is already valid. */
3883 * Clear the wired attribute from the mappings for the specified range of
3884 * addresses in the given pmap. Every valid mapping within that range
3885 * must have the wired attribute set. In contrast, invalid mappings
3886 * cannot have the wired attribute set, so they are ignored.
3888 * The wired attribute of the page table entry is not a hardware feature,
3889 * so there is no need to invalidate any TLB entries.
3892 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3897 boolean_t pv_lists_locked;
3899 if (pmap_is_current(pmap))
3900 pv_lists_locked = FALSE;
3902 pv_lists_locked = TRUE;
3904 rw_wlock(&pvh_global_lock);
3908 for (; sva < eva; sva = pdnxt) {
3909 pdnxt = (sva + NBPDR) & ~PDRMASK;
3912 pde = pmap_pde(pmap, sva);
3913 if ((*pde & PG_V) == 0)
3915 if ((*pde & PG_PS) != 0) {
3916 if ((*pde & PG_W) == 0)
3917 panic("pmap_unwire: pde %#jx is missing PG_W",
3921 * Are we unwiring the entire large page? If not,
3922 * demote the mapping and fall through.
3924 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3926 * Regardless of whether a pde (or pte) is 32
3927 * or 64 bits in size, PG_W is among the least
3928 * significant 32 bits.
3930 atomic_clear_int((u_int *)pde, PG_W);
3931 pmap->pm_stats.wired_count -= NBPDR /
3935 if (!pv_lists_locked) {
3936 pv_lists_locked = TRUE;
3937 if (!rw_try_wlock(&pvh_global_lock)) {
3944 if (!pmap_demote_pde(pmap, pde, sva))
3945 panic("pmap_unwire: demotion failed");
3950 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3952 if ((*pte & PG_V) == 0)
3954 if ((*pte & PG_W) == 0)
3955 panic("pmap_unwire: pte %#jx is missing PG_W",
3959 * PG_W must be cleared atomically. Although the pmap
3960 * lock synchronizes access to PG_W, another processor
3961 * could be setting PG_M and/or PG_A concurrently.
3963 * PG_W is among the least significant 32 bits.
3965 atomic_clear_int((u_int *)pte, PG_W);
3966 pmap->pm_stats.wired_count--;
3969 if (pv_lists_locked) {
3971 rw_wunlock(&pvh_global_lock);
3978 * Copy the range specified by src_addr/len
3979 * from the source map to the range dst_addr/len
3980 * in the destination map.
3982 * This routine is only advisory and need not do anything.
3986 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3987 vm_offset_t src_addr)
3989 struct spglist free;
3991 vm_offset_t end_addr = src_addr + len;
3994 if (dst_addr != src_addr)
3997 if (!pmap_is_current(src_pmap))
4000 rw_wlock(&pvh_global_lock);
4001 if (dst_pmap < src_pmap) {
4002 PMAP_LOCK(dst_pmap);
4003 PMAP_LOCK(src_pmap);
4005 PMAP_LOCK(src_pmap);
4006 PMAP_LOCK(dst_pmap);
4009 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4010 pt_entry_t *src_pte, *dst_pte;
4011 vm_page_t dstmpte, srcmpte;
4012 pd_entry_t srcptepaddr;
4015 KASSERT(addr < UPT_MIN_ADDRESS,
4016 ("pmap_copy: invalid to pmap_copy page tables"));
4018 pdnxt = (addr + NBPDR) & ~PDRMASK;
4021 ptepindex = addr >> PDRSHIFT;
4023 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4024 if (srcptepaddr == 0)
4027 if (srcptepaddr & PG_PS) {
4028 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4030 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4031 ((srcptepaddr & PG_MANAGED) == 0 ||
4032 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4034 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4036 dst_pmap->pm_stats.resident_count +=
4042 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4043 KASSERT(srcmpte->wire_count > 0,
4044 ("pmap_copy: source page table page is unused"));
4046 if (pdnxt > end_addr)
4049 src_pte = vtopte(addr);
4050 while (addr < pdnxt) {
4054 * we only virtual copy managed pages
4056 if ((ptetemp & PG_MANAGED) != 0) {
4057 dstmpte = pmap_allocpte(dst_pmap, addr,
4058 PMAP_ENTER_NOSLEEP);
4059 if (dstmpte == NULL)
4061 dst_pte = pmap_pte_quick(dst_pmap, addr);
4062 if (*dst_pte == 0 &&
4063 pmap_try_insert_pv_entry(dst_pmap, addr,
4064 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4066 * Clear the wired, modified, and
4067 * accessed (referenced) bits
4070 *dst_pte = ptetemp & ~(PG_W | PG_M |
4072 dst_pmap->pm_stats.resident_count++;
4075 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4077 pmap_invalidate_page(dst_pmap,
4079 pmap_free_zero_pages(&free);
4083 if (dstmpte->wire_count >= srcmpte->wire_count)
4092 rw_wunlock(&pvh_global_lock);
4093 PMAP_UNLOCK(src_pmap);
4094 PMAP_UNLOCK(dst_pmap);
4097 static __inline void
4098 pagezero(void *page)
4100 #if defined(I686_CPU)
4101 if (cpu_class == CPUCLASS_686) {
4102 #if defined(CPU_ENABLE_SSE)
4103 if (cpu_feature & CPUID_SSE2)
4104 sse2_pagezero(page);
4107 i686_pagezero(page);
4110 bzero(page, PAGE_SIZE);
4114 * pmap_zero_page zeros the specified hardware page by mapping
4115 * the page into KVM and using bzero to clear its contents.
4118 pmap_zero_page(vm_page_t m)
4120 struct sysmaps *sysmaps;
4122 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4123 mtx_lock(&sysmaps->lock);
4124 if (*sysmaps->CMAP2)
4125 panic("pmap_zero_page: CMAP2 busy");
4127 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4128 pmap_cache_bits(m->md.pat_mode, 0);
4129 invlcaddr(sysmaps->CADDR2);
4130 pagezero(sysmaps->CADDR2);
4131 *sysmaps->CMAP2 = 0;
4133 mtx_unlock(&sysmaps->lock);
4137 * pmap_zero_page_area zeros the specified hardware page by mapping
4138 * the page into KVM and using bzero to clear its contents.
4140 * off and size may not cover an area beyond a single hardware page.
4143 pmap_zero_page_area(vm_page_t m, int off, int size)
4145 struct sysmaps *sysmaps;
4147 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4148 mtx_lock(&sysmaps->lock);
4149 if (*sysmaps->CMAP2)
4150 panic("pmap_zero_page_area: CMAP2 busy");
4152 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4153 pmap_cache_bits(m->md.pat_mode, 0);
4154 invlcaddr(sysmaps->CADDR2);
4155 if (off == 0 && size == PAGE_SIZE)
4156 pagezero(sysmaps->CADDR2);
4158 bzero((char *)sysmaps->CADDR2 + off, size);
4159 *sysmaps->CMAP2 = 0;
4161 mtx_unlock(&sysmaps->lock);
4165 * pmap_zero_page_idle zeros the specified hardware page by mapping
4166 * the page into KVM and using bzero to clear its contents. This
4167 * is intended to be called from the vm_pagezero process only and
4171 pmap_zero_page_idle(vm_page_t m)
4175 panic("pmap_zero_page_idle: CMAP3 busy");
4177 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4178 pmap_cache_bits(m->md.pat_mode, 0);
4186 * pmap_copy_page copies the specified (machine independent)
4187 * page by mapping the page into virtual memory and using
4188 * bcopy to copy the page, one machine dependent page at a
4192 pmap_copy_page(vm_page_t src, vm_page_t dst)
4194 struct sysmaps *sysmaps;
4196 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4197 mtx_lock(&sysmaps->lock);
4198 if (*sysmaps->CMAP1)
4199 panic("pmap_copy_page: CMAP1 busy");
4200 if (*sysmaps->CMAP2)
4201 panic("pmap_copy_page: CMAP2 busy");
4203 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4204 pmap_cache_bits(src->md.pat_mode, 0);
4205 invlcaddr(sysmaps->CADDR1);
4206 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4207 pmap_cache_bits(dst->md.pat_mode, 0);
4208 invlcaddr(sysmaps->CADDR2);
4209 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4210 *sysmaps->CMAP1 = 0;
4211 *sysmaps->CMAP2 = 0;
4213 mtx_unlock(&sysmaps->lock);
4216 int unmapped_buf_allowed = 1;
4219 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4220 vm_offset_t b_offset, int xfersize)
4222 struct sysmaps *sysmaps;
4223 vm_page_t a_pg, b_pg;
4225 vm_offset_t a_pg_offset, b_pg_offset;
4228 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4229 mtx_lock(&sysmaps->lock);
4230 if (*sysmaps->CMAP1 != 0)
4231 panic("pmap_copy_pages: CMAP1 busy");
4232 if (*sysmaps->CMAP2 != 0)
4233 panic("pmap_copy_pages: CMAP2 busy");
4235 while (xfersize > 0) {
4236 a_pg = ma[a_offset >> PAGE_SHIFT];
4237 a_pg_offset = a_offset & PAGE_MASK;
4238 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4239 b_pg = mb[b_offset >> PAGE_SHIFT];
4240 b_pg_offset = b_offset & PAGE_MASK;
4241 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4242 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4243 pmap_cache_bits(a_pg->md.pat_mode, 0);
4244 invlcaddr(sysmaps->CADDR1);
4245 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4246 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4247 invlcaddr(sysmaps->CADDR2);
4248 a_cp = sysmaps->CADDR1 + a_pg_offset;
4249 b_cp = sysmaps->CADDR2 + b_pg_offset;
4250 bcopy(a_cp, b_cp, cnt);
4255 *sysmaps->CMAP1 = 0;
4256 *sysmaps->CMAP2 = 0;
4258 mtx_unlock(&sysmaps->lock);
4262 * Returns true if the pmap's pv is one of the first
4263 * 16 pvs linked to from this page. This count may
4264 * be changed upwards or downwards in the future; it
4265 * is only necessary that true be returned for a small
4266 * subset of pmaps for proper page aging.
4269 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4271 struct md_page *pvh;
4276 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4277 ("pmap_page_exists_quick: page %p is not managed", m));
4279 rw_wlock(&pvh_global_lock);
4280 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4281 if (PV_PMAP(pv) == pmap) {
4289 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4290 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4291 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4292 if (PV_PMAP(pv) == pmap) {
4301 rw_wunlock(&pvh_global_lock);
4306 * pmap_page_wired_mappings:
4308 * Return the number of managed mappings to the given physical page
4312 pmap_page_wired_mappings(vm_page_t m)
4317 if ((m->oflags & VPO_UNMANAGED) != 0)
4319 rw_wlock(&pvh_global_lock);
4320 count = pmap_pvh_wired_mappings(&m->md, count);
4321 if ((m->flags & PG_FICTITIOUS) == 0) {
4322 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4325 rw_wunlock(&pvh_global_lock);
4330 * pmap_pvh_wired_mappings:
4332 * Return the updated number "count" of managed mappings that are wired.
4335 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4341 rw_assert(&pvh_global_lock, RA_WLOCKED);
4343 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4346 pte = pmap_pte_quick(pmap, pv->pv_va);
4347 if ((*pte & PG_W) != 0)
4356 * Returns TRUE if the given page is mapped individually or as part of
4357 * a 4mpage. Otherwise, returns FALSE.
4360 pmap_page_is_mapped(vm_page_t m)
4364 if ((m->oflags & VPO_UNMANAGED) != 0)
4366 rw_wlock(&pvh_global_lock);
4367 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4368 ((m->flags & PG_FICTITIOUS) == 0 &&
4369 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4370 rw_wunlock(&pvh_global_lock);
4375 * Remove all pages from specified address space
4376 * this aids process exit speeds. Also, this code
4377 * is special cased for current process only, but
4378 * can have the more generic (and slightly slower)
4379 * mode enabled. This is much faster than pmap_remove
4380 * in the case of running down an entire address space.
4383 pmap_remove_pages(pmap_t pmap)
4385 pt_entry_t *pte, tpte;
4386 vm_page_t m, mpte, mt;
4388 struct md_page *pvh;
4389 struct pv_chunk *pc, *npc;
4390 struct spglist free;
4393 uint32_t inuse, bitmask;
4396 if (pmap != PCPU_GET(curpmap)) {
4397 printf("warning: pmap_remove_pages called with non-current pmap\n");
4401 rw_wlock(&pvh_global_lock);
4404 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4405 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4408 for (field = 0; field < _NPCM; field++) {
4409 inuse = ~pc->pc_map[field] & pc_freemask[field];
4410 while (inuse != 0) {
4412 bitmask = 1UL << bit;
4413 idx = field * 32 + bit;
4414 pv = &pc->pc_pventry[idx];
4417 pte = pmap_pde(pmap, pv->pv_va);
4419 if ((tpte & PG_PS) == 0) {
4420 pte = vtopte(pv->pv_va);
4421 tpte = *pte & ~PG_PTE_PAT;
4426 "TPTE at %p IS ZERO @ VA %08x\n",
4432 * We cannot remove wired pages from a process' mapping at this time
4439 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4440 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4441 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4442 m, (uintmax_t)m->phys_addr,
4445 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4446 m < &vm_page_array[vm_page_array_size],
4447 ("pmap_remove_pages: bad tpte %#jx",
4453 * Update the vm_page_t clean/reference bits.
4455 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4456 if ((tpte & PG_PS) != 0) {
4457 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4464 PV_STAT(pv_entry_frees++);
4465 PV_STAT(pv_entry_spare++);
4467 pc->pc_map[field] |= bitmask;
4468 if ((tpte & PG_PS) != 0) {
4469 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4470 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4471 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4472 if (TAILQ_EMPTY(&pvh->pv_list)) {
4473 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4474 if (TAILQ_EMPTY(&mt->md.pv_list))
4475 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4477 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4479 pmap_remove_pt_page(pmap, mpte);
4480 pmap->pm_stats.resident_count--;
4481 KASSERT(mpte->wire_count == NPTEPG,
4482 ("pmap_remove_pages: pte page wire count error"));
4483 mpte->wire_count = 0;
4484 pmap_add_delayed_free_list(mpte, &free, FALSE);
4485 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
4488 pmap->pm_stats.resident_count--;
4489 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4490 if (TAILQ_EMPTY(&m->md.pv_list) &&
4491 (m->flags & PG_FICTITIOUS) == 0) {
4492 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4493 if (TAILQ_EMPTY(&pvh->pv_list))
4494 vm_page_aflag_clear(m, PGA_WRITEABLE);
4496 pmap_unuse_pt(pmap, pv->pv_va, &free);
4501 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4506 pmap_invalidate_all(pmap);
4507 rw_wunlock(&pvh_global_lock);
4509 pmap_free_zero_pages(&free);
4515 * Return whether or not the specified physical page was modified
4516 * in any physical maps.
4519 pmap_is_modified(vm_page_t m)
4523 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4524 ("pmap_is_modified: page %p is not managed", m));
4527 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4528 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4529 * is clear, no PTEs can have PG_M set.
4531 VM_OBJECT_ASSERT_WLOCKED(m->object);
4532 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4534 rw_wlock(&pvh_global_lock);
4535 rv = pmap_is_modified_pvh(&m->md) ||
4536 ((m->flags & PG_FICTITIOUS) == 0 &&
4537 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4538 rw_wunlock(&pvh_global_lock);
4543 * Returns TRUE if any of the given mappings were used to modify
4544 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4545 * mappings are supported.
4548 pmap_is_modified_pvh(struct md_page *pvh)
4555 rw_assert(&pvh_global_lock, RA_WLOCKED);
4558 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4561 pte = pmap_pte_quick(pmap, pv->pv_va);
4562 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4572 * pmap_is_prefaultable:
4574 * Return whether or not the specified virtual address is elgible
4578 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4586 pde = pmap_pde(pmap, addr);
4587 if (*pde != 0 && (*pde & PG_PS) == 0) {
4596 * pmap_is_referenced:
4598 * Return whether or not the specified physical page was referenced
4599 * in any physical maps.
4602 pmap_is_referenced(vm_page_t m)
4606 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4607 ("pmap_is_referenced: page %p is not managed", m));
4608 rw_wlock(&pvh_global_lock);
4609 rv = pmap_is_referenced_pvh(&m->md) ||
4610 ((m->flags & PG_FICTITIOUS) == 0 &&
4611 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4612 rw_wunlock(&pvh_global_lock);
4617 * Returns TRUE if any of the given mappings were referenced and FALSE
4618 * otherwise. Both page and 4mpage mappings are supported.
4621 pmap_is_referenced_pvh(struct md_page *pvh)
4628 rw_assert(&pvh_global_lock, RA_WLOCKED);
4631 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4634 pte = pmap_pte_quick(pmap, pv->pv_va);
4635 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4645 * Clear the write and modified bits in each of the given page's mappings.
4648 pmap_remove_write(vm_page_t m)
4650 struct md_page *pvh;
4651 pv_entry_t next_pv, pv;
4654 pt_entry_t oldpte, *pte;
4657 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4658 ("pmap_remove_write: page %p is not managed", m));
4661 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4662 * set by another thread while the object is locked. Thus,
4663 * if PGA_WRITEABLE is clear, no page table entries need updating.
4665 VM_OBJECT_ASSERT_WLOCKED(m->object);
4666 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4668 rw_wlock(&pvh_global_lock);
4670 if ((m->flags & PG_FICTITIOUS) != 0)
4671 goto small_mappings;
4672 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4673 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4677 pde = pmap_pde(pmap, va);
4678 if ((*pde & PG_RW) != 0)
4679 (void)pmap_demote_pde(pmap, pde, va);
4683 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4686 pde = pmap_pde(pmap, pv->pv_va);
4687 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4688 " a 4mpage in page %p's pv list", m));
4689 pte = pmap_pte_quick(pmap, pv->pv_va);
4692 if ((oldpte & PG_RW) != 0) {
4694 * Regardless of whether a pte is 32 or 64 bits
4695 * in size, PG_RW and PG_M are among the least
4696 * significant 32 bits.
4698 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4699 oldpte & ~(PG_RW | PG_M)))
4701 if ((oldpte & PG_M) != 0)
4703 pmap_invalidate_page(pmap, pv->pv_va);
4707 vm_page_aflag_clear(m, PGA_WRITEABLE);
4709 rw_wunlock(&pvh_global_lock);
4712 #define PMAP_TS_REFERENCED_MAX 5
4715 * pmap_ts_referenced:
4717 * Return a count of reference bits for a page, clearing those bits.
4718 * It is not necessary for every reference bit to be cleared, but it
4719 * is necessary that 0 only be returned when there are truly no
4720 * reference bits set.
4722 * XXX: The exact number of bits to check and clear is a matter that
4723 * should be tested and standardized at some point in the future for
4724 * optimal aging of shared pages.
4727 pmap_ts_referenced(vm_page_t m)
4729 struct md_page *pvh;
4737 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4738 ("pmap_ts_referenced: page %p is not managed", m));
4739 pa = VM_PAGE_TO_PHYS(m);
4740 pvh = pa_to_pvh(pa);
4741 rw_wlock(&pvh_global_lock);
4743 if ((m->flags & PG_FICTITIOUS) != 0 ||
4744 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4745 goto small_mappings;
4750 pde = pmap_pde(pmap, pv->pv_va);
4751 if ((*pde & PG_A) != 0) {
4753 * Since this reference bit is shared by either 1024
4754 * or 512 4KB pages, it should not be cleared every
4755 * time it is tested. Apply a simple "hash" function
4756 * on the physical page number, the virtual superpage
4757 * number, and the pmap address to select one 4KB page
4758 * out of the 1024 or 512 on which testing the
4759 * reference bit will result in clearing that bit.
4760 * This function is designed to avoid the selection of
4761 * the same 4KB page for every 2- or 4MB page mapping.
4763 * On demotion, a mapping that hasn't been referenced
4764 * is simply destroyed. To avoid the possibility of a
4765 * subsequent page fault on a demoted wired mapping,
4766 * always leave its reference bit set. Moreover,
4767 * since the superpage is wired, the current state of
4768 * its reference bit won't affect page replacement.
4770 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4771 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4772 (*pde & PG_W) == 0) {
4773 atomic_clear_int((u_int *)pde, PG_A);
4774 pmap_invalidate_page(pmap, pv->pv_va);
4779 /* Rotate the PV list if it has more than one entry. */
4780 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4781 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4782 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4784 if (rtval >= PMAP_TS_REFERENCED_MAX)
4786 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4788 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4794 pde = pmap_pde(pmap, pv->pv_va);
4795 KASSERT((*pde & PG_PS) == 0,
4796 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4798 pte = pmap_pte_quick(pmap, pv->pv_va);
4799 if ((*pte & PG_A) != 0) {
4800 atomic_clear_int((u_int *)pte, PG_A);
4801 pmap_invalidate_page(pmap, pv->pv_va);
4805 /* Rotate the PV list if it has more than one entry. */
4806 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4807 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4808 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4810 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4811 PMAP_TS_REFERENCED_MAX);
4814 rw_wunlock(&pvh_global_lock);
4819 * Apply the given advice to the specified range of addresses within the
4820 * given pmap. Depending on the advice, clear the referenced and/or
4821 * modified flags in each mapping and set the mapped page's dirty field.
4824 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4826 pd_entry_t oldpde, *pde;
4830 boolean_t anychanged, pv_lists_locked;
4832 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4834 if (pmap_is_current(pmap))
4835 pv_lists_locked = FALSE;
4837 pv_lists_locked = TRUE;
4839 rw_wlock(&pvh_global_lock);
4844 for (; sva < eva; sva = pdnxt) {
4845 pdnxt = (sva + NBPDR) & ~PDRMASK;
4848 pde = pmap_pde(pmap, sva);
4850 if ((oldpde & PG_V) == 0)
4852 else if ((oldpde & PG_PS) != 0) {
4853 if ((oldpde & PG_MANAGED) == 0)
4855 if (!pv_lists_locked) {
4856 pv_lists_locked = TRUE;
4857 if (!rw_try_wlock(&pvh_global_lock)) {
4859 pmap_invalidate_all(pmap);
4865 if (!pmap_demote_pde(pmap, pde, sva)) {
4867 * The large page mapping was destroyed.
4873 * Unless the page mappings are wired, remove the
4874 * mapping to a single page so that a subsequent
4875 * access may repromote. Since the underlying page
4876 * table page is fully populated, this removal never
4877 * frees a page table page.
4879 if ((oldpde & PG_W) == 0) {
4880 pte = pmap_pte_quick(pmap, sva);
4881 KASSERT((*pte & PG_V) != 0,
4882 ("pmap_advise: invalid PTE"));
4883 pmap_remove_pte(pmap, pte, sva, NULL);
4889 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4891 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
4894 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4895 if (advice == MADV_DONTNEED) {
4897 * Future calls to pmap_is_modified()
4898 * can be avoided by making the page
4901 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4904 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4905 } else if ((*pte & PG_A) != 0)
4906 atomic_clear_int((u_int *)pte, PG_A);
4909 if ((*pte & PG_G) != 0)
4910 pmap_invalidate_page(pmap, sva);
4916 pmap_invalidate_all(pmap);
4917 if (pv_lists_locked) {
4919 rw_wunlock(&pvh_global_lock);
4925 * Clear the modify bits on the specified physical page.
4928 pmap_clear_modify(vm_page_t m)
4930 struct md_page *pvh;
4931 pv_entry_t next_pv, pv;
4933 pd_entry_t oldpde, *pde;
4934 pt_entry_t oldpte, *pte;
4937 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4938 ("pmap_clear_modify: page %p is not managed", m));
4939 VM_OBJECT_ASSERT_WLOCKED(m->object);
4940 KASSERT(!vm_page_xbusied(m),
4941 ("pmap_clear_modify: page %p is exclusive busied", m));
4944 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4945 * If the object containing the page is locked and the page is not
4946 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4948 if ((m->aflags & PGA_WRITEABLE) == 0)
4950 rw_wlock(&pvh_global_lock);
4952 if ((m->flags & PG_FICTITIOUS) != 0)
4953 goto small_mappings;
4954 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4955 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4959 pde = pmap_pde(pmap, va);
4961 if ((oldpde & PG_RW) != 0) {
4962 if (pmap_demote_pde(pmap, pde, va)) {
4963 if ((oldpde & PG_W) == 0) {
4965 * Write protect the mapping to a
4966 * single page so that a subsequent
4967 * write access may repromote.
4969 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4971 pte = pmap_pte_quick(pmap, va);
4973 if ((oldpte & PG_V) != 0) {
4975 * Regardless of whether a pte is 32 or 64 bits
4976 * in size, PG_RW and PG_M are among the least
4977 * significant 32 bits.
4979 while (!atomic_cmpset_int((u_int *)pte,
4981 oldpte & ~(PG_M | PG_RW)))
4984 pmap_invalidate_page(pmap, va);
4992 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4995 pde = pmap_pde(pmap, pv->pv_va);
4996 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4997 " a 4mpage in page %p's pv list", m));
4998 pte = pmap_pte_quick(pmap, pv->pv_va);
4999 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5001 * Regardless of whether a pte is 32 or 64 bits
5002 * in size, PG_M is among the least significant
5005 atomic_clear_int((u_int *)pte, PG_M);
5006 pmap_invalidate_page(pmap, pv->pv_va);
5011 rw_wunlock(&pvh_global_lock);
5015 * Miscellaneous support routines follow
5018 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5019 static __inline void
5020 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5025 * The cache mode bits are all in the low 32-bits of the
5026 * PTE, so we can just spin on updating the low 32-bits.
5029 opte = *(u_int *)pte;
5030 npte = opte & ~PG_PTE_CACHE;
5032 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5035 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5036 static __inline void
5037 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5042 * The cache mode bits are all in the low 32-bits of the
5043 * PDE, so we can just spin on updating the low 32-bits.
5046 opde = *(u_int *)pde;
5047 npde = opde & ~PG_PDE_CACHE;
5049 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5053 * Map a set of physical memory pages into the kernel virtual
5054 * address space. Return a pointer to where it is mapped. This
5055 * routine is intended to be used for mapping device memory,
5059 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5061 vm_offset_t va, offset;
5064 offset = pa & PAGE_MASK;
5065 size = round_page(offset + size);
5068 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5071 va = kva_alloc(size);
5073 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5075 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5076 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5077 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5078 pmap_invalidate_cache_range(va, va + size, FALSE);
5079 return ((void *)(va + offset));
5083 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5086 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5090 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5093 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5097 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5099 vm_offset_t base, offset;
5101 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5103 base = trunc_page(va);
5104 offset = va & PAGE_MASK;
5105 size = round_page(offset + size);
5106 kva_free(base, size);
5110 * Sets the memory attribute for the specified page.
5113 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5116 m->md.pat_mode = ma;
5117 if ((m->flags & PG_FICTITIOUS) != 0)
5121 * If "m" is a normal page, flush it from the cache.
5122 * See pmap_invalidate_cache_range().
5124 * First, try to find an existing mapping of the page by sf
5125 * buffer. sf_buf_invalidate_cache() modifies mapping and
5126 * flushes the cache.
5128 if (sf_buf_invalidate_cache(m))
5132 * If page is not mapped by sf buffer, but CPU does not
5133 * support self snoop, map the page transient and do
5134 * invalidation. In the worst case, whole cache is flushed by
5135 * pmap_invalidate_cache_range().
5137 if ((cpu_feature & CPUID_SS) == 0)
5142 pmap_flush_page(vm_page_t m)
5144 struct sysmaps *sysmaps;
5145 vm_offset_t sva, eva;
5147 if ((cpu_feature & CPUID_CLFSH) != 0) {
5148 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5149 mtx_lock(&sysmaps->lock);
5150 if (*sysmaps->CMAP2)
5151 panic("pmap_flush_page: CMAP2 busy");
5153 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5154 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5155 invlcaddr(sysmaps->CADDR2);
5156 sva = (vm_offset_t)sysmaps->CADDR2;
5157 eva = sva + PAGE_SIZE;
5160 * Use mfence despite the ordering implied by
5161 * mtx_{un,}lock() because clflush is not guaranteed
5162 * to be ordered by any other instruction.
5165 for (; sva < eva; sva += cpu_clflush_line_size)
5168 *sysmaps->CMAP2 = 0;
5170 mtx_unlock(&sysmaps->lock);
5172 pmap_invalidate_cache();
5176 * Changes the specified virtual address range's memory type to that given by
5177 * the parameter "mode". The specified virtual address range must be
5178 * completely contained within either the kernel map.
5180 * Returns zero if the change completed successfully, and either EINVAL or
5181 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5182 * of the virtual address range was not mapped, and ENOMEM is returned if
5183 * there was insufficient memory available to complete the change.
5186 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5188 vm_offset_t base, offset, tmpva;
5191 int cache_bits_pte, cache_bits_pde;
5194 base = trunc_page(va);
5195 offset = va & PAGE_MASK;
5196 size = round_page(offset + size);
5199 * Only supported on kernel virtual addresses above the recursive map.
5201 if (base < VM_MIN_KERNEL_ADDRESS)
5204 cache_bits_pde = pmap_cache_bits(mode, 1);
5205 cache_bits_pte = pmap_cache_bits(mode, 0);
5209 * Pages that aren't mapped aren't supported. Also break down
5210 * 2/4MB pages into 4KB pages if required.
5212 PMAP_LOCK(kernel_pmap);
5213 for (tmpva = base; tmpva < base + size; ) {
5214 pde = pmap_pde(kernel_pmap, tmpva);
5216 PMAP_UNLOCK(kernel_pmap);
5221 * If the current 2/4MB page already has
5222 * the required memory type, then we need not
5223 * demote this page. Just increment tmpva to
5224 * the next 2/4MB page frame.
5226 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5227 tmpva = trunc_4mpage(tmpva) + NBPDR;
5232 * If the current offset aligns with a 2/4MB
5233 * page frame and there is at least 2/4MB left
5234 * within the range, then we need not break
5235 * down this page into 4KB pages.
5237 if ((tmpva & PDRMASK) == 0 &&
5238 tmpva + PDRMASK < base + size) {
5242 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5243 PMAP_UNLOCK(kernel_pmap);
5247 pte = vtopte(tmpva);
5249 PMAP_UNLOCK(kernel_pmap);
5254 PMAP_UNLOCK(kernel_pmap);
5257 * Ok, all the pages exist, so run through them updating their
5258 * cache mode if required.
5260 for (tmpva = base; tmpva < base + size; ) {
5261 pde = pmap_pde(kernel_pmap, tmpva);
5263 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5264 pmap_pde_attr(pde, cache_bits_pde);
5267 tmpva = trunc_4mpage(tmpva) + NBPDR;
5269 pte = vtopte(tmpva);
5270 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5271 pmap_pte_attr(pte, cache_bits_pte);
5279 * Flush CPU caches to make sure any data isn't cached that
5280 * shouldn't be, etc.
5283 pmap_invalidate_range(kernel_pmap, base, tmpva);
5284 pmap_invalidate_cache_range(base, tmpva, FALSE);
5290 * perform the pmap work for mincore
5293 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5296 pt_entry_t *ptep, pte;
5302 pdep = pmap_pde(pmap, addr);
5304 if (*pdep & PG_PS) {
5306 /* Compute the physical address of the 4KB page. */
5307 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5309 val = MINCORE_SUPER;
5311 ptep = pmap_pte(pmap, addr);
5313 pmap_pte_release(ptep);
5314 pa = pte & PG_FRAME;
5322 if ((pte & PG_V) != 0) {
5323 val |= MINCORE_INCORE;
5324 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5325 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5326 if ((pte & PG_A) != 0)
5327 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5329 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5330 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5331 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5332 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5333 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5336 PA_UNLOCK_COND(*locked_pa);
5342 pmap_activate(struct thread *td)
5344 pmap_t pmap, oldpmap;
5349 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5350 oldpmap = PCPU_GET(curpmap);
5351 cpuid = PCPU_GET(cpuid);
5353 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5354 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5356 CPU_CLR(cpuid, &oldpmap->pm_active);
5357 CPU_SET(cpuid, &pmap->pm_active);
5359 #if defined(PAE) || defined(PAE_TABLES)
5360 cr3 = vtophys(pmap->pm_pdpt);
5362 cr3 = vtophys(pmap->pm_pdir);
5365 * pmap_activate is for the current thread on the current cpu
5367 td->td_pcb->pcb_cr3 = cr3;
5369 PCPU_SET(curpmap, pmap);
5374 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5379 * Increase the starting virtual address of the given mapping if a
5380 * different alignment might result in more superpage mappings.
5383 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5384 vm_offset_t *addr, vm_size_t size)
5386 vm_offset_t superpage_offset;
5390 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5391 offset += ptoa(object->pg_color);
5392 superpage_offset = offset & PDRMASK;
5393 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5394 (*addr & PDRMASK) == superpage_offset)
5396 if ((*addr & PDRMASK) < superpage_offset)
5397 *addr = (*addr & ~PDRMASK) + superpage_offset;
5399 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5403 #if defined(PMAP_DEBUG)
5404 pmap_pid_dump(int pid)
5411 sx_slock(&allproc_lock);
5412 FOREACH_PROC_IN_SYSTEM(p) {
5413 if (p->p_pid != pid)
5419 pmap = vmspace_pmap(p->p_vmspace);
5420 for (i = 0; i < NPDEPTD; i++) {
5423 vm_offset_t base = i << PDRSHIFT;
5425 pde = &pmap->pm_pdir[i];
5426 if (pde && pmap_pde_v(pde)) {
5427 for (j = 0; j < NPTEPG; j++) {
5428 vm_offset_t va = base + (j << PAGE_SHIFT);
5429 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5434 sx_sunlock(&allproc_lock);
5437 pte = pmap_pte(pmap, va);
5438 if (pte && pmap_pte_v(pte)) {
5442 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5443 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5444 va, pa, m->hold_count, m->wire_count, m->flags);
5459 sx_sunlock(&allproc_lock);
5466 static void pads(pmap_t pm);
5467 void pmap_pvdump(vm_paddr_t pa);
5469 /* print address space of pmap*/
5477 if (pm == kernel_pmap)
5479 for (i = 0; i < NPDEPTD; i++)
5481 for (j = 0; j < NPTEPG; j++) {
5482 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5483 if (pm == kernel_pmap && va < KERNBASE)
5485 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5487 ptep = pmap_pte(pm, va);
5488 if (pmap_pte_v(ptep))
5489 printf("%x:%x ", va, *ptep);
5495 pmap_pvdump(vm_paddr_t pa)
5501 printf("pa %x", pa);
5502 m = PHYS_TO_VM_PAGE(pa);
5503 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5505 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);