2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
150 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
151 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
154 #define NUL0E L0_ENTRIES
155 #define NUL1E (NUL0E * NL1PG)
156 #define NUL2E (NUL1E * NL2PG)
158 #if !defined(DIAGNOSTIC)
159 #ifdef __GNUC_GNU_INLINE__
160 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
162 #define PMAP_INLINE extern inline
169 * These are configured by the mair_el1 register. This is set up in locore.S
171 #define DEVICE_MEMORY 0
172 #define UNCACHED_MEMORY 1
173 #define CACHED_MEMORY 2
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
185 #define NPV_LIST_LOCKS MAXCPU
187 #define PHYS_TO_PV_LIST_LOCK(pa) \
188 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
190 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
191 struct rwlock **_lockp = (lockp); \
192 struct rwlock *_new_lock; \
194 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
195 if (_new_lock != *_lockp) { \
196 if (*_lockp != NULL) \
197 rw_wunlock(*_lockp); \
198 *_lockp = _new_lock; \
203 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
204 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
206 #define RELEASE_PV_LIST_LOCK(lockp) do { \
207 struct rwlock **_lockp = (lockp); \
209 if (*_lockp != NULL) { \
210 rw_wunlock(*_lockp); \
215 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
216 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
218 struct pmap kernel_pmap_store;
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t kernel_vm_end = 0;
224 struct msgbuf *msgbufp = NULL;
227 * Data for the pv entry allocation mechanism.
228 * Updates to pv_invl_gen are protected by the pv_list_locks[]
229 * elements, but reads are not.
231 static struct md_page *pv_table;
232 static struct md_page pv_dummy;
234 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
235 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
236 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
238 /* This code assumes all L1 DMAP entries will be used */
239 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
240 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
242 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
243 extern pt_entry_t pagetable_dmap[];
245 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
247 static int superpages_enabled = 1;
248 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
249 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
250 "Are large page mappings enabled?");
253 * Data for the pv entry allocation mechanism
255 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
256 static struct mtx pv_chunks_mutex;
257 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
259 static void free_pv_chunk(struct pv_chunk *pc);
260 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
261 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
262 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
263 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
264 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
267 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
268 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
269 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
270 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
271 vm_offset_t va, struct rwlock **lockp);
272 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
273 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
274 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
275 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
276 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
277 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
278 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
279 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
280 vm_page_t m, struct rwlock **lockp);
282 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
283 struct rwlock **lockp);
285 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
286 struct spglist *free);
287 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
288 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
291 * These load the old table data and store the new value.
292 * They need to be atomic as the System MMU may write to the table at
293 * the same time as the CPU.
295 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
296 #define pmap_set(table, mask) atomic_set_64(table, mask)
297 #define pmap_load_clear(table) atomic_swap_64(table, 0)
298 #define pmap_load(table) (*table)
300 /********************/
301 /* Inline functions */
302 /********************/
305 pagecopy(void *s, void *d)
308 memcpy(d, s, PAGE_SIZE);
311 static __inline pd_entry_t *
312 pmap_l0(pmap_t pmap, vm_offset_t va)
315 return (&pmap->pm_l0[pmap_l0_index(va)]);
318 static __inline pd_entry_t *
319 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
323 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
324 return (&l1[pmap_l1_index(va)]);
327 static __inline pd_entry_t *
328 pmap_l1(pmap_t pmap, vm_offset_t va)
332 l0 = pmap_l0(pmap, va);
333 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
336 return (pmap_l0_to_l1(l0, va));
339 static __inline pd_entry_t *
340 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
344 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
345 return (&l2[pmap_l2_index(va)]);
348 static __inline pd_entry_t *
349 pmap_l2(pmap_t pmap, vm_offset_t va)
353 l1 = pmap_l1(pmap, va);
354 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
357 return (pmap_l1_to_l2(l1, va));
360 static __inline pt_entry_t *
361 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
365 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
366 return (&l3[pmap_l3_index(va)]);
370 * Returns the lowest valid pde for a given virtual address.
371 * The next level may or may not point to a valid page or block.
373 static __inline pd_entry_t *
374 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
376 pd_entry_t *l0, *l1, *l2, desc;
378 l0 = pmap_l0(pmap, va);
379 desc = pmap_load(l0) & ATTR_DESCR_MASK;
380 if (desc != L0_TABLE) {
385 l1 = pmap_l0_to_l1(l0, va);
386 desc = pmap_load(l1) & ATTR_DESCR_MASK;
387 if (desc != L1_TABLE) {
392 l2 = pmap_l1_to_l2(l1, va);
393 desc = pmap_load(l2) & ATTR_DESCR_MASK;
394 if (desc != L2_TABLE) {
404 * Returns the lowest valid pte block or table entry for a given virtual
405 * address. If there are no valid entries return NULL and set the level to
406 * the first invalid level.
408 static __inline pt_entry_t *
409 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
411 pd_entry_t *l1, *l2, desc;
414 l1 = pmap_l1(pmap, va);
419 desc = pmap_load(l1) & ATTR_DESCR_MASK;
420 if (desc == L1_BLOCK) {
425 if (desc != L1_TABLE) {
430 l2 = pmap_l1_to_l2(l1, va);
431 desc = pmap_load(l2) & ATTR_DESCR_MASK;
432 if (desc == L2_BLOCK) {
437 if (desc != L2_TABLE) {
443 l3 = pmap_l2_to_l3(l2, va);
444 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
451 pmap_superpages_enabled(void)
454 return (superpages_enabled != 0);
458 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
459 pd_entry_t **l2, pt_entry_t **l3)
461 pd_entry_t *l0p, *l1p, *l2p;
463 if (pmap->pm_l0 == NULL)
466 l0p = pmap_l0(pmap, va);
469 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
472 l1p = pmap_l0_to_l1(l0p, va);
475 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
481 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
484 l2p = pmap_l1_to_l2(l1p, va);
487 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
492 *l3 = pmap_l2_to_l3(l2p, va);
498 pmap_l3_valid(pt_entry_t l3)
501 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
505 CTASSERT(L1_BLOCK == L2_BLOCK);
508 * Checks if the page is dirty. We currently lack proper tracking of this on
509 * arm64 so for now assume is a page mapped as rw was accessed it is.
512 pmap_page_dirty(pt_entry_t pte)
515 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
516 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
520 pmap_resident_count_inc(pmap_t pmap, int count)
523 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
524 pmap->pm_stats.resident_count += count;
528 pmap_resident_count_dec(pmap_t pmap, int count)
531 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
532 KASSERT(pmap->pm_stats.resident_count >= count,
533 ("pmap %p resident count underflow %ld %d", pmap,
534 pmap->pm_stats.resident_count, count));
535 pmap->pm_stats.resident_count -= count;
539 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
545 l1 = (pd_entry_t *)l1pt;
546 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
548 /* Check locore has used a table L1 map */
549 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
550 ("Invalid bootstrap L1 table"));
551 /* Find the address of the L2 table */
552 l2 = (pt_entry_t *)init_pt_va;
553 *l2_slot = pmap_l2_index(va);
559 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
561 u_int l1_slot, l2_slot;
564 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
566 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
570 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
576 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
577 va = DMAP_MIN_ADDRESS;
578 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
579 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
580 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
582 pmap_load_store(&pagetable_dmap[l1_slot],
583 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
584 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
587 /* Set the upper limit of the DMAP region */
595 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
602 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
604 l1 = (pd_entry_t *)l1pt;
605 l1_slot = pmap_l1_index(va);
608 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
609 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
611 pa = pmap_early_vtophys(l1pt, l2pt);
612 pmap_load_store(&l1[l1_slot],
613 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
617 /* Clean the L2 page table */
618 memset((void *)l2_start, 0, l2pt - l2_start);
624 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
626 vm_offset_t l2pt, l3pt;
631 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
633 l2 = pmap_l2(kernel_pmap, va);
634 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
635 l2pt = (vm_offset_t)l2;
636 l2_slot = pmap_l2_index(va);
639 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
640 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
642 pa = pmap_early_vtophys(l1pt, l3pt);
643 pmap_load_store(&l2[l2_slot],
644 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
648 /* Clean the L2 page table */
649 memset((void *)l3_start, 0, l3pt - l3_start);
655 * Bootstrap the system enough to run with virtual memory.
658 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
661 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
664 vm_offset_t va, freemempos;
665 vm_offset_t dpcpu, msgbufpv;
666 vm_paddr_t pa, max_pa, min_pa;
669 kern_delta = KERNBASE - kernstart;
672 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
673 printf("%lx\n", l1pt);
674 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
676 /* Set this early so we can use the pagetable walking functions */
677 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
678 PMAP_LOCK_INIT(kernel_pmap);
680 /* Assume the address we were loaded to is a valid physical address */
681 min_pa = max_pa = KERNBASE - kern_delta;
684 * Find the minimum physical address. physmap is sorted,
685 * but may contain empty ranges.
687 for (i = 0; i < (physmap_idx * 2); i += 2) {
688 if (physmap[i] == physmap[i + 1])
690 if (physmap[i] <= min_pa)
692 if (physmap[i + 1] > max_pa)
693 max_pa = physmap[i + 1];
696 /* Create a direct map region early so we can use it for pa -> va */
697 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
700 pa = KERNBASE - kern_delta;
703 * Start to initialise phys_avail by copying from physmap
704 * up to the physical address KERNBASE points at.
706 map_slot = avail_slot = 0;
707 for (; map_slot < (physmap_idx * 2) &&
708 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
709 if (physmap[map_slot] == physmap[map_slot + 1])
712 if (physmap[map_slot] <= pa &&
713 physmap[map_slot + 1] > pa)
716 phys_avail[avail_slot] = physmap[map_slot];
717 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
718 physmem += (phys_avail[avail_slot + 1] -
719 phys_avail[avail_slot]) >> PAGE_SHIFT;
723 /* Add the memory before the kernel */
724 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
725 phys_avail[avail_slot] = physmap[map_slot];
726 phys_avail[avail_slot + 1] = pa;
727 physmem += (phys_avail[avail_slot + 1] -
728 phys_avail[avail_slot]) >> PAGE_SHIFT;
731 used_map_slot = map_slot;
734 * Read the page table to find out what is already mapped.
735 * This assumes we have mapped a block of memory from KERNBASE
736 * using a single L1 entry.
738 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
740 /* Sanity check the index, KERNBASE should be the first VA */
741 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
743 /* Find how many pages we have mapped */
744 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
745 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
748 /* Check locore used L2 blocks */
749 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
750 ("Invalid bootstrap L2 table"));
751 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
752 ("Incorrect PA in L2 table"));
758 va = roundup2(va, L1_SIZE);
760 freemempos = KERNBASE + kernlen;
761 freemempos = roundup2(freemempos, PAGE_SIZE);
762 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
763 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
764 /* And the l3 tables for the early devmap */
765 freemempos = pmap_bootstrap_l3(l1pt,
766 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
770 #define alloc_pages(var, np) \
771 (var) = freemempos; \
772 freemempos += (np * PAGE_SIZE); \
773 memset((char *)(var), 0, ((np) * PAGE_SIZE));
775 /* Allocate dynamic per-cpu area. */
776 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
777 dpcpu_init((void *)dpcpu, 0);
779 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
780 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
781 msgbufp = (void *)msgbufpv;
783 virtual_avail = roundup2(freemempos, L1_SIZE);
784 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
785 kernel_vm_end = virtual_avail;
787 pa = pmap_early_vtophys(l1pt, freemempos);
789 /* Finish initialising physmap */
790 map_slot = used_map_slot;
791 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
792 map_slot < (physmap_idx * 2); map_slot += 2) {
793 if (physmap[map_slot] == physmap[map_slot + 1])
796 /* Have we used the current range? */
797 if (physmap[map_slot + 1] <= pa)
800 /* Do we need to split the entry? */
801 if (physmap[map_slot] < pa) {
802 phys_avail[avail_slot] = pa;
803 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
805 phys_avail[avail_slot] = physmap[map_slot];
806 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
808 physmem += (phys_avail[avail_slot + 1] -
809 phys_avail[avail_slot]) >> PAGE_SHIFT;
813 phys_avail[avail_slot] = 0;
814 phys_avail[avail_slot + 1] = 0;
817 * Maxmem isn't the "maximum memory", it's one larger than the
818 * highest page of the physical address space. It should be
819 * called something like "Maxphyspage".
821 Maxmem = atop(phys_avail[avail_slot - 1]);
827 * Initialize a vm_page's machine-dependent fields.
830 pmap_page_init(vm_page_t m)
833 TAILQ_INIT(&m->md.pv_list);
834 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
838 * Initialize the pmap module.
839 * Called by vm_init, to initialize any structures that the pmap
840 * system needs to map virtual memory.
849 * Are large page mappings enabled?
851 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
854 * Initialize the pv chunk list mutex.
856 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
859 * Initialize the pool of pv list locks.
861 for (i = 0; i < NPV_LIST_LOCKS; i++)
862 rw_init(&pv_list_locks[i], "pmap pv list");
865 * Calculate the size of the pv head table for superpages.
867 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
870 * Allocate memory for the pv head table for superpages.
872 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
874 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
876 for (i = 0; i < pv_npg; i++)
877 TAILQ_INIT(&pv_table[i].pv_list);
878 TAILQ_INIT(&pv_dummy.pv_list);
881 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
882 "2MB page mapping counters");
884 static u_long pmap_l2_demotions;
885 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
886 &pmap_l2_demotions, 0, "2MB page demotions");
888 static u_long pmap_l2_p_failures;
889 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
890 &pmap_l2_p_failures, 0, "2MB page promotion failures");
892 static u_long pmap_l2_promotions;
893 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
894 &pmap_l2_promotions, 0, "2MB page promotions");
897 * Invalidate a single TLB entry.
900 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
906 "tlbi vaae1is, %0 \n"
909 : : "r"(va >> PAGE_SHIFT));
914 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
920 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
922 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
931 pmap_invalidate_all(pmap_t pmap)
944 * Routine: pmap_extract
946 * Extract the physical page address associated
947 * with the given map/virtual_address pair.
950 pmap_extract(pmap_t pmap, vm_offset_t va)
952 pt_entry_t *pte, tpte;
959 * Find the block or page map for this virtual address. pmap_pte
960 * will return either a valid block/page entry, or NULL.
962 pte = pmap_pte(pmap, va, &lvl);
964 tpte = pmap_load(pte);
965 pa = tpte & ~ATTR_MASK;
968 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
969 ("pmap_extract: Invalid L1 pte found: %lx",
970 tpte & ATTR_DESCR_MASK));
971 pa |= (va & L1_OFFSET);
974 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
975 ("pmap_extract: Invalid L2 pte found: %lx",
976 tpte & ATTR_DESCR_MASK));
977 pa |= (va & L2_OFFSET);
980 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
981 ("pmap_extract: Invalid L3 pte found: %lx",
982 tpte & ATTR_DESCR_MASK));
983 pa |= (va & L3_OFFSET);
992 * Routine: pmap_extract_and_hold
994 * Atomically extract and hold the physical page
995 * with the given pmap and virtual address pair
996 * if that mapping permits the given protection.
999 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1001 pt_entry_t *pte, tpte;
1011 pte = pmap_pte(pmap, va, &lvl);
1013 tpte = pmap_load(pte);
1015 KASSERT(lvl > 0 && lvl <= 3,
1016 ("pmap_extract_and_hold: Invalid level %d", lvl));
1017 CTASSERT(L1_BLOCK == L2_BLOCK);
1018 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1019 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1020 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1021 tpte & ATTR_DESCR_MASK));
1022 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1023 ((prot & VM_PROT_WRITE) == 0)) {
1026 off = va & L1_OFFSET;
1029 off = va & L2_OFFSET;
1035 if (vm_page_pa_tryrelock(pmap,
1036 (tpte & ~ATTR_MASK) | off, &pa))
1038 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1048 pmap_kextract(vm_offset_t va)
1050 pt_entry_t *pte, tpte;
1054 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1055 pa = DMAP_TO_PHYS(va);
1058 pte = pmap_pte(kernel_pmap, va, &lvl);
1060 tpte = pmap_load(pte);
1061 pa = tpte & ~ATTR_MASK;
1064 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1065 ("pmap_kextract: Invalid L1 pte found: %lx",
1066 tpte & ATTR_DESCR_MASK));
1067 pa |= (va & L1_OFFSET);
1070 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1071 ("pmap_kextract: Invalid L2 pte found: %lx",
1072 tpte & ATTR_DESCR_MASK));
1073 pa |= (va & L2_OFFSET);
1076 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1077 ("pmap_kextract: Invalid L3 pte found: %lx",
1078 tpte & ATTR_DESCR_MASK));
1079 pa |= (va & L3_OFFSET);
1087 /***************************************************
1088 * Low level mapping routines.....
1089 ***************************************************/
1092 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1095 pt_entry_t *pte, attr;
1099 KASSERT((pa & L3_OFFSET) == 0,
1100 ("pmap_kenter: Invalid physical address"));
1101 KASSERT((sva & L3_OFFSET) == 0,
1102 ("pmap_kenter: Invalid virtual address"));
1103 KASSERT((size & PAGE_MASK) == 0,
1104 ("pmap_kenter: Mapping is not page-sized"));
1106 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1107 if (mode == DEVICE_MEMORY)
1112 pde = pmap_pde(kernel_pmap, va, &lvl);
1113 KASSERT(pde != NULL,
1114 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1115 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1117 pte = pmap_l2_to_l3(pde, va);
1118 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1124 pmap_invalidate_range(kernel_pmap, sva, va);
1128 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1131 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1135 * Remove a page from the kernel pagetables.
1138 pmap_kremove(vm_offset_t va)
1143 pte = pmap_pte(kernel_pmap, va, &lvl);
1144 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1145 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1147 pmap_load_clear(pte);
1148 pmap_invalidate_page(kernel_pmap, va);
1152 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1158 KASSERT((sva & L3_OFFSET) == 0,
1159 ("pmap_kremove_device: Invalid virtual address"));
1160 KASSERT((size & PAGE_MASK) == 0,
1161 ("pmap_kremove_device: Mapping is not page-sized"));
1165 pte = pmap_pte(kernel_pmap, va, &lvl);
1166 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1168 ("Invalid device pagetable level: %d != 3", lvl));
1169 pmap_load_clear(pte);
1174 pmap_invalidate_range(kernel_pmap, sva, va);
1178 * Used to map a range of physical addresses into kernel
1179 * virtual address space.
1181 * The value passed in '*virt' is a suggested virtual address for
1182 * the mapping. Architectures which can support a direct-mapped
1183 * physical to virtual region can return the appropriate address
1184 * within that region, leaving '*virt' unchanged. Other
1185 * architectures should map the pages starting at '*virt' and
1186 * update '*virt' with the first usable address after the mapped
1190 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1192 return PHYS_TO_DMAP(start);
1197 * Add a list of wired pages to the kva
1198 * this routine is only used for temporary
1199 * kernel mappings that do not need to have
1200 * page modification or references recorded.
1201 * Note that old mappings are simply written
1202 * over. The page *must* be wired.
1203 * Note: SMP coherent. Uses a ranged shootdown IPI.
1206 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1209 pt_entry_t *pte, pa;
1215 for (i = 0; i < count; i++) {
1216 pde = pmap_pde(kernel_pmap, va, &lvl);
1217 KASSERT(pde != NULL,
1218 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1220 ("pmap_qenter: Invalid level %d", lvl));
1223 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1224 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1225 if (m->md.pv_memattr == DEVICE_MEMORY)
1227 pte = pmap_l2_to_l3(pde, va);
1228 pmap_load_store(pte, pa);
1232 pmap_invalidate_range(kernel_pmap, sva, va);
1236 * This routine tears out page mappings from the
1237 * kernel -- it is meant only for temporary mappings.
1240 pmap_qremove(vm_offset_t sva, int count)
1246 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1249 while (count-- > 0) {
1250 pte = pmap_pte(kernel_pmap, va, &lvl);
1252 ("Invalid device pagetable level: %d != 3", lvl));
1254 pmap_load_clear(pte);
1259 pmap_invalidate_range(kernel_pmap, sva, va);
1262 /***************************************************
1263 * Page table page management routines.....
1264 ***************************************************/
1265 static __inline void
1266 pmap_free_zero_pages(struct spglist *free)
1270 while ((m = SLIST_FIRST(free)) != NULL) {
1271 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1272 /* Preserve the page's PG_ZERO setting. */
1273 vm_page_free_toq(m);
1278 * Schedule the specified unused page table page to be freed. Specifically,
1279 * add the page to the specified list of pages that will be released to the
1280 * physical memory manager after the TLB has been updated.
1282 static __inline void
1283 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1284 boolean_t set_PG_ZERO)
1288 m->flags |= PG_ZERO;
1290 m->flags &= ~PG_ZERO;
1291 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1295 * Decrements a page table page's wire count, which is used to record the
1296 * number of valid page table entries within the page. If the wire count
1297 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1298 * page table page was unmapped and FALSE otherwise.
1300 static inline boolean_t
1301 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1305 if (m->wire_count == 0) {
1306 _pmap_unwire_l3(pmap, va, m, free);
1313 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1316 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1318 * unmap the page table page
1320 if (m->pindex >= (NUL2E + NUL1E)) {
1324 l0 = pmap_l0(pmap, va);
1325 pmap_load_clear(l0);
1326 } else if (m->pindex >= NUL2E) {
1330 l1 = pmap_l1(pmap, va);
1331 pmap_load_clear(l1);
1336 l2 = pmap_l2(pmap, va);
1337 pmap_load_clear(l2);
1339 pmap_resident_count_dec(pmap, 1);
1340 if (m->pindex < NUL2E) {
1341 /* We just released an l3, unhold the matching l2 */
1342 pd_entry_t *l1, tl1;
1345 l1 = pmap_l1(pmap, va);
1346 tl1 = pmap_load(l1);
1347 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1348 pmap_unwire_l3(pmap, va, l2pg, free);
1349 } else if (m->pindex < (NUL2E + NUL1E)) {
1350 /* We just released an l2, unhold the matching l1 */
1351 pd_entry_t *l0, tl0;
1354 l0 = pmap_l0(pmap, va);
1355 tl0 = pmap_load(l0);
1356 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1357 pmap_unwire_l3(pmap, va, l1pg, free);
1359 pmap_invalidate_page(pmap, va);
1362 * This is a release store so that the ordinary store unmapping
1363 * the page table page is globally performed before TLB shoot-
1366 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1369 * Put page on a list so that it is released after
1370 * *ALL* TLB shootdown is done
1372 pmap_add_delayed_free_list(m, free, TRUE);
1376 * After removing a page table entry, this routine is used to
1377 * conditionally free the page, and manage the hold/wire counts.
1380 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1381 struct spglist *free)
1385 if (va >= VM_MAXUSER_ADDRESS)
1387 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1388 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1389 return (pmap_unwire_l3(pmap, va, mpte, free));
1393 pmap_pinit0(pmap_t pmap)
1396 PMAP_LOCK_INIT(pmap);
1397 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1398 pmap->pm_l0 = kernel_pmap->pm_l0;
1399 pmap->pm_root.rt_root = 0;
1403 pmap_pinit(pmap_t pmap)
1409 * allocate the l0 page
1411 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1412 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1415 l0phys = VM_PAGE_TO_PHYS(l0pt);
1416 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1418 if ((l0pt->flags & PG_ZERO) == 0)
1419 pagezero(pmap->pm_l0);
1421 pmap->pm_root.rt_root = 0;
1422 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1428 * This routine is called if the desired page table page does not exist.
1430 * If page table page allocation fails, this routine may sleep before
1431 * returning NULL. It sleeps only if a lock pointer was given.
1433 * Note: If a page allocation fails at page table level two or three,
1434 * one or two pages may be held during the wait, only to be released
1435 * afterwards. This conservative approach is easily argued to avoid
1439 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1441 vm_page_t m, l1pg, l2pg;
1443 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1446 * Allocate a page table page.
1448 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1449 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1450 if (lockp != NULL) {
1451 RELEASE_PV_LIST_LOCK(lockp);
1458 * Indicate the need to retry. While waiting, the page table
1459 * page may have been allocated.
1463 if ((m->flags & PG_ZERO) == 0)
1467 * Map the pagetable page into the process address space, if
1468 * it isn't already there.
1471 if (ptepindex >= (NUL2E + NUL1E)) {
1473 vm_pindex_t l0index;
1475 l0index = ptepindex - (NUL2E + NUL1E);
1476 l0 = &pmap->pm_l0[l0index];
1477 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1478 } else if (ptepindex >= NUL2E) {
1479 vm_pindex_t l0index, l1index;
1480 pd_entry_t *l0, *l1;
1483 l1index = ptepindex - NUL2E;
1484 l0index = l1index >> L0_ENTRIES_SHIFT;
1486 l0 = &pmap->pm_l0[l0index];
1487 tl0 = pmap_load(l0);
1489 /* recurse for allocating page dir */
1490 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1493 /* XXX: release mem barrier? */
1494 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1495 vm_page_free_zero(m);
1499 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1503 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1504 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1505 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1507 vm_pindex_t l0index, l1index;
1508 pd_entry_t *l0, *l1, *l2;
1509 pd_entry_t tl0, tl1;
1511 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1512 l0index = l1index >> L0_ENTRIES_SHIFT;
1514 l0 = &pmap->pm_l0[l0index];
1515 tl0 = pmap_load(l0);
1517 /* recurse for allocating page dir */
1518 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1521 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1522 vm_page_free_zero(m);
1525 tl0 = pmap_load(l0);
1526 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1527 l1 = &l1[l1index & Ln_ADDR_MASK];
1529 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1530 l1 = &l1[l1index & Ln_ADDR_MASK];
1531 tl1 = pmap_load(l1);
1533 /* recurse for allocating page dir */
1534 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1537 /* XXX: release mem barrier? */
1538 atomic_subtract_int(
1539 &vm_cnt.v_wire_count, 1);
1540 vm_page_free_zero(m);
1544 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1549 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1550 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1551 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1554 pmap_resident_count_inc(pmap, 1);
1560 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1562 vm_pindex_t ptepindex;
1563 pd_entry_t *pde, tpde;
1571 * Calculate pagetable page index
1573 ptepindex = pmap_l2_pindex(va);
1576 * Get the page directory entry
1578 pde = pmap_pde(pmap, va, &lvl);
1581 * If the page table page is mapped, we just increment the hold count,
1582 * and activate it. If we get a level 2 pde it will point to a level 3
1590 pte = pmap_l0_to_l1(pde, va);
1591 KASSERT(pmap_load(pte) == 0,
1592 ("pmap_alloc_l3: TODO: l0 superpages"));
1597 pte = pmap_l1_to_l2(pde, va);
1598 KASSERT(pmap_load(pte) == 0,
1599 ("pmap_alloc_l3: TODO: l1 superpages"));
1603 tpde = pmap_load(pde);
1605 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1611 panic("pmap_alloc_l3: Invalid level %d", lvl);
1615 * Here if the pte page isn't mapped, or if it has been deallocated.
1617 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1618 if (m == NULL && lockp != NULL)
1625 /***************************************************
1626 * Pmap allocation/deallocation routines.
1627 ***************************************************/
1630 * Release any resources held by the given physical map.
1631 * Called when a pmap initialized by pmap_pinit is being released.
1632 * Should only be called if the map contains no valid mappings.
1635 pmap_release(pmap_t pmap)
1639 KASSERT(pmap->pm_stats.resident_count == 0,
1640 ("pmap_release: pmap resident count %ld != 0",
1641 pmap->pm_stats.resident_count));
1642 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1643 ("pmap_release: pmap has reserved page table page(s)"));
1645 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1648 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1649 vm_page_free_zero(m);
1653 kvm_size(SYSCTL_HANDLER_ARGS)
1655 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1657 return sysctl_handle_long(oidp, &ksize, 0, req);
1659 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1660 0, 0, kvm_size, "LU", "Size of KVM");
1663 kvm_free(SYSCTL_HANDLER_ARGS)
1665 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1667 return sysctl_handle_long(oidp, &kfree, 0, req);
1669 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1670 0, 0, kvm_free, "LU", "Amount of KVM free");
1673 * grow the number of kernel page table entries, if needed
1676 pmap_growkernel(vm_offset_t addr)
1680 pd_entry_t *l0, *l1, *l2;
1682 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1684 addr = roundup2(addr, L2_SIZE);
1685 if (addr - 1 >= kernel_map->max_offset)
1686 addr = kernel_map->max_offset;
1687 while (kernel_vm_end < addr) {
1688 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1689 KASSERT(pmap_load(l0) != 0,
1690 ("pmap_growkernel: No level 0 kernel entry"));
1692 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1693 if (pmap_load(l1) == 0) {
1694 /* We need a new PDP entry */
1695 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1696 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1697 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1699 panic("pmap_growkernel: no memory to grow kernel");
1700 if ((nkpg->flags & PG_ZERO) == 0)
1701 pmap_zero_page(nkpg);
1702 paddr = VM_PAGE_TO_PHYS(nkpg);
1703 pmap_load_store(l1, paddr | L1_TABLE);
1704 continue; /* try again */
1706 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1707 if ((pmap_load(l2) & ATTR_AF) != 0) {
1708 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1709 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1710 kernel_vm_end = kernel_map->max_offset;
1716 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1717 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1720 panic("pmap_growkernel: no memory to grow kernel");
1721 if ((nkpg->flags & PG_ZERO) == 0)
1722 pmap_zero_page(nkpg);
1723 paddr = VM_PAGE_TO_PHYS(nkpg);
1724 pmap_load_store(l2, paddr | L2_TABLE);
1725 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1727 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1728 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1729 kernel_vm_end = kernel_map->max_offset;
1736 /***************************************************
1737 * page management routines.
1738 ***************************************************/
1740 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1741 CTASSERT(_NPCM == 3);
1742 CTASSERT(_NPCPV == 168);
1744 static __inline struct pv_chunk *
1745 pv_to_chunk(pv_entry_t pv)
1748 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1751 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1753 #define PC_FREE0 0xfffffffffffffffful
1754 #define PC_FREE1 0xfffffffffffffffful
1755 #define PC_FREE2 0x000000fffffffffful
1757 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1761 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1763 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1764 "Current number of pv entry chunks");
1765 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1766 "Current number of pv entry chunks allocated");
1767 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1768 "Current number of pv entry chunks frees");
1769 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1770 "Number of times tried to get a chunk page but failed.");
1772 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1773 static int pv_entry_spare;
1775 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1776 "Current number of pv entry frees");
1777 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1778 "Current number of pv entry allocs");
1779 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1780 "Current number of pv entries");
1781 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1782 "Current number of spare pv entries");
1787 * We are in a serious low memory condition. Resort to
1788 * drastic measures to free some pages so we can allocate
1789 * another pv entry chunk.
1791 * Returns NULL if PV entries were reclaimed from the specified pmap.
1793 * We do not, however, unmap 2mpages because subsequent accesses will
1794 * allocate per-page pv entries until repromotion occurs, thereby
1795 * exacerbating the shortage of free pv entries.
1798 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1800 struct pch new_tail;
1801 struct pv_chunk *pc;
1802 struct md_page *pvh;
1805 pt_entry_t *pte, tpte;
1809 struct spglist free;
1811 int bit, field, freed, lvl;
1813 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1814 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1818 TAILQ_INIT(&new_tail);
1819 mtx_lock(&pv_chunks_mutex);
1820 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
1821 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1822 mtx_unlock(&pv_chunks_mutex);
1823 if (pmap != pc->pc_pmap) {
1824 if (pmap != NULL && pmap != locked_pmap)
1827 /* Avoid deadlock and lock recursion. */
1828 if (pmap > locked_pmap) {
1829 RELEASE_PV_LIST_LOCK(lockp);
1831 } else if (pmap != locked_pmap &&
1832 !PMAP_TRYLOCK(pmap)) {
1834 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1835 mtx_lock(&pv_chunks_mutex);
1841 * Destroy every non-wired, 4 KB page mapping in the chunk.
1844 for (field = 0; field < _NPCM; field++) {
1845 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1846 inuse != 0; inuse &= ~(1UL << bit)) {
1847 bit = ffsl(inuse) - 1;
1848 pv = &pc->pc_pventry[field * 64 + bit];
1850 pde = pmap_pde(pmap, va, &lvl);
1853 pte = pmap_l2_to_l3(pde, va);
1854 tpte = pmap_load(pte);
1855 if ((tpte & ATTR_SW_WIRED) != 0)
1857 tpte = pmap_load_clear(pte);
1858 pmap_invalidate_page(pmap, va);
1859 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1860 if (pmap_page_dirty(tpte))
1862 if ((tpte & ATTR_AF) != 0)
1863 vm_page_aflag_set(m, PGA_REFERENCED);
1864 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1865 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1867 if (TAILQ_EMPTY(&m->md.pv_list) &&
1868 (m->flags & PG_FICTITIOUS) == 0) {
1869 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1870 if (TAILQ_EMPTY(&pvh->pv_list)) {
1871 vm_page_aflag_clear(m,
1875 pc->pc_map[field] |= 1UL << bit;
1876 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1881 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1882 mtx_lock(&pv_chunks_mutex);
1885 /* Every freed mapping is for a 4 KB page. */
1886 pmap_resident_count_dec(pmap, freed);
1887 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1888 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1889 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1890 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1891 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1892 pc->pc_map[2] == PC_FREE2) {
1893 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1894 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1895 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1896 /* Entire chunk is free; return it. */
1897 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1898 dump_drop_page(m_pc->phys_addr);
1899 mtx_lock(&pv_chunks_mutex);
1902 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1903 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1904 mtx_lock(&pv_chunks_mutex);
1905 /* One freed pv entry in locked_pmap is sufficient. */
1906 if (pmap == locked_pmap)
1909 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1910 mtx_unlock(&pv_chunks_mutex);
1911 if (pmap != NULL && pmap != locked_pmap)
1913 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
1914 m_pc = SLIST_FIRST(&free);
1915 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
1916 /* Recycle a freed page table page. */
1917 m_pc->wire_count = 1;
1918 atomic_add_int(&vm_cnt.v_wire_count, 1);
1920 pmap_free_zero_pages(&free);
1925 * free the pv_entry back to the free list
1928 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1930 struct pv_chunk *pc;
1931 int idx, field, bit;
1933 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1934 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1935 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1936 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1937 pc = pv_to_chunk(pv);
1938 idx = pv - &pc->pc_pventry[0];
1941 pc->pc_map[field] |= 1ul << bit;
1942 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1943 pc->pc_map[2] != PC_FREE2) {
1944 /* 98% of the time, pc is already at the head of the list. */
1945 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1946 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1947 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1951 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1956 free_pv_chunk(struct pv_chunk *pc)
1960 mtx_lock(&pv_chunks_mutex);
1961 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1962 mtx_unlock(&pv_chunks_mutex);
1963 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1964 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1965 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1966 /* entire chunk is free, return it */
1967 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1968 dump_drop_page(m->phys_addr);
1969 vm_page_unwire(m, PQ_NONE);
1974 * Returns a new PV entry, allocating a new PV chunk from the system when
1975 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1976 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1979 * The given PV list lock may be released.
1982 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1986 struct pv_chunk *pc;
1989 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1990 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1992 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1994 for (field = 0; field < _NPCM; field++) {
1995 if (pc->pc_map[field]) {
1996 bit = ffsl(pc->pc_map[field]) - 1;
2000 if (field < _NPCM) {
2001 pv = &pc->pc_pventry[field * 64 + bit];
2002 pc->pc_map[field] &= ~(1ul << bit);
2003 /* If this was the last item, move it to tail */
2004 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
2005 pc->pc_map[2] == 0) {
2006 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2007 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
2010 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2011 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
2015 /* No free items, allocate another chunk */
2016 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2019 if (lockp == NULL) {
2020 PV_STAT(pc_chunk_tryfail++);
2023 m = reclaim_pv_chunk(pmap, lockp);
2027 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2028 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2029 dump_add_page(m->phys_addr);
2030 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2032 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2033 pc->pc_map[1] = PC_FREE1;
2034 pc->pc_map[2] = PC_FREE2;
2035 mtx_lock(&pv_chunks_mutex);
2036 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2037 mtx_unlock(&pv_chunks_mutex);
2038 pv = &pc->pc_pventry[0];
2039 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2040 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2041 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2046 * Ensure that the number of spare PV entries in the specified pmap meets or
2047 * exceeds the given count, "needed".
2049 * The given PV list lock may be released.
2052 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2054 struct pch new_tail;
2055 struct pv_chunk *pc;
2059 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2060 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2063 * Newly allocated PV chunks must be stored in a private list until
2064 * the required number of PV chunks have been allocated. Otherwise,
2065 * reclaim_pv_chunk() could recycle one of these chunks. In
2066 * contrast, these chunks must be added to the pmap upon allocation.
2068 TAILQ_INIT(&new_tail);
2071 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2072 bit_count((bitstr_t *)pc->pc_map, 0,
2073 sizeof(pc->pc_map) * NBBY, &free);
2077 if (avail >= needed)
2080 for (; avail < needed; avail += _NPCPV) {
2081 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2084 m = reclaim_pv_chunk(pmap, lockp);
2088 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2089 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2090 dump_add_page(m->phys_addr);
2091 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2093 pc->pc_map[0] = PC_FREE0;
2094 pc->pc_map[1] = PC_FREE1;
2095 pc->pc_map[2] = PC_FREE2;
2096 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2097 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2098 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2100 if (!TAILQ_EMPTY(&new_tail)) {
2101 mtx_lock(&pv_chunks_mutex);
2102 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2103 mtx_unlock(&pv_chunks_mutex);
2108 * First find and then remove the pv entry for the specified pmap and virtual
2109 * address from the specified pv list. Returns the pv entry if found and NULL
2110 * otherwise. This operation can be performed on pv lists for either 4KB or
2111 * 2MB page mappings.
2113 static __inline pv_entry_t
2114 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2118 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2119 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2120 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2129 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2130 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2131 * entries for each of the 4KB page mappings.
2134 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2135 struct rwlock **lockp)
2137 struct md_page *pvh;
2138 struct pv_chunk *pc;
2140 vm_offset_t va_last;
2144 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2145 KASSERT((pa & L2_OFFSET) == 0,
2146 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2147 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2150 * Transfer the 2mpage's pv entry for this mapping to the first
2151 * page's pv list. Once this transfer begins, the pv list lock
2152 * must not be released until the last pv entry is reinstantiated.
2154 pvh = pa_to_pvh(pa);
2155 va = va & ~L2_OFFSET;
2156 pv = pmap_pvh_remove(pvh, pmap, va);
2157 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2158 m = PHYS_TO_VM_PAGE(pa);
2159 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2161 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2162 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2163 va_last = va + L2_SIZE - PAGE_SIZE;
2165 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2166 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2167 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2168 for (field = 0; field < _NPCM; field++) {
2169 while (pc->pc_map[field]) {
2170 bit = ffsl(pc->pc_map[field]) - 1;
2171 pc->pc_map[field] &= ~(1ul << bit);
2172 pv = &pc->pc_pventry[field * 64 + bit];
2176 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2177 ("pmap_pv_demote_l2: page %p is not managed", m));
2178 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2184 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2185 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2188 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2189 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2190 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2192 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2193 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2197 * First find and then destroy the pv entry for the specified pmap and virtual
2198 * address. This operation can be performed on pv lists for either 4KB or 2MB
2202 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2206 pv = pmap_pvh_remove(pvh, pmap, va);
2207 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2208 free_pv_entry(pmap, pv);
2212 * Conditionally create the PV entry for a 4KB page mapping if the required
2213 * memory can be allocated without resorting to reclamation.
2216 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2217 struct rwlock **lockp)
2221 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2222 /* Pass NULL instead of the lock pointer to disable reclamation. */
2223 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2225 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2226 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2234 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2237 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2238 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2240 struct md_page *pvh;
2242 vm_offset_t eva, va;
2245 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2246 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2247 old_l2 = pmap_load_clear(l2);
2248 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2249 if (old_l2 & ATTR_SW_WIRED)
2250 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2251 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2252 if (old_l2 & ATTR_SW_MANAGED) {
2253 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2254 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2255 pmap_pvh_free(pvh, pmap, sva);
2256 eva = sva + L2_SIZE;
2257 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2258 va < eva; va += PAGE_SIZE, m++) {
2259 if (pmap_page_dirty(old_l2))
2261 if (old_l2 & ATTR_AF)
2262 vm_page_aflag_set(m, PGA_REFERENCED);
2263 if (TAILQ_EMPTY(&m->md.pv_list) &&
2264 TAILQ_EMPTY(&pvh->pv_list))
2265 vm_page_aflag_clear(m, PGA_WRITEABLE);
2268 KASSERT(pmap != kernel_pmap,
2269 ("Attempting to remove an l2 kernel page"));
2270 ml3 = pmap_remove_pt_page(pmap, sva);
2272 pmap_resident_count_dec(pmap, 1);
2273 KASSERT(ml3->wire_count == NL3PG,
2274 ("pmap_remove_pages: l3 page wire count error"));
2275 ml3->wire_count = 0;
2276 pmap_add_delayed_free_list(ml3, free, FALSE);
2277 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2279 return (pmap_unuse_pt(pmap, sva, l1e, free));
2283 * pmap_remove_l3: do the things to unmap a page in a process
2286 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2287 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2289 struct md_page *pvh;
2293 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2294 old_l3 = pmap_load_clear(l3);
2295 pmap_invalidate_page(pmap, va);
2296 if (old_l3 & ATTR_SW_WIRED)
2297 pmap->pm_stats.wired_count -= 1;
2298 pmap_resident_count_dec(pmap, 1);
2299 if (old_l3 & ATTR_SW_MANAGED) {
2300 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2301 if (pmap_page_dirty(old_l3))
2303 if (old_l3 & ATTR_AF)
2304 vm_page_aflag_set(m, PGA_REFERENCED);
2305 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2306 pmap_pvh_free(&m->md, pmap, va);
2307 if (TAILQ_EMPTY(&m->md.pv_list) &&
2308 (m->flags & PG_FICTITIOUS) == 0) {
2309 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2310 if (TAILQ_EMPTY(&pvh->pv_list))
2311 vm_page_aflag_clear(m, PGA_WRITEABLE);
2314 return (pmap_unuse_pt(pmap, va, l2e, free));
2318 * Remove the given range of addresses from the specified map.
2320 * It is assumed that the start and end are properly
2321 * rounded to the page size.
2324 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2326 struct rwlock *lock;
2327 vm_offset_t va, va_next;
2328 pd_entry_t *l0, *l1, *l2;
2329 pt_entry_t l3_paddr, *l3;
2330 struct spglist free;
2333 * Perform an unsynchronized read. This is, however, safe.
2335 if (pmap->pm_stats.resident_count == 0)
2343 for (; sva < eva; sva = va_next) {
2345 if (pmap->pm_stats.resident_count == 0)
2348 l0 = pmap_l0(pmap, sva);
2349 if (pmap_load(l0) == 0) {
2350 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2356 l1 = pmap_l0_to_l1(l0, sva);
2357 if (pmap_load(l1) == 0) {
2358 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2365 * Calculate index for next page table.
2367 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2371 l2 = pmap_l1_to_l2(l1, sva);
2375 l3_paddr = pmap_load(l2);
2377 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2378 if (sva + L2_SIZE == va_next && eva >= va_next) {
2379 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2382 } else if (pmap_demote_l2_locked(pmap, l2,
2383 sva &~L2_OFFSET, &lock) == NULL)
2385 l3_paddr = pmap_load(l2);
2389 * Weed out invalid mappings.
2391 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2395 * Limit our scan to either the end of the va represented
2396 * by the current page table page, or to the end of the
2397 * range being removed.
2403 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2406 panic("l3 == NULL");
2407 if (pmap_load(l3) == 0) {
2408 if (va != va_next) {
2409 pmap_invalidate_range(pmap, va, sva);
2416 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2423 pmap_invalidate_range(pmap, va, sva);
2428 pmap_free_zero_pages(&free);
2432 * Routine: pmap_remove_all
2434 * Removes this physical page from
2435 * all physical maps in which it resides.
2436 * Reflects back modify bits to the pager.
2439 * Original versions of this routine were very
2440 * inefficient because they iteratively called
2441 * pmap_remove (slow...)
2445 pmap_remove_all(vm_page_t m)
2447 struct md_page *pvh;
2450 struct rwlock *lock;
2451 pd_entry_t *pde, tpde;
2452 pt_entry_t *pte, tpte;
2454 struct spglist free;
2455 int lvl, pvh_gen, md_gen;
2457 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2458 ("pmap_remove_all: page %p is not managed", m));
2460 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2461 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2462 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2465 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2467 if (!PMAP_TRYLOCK(pmap)) {
2468 pvh_gen = pvh->pv_gen;
2472 if (pvh_gen != pvh->pv_gen) {
2479 pte = pmap_pte(pmap, va, &lvl);
2480 KASSERT(pte != NULL,
2481 ("pmap_remove_all: no page table entry found"));
2483 ("pmap_remove_all: invalid pte level %d", lvl));
2485 pmap_demote_l2_locked(pmap, pte, va, &lock);
2488 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2490 if (!PMAP_TRYLOCK(pmap)) {
2491 pvh_gen = pvh->pv_gen;
2492 md_gen = m->md.pv_gen;
2496 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2502 pmap_resident_count_dec(pmap, 1);
2504 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2505 KASSERT(pde != NULL,
2506 ("pmap_remove_all: no page directory entry found"));
2508 ("pmap_remove_all: invalid pde level %d", lvl));
2509 tpde = pmap_load(pde);
2511 pte = pmap_l2_to_l3(pde, pv->pv_va);
2512 tpte = pmap_load(pte);
2513 pmap_load_clear(pte);
2514 pmap_invalidate_page(pmap, pv->pv_va);
2515 if (tpte & ATTR_SW_WIRED)
2516 pmap->pm_stats.wired_count--;
2517 if ((tpte & ATTR_AF) != 0)
2518 vm_page_aflag_set(m, PGA_REFERENCED);
2521 * Update the vm_page_t clean and reference bits.
2523 if (pmap_page_dirty(tpte))
2525 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2526 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2528 free_pv_entry(pmap, pv);
2531 vm_page_aflag_clear(m, PGA_WRITEABLE);
2533 pmap_free_zero_pages(&free);
2537 * Set the physical protection on the
2538 * specified range of this map as requested.
2541 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2543 vm_offset_t va, va_next;
2544 pd_entry_t *l0, *l1, *l2;
2545 pt_entry_t *l3p, l3, nbits;
2547 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2548 if (prot == VM_PROT_NONE) {
2549 pmap_remove(pmap, sva, eva);
2553 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2554 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2558 for (; sva < eva; sva = va_next) {
2560 l0 = pmap_l0(pmap, sva);
2561 if (pmap_load(l0) == 0) {
2562 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2568 l1 = pmap_l0_to_l1(l0, sva);
2569 if (pmap_load(l1) == 0) {
2570 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2576 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2580 l2 = pmap_l1_to_l2(l1, sva);
2581 if (pmap_load(l2) == 0)
2584 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2585 l3p = pmap_demote_l2(pmap, l2, sva);
2589 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2590 ("pmap_protect: Invalid L2 entry after demotion"));
2596 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2598 l3 = pmap_load(l3p);
2599 if (!pmap_l3_valid(l3))
2603 if ((prot & VM_PROT_WRITE) == 0) {
2604 if ((l3 & ATTR_SW_MANAGED) &&
2605 pmap_page_dirty(l3)) {
2606 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2609 nbits |= ATTR_AP(ATTR_AP_RO);
2611 if ((prot & VM_PROT_EXECUTE) == 0)
2614 pmap_set(l3p, nbits);
2615 /* XXX: Use pmap_invalidate_range */
2616 pmap_invalidate_page(pmap, sva);
2623 * Inserts the specified page table page into the specified pmap's collection
2624 * of idle page table pages. Each of a pmap's page table pages is responsible
2625 * for mapping a distinct range of virtual addresses. The pmap's collection is
2626 * ordered by this virtual address range.
2629 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2632 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2633 return (vm_radix_insert(&pmap->pm_root, mpte));
2637 * Removes the page table page mapping the specified virtual address from the
2638 * specified pmap's collection of idle page table pages, and returns it.
2639 * Otherwise, returns NULL if there is no page table page corresponding to the
2640 * specified virtual address.
2642 static __inline vm_page_t
2643 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2646 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2647 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2651 * Performs a break-before-make update of a pmap entry. This is needed when
2652 * either promoting or demoting pages to ensure the TLB doesn't get into an
2653 * inconsistent state.
2656 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2657 vm_offset_t va, vm_size_t size)
2661 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2664 * Ensure we don't get switched out with the page table in an
2665 * inconsistent state. We also need to ensure no interrupts fire
2666 * as they may make use of an address we are about to invalidate.
2668 intr = intr_disable();
2671 /* Clear the old mapping */
2672 pmap_load_clear(pte);
2673 pmap_invalidate_range(pmap, va, va + size);
2675 /* Create the new mapping */
2676 pmap_load_store(pte, newpte);
2682 #if VM_NRESERVLEVEL > 0
2684 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2685 * replace the many pv entries for the 4KB page mappings by a single pv entry
2686 * for the 2MB page mapping.
2689 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2690 struct rwlock **lockp)
2692 struct md_page *pvh;
2694 vm_offset_t va_last;
2697 KASSERT((pa & L2_OFFSET) == 0,
2698 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2699 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2702 * Transfer the first page's pv entry for this mapping to the 2mpage's
2703 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2704 * a transfer avoids the possibility that get_pv_entry() calls
2705 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2706 * mappings that is being promoted.
2708 m = PHYS_TO_VM_PAGE(pa);
2709 va = va & ~L2_OFFSET;
2710 pv = pmap_pvh_remove(&m->md, pmap, va);
2711 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2712 pvh = pa_to_pvh(pa);
2713 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2715 /* Free the remaining NPTEPG - 1 pv entries. */
2716 va_last = va + L2_SIZE - PAGE_SIZE;
2720 pmap_pvh_free(&m->md, pmap, va);
2721 } while (va < va_last);
2725 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2726 * single level 2 table entry to a single 2MB page mapping. For promotion
2727 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2728 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2729 * identical characteristics.
2732 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2733 struct rwlock **lockp)
2735 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2739 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2741 sva = va & ~L2_OFFSET;
2742 firstl3 = pmap_l2_to_l3(l2, sva);
2743 newl2 = pmap_load(firstl3);
2745 /* Check the alingment is valid */
2746 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2747 atomic_add_long(&pmap_l2_p_failures, 1);
2748 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2749 " in pmap %p", va, pmap);
2753 pa = newl2 + L2_SIZE - PAGE_SIZE;
2754 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2755 oldl3 = pmap_load(l3);
2757 atomic_add_long(&pmap_l2_p_failures, 1);
2758 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2759 " in pmap %p", va, pmap);
2766 * Save the page table page in its current state until the L2
2767 * mapping the superpage is demoted by pmap_demote_l2() or
2768 * destroyed by pmap_remove_l3().
2770 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2771 KASSERT(mpte >= vm_page_array &&
2772 mpte < &vm_page_array[vm_page_array_size],
2773 ("pmap_promote_l2: page table page is out of range"));
2774 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2775 ("pmap_promote_l2: page table page's pindex is wrong"));
2776 if (pmap_insert_pt_page(pmap, mpte)) {
2777 atomic_add_long(&pmap_l2_p_failures, 1);
2779 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2784 if ((newl2 & ATTR_SW_MANAGED) != 0)
2785 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2787 newl2 &= ~ATTR_DESCR_MASK;
2790 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2792 atomic_add_long(&pmap_l2_promotions, 1);
2793 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2796 #endif /* VM_NRESERVLEVEL > 0 */
2799 * Insert the given physical page (p) at
2800 * the specified virtual address (v) in the
2801 * target physical map with the protection requested.
2803 * If specified, the page will be wired down, meaning
2804 * that the related pte can not be reclaimed.
2806 * NB: This is the only routine which MAY NOT lazy-evaluate
2807 * or lose information. That is, this routine must actually
2808 * insert this page into the given map NOW.
2811 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2812 u_int flags, int8_t psind __unused)
2814 struct rwlock *lock;
2816 pt_entry_t new_l3, orig_l3;
2817 pt_entry_t *l2, *l3;
2819 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2820 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2824 va = trunc_page(va);
2825 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2826 VM_OBJECT_ASSERT_LOCKED(m->object);
2827 pa = VM_PAGE_TO_PHYS(m);
2828 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2830 if ((prot & VM_PROT_WRITE) == 0)
2831 new_l3 |= ATTR_AP(ATTR_AP_RO);
2832 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2834 if ((flags & PMAP_ENTER_WIRED) != 0)
2835 new_l3 |= ATTR_SW_WIRED;
2836 if (va < VM_MAXUSER_ADDRESS)
2837 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2839 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2846 pde = pmap_pde(pmap, va, &lvl);
2847 if (pde != NULL && lvl == 1) {
2848 l2 = pmap_l1_to_l2(pde, va);
2849 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2850 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2852 l3 = &l3[pmap_l3_index(va)];
2853 if (va < VM_MAXUSER_ADDRESS) {
2854 mpte = PHYS_TO_VM_PAGE(
2855 pmap_load(l2) & ~ATTR_MASK);
2862 if (va < VM_MAXUSER_ADDRESS) {
2863 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2864 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2865 if (mpte == NULL && nosleep) {
2866 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2870 return (KERN_RESOURCE_SHORTAGE);
2872 pde = pmap_pde(pmap, va, &lvl);
2873 KASSERT(pde != NULL,
2874 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2876 ("pmap_enter: Invalid level %d", lvl));
2878 l3 = pmap_l2_to_l3(pde, va);
2881 * If we get a level 2 pde it must point to a level 3 entry
2882 * otherwise we will need to create the intermediate tables
2888 /* Get the l0 pde to update */
2889 pde = pmap_l0(pmap, va);
2890 KASSERT(pde != NULL, ("..."));
2892 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2893 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2896 panic("pmap_enter: l1 pte_m == NULL");
2897 if ((l1_m->flags & PG_ZERO) == 0)
2898 pmap_zero_page(l1_m);
2900 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2901 pmap_load_store(pde, l1_pa | L0_TABLE);
2904 /* Get the l1 pde to update */
2905 pde = pmap_l1_to_l2(pde, va);
2906 KASSERT(pde != NULL, ("..."));
2908 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2909 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2912 panic("pmap_enter: l2 pte_m == NULL");
2913 if ((l2_m->flags & PG_ZERO) == 0)
2914 pmap_zero_page(l2_m);
2916 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2917 pmap_load_store(pde, l2_pa | L1_TABLE);
2920 /* Get the l2 pde to update */
2921 pde = pmap_l1_to_l2(pde, va);
2923 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2924 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2927 panic("pmap_enter: l3 pte_m == NULL");
2928 if ((l3_m->flags & PG_ZERO) == 0)
2929 pmap_zero_page(l3_m);
2931 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2932 pmap_load_store(pde, l3_pa | L2_TABLE);
2936 l3 = pmap_l2_to_l3(pde, va);
2937 pmap_invalidate_page(pmap, va);
2942 orig_l3 = pmap_load(l3);
2943 opa = orig_l3 & ~ATTR_MASK;
2946 * Is the specified virtual address already mapped?
2948 if (pmap_l3_valid(orig_l3)) {
2950 * Wiring change, just update stats. We don't worry about
2951 * wiring PT pages as they remain resident as long as there
2952 * are valid mappings in them. Hence, if a user page is wired,
2953 * the PT page will be also.
2955 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2956 (orig_l3 & ATTR_SW_WIRED) == 0)
2957 pmap->pm_stats.wired_count++;
2958 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2959 (orig_l3 & ATTR_SW_WIRED) != 0)
2960 pmap->pm_stats.wired_count--;
2963 * Remove the extra PT page reference.
2967 KASSERT(mpte->wire_count > 0,
2968 ("pmap_enter: missing reference to page table page,"
2973 * Has the physical page changed?
2977 * No, might be a protection or wiring change.
2979 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2980 new_l3 |= ATTR_SW_MANAGED;
2981 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2982 ATTR_AP(ATTR_AP_RW)) {
2983 vm_page_aflag_set(m, PGA_WRITEABLE);
2990 * Increment the counters.
2992 if ((new_l3 & ATTR_SW_WIRED) != 0)
2993 pmap->pm_stats.wired_count++;
2994 pmap_resident_count_inc(pmap, 1);
2997 * Enter on the PV list if part of our managed memory.
2999 if ((m->oflags & VPO_UNMANAGED) == 0) {
3000 new_l3 |= ATTR_SW_MANAGED;
3001 pv = get_pv_entry(pmap, &lock);
3003 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
3004 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3006 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3007 vm_page_aflag_set(m, PGA_WRITEABLE);
3011 * Update the L3 entry.
3015 orig_l3 = pmap_load(l3);
3016 opa = orig_l3 & ~ATTR_MASK;
3019 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
3020 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3021 om = PHYS_TO_VM_PAGE(opa);
3022 if (pmap_page_dirty(orig_l3))
3024 if ((orig_l3 & ATTR_AF) != 0)
3025 vm_page_aflag_set(om, PGA_REFERENCED);
3026 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3027 pmap_pvh_free(&om->md, pmap, va);
3028 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3029 TAILQ_EMPTY(&om->md.pv_list) &&
3030 ((om->flags & PG_FICTITIOUS) != 0 ||
3031 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3032 vm_page_aflag_clear(om, PGA_WRITEABLE);
3035 pmap_load_store(l3, new_l3);
3036 pmap_invalidate_page(pmap, va);
3037 if (pmap_page_dirty(orig_l3) &&
3038 (orig_l3 & ATTR_SW_MANAGED) != 0)
3042 pmap_load_store(l3, new_l3);
3045 pmap_invalidate_page(pmap, va);
3047 if (pmap != pmap_kernel()) {
3048 if (pmap == &curproc->p_vmspace->vm_pmap &&
3049 (prot & VM_PROT_EXECUTE) != 0)
3050 cpu_icache_sync_range(va, PAGE_SIZE);
3052 #if VM_NRESERVLEVEL > 0
3053 if ((mpte == NULL || mpte->wire_count == NL3PG) &&
3054 pmap_superpages_enabled() &&
3055 (m->flags & PG_FICTITIOUS) == 0 &&
3056 vm_reserv_level_iffullpop(m) == 0) {
3057 pmap_promote_l2(pmap, pde, va, &lock);
3065 return (KERN_SUCCESS);
3069 * Maps a sequence of resident pages belonging to the same object.
3070 * The sequence begins with the given page m_start. This page is
3071 * mapped at the given virtual address start. Each subsequent page is
3072 * mapped at a virtual address that is offset from start by the same
3073 * amount as the page is offset from m_start within the object. The
3074 * last page in the sequence is the page with the largest offset from
3075 * m_start that can be mapped at a virtual address less than the given
3076 * virtual address end. Not every virtual page between start and end
3077 * is mapped; only those for which a resident page exists with the
3078 * corresponding offset from m_start are mapped.
3081 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3082 vm_page_t m_start, vm_prot_t prot)
3084 struct rwlock *lock;
3087 vm_pindex_t diff, psize;
3089 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3091 psize = atop(end - start);
3096 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3097 va = start + ptoa(diff);
3098 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
3099 m = TAILQ_NEXT(m, listq);
3107 * this code makes some *MAJOR* assumptions:
3108 * 1. Current pmap & pmap exists.
3111 * 4. No page table pages.
3112 * but is *MUCH* faster than pmap_enter...
3116 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3118 struct rwlock *lock;
3122 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3129 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3130 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3132 struct spglist free;
3134 pt_entry_t *l2, *l3;
3138 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3139 (m->oflags & VPO_UNMANAGED) != 0,
3140 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3141 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3143 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3145 * In the case that a page table page is not
3146 * resident, we are creating it here.
3148 if (va < VM_MAXUSER_ADDRESS) {
3149 vm_pindex_t l2pindex;
3152 * Calculate pagetable page index
3154 l2pindex = pmap_l2_pindex(va);
3155 if (mpte && (mpte->pindex == l2pindex)) {
3161 pde = pmap_pde(pmap, va, &lvl);
3164 * If the page table page is mapped, we just increment
3165 * the hold count, and activate it. Otherwise, we
3166 * attempt to allocate a page table page. If this
3167 * attempt fails, we don't retry. Instead, we give up.
3170 l2 = pmap_l1_to_l2(pde, va);
3171 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3175 if (lvl == 2 && pmap_load(pde) != 0) {
3177 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3181 * Pass NULL instead of the PV list lock
3182 * pointer, because we don't intend to sleep.
3184 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3189 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3190 l3 = &l3[pmap_l3_index(va)];
3193 pde = pmap_pde(kernel_pmap, va, &lvl);
3194 KASSERT(pde != NULL,
3195 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3198 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3199 l3 = pmap_l2_to_l3(pde, va);
3202 if (pmap_load(l3) != 0) {
3211 * Enter on the PV list if part of our managed memory.
3213 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3214 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3217 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3218 pmap_invalidate_page(pmap, va);
3219 pmap_free_zero_pages(&free);
3227 * Increment counters
3229 pmap_resident_count_inc(pmap, 1);
3231 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3232 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3233 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3235 else if (va < VM_MAXUSER_ADDRESS)
3239 * Now validate mapping with RO protection
3241 if ((m->oflags & VPO_UNMANAGED) == 0)
3242 pa |= ATTR_SW_MANAGED;
3243 pmap_load_store(l3, pa);
3244 pmap_invalidate_page(pmap, va);
3249 * This code maps large physical mmap regions into the
3250 * processor address space. Note that some shortcuts
3251 * are taken, but the code works.
3254 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3255 vm_pindex_t pindex, vm_size_t size)
3258 VM_OBJECT_ASSERT_WLOCKED(object);
3259 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3260 ("pmap_object_init_pt: non-device object"));
3264 * Clear the wired attribute from the mappings for the specified range of
3265 * addresses in the given pmap. Every valid mapping within that range
3266 * must have the wired attribute set. In contrast, invalid mappings
3267 * cannot have the wired attribute set, so they are ignored.
3269 * The wired attribute of the page table entry is not a hardware feature,
3270 * so there is no need to invalidate any TLB entries.
3273 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3275 vm_offset_t va_next;
3276 pd_entry_t *l0, *l1, *l2;
3280 for (; sva < eva; sva = va_next) {
3281 l0 = pmap_l0(pmap, sva);
3282 if (pmap_load(l0) == 0) {
3283 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3289 l1 = pmap_l0_to_l1(l0, sva);
3290 if (pmap_load(l1) == 0) {
3291 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3297 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3301 l2 = pmap_l1_to_l2(l1, sva);
3302 if (pmap_load(l2) == 0)
3305 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3306 l3 = pmap_demote_l2(pmap, l2, sva);
3310 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3311 ("pmap_unwire: Invalid l2 entry after demotion"));
3315 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3317 if (pmap_load(l3) == 0)
3319 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3320 panic("pmap_unwire: l3 %#jx is missing "
3321 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3324 * PG_W must be cleared atomically. Although the pmap
3325 * lock synchronizes access to PG_W, another processor
3326 * could be setting PG_M and/or PG_A concurrently.
3328 atomic_clear_long(l3, ATTR_SW_WIRED);
3329 pmap->pm_stats.wired_count--;
3336 * Copy the range specified by src_addr/len
3337 * from the source map to the range dst_addr/len
3338 * in the destination map.
3340 * This routine is only advisory and need not do anything.
3344 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3345 vm_offset_t src_addr)
3350 * pmap_zero_page zeros the specified hardware page by mapping
3351 * the page into KVM and using bzero to clear its contents.
3354 pmap_zero_page(vm_page_t m)
3356 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3358 pagezero((void *)va);
3362 * pmap_zero_page_area zeros the specified hardware page by mapping
3363 * the page into KVM and using bzero to clear its contents.
3365 * off and size may not cover an area beyond a single hardware page.
3368 pmap_zero_page_area(vm_page_t m, int off, int size)
3370 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3372 if (off == 0 && size == PAGE_SIZE)
3373 pagezero((void *)va);
3375 bzero((char *)va + off, size);
3379 * pmap_copy_page copies the specified (machine independent)
3380 * page by mapping the page into virtual memory and using
3381 * bcopy to copy the page, one machine dependent page at a
3385 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3387 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3388 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3390 pagecopy((void *)src, (void *)dst);
3393 int unmapped_buf_allowed = 1;
3396 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3397 vm_offset_t b_offset, int xfersize)
3401 vm_paddr_t p_a, p_b;
3402 vm_offset_t a_pg_offset, b_pg_offset;
3405 while (xfersize > 0) {
3406 a_pg_offset = a_offset & PAGE_MASK;
3407 m_a = ma[a_offset >> PAGE_SHIFT];
3408 p_a = m_a->phys_addr;
3409 b_pg_offset = b_offset & PAGE_MASK;
3410 m_b = mb[b_offset >> PAGE_SHIFT];
3411 p_b = m_b->phys_addr;
3412 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3413 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3414 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3415 panic("!DMAP a %lx", p_a);
3417 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3419 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3420 panic("!DMAP b %lx", p_b);
3422 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3424 bcopy(a_cp, b_cp, cnt);
3432 pmap_quick_enter_page(vm_page_t m)
3435 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3439 pmap_quick_remove_page(vm_offset_t addr)
3444 * Returns true if the pmap's pv is one of the first
3445 * 16 pvs linked to from this page. This count may
3446 * be changed upwards or downwards in the future; it
3447 * is only necessary that true be returned for a small
3448 * subset of pmaps for proper page aging.
3451 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3453 struct md_page *pvh;
3454 struct rwlock *lock;
3459 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3460 ("pmap_page_exists_quick: page %p is not managed", m));
3462 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3464 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3465 if (PV_PMAP(pv) == pmap) {
3473 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3474 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3475 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3476 if (PV_PMAP(pv) == pmap) {
3490 * pmap_page_wired_mappings:
3492 * Return the number of managed mappings to the given physical page
3496 pmap_page_wired_mappings(vm_page_t m)
3498 struct rwlock *lock;
3499 struct md_page *pvh;
3503 int count, lvl, md_gen, pvh_gen;
3505 if ((m->oflags & VPO_UNMANAGED) != 0)
3507 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3511 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3513 if (!PMAP_TRYLOCK(pmap)) {
3514 md_gen = m->md.pv_gen;
3518 if (md_gen != m->md.pv_gen) {
3523 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3524 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3528 if ((m->flags & PG_FICTITIOUS) == 0) {
3529 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3530 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3532 if (!PMAP_TRYLOCK(pmap)) {
3533 md_gen = m->md.pv_gen;
3534 pvh_gen = pvh->pv_gen;
3538 if (md_gen != m->md.pv_gen ||
3539 pvh_gen != pvh->pv_gen) {
3544 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3546 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3556 * Destroy all managed, non-wired mappings in the given user-space
3557 * pmap. This pmap cannot be active on any processor besides the
3560 * This function cannot be applied to the kernel pmap. Moreover, it
3561 * is not intended for general use. It is only to be used during
3562 * process termination. Consequently, it can be implemented in ways
3563 * that make it faster than pmap_remove(). First, it can more quickly
3564 * destroy mappings by iterating over the pmap's collection of PV
3565 * entries, rather than searching the page table. Second, it doesn't
3566 * have to test and clear the page table entries atomically, because
3567 * no processor is currently accessing the user address space. In
3568 * particular, a page table entry's dirty bit won't change state once
3569 * this function starts.
3572 pmap_remove_pages(pmap_t pmap)
3575 pt_entry_t *pte, tpte;
3576 struct spglist free;
3577 vm_page_t m, ml3, mt;
3579 struct md_page *pvh;
3580 struct pv_chunk *pc, *npc;
3581 struct rwlock *lock;
3583 uint64_t inuse, bitmask;
3584 int allfree, field, freed, idx, lvl;
3591 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3594 for (field = 0; field < _NPCM; field++) {
3595 inuse = ~pc->pc_map[field] & pc_freemask[field];
3596 while (inuse != 0) {
3597 bit = ffsl(inuse) - 1;
3598 bitmask = 1UL << bit;
3599 idx = field * 64 + bit;
3600 pv = &pc->pc_pventry[idx];
3603 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3604 KASSERT(pde != NULL,
3605 ("Attempting to remove an unmapped page"));
3609 pte = pmap_l1_to_l2(pde, pv->pv_va);
3610 tpte = pmap_load(pte);
3611 KASSERT((tpte & ATTR_DESCR_MASK) ==
3613 ("Attempting to remove an invalid "
3614 "block: %lx", tpte));
3615 tpte = pmap_load(pte);
3618 pte = pmap_l2_to_l3(pde, pv->pv_va);
3619 tpte = pmap_load(pte);
3620 KASSERT((tpte & ATTR_DESCR_MASK) ==
3622 ("Attempting to remove an invalid "
3623 "page: %lx", tpte));
3627 "Invalid page directory level: %d",
3632 * We cannot remove wired pages from a process' mapping at this time
3634 if (tpte & ATTR_SW_WIRED) {
3639 pa = tpte & ~ATTR_MASK;
3641 m = PHYS_TO_VM_PAGE(pa);
3642 KASSERT(m->phys_addr == pa,
3643 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3644 m, (uintmax_t)m->phys_addr,
3647 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3648 m < &vm_page_array[vm_page_array_size],
3649 ("pmap_remove_pages: bad pte %#jx",
3652 pmap_load_clear(pte);
3655 * Update the vm_page_t clean/reference bits.
3657 if ((tpte & ATTR_AP_RW_BIT) ==
3658 ATTR_AP(ATTR_AP_RW)) {
3661 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3670 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3673 pc->pc_map[field] |= bitmask;
3676 pmap_resident_count_dec(pmap,
3677 L2_SIZE / PAGE_SIZE);
3678 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3679 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3681 if (TAILQ_EMPTY(&pvh->pv_list)) {
3682 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3683 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3684 TAILQ_EMPTY(&mt->md.pv_list))
3685 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3687 ml3 = pmap_remove_pt_page(pmap,
3690 pmap_resident_count_dec(pmap,1);
3691 KASSERT(ml3->wire_count == NL3PG,
3692 ("pmap_remove_pages: l3 page wire count error"));
3693 ml3->wire_count = 0;
3694 pmap_add_delayed_free_list(ml3,
3696 atomic_subtract_int(
3697 &vm_cnt.v_wire_count, 1);
3701 pmap_resident_count_dec(pmap, 1);
3702 TAILQ_REMOVE(&m->md.pv_list, pv,
3705 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3706 TAILQ_EMPTY(&m->md.pv_list) &&
3707 (m->flags & PG_FICTITIOUS) == 0) {
3709 VM_PAGE_TO_PHYS(m));
3710 if (TAILQ_EMPTY(&pvh->pv_list))
3711 vm_page_aflag_clear(m,
3716 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
3721 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3722 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3723 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3725 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3729 pmap_invalidate_all(pmap);
3733 pmap_free_zero_pages(&free);
3737 * This is used to check if a page has been accessed or modified. As we
3738 * don't have a bit to see if it has been modified we have to assume it
3739 * has been if the page is read/write.
3742 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3744 struct rwlock *lock;
3746 struct md_page *pvh;
3747 pt_entry_t *pte, mask, value;
3749 int lvl, md_gen, pvh_gen;
3753 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3756 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3758 if (!PMAP_TRYLOCK(pmap)) {
3759 md_gen = m->md.pv_gen;
3763 if (md_gen != m->md.pv_gen) {
3768 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3770 ("pmap_page_test_mappings: Invalid level %d", lvl));
3774 mask |= ATTR_AP_RW_BIT;
3775 value |= ATTR_AP(ATTR_AP_RW);
3778 mask |= ATTR_AF | ATTR_DESCR_MASK;
3779 value |= ATTR_AF | L3_PAGE;
3781 rv = (pmap_load(pte) & mask) == value;
3786 if ((m->flags & PG_FICTITIOUS) == 0) {
3787 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3788 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3790 if (!PMAP_TRYLOCK(pmap)) {
3791 md_gen = m->md.pv_gen;
3792 pvh_gen = pvh->pv_gen;
3796 if (md_gen != m->md.pv_gen ||
3797 pvh_gen != pvh->pv_gen) {
3802 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3804 ("pmap_page_test_mappings: Invalid level %d", lvl));
3808 mask |= ATTR_AP_RW_BIT;
3809 value |= ATTR_AP(ATTR_AP_RW);
3812 mask |= ATTR_AF | ATTR_DESCR_MASK;
3813 value |= ATTR_AF | L2_BLOCK;
3815 rv = (pmap_load(pte) & mask) == value;
3829 * Return whether or not the specified physical page was modified
3830 * in any physical maps.
3833 pmap_is_modified(vm_page_t m)
3836 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3837 ("pmap_is_modified: page %p is not managed", m));
3840 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3841 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3842 * is clear, no PTEs can have PG_M set.
3844 VM_OBJECT_ASSERT_WLOCKED(m->object);
3845 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3847 return (pmap_page_test_mappings(m, FALSE, TRUE));
3851 * pmap_is_prefaultable:
3853 * Return whether or not the specified virtual address is eligible
3857 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3865 pte = pmap_pte(pmap, addr, &lvl);
3866 if (pte != NULL && pmap_load(pte) != 0) {
3874 * pmap_is_referenced:
3876 * Return whether or not the specified physical page was referenced
3877 * in any physical maps.
3880 pmap_is_referenced(vm_page_t m)
3883 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3884 ("pmap_is_referenced: page %p is not managed", m));
3885 return (pmap_page_test_mappings(m, TRUE, FALSE));
3889 * Clear the write and modified bits in each of the given page's mappings.
3892 pmap_remove_write(vm_page_t m)
3894 struct md_page *pvh;
3896 struct rwlock *lock;
3897 pv_entry_t next_pv, pv;
3898 pt_entry_t oldpte, *pte;
3900 int lvl, md_gen, pvh_gen;
3902 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3903 ("pmap_remove_write: page %p is not managed", m));
3906 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3907 * set by another thread while the object is locked. Thus,
3908 * if PGA_WRITEABLE is clear, no page table entries need updating.
3910 VM_OBJECT_ASSERT_WLOCKED(m->object);
3911 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3913 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3914 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3915 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3918 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3920 if (!PMAP_TRYLOCK(pmap)) {
3921 pvh_gen = pvh->pv_gen;
3925 if (pvh_gen != pvh->pv_gen) {
3932 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3933 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3934 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3936 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3937 ("inconsistent pv lock %p %p for page %p",
3938 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3941 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3943 if (!PMAP_TRYLOCK(pmap)) {
3944 pvh_gen = pvh->pv_gen;
3945 md_gen = m->md.pv_gen;
3949 if (pvh_gen != pvh->pv_gen ||
3950 md_gen != m->md.pv_gen) {
3956 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3958 oldpte = pmap_load(pte);
3959 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3960 if (!atomic_cmpset_long(pte, oldpte,
3961 oldpte | ATTR_AP(ATTR_AP_RO)))
3963 if ((oldpte & ATTR_AF) != 0)
3965 pmap_invalidate_page(pmap, pv->pv_va);
3970 vm_page_aflag_clear(m, PGA_WRITEABLE);
3973 static __inline boolean_t
3974 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3981 * pmap_ts_referenced:
3983 * Return a count of reference bits for a page, clearing those bits.
3984 * It is not necessary for every reference bit to be cleared, but it
3985 * is necessary that 0 only be returned when there are truly no
3986 * reference bits set.
3988 * As an optimization, update the page's dirty field if a modified bit is
3989 * found while counting reference bits. This opportunistic update can be
3990 * performed at low cost and can eliminate the need for some future calls
3991 * to pmap_is_modified(). However, since this function stops after
3992 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3993 * dirty pages. Those dirty pages will only be detected by a future call
3994 * to pmap_is_modified().
3997 pmap_ts_referenced(vm_page_t m)
3999 struct md_page *pvh;
4002 struct rwlock *lock;
4003 pd_entry_t *pde, tpde;
4004 pt_entry_t *pte, tpte;
4008 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4009 struct spglist free;
4012 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4013 ("pmap_ts_referenced: page %p is not managed", m));
4016 pa = VM_PAGE_TO_PHYS(m);
4017 lock = PHYS_TO_PV_LIST_LOCK(pa);
4018 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4022 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4023 goto small_mappings;
4029 if (!PMAP_TRYLOCK(pmap)) {
4030 pvh_gen = pvh->pv_gen;
4034 if (pvh_gen != pvh->pv_gen) {
4040 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4041 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4043 ("pmap_ts_referenced: invalid pde level %d", lvl));
4044 tpde = pmap_load(pde);
4045 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4046 ("pmap_ts_referenced: found an invalid l1 table"));
4047 pte = pmap_l1_to_l2(pde, pv->pv_va);
4048 tpte = pmap_load(pte);
4049 if (pmap_page_dirty(tpte)) {
4051 * Although "tpte" is mapping a 2MB page, because
4052 * this function is called at a 4KB page granularity,
4053 * we only update the 4KB page under test.
4057 if ((tpte & ATTR_AF) != 0) {
4059 * Since this reference bit is shared by 512 4KB
4060 * pages, it should not be cleared every time it is
4061 * tested. Apply a simple "hash" function on the
4062 * physical page number, the virtual superpage number,
4063 * and the pmap address to select one 4KB page out of
4064 * the 512 on which testing the reference bit will
4065 * result in clearing that reference bit. This
4066 * function is designed to avoid the selection of the
4067 * same 4KB page for every 2MB page mapping.
4069 * On demotion, a mapping that hasn't been referenced
4070 * is simply destroyed. To avoid the possibility of a
4071 * subsequent page fault on a demoted wired mapping,
4072 * always leave its reference bit set. Moreover,
4073 * since the superpage is wired, the current state of
4074 * its reference bit won't affect page replacement.
4076 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4077 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4078 (tpte & ATTR_SW_WIRED) == 0) {
4079 if (safe_to_clear_referenced(pmap, tpte)) {
4081 * TODO: We don't handle the access
4082 * flag at all. We need to be able
4083 * to set it in the exception handler.
4086 "safe_to_clear_referenced\n");
4087 } else if (pmap_demote_l2_locked(pmap, pte,
4088 pv->pv_va, &lock) != NULL) {
4090 va += VM_PAGE_TO_PHYS(m) -
4091 (tpte & ~ATTR_MASK);
4092 l3 = pmap_l2_to_l3(pte, va);
4093 pmap_remove_l3(pmap, l3, va,
4094 pmap_load(pte), NULL, &lock);
4100 * The superpage mapping was removed
4101 * entirely and therefore 'pv' is no
4109 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4110 ("inconsistent pv lock %p %p for page %p",
4111 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4116 /* Rotate the PV list if it has more than one entry. */
4117 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4118 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4119 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4122 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4124 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4126 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4133 if (!PMAP_TRYLOCK(pmap)) {
4134 pvh_gen = pvh->pv_gen;
4135 md_gen = m->md.pv_gen;
4139 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4144 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4145 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4147 ("pmap_ts_referenced: invalid pde level %d", lvl));
4148 tpde = pmap_load(pde);
4149 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4150 ("pmap_ts_referenced: found an invalid l2 table"));
4151 pte = pmap_l2_to_l3(pde, pv->pv_va);
4152 tpte = pmap_load(pte);
4153 if (pmap_page_dirty(tpte))
4155 if ((tpte & ATTR_AF) != 0) {
4156 if (safe_to_clear_referenced(pmap, tpte)) {
4158 * TODO: We don't handle the access flag
4159 * at all. We need to be able to set it in
4160 * the exception handler.
4162 panic("ARM64TODO: safe_to_clear_referenced\n");
4163 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4165 * Wired pages cannot be paged out so
4166 * doing accessed bit emulation for
4167 * them is wasted effort. We do the
4168 * hard work for unwired pages only.
4170 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4172 pmap_invalidate_page(pmap, pv->pv_va);
4177 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4178 ("inconsistent pv lock %p %p for page %p",
4179 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4184 /* Rotate the PV list if it has more than one entry. */
4185 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4186 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4187 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4190 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4191 not_cleared < PMAP_TS_REFERENCED_MAX);
4194 pmap_free_zero_pages(&free);
4195 return (cleared + not_cleared);
4199 * Apply the given advice to the specified range of addresses within the
4200 * given pmap. Depending on the advice, clear the referenced and/or
4201 * modified flags in each mapping and set the mapped page's dirty field.
4204 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4209 * Clear the modify bits on the specified physical page.
4212 pmap_clear_modify(vm_page_t m)
4215 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4216 ("pmap_clear_modify: page %p is not managed", m));
4217 VM_OBJECT_ASSERT_WLOCKED(m->object);
4218 KASSERT(!vm_page_xbusied(m),
4219 ("pmap_clear_modify: page %p is exclusive busied", m));
4222 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4223 * If the object containing the page is locked and the page is not
4224 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4226 if ((m->aflags & PGA_WRITEABLE) == 0)
4229 /* ARM64TODO: We lack support for tracking if a page is modified */
4233 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4236 return ((void *)PHYS_TO_DMAP(pa));
4240 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
4245 * Sets the memory attribute for the specified page.
4248 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4251 m->md.pv_memattr = ma;
4254 * If "m" is a normal page, update its direct mapping. This update
4255 * can be relied upon to perform any cache operations that are
4256 * required for data coherence.
4258 if ((m->flags & PG_FICTITIOUS) == 0 &&
4259 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4260 m->md.pv_memattr) != 0)
4261 panic("memory attribute change on the direct map failed");
4265 * Changes the specified virtual address range's memory type to that given by
4266 * the parameter "mode". The specified virtual address range must be
4267 * completely contained within either the direct map or the kernel map. If
4268 * the virtual address range is contained within the kernel map, then the
4269 * memory type for each of the corresponding ranges of the direct map is also
4270 * changed. (The corresponding ranges of the direct map are those ranges that
4271 * map the same physical pages as the specified virtual address range.) These
4272 * changes to the direct map are necessary because Intel describes the
4273 * behavior of their processors as "undefined" if two or more mappings to the
4274 * same physical page have different memory types.
4276 * Returns zero if the change completed successfully, and either EINVAL or
4277 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4278 * of the virtual address range was not mapped, and ENOMEM is returned if
4279 * there was insufficient memory available to complete the change. In the
4280 * latter case, the memory type may have been changed on some part of the
4281 * virtual address range or the direct map.
4284 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4288 PMAP_LOCK(kernel_pmap);
4289 error = pmap_change_attr_locked(va, size, mode);
4290 PMAP_UNLOCK(kernel_pmap);
4295 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4297 vm_offset_t base, offset, tmpva;
4298 pt_entry_t l3, *pte, *newpte;
4301 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4302 base = trunc_page(va);
4303 offset = va & PAGE_MASK;
4304 size = round_page(offset + size);
4306 if (!VIRT_IN_DMAP(base))
4309 for (tmpva = base; tmpva < base + size; ) {
4310 pte = pmap_pte(kernel_pmap, va, &lvl);
4314 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4316 * We already have the correct attribute,
4317 * ignore this entry.
4321 panic("Invalid DMAP table level: %d\n", lvl);
4323 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4326 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4334 * Split the entry to an level 3 table, then
4335 * set the new attribute.
4339 panic("Invalid DMAP table level: %d\n", lvl);
4341 newpte = pmap_demote_l1(kernel_pmap, pte,
4342 tmpva & ~L1_OFFSET);
4345 pte = pmap_l1_to_l2(pte, tmpva);
4347 newpte = pmap_demote_l2(kernel_pmap, pte,
4348 tmpva & ~L2_OFFSET);
4351 pte = pmap_l2_to_l3(pte, tmpva);
4353 /* Update the entry */
4354 l3 = pmap_load(pte);
4355 l3 &= ~ATTR_IDX_MASK;
4356 l3 |= ATTR_IDX(mode);
4357 if (mode == DEVICE_MEMORY)
4360 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4364 * If moving to a non-cacheable entry flush
4367 if (mode == VM_MEMATTR_UNCACHEABLE)
4368 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4380 * Create an L2 table to map all addresses within an L1 mapping.
4383 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4385 pt_entry_t *l2, newl2, oldl1;
4387 vm_paddr_t l2phys, phys;
4391 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4392 oldl1 = pmap_load(l1);
4393 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4394 ("pmap_demote_l1: Demoting a non-block entry"));
4395 KASSERT((va & L1_OFFSET) == 0,
4396 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4397 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4398 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4401 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4402 tmpl1 = kva_alloc(PAGE_SIZE);
4407 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4408 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4409 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4410 " in pmap %p", va, pmap);
4414 l2phys = VM_PAGE_TO_PHYS(ml2);
4415 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4417 /* Address the range points at */
4418 phys = oldl1 & ~ATTR_MASK;
4419 /* The attributed from the old l1 table to be copied */
4420 newl2 = oldl1 & ATTR_MASK;
4422 /* Create the new entries */
4423 for (i = 0; i < Ln_ENTRIES; i++) {
4424 l2[i] = newl2 | phys;
4427 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4428 ("Invalid l2 page (%lx != %lx)", l2[0],
4429 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4432 pmap_kenter(tmpl1, PAGE_SIZE,
4433 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4434 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4437 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4440 pmap_kremove(tmpl1);
4441 kva_free(tmpl1, PAGE_SIZE);
4448 * Create an L3 table to map all addresses within an L2 mapping.
4451 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4452 struct rwlock **lockp)
4454 pt_entry_t *l3, newl3, oldl2;
4456 vm_paddr_t l3phys, phys;
4460 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4462 oldl2 = pmap_load(l2);
4463 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4464 ("pmap_demote_l2: Demoting a non-block entry"));
4465 KASSERT((va & L2_OFFSET) == 0,
4466 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4469 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4470 tmpl2 = kva_alloc(PAGE_SIZE);
4475 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4476 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4477 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4478 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4480 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4481 " in pmap %p", va, pmap);
4484 if (va < VM_MAXUSER_ADDRESS)
4485 pmap_resident_count_inc(pmap, 1);
4488 l3phys = VM_PAGE_TO_PHYS(ml3);
4489 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4491 /* Address the range points at */
4492 phys = oldl2 & ~ATTR_MASK;
4493 /* The attributed from the old l2 table to be copied */
4494 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4497 * If the page table page is new, initialize it.
4499 if (ml3->wire_count == 1) {
4500 for (i = 0; i < Ln_ENTRIES; i++) {
4501 l3[i] = newl3 | phys;
4505 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4506 ("Invalid l3 page (%lx != %lx)", l3[0],
4507 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4510 * Map the temporary page so we don't lose access to the l2 table.
4513 pmap_kenter(tmpl2, PAGE_SIZE,
4514 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4515 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4519 * The spare PV entries must be reserved prior to demoting the
4520 * mapping, that is, prior to changing the PDE. Otherwise, the state
4521 * of the L2 and the PV lists will be inconsistent, which can result
4522 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4523 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4524 * PV entry for the 2MB page mapping that is being demoted.
4526 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4527 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4529 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4532 * Demote the PV entry.
4534 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4535 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4537 atomic_add_long(&pmap_l2_demotions, 1);
4538 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4539 " in pmap %p %lx", va, pmap, l3[0]);
4543 pmap_kremove(tmpl2);
4544 kva_free(tmpl2, PAGE_SIZE);
4552 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4554 struct rwlock *lock;
4558 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4565 * perform the pmap work for mincore
4568 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4570 pd_entry_t *l1p, l1;
4571 pd_entry_t *l2p, l2;
4572 pt_entry_t *l3p, l3;
4583 l1p = pmap_l1(pmap, addr);
4584 if (l1p == NULL) /* No l1 */
4587 l1 = pmap_load(l1p);
4588 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4591 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4592 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4593 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4594 val = MINCORE_SUPER | MINCORE_INCORE;
4595 if (pmap_page_dirty(l1))
4596 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4597 if ((l1 & ATTR_AF) == ATTR_AF)
4598 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4602 l2p = pmap_l1_to_l2(l1p, addr);
4603 if (l2p == NULL) /* No l2 */
4606 l2 = pmap_load(l2p);
4607 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4610 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4611 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4612 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4613 val = MINCORE_SUPER | MINCORE_INCORE;
4614 if (pmap_page_dirty(l2))
4615 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4616 if ((l2 & ATTR_AF) == ATTR_AF)
4617 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4621 l3p = pmap_l2_to_l3(l2p, addr);
4622 if (l3p == NULL) /* No l3 */
4625 l3 = pmap_load(l2p);
4626 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4629 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4630 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4631 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4632 val = MINCORE_INCORE;
4633 if (pmap_page_dirty(l3))
4634 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4635 if ((l3 & ATTR_AF) == ATTR_AF)
4636 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4640 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4641 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4642 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4643 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4646 PA_UNLOCK_COND(*locked_pa);
4653 pmap_activate(struct thread *td)
4658 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4659 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
4660 __asm __volatile("msr ttbr0_el1, %0" : :
4661 "r"(td->td_proc->p_md.md_l0addr));
4662 pmap_invalidate_all(pmap);
4667 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4670 if (va >= VM_MIN_KERNEL_ADDRESS) {
4671 cpu_icache_sync_range(va, sz);
4676 /* Find the length of data in this page to flush */
4677 offset = va & PAGE_MASK;
4678 len = imin(PAGE_SIZE - offset, sz);
4681 /* Extract the physical address & find it in the DMAP */
4682 pa = pmap_extract(pmap, va);
4684 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4686 /* Move to the next page */
4689 /* Set the length for the next iteration */
4690 len = imin(PAGE_SIZE, sz);
4696 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4702 switch (ESR_ELx_EXCEPTION(esr)) {
4703 case EXCP_DATA_ABORT_L:
4704 case EXCP_DATA_ABORT:
4707 return (KERN_FAILURE);
4712 switch (esr & ISS_DATA_DFSC_MASK) {
4713 case ISS_DATA_DFSC_TF_L0:
4714 case ISS_DATA_DFSC_TF_L1:
4715 case ISS_DATA_DFSC_TF_L2:
4716 case ISS_DATA_DFSC_TF_L3:
4717 /* Ask the MMU to check the address */
4718 if (pmap == kernel_pmap)
4719 par = arm64_address_translate_s1e1r(far);
4721 par = arm64_address_translate_s1e0r(far);
4724 * If the translation was successful the address was invalid
4725 * due to a break-before-make sequence. We can unlock and
4726 * return success to the trap handler.
4728 if (PAR_SUCCESS(par)) {
4730 return (KERN_SUCCESS);
4739 return (KERN_FAILURE);
4743 * Increase the starting virtual address of the given mapping if a
4744 * different alignment might result in more superpage mappings.
4747 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4748 vm_offset_t *addr, vm_size_t size)
4750 vm_offset_t superpage_offset;
4754 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4755 offset += ptoa(object->pg_color);
4756 superpage_offset = offset & L2_OFFSET;
4757 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4758 (*addr & L2_OFFSET) == superpage_offset)
4760 if ((*addr & L2_OFFSET) < superpage_offset)
4761 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4763 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4767 * Get the kernel virtual address of a set of physical pages. If there are
4768 * physical addresses not covered by the DMAP perform a transient mapping
4769 * that will be removed when calling pmap_unmap_io_transient.
4771 * \param page The pages the caller wishes to obtain the virtual
4772 * address on the kernel memory map.
4773 * \param vaddr On return contains the kernel virtual memory address
4774 * of the pages passed in the page parameter.
4775 * \param count Number of pages passed in.
4776 * \param can_fault TRUE if the thread using the mapped pages can take
4777 * page faults, FALSE otherwise.
4779 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4780 * finished or FALSE otherwise.
4784 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4785 boolean_t can_fault)
4788 boolean_t needs_mapping;
4792 * Allocate any KVA space that we need, this is done in a separate
4793 * loop to prevent calling vmem_alloc while pinned.
4795 needs_mapping = FALSE;
4796 for (i = 0; i < count; i++) {
4797 paddr = VM_PAGE_TO_PHYS(page[i]);
4798 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4799 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4800 M_BESTFIT | M_WAITOK, &vaddr[i]);
4801 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4802 needs_mapping = TRUE;
4804 vaddr[i] = PHYS_TO_DMAP(paddr);
4808 /* Exit early if everything is covered by the DMAP */
4814 for (i = 0; i < count; i++) {
4815 paddr = VM_PAGE_TO_PHYS(page[i]);
4816 if (!PHYS_IN_DMAP(paddr)) {
4818 "pmap_map_io_transient: TODO: Map out of DMAP data");
4822 return (needs_mapping);
4826 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4827 boolean_t can_fault)
4834 for (i = 0; i < count; i++) {
4835 paddr = VM_PAGE_TO_PHYS(page[i]);
4836 if (!PHYS_IN_DMAP(paddr)) {
4837 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");