1 //===--- Targets.cpp - Implement target feature support -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements construction of a TargetInfo object from a
13 //===----------------------------------------------------------------------===//
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "clang/Basic/Version.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetParser.h"
35 using namespace clang;
37 //===----------------------------------------------------------------------===//
38 // Common code shared among targets.
39 //===----------------------------------------------------------------------===//
41 /// DefineStd - Define a macro name and standard variants. For example if
42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
45 const LangOptions &Opts) {
46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
49 // in the user's namespace.
51 Builder.defineMacro(MacroName);
54 Builder.defineMacro("__" + MacroName);
57 Builder.defineMacro("__" + MacroName + "__");
60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
62 Builder.defineMacro("__" + CPUName);
63 Builder.defineMacro("__" + CPUName + "__");
65 Builder.defineMacro("__tune_" + CPUName + "__");
68 //===----------------------------------------------------------------------===//
69 // Defines specific to certain operating systems.
70 //===----------------------------------------------------------------------===//
73 template<typename TgtInfo>
74 class OSTargetInfo : public TgtInfo {
76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
77 MacroBuilder &Builder) const=0;
79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
80 void getTargetDefines(const LangOptions &Opts,
81 MacroBuilder &Builder) const override {
82 TgtInfo::getTargetDefines(Opts, Builder);
83 getOSDefines(Opts, TgtInfo::getTriple(), Builder);
89 template <typename Target>
90 class CloudABITargetInfo : public OSTargetInfo<Target> {
92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
93 MacroBuilder &Builder) const override {
94 Builder.defineMacro("__CloudABI__");
95 Builder.defineMacro("__ELF__");
97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
98 Builder.defineMacro("__STDC_ISO_10646__", "201206L");
99 Builder.defineMacro("__STDC_UTF_16__");
100 Builder.defineMacro("__STDC_UTF_32__");
104 CloudABITargetInfo(const llvm::Triple &Triple)
105 : OSTargetInfo<Target>(Triple) {
106 this->UserLabelPrefix = "";
110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
111 const llvm::Triple &Triple,
112 StringRef &PlatformName,
113 VersionTuple &PlatformMinVersion) {
114 Builder.defineMacro("__APPLE_CC__", "6000");
115 Builder.defineMacro("__APPLE__");
116 Builder.defineMacro("OBJC_NEW_PROPERTIES");
117 // AddressSanitizer doesn't play well with source fortification, which is on
118 // by default on Darwin.
119 if (Opts.Sanitize.has(SanitizerKind::Address))
120 Builder.defineMacro("_FORTIFY_SOURCE", "0");
122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
124 // __weak is always defined, for use in blocks and with objc pointers.
125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
126 Builder.defineMacro("__strong", "");
127 Builder.defineMacro("__unsafe_unretained", "");
131 Builder.defineMacro("__STATIC__");
133 Builder.defineMacro("__DYNAMIC__");
135 if (Opts.POSIXThreads)
136 Builder.defineMacro("_REENTRANT");
138 // Get the platform type and version number from the triple.
139 unsigned Maj, Min, Rev;
140 if (Triple.isMacOSX()) {
141 Triple.getMacOSXVersion(Maj, Min, Rev);
142 PlatformName = "macosx";
144 Triple.getOSVersion(Maj, Min, Rev);
145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
148 // If -target arch-pc-win32-macho option specified, we're
149 // generating code for Win32 ABI. No need to emit
150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
151 if (PlatformName == "win32") {
152 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
156 // Set the appropriate OS version define.
157 if (Triple.isiOS()) {
158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
161 Str[1] = '0' + (Min / 10);
162 Str[2] = '0' + (Min % 10);
163 Str[3] = '0' + (Rev / 10);
164 Str[4] = '0' + (Rev % 10);
167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
172 } else if (Triple.isWatchOS()) {
173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
176 Str[1] = '0' + (Min / 10);
177 Str[2] = '0' + (Min % 10);
178 Str[3] = '0' + (Rev / 10);
179 Str[4] = '0' + (Rev % 10);
181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
182 } else if (Triple.isMacOSX()) {
183 // Note that the Driver allows versions which aren't representable in the
184 // define (because we only get a single digit for the minor and micro
185 // revision numbers). So, we limit them to the maximum representable
187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
189 if (Maj < 10 || (Maj == 10 && Min < 10)) {
190 Str[0] = '0' + (Maj / 10);
191 Str[1] = '0' + (Maj % 10);
192 Str[2] = '0' + std::min(Min, 9U);
193 Str[3] = '0' + std::min(Rev, 9U);
196 // Handle versions > 10.9.
197 Str[0] = '0' + (Maj / 10);
198 Str[1] = '0' + (Maj % 10);
199 Str[2] = '0' + (Min / 10);
200 Str[3] = '0' + (Min % 10);
201 Str[4] = '0' + (Rev / 10);
202 Str[5] = '0' + (Rev % 10);
205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
208 // Tell users about the kernel if there is one.
209 if (Triple.isOSDarwin())
210 Builder.defineMacro("__MACH__");
212 PlatformMinVersion = VersionTuple(Maj, Min, Rev);
215 template<typename Target>
216 class DarwinTargetInfo : public OSTargetInfo<Target> {
218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
219 MacroBuilder &Builder) const override {
220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
221 this->PlatformMinVersion);
225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
226 // By default, no TLS, and we whitelist permitted architecture/OS
228 this->TLSSupported = false;
230 if (Triple.isMacOSX())
231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7);
232 else if (Triple.isiOS()) {
233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards.
234 if (Triple.getArch() == llvm::Triple::x86_64 ||
235 Triple.getArch() == llvm::Triple::aarch64)
236 this->TLSSupported = !Triple.isOSVersionLT(8);
237 else if (Triple.getArch() == llvm::Triple::x86 ||
238 Triple.getArch() == llvm::Triple::arm ||
239 Triple.getArch() == llvm::Triple::thumb)
240 this->TLSSupported = !Triple.isOSVersionLT(9);
241 } else if (Triple.isWatchOS())
242 this->TLSSupported = !Triple.isOSVersionLT(2);
244 this->MCountName = "\01mcount";
247 std::string isValidSectionSpecifier(StringRef SR) const override {
248 // Let MCSectionMachO validate this.
249 StringRef Segment, Section;
250 unsigned TAA, StubSize;
252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
253 TAA, HasTAA, StubSize);
256 const char *getStaticInitSectionSpecifier() const override {
257 // FIXME: We should return 0 when building kexts.
258 return "__TEXT,__StaticInit,regular,pure_instructions";
261 /// Darwin does not support protected visibility. Darwin's "default"
262 /// is very similar to ELF's "protected"; Darwin requires a "weak"
263 /// attribute on declarations that can be dynamically replaced.
264 bool hasProtectedVisibility() const override {
270 // DragonFlyBSD Target
271 template<typename Target>
272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
275 MacroBuilder &Builder) const override {
276 // DragonFly defines; list based off of gcc output
277 Builder.defineMacro("__DragonFly__");
278 Builder.defineMacro("__DragonFly_cc_version", "100001");
279 Builder.defineMacro("__ELF__");
280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
281 Builder.defineMacro("__tune_i386__");
282 DefineStd(Builder, "unix", Opts);
285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
286 : OSTargetInfo<Target>(Triple) {
287 this->UserLabelPrefix = "";
289 switch (Triple.getArch()) {
291 case llvm::Triple::x86:
292 case llvm::Triple::x86_64:
293 this->MCountName = ".mcount";
299 #ifndef FREEBSD_CC_VERSION
300 #define FREEBSD_CC_VERSION 0U
304 template<typename Target>
305 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
307 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
308 MacroBuilder &Builder) const override {
309 // FreeBSD defines; list based off of gcc output
311 unsigned Release = Triple.getOSMajorVersion();
314 unsigned CCVersion = FREEBSD_CC_VERSION;
316 CCVersion = Release * 100000U + 1U;
318 Builder.defineMacro("__FreeBSD__", Twine(Release));
319 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion));
320 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
321 DefineStd(Builder, "unix", Opts);
322 Builder.defineMacro("__ELF__");
324 // On FreeBSD, wchar_t contains the number of the code point as
325 // used by the character set of the locale. These character sets are
326 // not necessarily a superset of ASCII.
328 // FIXME: This is wrong; the macro refers to the numerical values
329 // of wchar_t *literals*, which are not locale-dependent. However,
330 // FreeBSD systems apparently depend on us getting this wrong, and
331 // setting this to 1 is conforming even if all the basic source
332 // character literals have the same encoding as char and wchar_t.
333 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
336 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
337 this->UserLabelPrefix = "";
339 switch (Triple.getArch()) {
341 case llvm::Triple::x86:
342 case llvm::Triple::x86_64:
343 this->MCountName = ".mcount";
345 case llvm::Triple::mips:
346 case llvm::Triple::mipsel:
347 case llvm::Triple::ppc:
348 case llvm::Triple::ppc64:
349 case llvm::Triple::ppc64le:
350 this->MCountName = "_mcount";
352 case llvm::Triple::arm:
353 this->MCountName = "__mcount";
359 // GNU/kFreeBSD Target
360 template<typename Target>
361 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
364 MacroBuilder &Builder) const override {
365 // GNU/kFreeBSD defines; list based off of gcc output
367 DefineStd(Builder, "unix", Opts);
368 Builder.defineMacro("__FreeBSD_kernel__");
369 Builder.defineMacro("__GLIBC__");
370 Builder.defineMacro("__ELF__");
371 if (Opts.POSIXThreads)
372 Builder.defineMacro("_REENTRANT");
374 Builder.defineMacro("_GNU_SOURCE");
377 KFreeBSDTargetInfo(const llvm::Triple &Triple)
378 : OSTargetInfo<Target>(Triple) {
379 this->UserLabelPrefix = "";
384 template<typename Target>
385 class MinixTargetInfo : public OSTargetInfo<Target> {
387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388 MacroBuilder &Builder) const override {
391 Builder.defineMacro("__minix", "3");
392 Builder.defineMacro("_EM_WSIZE", "4");
393 Builder.defineMacro("_EM_PSIZE", "4");
394 Builder.defineMacro("_EM_SSIZE", "2");
395 Builder.defineMacro("_EM_LSIZE", "4");
396 Builder.defineMacro("_EM_FSIZE", "4");
397 Builder.defineMacro("_EM_DSIZE", "8");
398 Builder.defineMacro("__ELF__");
399 DefineStd(Builder, "unix", Opts);
402 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403 this->UserLabelPrefix = "";
408 template<typename Target>
409 class LinuxTargetInfo : public OSTargetInfo<Target> {
411 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
412 MacroBuilder &Builder) const override {
413 // Linux defines; list based off of gcc output
414 DefineStd(Builder, "unix", Opts);
415 DefineStd(Builder, "linux", Opts);
416 Builder.defineMacro("__gnu_linux__");
417 Builder.defineMacro("__ELF__");
418 if (Triple.isAndroid()) {
419 Builder.defineMacro("__ANDROID__", "1");
420 unsigned Maj, Min, Rev;
421 Triple.getEnvironmentVersion(Maj, Min, Rev);
422 this->PlatformName = "android";
423 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
425 if (Opts.POSIXThreads)
426 Builder.defineMacro("_REENTRANT");
428 Builder.defineMacro("_GNU_SOURCE");
431 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
432 this->UserLabelPrefix = "";
433 this->WIntType = TargetInfo::UnsignedInt;
435 switch (Triple.getArch()) {
438 case llvm::Triple::ppc:
439 case llvm::Triple::ppc64:
440 case llvm::Triple::ppc64le:
441 this->MCountName = "_mcount";
446 const char *getStaticInitSectionSpecifier() const override {
447 return ".text.startup";
452 template<typename Target>
453 class NetBSDTargetInfo : public OSTargetInfo<Target> {
455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
456 MacroBuilder &Builder) const override {
457 // NetBSD defines; list based off of gcc output
458 Builder.defineMacro("__NetBSD__");
459 Builder.defineMacro("__unix__");
460 Builder.defineMacro("__ELF__");
461 if (Opts.POSIXThreads)
462 Builder.defineMacro("_POSIX_THREADS");
464 switch (Triple.getArch()) {
467 case llvm::Triple::arm:
468 case llvm::Triple::armeb:
469 case llvm::Triple::thumb:
470 case llvm::Triple::thumbeb:
471 Builder.defineMacro("__ARM_DWARF_EH__");
476 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
477 this->UserLabelPrefix = "";
478 this->MCountName = "_mcount";
483 template<typename Target>
484 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
486 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
487 MacroBuilder &Builder) const override {
488 // OpenBSD defines; list based off of gcc output
490 Builder.defineMacro("__OpenBSD__");
491 DefineStd(Builder, "unix", Opts);
492 Builder.defineMacro("__ELF__");
493 if (Opts.POSIXThreads)
494 Builder.defineMacro("_REENTRANT");
497 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
498 this->UserLabelPrefix = "";
499 this->TLSSupported = false;
501 switch (Triple.getArch()) {
503 case llvm::Triple::x86:
504 case llvm::Triple::x86_64:
505 case llvm::Triple::arm:
506 case llvm::Triple::sparc:
507 this->MCountName = "__mcount";
509 case llvm::Triple::mips64:
510 case llvm::Triple::mips64el:
511 case llvm::Triple::ppc:
512 case llvm::Triple::sparcv9:
513 this->MCountName = "_mcount";
520 template<typename Target>
521 class BitrigTargetInfo : public OSTargetInfo<Target> {
523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
524 MacroBuilder &Builder) const override {
525 // Bitrig defines; list based off of gcc output
527 Builder.defineMacro("__Bitrig__");
528 DefineStd(Builder, "unix", Opts);
529 Builder.defineMacro("__ELF__");
530 if (Opts.POSIXThreads)
531 Builder.defineMacro("_REENTRANT");
533 switch (Triple.getArch()) {
536 case llvm::Triple::arm:
537 case llvm::Triple::armeb:
538 case llvm::Triple::thumb:
539 case llvm::Triple::thumbeb:
540 Builder.defineMacro("__ARM_DWARF_EH__");
545 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
546 this->UserLabelPrefix = "";
547 this->MCountName = "__mcount";
552 template<typename Target>
553 class PSPTargetInfo : public OSTargetInfo<Target> {
555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
556 MacroBuilder &Builder) const override {
557 // PSP defines; list based on the output of the pspdev gcc toolchain.
558 Builder.defineMacro("PSP");
559 Builder.defineMacro("_PSP");
560 Builder.defineMacro("__psp__");
561 Builder.defineMacro("__ELF__");
564 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
565 this->UserLabelPrefix = "";
570 template<typename Target>
571 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
573 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
574 MacroBuilder &Builder) const override {
576 Builder.defineMacro("__PPC__");
577 Builder.defineMacro("__PPU__");
578 Builder.defineMacro("__CELLOS_LV2__");
579 Builder.defineMacro("__ELF__");
580 Builder.defineMacro("__LP32__");
581 Builder.defineMacro("_ARCH_PPC64");
582 Builder.defineMacro("__powerpc64__");
585 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
586 this->UserLabelPrefix = "";
587 this->LongWidth = this->LongAlign = 32;
588 this->PointerWidth = this->PointerAlign = 32;
589 this->IntMaxType = TargetInfo::SignedLongLong;
590 this->Int64Type = TargetInfo::SignedLongLong;
591 this->SizeType = TargetInfo::UnsignedInt;
592 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64";
596 template <typename Target>
597 class PS4OSTargetInfo : public OSTargetInfo<Target> {
599 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
600 MacroBuilder &Builder) const override {
601 Builder.defineMacro("__FreeBSD__", "9");
602 Builder.defineMacro("__FreeBSD_cc_version", "900001");
603 Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
604 DefineStd(Builder, "unix", Opts);
605 Builder.defineMacro("__ELF__");
606 Builder.defineMacro("__PS4__");
609 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
610 this->WCharType = this->UnsignedShort;
612 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
613 this->MaxTLSAlign = 256;
614 this->UserLabelPrefix = "";
616 switch (Triple.getArch()) {
618 case llvm::Triple::x86_64:
619 this->MCountName = ".mcount";
626 template<typename Target>
627 class SolarisTargetInfo : public OSTargetInfo<Target> {
629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
630 MacroBuilder &Builder) const override {
631 DefineStd(Builder, "sun", Opts);
632 DefineStd(Builder, "unix", Opts);
633 Builder.defineMacro("__ELF__");
634 Builder.defineMacro("__svr4__");
635 Builder.defineMacro("__SVR4");
636 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
637 // newer, but to 500 for everything else. feature_test.h has a check to
638 // ensure that you are not using C99 with an old version of X/Open or C89
639 // with a new version.
641 Builder.defineMacro("_XOPEN_SOURCE", "600");
643 Builder.defineMacro("_XOPEN_SOURCE", "500");
645 Builder.defineMacro("__C99FEATURES__");
646 Builder.defineMacro("_LARGEFILE_SOURCE");
647 Builder.defineMacro("_LARGEFILE64_SOURCE");
648 Builder.defineMacro("__EXTENSIONS__");
649 Builder.defineMacro("_REENTRANT");
652 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
653 this->UserLabelPrefix = "";
654 this->WCharType = this->SignedInt;
655 // FIXME: WIntType should be SignedLong
660 template<typename Target>
661 class WindowsTargetInfo : public OSTargetInfo<Target> {
663 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
664 MacroBuilder &Builder) const override {
665 Builder.defineMacro("_WIN32");
667 void getVisualStudioDefines(const LangOptions &Opts,
668 MacroBuilder &Builder) const {
669 if (Opts.CPlusPlus) {
671 Builder.defineMacro("_CPPRTTI");
673 if (Opts.CXXExceptions)
674 Builder.defineMacro("_CPPUNWIND");
678 Builder.defineMacro("__BOOL_DEFINED");
680 if (!Opts.CharIsSigned)
681 Builder.defineMacro("_CHAR_UNSIGNED");
683 // FIXME: POSIXThreads isn't exactly the option this should be defined for,
684 // but it works for now.
685 if (Opts.POSIXThreads)
686 Builder.defineMacro("_MT");
688 if (Opts.MSCompatibilityVersion) {
689 Builder.defineMacro("_MSC_VER",
690 Twine(Opts.MSCompatibilityVersion / 100000));
691 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
692 // FIXME We cannot encode the revision information into 32-bits
693 Builder.defineMacro("_MSC_BUILD", Twine(1));
695 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
696 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
699 if (Opts.MicrosoftExt) {
700 Builder.defineMacro("_MSC_EXTENSIONS");
702 if (Opts.CPlusPlus11) {
703 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
704 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
705 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
709 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
713 WindowsTargetInfo(const llvm::Triple &Triple)
714 : OSTargetInfo<Target>(Triple) {}
717 template <typename Target>
718 class NaClTargetInfo : public OSTargetInfo<Target> {
720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
721 MacroBuilder &Builder) const override {
722 if (Opts.POSIXThreads)
723 Builder.defineMacro("_REENTRANT");
725 Builder.defineMacro("_GNU_SOURCE");
727 DefineStd(Builder, "unix", Opts);
728 Builder.defineMacro("__ELF__");
729 Builder.defineMacro("__native_client__");
733 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
734 this->UserLabelPrefix = "";
735 this->LongAlign = 32;
736 this->LongWidth = 32;
737 this->PointerAlign = 32;
738 this->PointerWidth = 32;
739 this->IntMaxType = TargetInfo::SignedLongLong;
740 this->Int64Type = TargetInfo::SignedLongLong;
741 this->DoubleAlign = 64;
742 this->LongDoubleWidth = 64;
743 this->LongDoubleAlign = 64;
744 this->LongLongWidth = 64;
745 this->LongLongAlign = 64;
746 this->SizeType = TargetInfo::UnsignedInt;
747 this->PtrDiffType = TargetInfo::SignedInt;
748 this->IntPtrType = TargetInfo::SignedInt;
749 // RegParmMax is inherited from the underlying architecture
750 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
751 if (Triple.getArch() == llvm::Triple::arm) {
752 // Handled in ARM's setABI().
753 } else if (Triple.getArch() == llvm::Triple::x86) {
754 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
755 } else if (Triple.getArch() == llvm::Triple::x86_64) {
756 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
757 } else if (Triple.getArch() == llvm::Triple::mipsel) {
758 // Handled on mips' setDataLayoutString.
760 assert(Triple.getArch() == llvm::Triple::le32);
761 this->DataLayoutString = "e-p:32:32-i64:64";
766 // WebAssembly target
767 template <typename Target>
768 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
769 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
770 MacroBuilder &Builder) const final {
771 // A common platform macro.
772 if (Opts.POSIXThreads)
773 Builder.defineMacro("_REENTRANT");
774 // Follow g++ convention and predefine _GNU_SOURCE for C++.
776 Builder.defineMacro("_GNU_SOURCE");
779 // As an optimization, group static init code together in a section.
780 const char *getStaticInitSectionSpecifier() const final {
781 return ".text.__startup";
785 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple)
786 : OSTargetInfo<Target>(Triple) {
787 this->MCountName = "__mcount";
788 this->UserLabelPrefix = "";
789 this->TheCXXABI.set(TargetCXXABI::WebAssembly);
793 //===----------------------------------------------------------------------===//
794 // Specific target implementations.
795 //===----------------------------------------------------------------------===//
797 // PPC abstract base class
798 class PPCTargetInfo : public TargetInfo {
799 static const Builtin::Info BuiltinInfo[];
800 static const char * const GCCRegNames[];
801 static const TargetInfo::GCCRegAlias GCCRegAliases[];
804 // Target cpu features.
818 PPCTargetInfo(const llvm::Triple &Triple)
819 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
820 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
821 HasBPERMD(false), HasExtDiv(false) {
822 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
823 SimdDefaultAlign = 128;
824 LongDoubleWidth = LongDoubleAlign = 128;
825 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
828 /// \brief Flags for architecture specific defines.
831 ArchDefineName = 1 << 0, // <name> is substituted for arch name.
832 ArchDefinePpcgr = 1 << 1,
833 ArchDefinePpcsq = 1 << 2,
834 ArchDefine440 = 1 << 3,
835 ArchDefine603 = 1 << 4,
836 ArchDefine604 = 1 << 5,
837 ArchDefinePwr4 = 1 << 6,
838 ArchDefinePwr5 = 1 << 7,
839 ArchDefinePwr5x = 1 << 8,
840 ArchDefinePwr6 = 1 << 9,
841 ArchDefinePwr6x = 1 << 10,
842 ArchDefinePwr7 = 1 << 11,
843 ArchDefinePwr8 = 1 << 12,
844 ArchDefineA2 = 1 << 13,
845 ArchDefineA2q = 1 << 14
848 // Note: GCC recognizes the following additional cpus:
849 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
850 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
852 bool setCPU(const std::string &Name) override {
853 bool CPUKnown = llvm::StringSwitch<bool>(Name)
854 .Case("generic", true)
876 .Case("e500mc", true)
878 .Case("power3", true)
880 .Case("power4", true)
882 .Case("power5", true)
884 .Case("power5x", true)
886 .Case("power6", true)
888 .Case("power6x", true)
890 .Case("power7", true)
892 .Case("power8", true)
894 .Case("powerpc", true)
896 .Case("powerpc64", true)
898 .Case("powerpc64le", true)
899 .Case("ppc64le", true)
909 StringRef getABI() const override { return ABI; }
911 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
912 return llvm::makeArrayRef(BuiltinInfo,
913 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
916 bool isCLZForZeroUndef() const override { return false; }
918 void getTargetDefines(const LangOptions &Opts,
919 MacroBuilder &Builder) const override;
922 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
924 const std::vector<std::string> &FeaturesVec) const override;
926 bool handleTargetFeatures(std::vector<std::string> &Features,
927 DiagnosticsEngine &Diags) override;
928 bool hasFeature(StringRef Feature) const override;
929 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
930 bool Enabled) const override;
932 ArrayRef<const char *> getGCCRegNames() const override;
933 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
934 bool validateAsmConstraint(const char *&Name,
935 TargetInfo::ConstraintInfo &Info) const override {
937 default: return false;
940 case 'b': // Base register
941 case 'f': // Floating point register
942 Info.setAllowsRegister();
944 // FIXME: The following are added to allow parsing.
945 // I just took a guess at what the actions should be.
946 // Also, is more specific checking needed? I.e. specific registers?
947 case 'd': // Floating point register (containing 64-bit value)
948 case 'v': // Altivec vector register
949 Info.setAllowsRegister();
953 case 'd':// VSX vector register to hold vector double data
954 case 'f':// VSX vector register to hold vector float data
955 case 's':// VSX vector register to hold scalar float data
956 case 'a':// Any VSX register
957 case 'c':// An individual CR bit
962 Info.setAllowsRegister();
963 Name++; // Skip over 'w'.
965 case 'h': // `MQ', `CTR', or `LINK' register
966 case 'q': // `MQ' register
967 case 'c': // `CTR' register
968 case 'l': // `LINK' register
969 case 'x': // `CR' register (condition register) number 0
970 case 'y': // `CR' register (condition register)
971 case 'z': // `XER[CA]' carry bit (part of the XER register)
972 Info.setAllowsRegister();
974 case 'I': // Signed 16-bit constant
975 case 'J': // Unsigned 16-bit constant shifted left 16 bits
976 // (use `L' instead for SImode constants)
977 case 'K': // Unsigned 16-bit constant
978 case 'L': // Signed 16-bit constant shifted left 16 bits
979 case 'M': // Constant larger than 31
980 case 'N': // Exact power of 2
981 case 'P': // Constant whose negation is a signed 16-bit constant
982 case 'G': // Floating point constant that can be loaded into a
983 // register with one instruction per word
984 case 'H': // Integer/Floating point constant that can be loaded
985 // into a register using three instructions
987 case 'm': // Memory operand. Note that on PowerPC targets, m can
988 // include addresses that update the base register. It
989 // is therefore only safe to use `m' in an asm statement
990 // if that asm statement accesses the operand exactly once.
991 // The asm statement must also use `%U<opno>' as a
992 // placeholder for the "update" flag in the corresponding
993 // load or store instruction. For example:
994 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
996 // asm ("st %1,%0" : "=m" (mem) : "r" (val));
997 // is not. Use es rather than m if you don't want the base
998 // register to be updated.
1002 // es: A "stable" memory operand; that is, one which does not
1003 // include any automodification of the base register. Unlike
1004 // `m', this constraint can be used in asm statements that
1005 // might access the operand several times, or that might not
1006 // access it at all.
1007 Info.setAllowsMemory();
1008 Name++; // Skip over 'e'.
1010 case 'Q': // Memory operand that is an offset from a register (it is
1011 // usually better to use `m' or `es' in asm statements)
1012 case 'Z': // Memory operand that is an indexed or indirect from a
1013 // register (it is usually better to use `m' or `es' in
1015 Info.setAllowsMemory();
1016 Info.setAllowsRegister();
1018 case 'R': // AIX TOC entry
1019 case 'a': // Address operand that is an indexed or indirect from a
1020 // register (`p' is preferable for asm statements)
1021 case 'S': // Constant suitable as a 64-bit mask operand
1022 case 'T': // Constant suitable as a 32-bit mask operand
1023 case 'U': // System V Release 4 small data area reference
1024 case 't': // AND masks that can be performed by two rldic{l, r}
1026 case 'W': // Vector constant that does not require memory
1027 case 'j': // Vector constant that is all zeros.
1033 std::string convertConstraint(const char *&Constraint) const override {
1035 switch (*Constraint) {
1038 // Two-character constraint; add "^" hint for later parsing.
1039 R = std::string("^") + std::string(Constraint, 2);
1043 return TargetInfo::convertConstraint(Constraint);
1047 const char *getClobbers() const override {
1050 int getEHDataRegisterNumber(unsigned RegNo) const override {
1051 if (RegNo == 0) return 3;
1052 if (RegNo == 1) return 4;
1056 bool hasSjLjLowering() const override {
1060 bool useFloat128ManglingForLongDouble() const override {
1061 return LongDoubleWidth == 128 &&
1062 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1063 getTriple().isOSBinFormatELF();
1067 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1068 #define BUILTIN(ID, TYPE, ATTRS) \
1069 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1070 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1071 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1072 #include "clang/Basic/BuiltinsPPC.def"
1075 /// handleTargetFeatures - Perform initialization based on the user
1076 /// configured set of features.
1077 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1078 DiagnosticsEngine &Diags) {
1079 for (const auto &Feature : Features) {
1080 if (Feature == "+vsx") {
1082 } else if (Feature == "+bpermd") {
1084 } else if (Feature == "+extdiv") {
1086 } else if (Feature == "+power8-vector") {
1088 } else if (Feature == "+crypto") {
1090 } else if (Feature == "+direct-move") {
1091 HasDirectMove = true;
1092 } else if (Feature == "+qpx") {
1094 } else if (Feature == "+htm") {
1097 // TODO: Finish this list and add an assert that we've handled them
1104 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1105 /// #defines that are not tied to a specific subtarget.
1106 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1107 MacroBuilder &Builder) const {
1108 // Target identification.
1109 Builder.defineMacro("__ppc__");
1110 Builder.defineMacro("__PPC__");
1111 Builder.defineMacro("_ARCH_PPC");
1112 Builder.defineMacro("__powerpc__");
1113 Builder.defineMacro("__POWERPC__");
1114 if (PointerWidth == 64) {
1115 Builder.defineMacro("_ARCH_PPC64");
1116 Builder.defineMacro("__powerpc64__");
1117 Builder.defineMacro("__ppc64__");
1118 Builder.defineMacro("__PPC64__");
1121 // Target properties.
1122 if (getTriple().getArch() == llvm::Triple::ppc64le) {
1123 Builder.defineMacro("_LITTLE_ENDIAN");
1125 if (getTriple().getOS() != llvm::Triple::NetBSD &&
1126 getTriple().getOS() != llvm::Triple::OpenBSD)
1127 Builder.defineMacro("_BIG_ENDIAN");
1131 if (ABI == "elfv1" || ABI == "elfv1-qpx")
1132 Builder.defineMacro("_CALL_ELF", "1");
1134 Builder.defineMacro("_CALL_ELF", "2");
1136 // Subtarget options.
1137 Builder.defineMacro("__NATURAL_ALIGNMENT__");
1138 Builder.defineMacro("__REGISTER_PREFIX__", "");
1140 // FIXME: Should be controlled by command line option.
1141 if (LongDoubleWidth == 128)
1142 Builder.defineMacro("__LONG_DOUBLE_128__");
1145 Builder.defineMacro("__VEC__", "10206");
1146 Builder.defineMacro("__ALTIVEC__");
1149 // CPU identification.
1150 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1151 .Case("440", ArchDefineName)
1152 .Case("450", ArchDefineName | ArchDefine440)
1153 .Case("601", ArchDefineName)
1154 .Case("602", ArchDefineName | ArchDefinePpcgr)
1155 .Case("603", ArchDefineName | ArchDefinePpcgr)
1156 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1157 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1158 .Case("604", ArchDefineName | ArchDefinePpcgr)
1159 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1160 .Case("620", ArchDefineName | ArchDefinePpcgr)
1161 .Case("630", ArchDefineName | ArchDefinePpcgr)
1162 .Case("7400", ArchDefineName | ArchDefinePpcgr)
1163 .Case("7450", ArchDefineName | ArchDefinePpcgr)
1164 .Case("750", ArchDefineName | ArchDefinePpcgr)
1165 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1167 .Case("a2", ArchDefineA2)
1168 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1169 .Case("pwr3", ArchDefinePpcgr)
1170 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1171 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1173 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1174 | ArchDefinePpcgr | ArchDefinePpcsq)
1175 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1176 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1177 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1178 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1180 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1181 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1182 | ArchDefinePpcgr | ArchDefinePpcsq)
1183 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1184 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1185 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1186 .Case("power3", ArchDefinePpcgr)
1187 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1188 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1190 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1191 | ArchDefinePpcgr | ArchDefinePpcsq)
1192 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1193 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1194 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1195 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1197 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1198 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1199 | ArchDefinePpcgr | ArchDefinePpcsq)
1200 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1201 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1202 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1203 .Default(ArchDefineNone);
1205 if (defs & ArchDefineName)
1206 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1207 if (defs & ArchDefinePpcgr)
1208 Builder.defineMacro("_ARCH_PPCGR");
1209 if (defs & ArchDefinePpcsq)
1210 Builder.defineMacro("_ARCH_PPCSQ");
1211 if (defs & ArchDefine440)
1212 Builder.defineMacro("_ARCH_440");
1213 if (defs & ArchDefine603)
1214 Builder.defineMacro("_ARCH_603");
1215 if (defs & ArchDefine604)
1216 Builder.defineMacro("_ARCH_604");
1217 if (defs & ArchDefinePwr4)
1218 Builder.defineMacro("_ARCH_PWR4");
1219 if (defs & ArchDefinePwr5)
1220 Builder.defineMacro("_ARCH_PWR5");
1221 if (defs & ArchDefinePwr5x)
1222 Builder.defineMacro("_ARCH_PWR5X");
1223 if (defs & ArchDefinePwr6)
1224 Builder.defineMacro("_ARCH_PWR6");
1225 if (defs & ArchDefinePwr6x)
1226 Builder.defineMacro("_ARCH_PWR6X");
1227 if (defs & ArchDefinePwr7)
1228 Builder.defineMacro("_ARCH_PWR7");
1229 if (defs & ArchDefinePwr8)
1230 Builder.defineMacro("_ARCH_PWR8");
1231 if (defs & ArchDefineA2)
1232 Builder.defineMacro("_ARCH_A2");
1233 if (defs & ArchDefineA2q) {
1234 Builder.defineMacro("_ARCH_A2Q");
1235 Builder.defineMacro("_ARCH_QP");
1238 if (getTriple().getVendor() == llvm::Triple::BGQ) {
1239 Builder.defineMacro("__bg__");
1240 Builder.defineMacro("__THW_BLUEGENE__");
1241 Builder.defineMacro("__bgq__");
1242 Builder.defineMacro("__TOS_BGQ__");
1246 Builder.defineMacro("__VSX__");
1248 Builder.defineMacro("__POWER8_VECTOR__");
1250 Builder.defineMacro("__CRYPTO__");
1252 Builder.defineMacro("__HTM__");
1254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1257 if (PointerWidth == 64)
1258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1260 // FIXME: The following are not yet generated here by Clang, but are
1261 // generated by GCC:
1264 // __RECIP_PRECISION__
1265 // __APPLE_ALTIVEC__
1274 // __CMODEL_MEDIUM__
1281 // Handle explicit options being passed to the compiler here: if we've
1282 // explicitly turned off vsx and turned on power8-vector or direct-move then
1283 // go ahead and error since the customer has expressed a somewhat incompatible
1285 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1286 const std::vector<std::string> &FeaturesVec) {
1288 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1289 FeaturesVec.end()) {
1290 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1291 FeaturesVec.end()) {
1292 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1297 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1298 FeaturesVec.end()) {
1299 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1308 bool PPCTargetInfo::initFeatureMap(
1309 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1310 const std::vector<std::string> &FeaturesVec) const {
1311 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1321 .Case("ppc64", true)
1322 .Case("ppc64le", true)
1325 Features["qpx"] = (CPU == "a2q");
1326 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1327 .Case("ppc64le", true)
1330 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1331 .Case("ppc64le", true)
1334 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1335 .Case("ppc64le", true)
1339 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1340 .Case("ppc64le", true)
1344 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1345 .Case("ppc64le", true)
1348 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1349 .Case("ppc64le", true)
1354 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1357 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1360 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1361 return llvm::StringSwitch<bool>(Feature)
1362 .Case("powerpc", true)
1363 .Case("vsx", HasVSX)
1364 .Case("power8-vector", HasP8Vector)
1365 .Case("crypto", HasP8Crypto)
1366 .Case("direct-move", HasDirectMove)
1367 .Case("qpx", HasQPX)
1368 .Case("htm", HasHTM)
1369 .Case("bpermd", HasBPERMD)
1370 .Case("extdiv", HasExtDiv)
1374 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1375 StringRef Name, bool Enabled) const {
1376 // If we're enabling direct-move or power8-vector go ahead and enable vsx
1377 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1378 // incompatible options.
1380 if (Name == "vsx") {
1381 Features[Name] = true;
1382 } else if (Name == "direct-move") {
1383 Features[Name] = Features["vsx"] = true;
1384 } else if (Name == "power8-vector") {
1385 Features[Name] = Features["vsx"] = true;
1387 Features[Name] = true;
1390 if (Name == "vsx") {
1391 Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1394 Features[Name] = false;
1399 const char * const PPCTargetInfo::GCCRegNames[] = {
1400 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1401 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1402 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1403 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1408 "mq", "lr", "ctr", "ap",
1409 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1411 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1412 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1413 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1414 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1416 "spe_acc", "spefscr",
1420 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1421 return llvm::makeArrayRef(GCCRegNames);
1424 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1425 // While some of these aliases do map to different registers
1426 // they still share the same register name.
1437 { { "10" }, "r10" },
1438 { { "11" }, "r11" },
1439 { { "12" }, "r12" },
1440 { { "13" }, "r13" },
1441 { { "14" }, "r14" },
1442 { { "15" }, "r15" },
1443 { { "16" }, "r16" },
1444 { { "17" }, "r17" },
1445 { { "18" }, "r18" },
1446 { { "19" }, "r19" },
1447 { { "20" }, "r20" },
1448 { { "21" }, "r21" },
1449 { { "22" }, "r22" },
1450 { { "23" }, "r23" },
1451 { { "24" }, "r24" },
1452 { { "25" }, "r25" },
1453 { { "26" }, "r26" },
1454 { { "27" }, "r27" },
1455 { { "28" }, "r28" },
1456 { { "29" }, "r29" },
1457 { { "30" }, "r30" },
1458 { { "31" }, "r31" },
1459 { { "fr0" }, "f0" },
1460 { { "fr1" }, "f1" },
1461 { { "fr2" }, "f2" },
1462 { { "fr3" }, "f3" },
1463 { { "fr4" }, "f4" },
1464 { { "fr5" }, "f5" },
1465 { { "fr6" }, "f6" },
1466 { { "fr7" }, "f7" },
1467 { { "fr8" }, "f8" },
1468 { { "fr9" }, "f9" },
1469 { { "fr10" }, "f10" },
1470 { { "fr11" }, "f11" },
1471 { { "fr12" }, "f12" },
1472 { { "fr13" }, "f13" },
1473 { { "fr14" }, "f14" },
1474 { { "fr15" }, "f15" },
1475 { { "fr16" }, "f16" },
1476 { { "fr17" }, "f17" },
1477 { { "fr18" }, "f18" },
1478 { { "fr19" }, "f19" },
1479 { { "fr20" }, "f20" },
1480 { { "fr21" }, "f21" },
1481 { { "fr22" }, "f22" },
1482 { { "fr23" }, "f23" },
1483 { { "fr24" }, "f24" },
1484 { { "fr25" }, "f25" },
1485 { { "fr26" }, "f26" },
1486 { { "fr27" }, "f27" },
1487 { { "fr28" }, "f28" },
1488 { { "fr29" }, "f29" },
1489 { { "fr30" }, "f30" },
1490 { { "fr31" }, "f31" },
1491 { { "cc" }, "cr0" },
1494 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1495 return llvm::makeArrayRef(GCCRegAliases);
1498 class PPC32TargetInfo : public PPCTargetInfo {
1500 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1501 DataLayoutString = "E-m:e-p:32:32-i64:64-n32";
1503 switch (getTriple().getOS()) {
1504 case llvm::Triple::Linux:
1505 case llvm::Triple::FreeBSD:
1506 case llvm::Triple::NetBSD:
1507 SizeType = UnsignedInt;
1508 PtrDiffType = SignedInt;
1509 IntPtrType = SignedInt;
1515 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1516 LongDoubleWidth = LongDoubleAlign = 64;
1517 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1520 // PPC32 supports atomics up to 4 bytes.
1521 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1524 BuiltinVaListKind getBuiltinVaListKind() const override {
1525 // This is the ELF definition, and is overridden by the Darwin sub-target
1526 return TargetInfo::PowerABIBuiltinVaList;
1530 // Note: ABI differences may eventually require us to have a separate
1531 // TargetInfo for little endian.
1532 class PPC64TargetInfo : public PPCTargetInfo {
1534 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1535 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1536 IntMaxType = SignedLong;
1537 Int64Type = SignedLong;
1539 if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1540 DataLayoutString = "e-m:e-i64:64-n32:64";
1543 DataLayoutString = "E-m:e-i64:64-n32:64";
1547 switch (getTriple().getOS()) {
1548 case llvm::Triple::FreeBSD:
1549 LongDoubleWidth = LongDoubleAlign = 64;
1550 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1552 case llvm::Triple::NetBSD:
1553 IntMaxType = SignedLongLong;
1554 Int64Type = SignedLongLong;
1560 // PPC64 supports atomics up to 8 bytes.
1561 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1563 BuiltinVaListKind getBuiltinVaListKind() const override {
1564 return TargetInfo::CharPtrBuiltinVaList;
1566 // PPC64 Linux-specific ABI options.
1567 bool setABI(const std::string &Name) override {
1568 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1576 class DarwinPPC32TargetInfo :
1577 public DarwinTargetInfo<PPC32TargetInfo> {
1579 DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1580 : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1581 HasAlignMac68kSupport = true;
1582 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1583 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1585 SuitableAlign = 128;
1586 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32";
1588 BuiltinVaListKind getBuiltinVaListKind() const override {
1589 return TargetInfo::CharPtrBuiltinVaList;
1593 class DarwinPPC64TargetInfo :
1594 public DarwinTargetInfo<PPC64TargetInfo> {
1596 DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1597 : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1598 HasAlignMac68kSupport = true;
1599 SuitableAlign = 128;
1600 DataLayoutString = "E-m:o-i64:64-n32:64";
1604 static const unsigned NVPTXAddrSpaceMap[] = {
1607 4, // opencl_constant
1608 // FIXME: generic has to be added to the target
1609 0, // opencl_generic
1615 class NVPTXTargetInfo : public TargetInfo {
1616 static const char *const GCCRegNames[];
1617 static const Builtin::Info BuiltinInfo[];
1619 // The GPU profiles supported by the NVPTX backend
1630 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1632 TLSSupported = false;
1633 LongWidth = LongAlign = 64;
1634 AddrSpaceMap = &NVPTXAddrSpaceMap;
1635 UseAddrSpaceMapMangling = true;
1636 // Define available target features
1637 // These must be defined in sorted order!
1638 NoAsmVariants = true;
1639 // Set the default GPU to sm20
1642 void getTargetDefines(const LangOptions &Opts,
1643 MacroBuilder &Builder) const override {
1644 Builder.defineMacro("__PTX__");
1645 Builder.defineMacro("__NVPTX__");
1646 if (Opts.CUDAIsDevice) {
1647 // Set __CUDA_ARCH__ for the GPU specified.
1648 std::string CUDAArchCode;
1651 CUDAArchCode = "200";
1654 CUDAArchCode = "210";
1657 CUDAArchCode = "300";
1660 CUDAArchCode = "350";
1663 CUDAArchCode = "370";
1666 llvm_unreachable("Unhandled target CPU");
1668 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1671 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1672 return llvm::makeArrayRef(BuiltinInfo,
1673 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1675 bool hasFeature(StringRef Feature) const override {
1676 return Feature == "ptx" || Feature == "nvptx";
1679 ArrayRef<const char *> getGCCRegNames() const override;
1680 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1684 bool validateAsmConstraint(const char *&Name,
1685 TargetInfo::ConstraintInfo &Info) const override {
1695 Info.setAllowsRegister();
1699 const char *getClobbers() const override {
1700 // FIXME: Is this really right?
1703 BuiltinVaListKind getBuiltinVaListKind() const override {
1705 return TargetInfo::CharPtrBuiltinVaList;
1707 bool setCPU(const std::string &Name) override {
1708 GPU = llvm::StringSwitch<GPUKind>(Name)
1709 .Case("sm_20", GK_SM20)
1710 .Case("sm_21", GK_SM21)
1711 .Case("sm_30", GK_SM30)
1712 .Case("sm_35", GK_SM35)
1713 .Case("sm_37", GK_SM37)
1716 return GPU != GK_NONE;
1720 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1721 #define BUILTIN(ID, TYPE, ATTRS) \
1722 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1723 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1724 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1725 #include "clang/Basic/BuiltinsNVPTX.def"
1728 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1730 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1731 return llvm::makeArrayRef(GCCRegNames);
1734 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1736 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1737 LongWidth = LongAlign = 32;
1738 PointerWidth = PointerAlign = 32;
1739 SizeType = TargetInfo::UnsignedInt;
1740 PtrDiffType = TargetInfo::SignedInt;
1741 IntPtrType = TargetInfo::SignedInt;
1742 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1746 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1748 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1749 PointerWidth = PointerAlign = 64;
1750 SizeType = TargetInfo::UnsignedLong;
1751 PtrDiffType = TargetInfo::SignedLong;
1752 IntPtrType = TargetInfo::SignedLong;
1753 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64";
1757 static const unsigned AMDGPUAddrSpaceMap[] = {
1760 2, // opencl_constant
1761 4, // opencl_generic
1767 // If you edit the description strings, make sure you update
1768 // getPointerWidthV().
1770 static const char *const DataLayoutStringR600 =
1771 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1772 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1774 static const char *const DataLayoutStringR600DoubleOps =
1775 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1776 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1778 static const char *const DataLayoutStringSI =
1779 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1780 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1781 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1783 class AMDGPUTargetInfo : public TargetInfo {
1784 static const Builtin::Info BuiltinInfo[];
1785 static const char * const GCCRegNames[];
1787 /// \brief The GPU profiles supported by the AMDGPU target.
1795 GK_EVERGREEN_DOUBLE_OPS,
1796 GK_NORTHERN_ISLANDS,
1798 GK_SOUTHERN_ISLANDS,
1808 AMDGPUTargetInfo(const llvm::Triple &Triple)
1809 : TargetInfo(Triple) {
1811 if (Triple.getArch() == llvm::Triple::amdgcn) {
1812 DataLayoutString = DataLayoutStringSI;
1813 GPU = GK_SOUTHERN_ISLANDS;
1818 DataLayoutString = DataLayoutStringR600;
1824 AddrSpaceMap = &AMDGPUAddrSpaceMap;
1825 UseAddrSpaceMapMangling = true;
1828 uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1829 if (GPU <= GK_CAYMAN)
1842 const char * getClobbers() const override {
1846 ArrayRef<const char *> getGCCRegNames() const override;
1848 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1852 bool validateAsmConstraint(const char *&Name,
1853 TargetInfo::ConstraintInfo &Info) const override {
1858 Info.setAllowsRegister();
1864 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1865 return llvm::makeArrayRef(BuiltinInfo,
1866 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
1869 void getTargetDefines(const LangOptions &Opts,
1870 MacroBuilder &Builder) const override {
1871 Builder.defineMacro("__R600__");
1873 Builder.defineMacro("__HAS_FMAF__");
1875 Builder.defineMacro("__HAS_LDEXPF__");
1876 if (hasFP64 && Opts.OpenCL)
1877 Builder.defineMacro("cl_khr_fp64");
1879 if (GPU >= GK_NORTHERN_ISLANDS) {
1880 Builder.defineMacro("cl_khr_byte_addressable_store");
1881 Builder.defineMacro("cl_khr_global_int32_base_atomics");
1882 Builder.defineMacro("cl_khr_global_int32_extended_atomics");
1883 Builder.defineMacro("cl_khr_local_int32_base_atomics");
1884 Builder.defineMacro("cl_khr_local_int32_extended_atomics");
1889 BuiltinVaListKind getBuiltinVaListKind() const override {
1890 return TargetInfo::CharPtrBuiltinVaList;
1893 bool setCPU(const std::string &Name) override {
1894 GPU = llvm::StringSwitch<GPUKind>(Name)
1895 .Case("r600" , GK_R600)
1896 .Case("rv610", GK_R600)
1897 .Case("rv620", GK_R600)
1898 .Case("rv630", GK_R600)
1899 .Case("rv635", GK_R600)
1900 .Case("rs780", GK_R600)
1901 .Case("rs880", GK_R600)
1902 .Case("rv670", GK_R600_DOUBLE_OPS)
1903 .Case("rv710", GK_R700)
1904 .Case("rv730", GK_R700)
1905 .Case("rv740", GK_R700_DOUBLE_OPS)
1906 .Case("rv770", GK_R700_DOUBLE_OPS)
1907 .Case("palm", GK_EVERGREEN)
1908 .Case("cedar", GK_EVERGREEN)
1909 .Case("sumo", GK_EVERGREEN)
1910 .Case("sumo2", GK_EVERGREEN)
1911 .Case("redwood", GK_EVERGREEN)
1912 .Case("juniper", GK_EVERGREEN)
1913 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS)
1914 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS)
1915 .Case("barts", GK_NORTHERN_ISLANDS)
1916 .Case("turks", GK_NORTHERN_ISLANDS)
1917 .Case("caicos", GK_NORTHERN_ISLANDS)
1918 .Case("cayman", GK_CAYMAN)
1919 .Case("aruba", GK_CAYMAN)
1920 .Case("tahiti", GK_SOUTHERN_ISLANDS)
1921 .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1922 .Case("verde", GK_SOUTHERN_ISLANDS)
1923 .Case("oland", GK_SOUTHERN_ISLANDS)
1924 .Case("hainan", GK_SOUTHERN_ISLANDS)
1925 .Case("bonaire", GK_SEA_ISLANDS)
1926 .Case("kabini", GK_SEA_ISLANDS)
1927 .Case("kaveri", GK_SEA_ISLANDS)
1928 .Case("hawaii", GK_SEA_ISLANDS)
1929 .Case("mullins", GK_SEA_ISLANDS)
1930 .Case("tonga", GK_VOLCANIC_ISLANDS)
1931 .Case("iceland", GK_VOLCANIC_ISLANDS)
1932 .Case("carrizo", GK_VOLCANIC_ISLANDS)
1935 if (GPU == GK_NONE) {
1939 // Set the correct data layout
1945 case GK_NORTHERN_ISLANDS:
1946 DataLayoutString = DataLayoutStringR600;
1951 case GK_R600_DOUBLE_OPS:
1952 case GK_R700_DOUBLE_OPS:
1953 case GK_EVERGREEN_DOUBLE_OPS:
1955 DataLayoutString = DataLayoutStringR600DoubleOps;
1960 case GK_SOUTHERN_ISLANDS:
1961 case GK_SEA_ISLANDS:
1962 case GK_VOLCANIC_ISLANDS:
1963 DataLayoutString = DataLayoutStringSI;
1974 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1975 #define BUILTIN(ID, TYPE, ATTRS) \
1976 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1977 #include "clang/Basic/BuiltinsAMDGPU.def"
1979 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1980 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1981 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1982 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1983 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1984 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1985 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1986 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1987 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1988 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1989 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1990 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1991 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1992 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1993 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1994 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1995 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1996 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1997 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1998 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1999 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
2000 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
2001 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
2002 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
2003 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
2004 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
2005 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
2006 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
2007 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
2008 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
2009 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
2010 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
2011 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
2012 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2013 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2014 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2015 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2016 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2017 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2018 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2019 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2020 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2021 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2022 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2023 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2024 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2025 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2026 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2027 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
2028 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
2029 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
2032 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2033 return llvm::makeArrayRef(GCCRegNames);
2036 // Namespace for x86 abstract base class
2037 const Builtin::Info BuiltinInfo[] = {
2038 #define BUILTIN(ID, TYPE, ATTRS) \
2039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2040 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
2041 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2042 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
2043 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2044 #include "clang/Basic/BuiltinsX86.def"
2047 static const char* const GCCRegNames[] = {
2048 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2049 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2050 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2051 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2052 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2053 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2054 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2055 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2056 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2059 const TargetInfo::AddlRegName AddlRegNames[] = {
2060 { { "al", "ah", "eax", "rax" }, 0 },
2061 { { "bl", "bh", "ebx", "rbx" }, 3 },
2062 { { "cl", "ch", "ecx", "rcx" }, 2 },
2063 { { "dl", "dh", "edx", "rdx" }, 1 },
2064 { { "esi", "rsi" }, 4 },
2065 { { "edi", "rdi" }, 5 },
2066 { { "esp", "rsp" }, 7 },
2067 { { "ebp", "rbp" }, 6 },
2068 { { "r8d", "r8w", "r8b" }, 38 },
2069 { { "r9d", "r9w", "r9b" }, 39 },
2070 { { "r10d", "r10w", "r10b" }, 40 },
2071 { { "r11d", "r11w", "r11b" }, 41 },
2072 { { "r12d", "r12w", "r12b" }, 42 },
2073 { { "r13d", "r13w", "r13b" }, 43 },
2074 { { "r14d", "r14w", "r14b" }, 44 },
2075 { { "r15d", "r15w", "r15b" }, 45 },
2078 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2079 // most of the implementation can be shared.
2080 class X86TargetInfo : public TargetInfo {
2082 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2085 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2086 } MMX3DNowLevel = NoMMX3DNow;
2094 bool HasAES = false;
2095 bool HasPCLMUL = false;
2096 bool HasLZCNT = false;
2097 bool HasRDRND = false;
2098 bool HasFSGSBASE = false;
2099 bool HasBMI = false;
2100 bool HasBMI2 = false;
2101 bool HasPOPCNT = false;
2102 bool HasRTM = false;
2103 bool HasPRFCHW = false;
2104 bool HasRDSEED = false;
2105 bool HasADX = false;
2106 bool HasTBM = false;
2107 bool HasFMA = false;
2108 bool HasF16C = false;
2109 bool HasAVX512CD = false;
2110 bool HasAVX512ER = false;
2111 bool HasAVX512PF = false;
2112 bool HasAVX512DQ = false;
2113 bool HasAVX512BW = false;
2114 bool HasAVX512VL = false;
2115 bool HasSHA = false;
2116 bool HasCX16 = false;
2117 bool HasFXSR = false;
2118 bool HasXSAVE = false;
2119 bool HasXSAVEOPT = false;
2120 bool HasXSAVEC = false;
2121 bool HasXSAVES = false;
2122 bool HasPKU = false;
2124 /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2126 /// Each enumeration represents a particular CPU supported by Clang. These
2127 /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2132 /// i386-generation processors.
2138 /// i486-generation processors.
2147 /// i586-generation processors, P5 microarchitecture based.
2155 /// i686-generation processors, P6 / Pentium M microarchitecture based.
2165 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2166 /// Clang however has some logic to suport this.
2167 // FIXME: Warn, deprecate, and potentially remove this.
2172 /// Netburst microarchitecture based processors.
2181 /// Core microarchitecture based processors.
2185 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2186 /// codename which GCC no longer accepts as an option to -march, but Clang
2187 /// has some logic for recognizing it.
2188 // FIXME: Warn, deprecate, and potentially remove this.
2200 /// Nehalem microarchitecture based processors.
2204 /// Westmere microarchitecture based processors.
2207 /// \name Sandy Bridge
2208 /// Sandy Bridge microarchitecture based processors.
2211 /// \name Ivy Bridge
2212 /// Ivy Bridge microarchitecture based processors.
2216 /// Haswell microarchitecture based processors.
2220 /// Broadwell microarchitecture based processors.
2224 /// Skylake microarchitecture based processors.
2227 /// \name Knights Landing
2228 /// Knights Landing processor.
2232 /// K6 architecture processors.
2240 /// K7 architecture processors.
2243 CK_AthlonThunderbird,
2250 /// K8 architecture processors.
2263 /// Bobcat architecture processors.
2270 /// Bulldozer architecture processors.
2278 /// This specification is deprecated and will be removed in the future.
2279 /// Users should prefer \see CK_K8.
2280 // FIXME: Warn on this when the CPU is set to it.
2286 /// Geode processors.
2292 CPUKind getCPUKind(StringRef CPU) const {
2293 return llvm::StringSwitch<CPUKind>(CPU)
2294 .Case("i386", CK_i386)
2295 .Case("i486", CK_i486)
2296 .Case("winchip-c6", CK_WinChipC6)
2297 .Case("winchip2", CK_WinChip2)
2299 .Case("i586", CK_i586)
2300 .Case("pentium", CK_Pentium)
2301 .Case("pentium-mmx", CK_PentiumMMX)
2302 .Case("i686", CK_i686)
2303 .Case("pentiumpro", CK_PentiumPro)
2304 .Case("pentium2", CK_Pentium2)
2305 .Case("pentium3", CK_Pentium3)
2306 .Case("pentium3m", CK_Pentium3M)
2307 .Case("pentium-m", CK_PentiumM)
2308 .Case("c3-2", CK_C3_2)
2309 .Case("yonah", CK_Yonah)
2310 .Case("pentium4", CK_Pentium4)
2311 .Case("pentium4m", CK_Pentium4M)
2312 .Case("prescott", CK_Prescott)
2313 .Case("nocona", CK_Nocona)
2314 .Case("core2", CK_Core2)
2315 .Case("penryn", CK_Penryn)
2316 .Case("bonnell", CK_Bonnell)
2317 .Case("atom", CK_Bonnell) // Legacy name.
2318 .Case("silvermont", CK_Silvermont)
2319 .Case("slm", CK_Silvermont) // Legacy name.
2320 .Case("nehalem", CK_Nehalem)
2321 .Case("corei7", CK_Nehalem) // Legacy name.
2322 .Case("westmere", CK_Westmere)
2323 .Case("sandybridge", CK_SandyBridge)
2324 .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2325 .Case("ivybridge", CK_IvyBridge)
2326 .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2327 .Case("haswell", CK_Haswell)
2328 .Case("core-avx2", CK_Haswell) // Legacy name.
2329 .Case("broadwell", CK_Broadwell)
2330 .Case("skylake", CK_Skylake)
2331 .Case("skx", CK_Skylake) // Legacy name.
2332 .Case("knl", CK_KNL)
2334 .Case("k6-2", CK_K6_2)
2335 .Case("k6-3", CK_K6_3)
2336 .Case("athlon", CK_Athlon)
2337 .Case("athlon-tbird", CK_AthlonThunderbird)
2338 .Case("athlon-4", CK_Athlon4)
2339 .Case("athlon-xp", CK_AthlonXP)
2340 .Case("athlon-mp", CK_AthlonMP)
2341 .Case("athlon64", CK_Athlon64)
2342 .Case("athlon64-sse3", CK_Athlon64SSE3)
2343 .Case("athlon-fx", CK_AthlonFX)
2345 .Case("k8-sse3", CK_K8SSE3)
2346 .Case("opteron", CK_Opteron)
2347 .Case("opteron-sse3", CK_OpteronSSE3)
2348 .Case("barcelona", CK_AMDFAM10)
2349 .Case("amdfam10", CK_AMDFAM10)
2350 .Case("btver1", CK_BTVER1)
2351 .Case("btver2", CK_BTVER2)
2352 .Case("bdver1", CK_BDVER1)
2353 .Case("bdver2", CK_BDVER2)
2354 .Case("bdver3", CK_BDVER3)
2355 .Case("bdver4", CK_BDVER4)
2356 .Case("x86-64", CK_x86_64)
2357 .Case("geode", CK_Geode)
2358 .Default(CK_Generic);
2365 } FPMath = FP_Default;
2368 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
2370 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2372 unsigned getFloatEvalMethod() const override {
2373 // X87 evaluates with 80 bits "long double" precision.
2374 return SSELevel == NoSSE ? 2 : 0;
2376 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2377 return llvm::makeArrayRef(BuiltinInfo,
2378 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin);
2380 ArrayRef<const char *> getGCCRegNames() const override {
2381 return llvm::makeArrayRef(GCCRegNames);
2383 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2386 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2387 return llvm::makeArrayRef(AddlRegNames);
2389 bool validateCpuSupports(StringRef Name) const override;
2390 bool validateAsmConstraint(const char *&Name,
2391 TargetInfo::ConstraintInfo &info) const override;
2393 bool validateGlobalRegisterVariable(StringRef RegName,
2395 bool &HasSizeMismatch) const override {
2396 // esp and ebp are the only 32-bit registers the x86 backend can currently
2398 if (RegName.equals("esp") || RegName.equals("ebp")) {
2399 // Check that the register size is 32-bit.
2400 HasSizeMismatch = RegSize != 32;
2407 bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2409 bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2411 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2413 std::string convertConstraint(const char *&Constraint) const override;
2414 const char *getClobbers() const override {
2415 return "~{dirflag},~{fpsr},~{flags}";
2417 void getTargetDefines(const LangOptions &Opts,
2418 MacroBuilder &Builder) const override;
2419 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2421 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2423 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2425 void setFeatureEnabled(llvm::StringMap<bool> &Features,
2426 StringRef Name, bool Enabled) const override {
2427 setFeatureEnabledImpl(Features, Name, Enabled);
2429 // This exists purely to cut down on the number of virtual calls in
2430 // initFeatureMap which calls this repeatedly.
2431 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2432 StringRef Name, bool Enabled);
2434 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2436 const std::vector<std::string> &FeaturesVec) const override;
2437 bool hasFeature(StringRef Feature) const override;
2438 bool handleTargetFeatures(std::vector<std::string> &Features,
2439 DiagnosticsEngine &Diags) override;
2440 StringRef getABI() const override {
2441 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2443 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2445 if (getTriple().getArch() == llvm::Triple::x86 &&
2446 MMX3DNowLevel == NoMMX3DNow)
2450 bool setCPU(const std::string &Name) override {
2451 CPU = getCPUKind(Name);
2453 // Perform any per-CPU checks necessary to determine if this CPU is
2455 // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2456 // invalid without explaining *why*.
2459 // No processor selected!
2485 case CK_AthlonThunderbird:
2490 // Only accept certain architectures when compiling in 32-bit mode.
2491 if (getTriple().getArch() != llvm::Triple::x86)
2502 case CK_SandyBridge:
2509 case CK_Athlon64SSE3:
2514 case CK_OpteronSSE3:
2525 llvm_unreachable("Unhandled CPU kind");
2528 bool setFPMath(StringRef Name) override;
2530 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2531 // We accept all non-ARM calling conventions
2532 return (CC == CC_X86ThisCall ||
2533 CC == CC_X86FastCall ||
2534 CC == CC_X86StdCall ||
2535 CC == CC_X86VectorCall ||
2537 CC == CC_X86Pascal ||
2538 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2541 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2542 return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2545 bool hasSjLjLowering() const override {
2550 bool X86TargetInfo::setFPMath(StringRef Name) {
2551 if (Name == "387") {
2555 if (Name == "sse") {
2562 bool X86TargetInfo::initFeatureMap(
2563 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2564 const std::vector<std::string> &FeaturesVec) const {
2565 // FIXME: This *really* should not be here.
2566 // X86_64 always has SSE2.
2567 if (getTriple().getArch() == llvm::Triple::x86_64)
2568 setFeatureEnabledImpl(Features, "sse2", true);
2570 switch (getCPUKind(CPU)) {
2583 setFeatureEnabledImpl(Features, "mmx", true);
2588 setFeatureEnabledImpl(Features, "sse", true);
2589 setFeatureEnabledImpl(Features, "fxsr", true);
2595 setFeatureEnabledImpl(Features, "sse2", true);
2596 setFeatureEnabledImpl(Features, "fxsr", true);
2601 setFeatureEnabledImpl(Features, "sse3", true);
2602 setFeatureEnabledImpl(Features, "fxsr", true);
2603 setFeatureEnabledImpl(Features, "cx16", true);
2607 setFeatureEnabledImpl(Features, "ssse3", true);
2608 setFeatureEnabledImpl(Features, "fxsr", true);
2609 setFeatureEnabledImpl(Features, "cx16", true);
2612 setFeatureEnabledImpl(Features, "sse4.1", true);
2613 setFeatureEnabledImpl(Features, "fxsr", true);
2614 setFeatureEnabledImpl(Features, "cx16", true);
2617 setFeatureEnabledImpl(Features, "avx512f", true);
2618 setFeatureEnabledImpl(Features, "avx512cd", true);
2619 setFeatureEnabledImpl(Features, "avx512dq", true);
2620 setFeatureEnabledImpl(Features, "avx512bw", true);
2621 setFeatureEnabledImpl(Features, "avx512vl", true);
2622 setFeatureEnabledImpl(Features, "xsavec", true);
2623 setFeatureEnabledImpl(Features, "xsaves", true);
2624 setFeatureEnabledImpl(Features, "pku", true);
2627 setFeatureEnabledImpl(Features, "rdseed", true);
2628 setFeatureEnabledImpl(Features, "adx", true);
2631 setFeatureEnabledImpl(Features, "avx2", true);
2632 setFeatureEnabledImpl(Features, "lzcnt", true);
2633 setFeatureEnabledImpl(Features, "bmi", true);
2634 setFeatureEnabledImpl(Features, "bmi2", true);
2635 setFeatureEnabledImpl(Features, "rtm", true);
2636 setFeatureEnabledImpl(Features, "fma", true);
2639 setFeatureEnabledImpl(Features, "rdrnd", true);
2640 setFeatureEnabledImpl(Features, "f16c", true);
2641 setFeatureEnabledImpl(Features, "fsgsbase", true);
2643 case CK_SandyBridge:
2644 setFeatureEnabledImpl(Features, "avx", true);
2645 setFeatureEnabledImpl(Features, "xsave", true);
2646 setFeatureEnabledImpl(Features, "xsaveopt", true);
2650 setFeatureEnabledImpl(Features, "aes", true);
2651 setFeatureEnabledImpl(Features, "pclmul", true);
2654 setFeatureEnabledImpl(Features, "sse4.2", true);
2655 setFeatureEnabledImpl(Features, "fxsr", true);
2656 setFeatureEnabledImpl(Features, "cx16", true);
2659 setFeatureEnabledImpl(Features, "avx512f", true);
2660 setFeatureEnabledImpl(Features, "avx512cd", true);
2661 setFeatureEnabledImpl(Features, "avx512er", true);
2662 setFeatureEnabledImpl(Features, "avx512pf", true);
2663 setFeatureEnabledImpl(Features, "fxsr", true);
2664 setFeatureEnabledImpl(Features, "rdseed", true);
2665 setFeatureEnabledImpl(Features, "adx", true);
2666 setFeatureEnabledImpl(Features, "lzcnt", true);
2667 setFeatureEnabledImpl(Features, "bmi", true);
2668 setFeatureEnabledImpl(Features, "bmi2", true);
2669 setFeatureEnabledImpl(Features, "rtm", true);
2670 setFeatureEnabledImpl(Features, "fma", true);
2671 setFeatureEnabledImpl(Features, "rdrnd", true);
2672 setFeatureEnabledImpl(Features, "f16c", true);
2673 setFeatureEnabledImpl(Features, "fsgsbase", true);
2674 setFeatureEnabledImpl(Features, "aes", true);
2675 setFeatureEnabledImpl(Features, "pclmul", true);
2676 setFeatureEnabledImpl(Features, "cx16", true);
2677 setFeatureEnabledImpl(Features, "xsaveopt", true);
2678 setFeatureEnabledImpl(Features, "xsave", true);
2684 setFeatureEnabledImpl(Features, "3dnow", true);
2687 case CK_AthlonThunderbird:
2689 setFeatureEnabledImpl(Features, "3dnowa", true);
2694 setFeatureEnabledImpl(Features, "sse", true);
2695 setFeatureEnabledImpl(Features, "3dnowa", true);
2696 setFeatureEnabledImpl(Features, "fxsr", true);
2702 setFeatureEnabledImpl(Features, "sse2", true);
2703 setFeatureEnabledImpl(Features, "3dnowa", true);
2704 setFeatureEnabledImpl(Features, "fxsr", true);
2707 setFeatureEnabledImpl(Features, "sse4a", true);
2708 setFeatureEnabledImpl(Features, "lzcnt", true);
2709 setFeatureEnabledImpl(Features, "popcnt", true);
2712 case CK_OpteronSSE3:
2713 case CK_Athlon64SSE3:
2714 setFeatureEnabledImpl(Features, "sse3", true);
2715 setFeatureEnabledImpl(Features, "3dnowa", true);
2716 setFeatureEnabledImpl(Features, "fxsr", true);
2719 setFeatureEnabledImpl(Features, "avx", true);
2720 setFeatureEnabledImpl(Features, "aes", true);
2721 setFeatureEnabledImpl(Features, "pclmul", true);
2722 setFeatureEnabledImpl(Features, "bmi", true);
2723 setFeatureEnabledImpl(Features, "f16c", true);
2724 setFeatureEnabledImpl(Features, "xsaveopt", true);
2727 setFeatureEnabledImpl(Features, "ssse3", true);
2728 setFeatureEnabledImpl(Features, "sse4a", true);
2729 setFeatureEnabledImpl(Features, "lzcnt", true);
2730 setFeatureEnabledImpl(Features, "popcnt", true);
2731 setFeatureEnabledImpl(Features, "prfchw", true);
2732 setFeatureEnabledImpl(Features, "cx16", true);
2733 setFeatureEnabledImpl(Features, "fxsr", true);
2734 setFeatureEnabledImpl(Features, "xsave", true);
2737 setFeatureEnabledImpl(Features, "avx2", true);
2738 setFeatureEnabledImpl(Features, "bmi2", true);
2741 setFeatureEnabledImpl(Features, "fsgsbase", true);
2742 setFeatureEnabledImpl(Features, "xsaveopt", true);
2745 setFeatureEnabledImpl(Features, "bmi", true);
2746 setFeatureEnabledImpl(Features, "fma", true);
2747 setFeatureEnabledImpl(Features, "f16c", true);
2748 setFeatureEnabledImpl(Features, "tbm", true);
2751 // xop implies avx, sse4a and fma4.
2752 setFeatureEnabledImpl(Features, "xop", true);
2753 setFeatureEnabledImpl(Features, "lzcnt", true);
2754 setFeatureEnabledImpl(Features, "aes", true);
2755 setFeatureEnabledImpl(Features, "pclmul", true);
2756 setFeatureEnabledImpl(Features, "prfchw", true);
2757 setFeatureEnabledImpl(Features, "cx16", true);
2758 setFeatureEnabledImpl(Features, "fxsr", true);
2759 setFeatureEnabledImpl(Features, "xsave", true);
2762 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
2765 // Can't do this earlier because we need to be able to explicitly enable
2766 // or disable these features and the things that they depend upon.
2768 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2769 auto I = Features.find("sse4.2");
2770 if (I != Features.end() && I->getValue() &&
2771 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
2773 Features["popcnt"] = true;
2775 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2776 I = Features.find("3dnow");
2777 if (I != Features.end() && I->getValue() &&
2778 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
2780 Features["prfchw"] = true;
2782 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2784 I = Features.find("sse");
2785 if (I != Features.end() && I->getValue() &&
2786 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
2788 Features["mmx"] = true;
2793 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2794 X86SSEEnum Level, bool Enabled) {
2798 Features["avx512f"] = true;
2800 Features["avx2"] = true;
2802 Features["avx"] = true;
2803 Features["xsave"] = true;
2805 Features["sse4.2"] = true;
2807 Features["sse4.1"] = true;
2809 Features["ssse3"] = true;
2811 Features["sse3"] = true;
2813 Features["sse2"] = true;
2815 Features["sse"] = true;
2825 Features["sse"] = false;
2827 Features["sse2"] = Features["pclmul"] = Features["aes"] =
2828 Features["sha"] = false;
2830 Features["sse3"] = false;
2831 setXOPLevel(Features, NoXOP, false);
2833 Features["ssse3"] = false;
2835 Features["sse4.1"] = false;
2837 Features["sse4.2"] = false;
2839 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
2840 Features["xsaveopt"] = false;
2841 setXOPLevel(Features, FMA4, false);
2843 Features["avx2"] = false;
2845 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2846 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2847 Features["avx512vl"] = false;
2851 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2852 MMX3DNowEnum Level, bool Enabled) {
2855 case AMD3DNowAthlon:
2856 Features["3dnowa"] = true;
2858 Features["3dnow"] = true;
2860 Features["mmx"] = true;
2870 Features["mmx"] = false;
2872 Features["3dnow"] = false;
2873 case AMD3DNowAthlon:
2874 Features["3dnowa"] = false;
2878 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2883 Features["xop"] = true;
2885 Features["fma4"] = true;
2886 setSSELevel(Features, AVX, true);
2888 Features["sse4a"] = true;
2889 setSSELevel(Features, SSE3, true);
2899 Features["sse4a"] = false;
2901 Features["fma4"] = false;
2903 Features["xop"] = false;
2907 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2908 StringRef Name, bool Enabled) {
2909 // This is a bit of a hack to deal with the sse4 target feature when used
2910 // as part of the target attribute. We handle sse4 correctly everywhere
2911 // else. See below for more information on how we handle the sse4 options.
2913 Features[Name] = Enabled;
2915 if (Name == "mmx") {
2916 setMMXLevel(Features, MMX, Enabled);
2917 } else if (Name == "sse") {
2918 setSSELevel(Features, SSE1, Enabled);
2919 } else if (Name == "sse2") {
2920 setSSELevel(Features, SSE2, Enabled);
2921 } else if (Name == "sse3") {
2922 setSSELevel(Features, SSE3, Enabled);
2923 } else if (Name == "ssse3") {
2924 setSSELevel(Features, SSSE3, Enabled);
2925 } else if (Name == "sse4.2") {
2926 setSSELevel(Features, SSE42, Enabled);
2927 } else if (Name == "sse4.1") {
2928 setSSELevel(Features, SSE41, Enabled);
2929 } else if (Name == "3dnow") {
2930 setMMXLevel(Features, AMD3DNow, Enabled);
2931 } else if (Name == "3dnowa") {
2932 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2933 } else if (Name == "aes") {
2935 setSSELevel(Features, SSE2, Enabled);
2936 } else if (Name == "pclmul") {
2938 setSSELevel(Features, SSE2, Enabled);
2939 } else if (Name == "avx") {
2940 setSSELevel(Features, AVX, Enabled);
2941 } else if (Name == "avx2") {
2942 setSSELevel(Features, AVX2, Enabled);
2943 } else if (Name == "avx512f") {
2944 setSSELevel(Features, AVX512F, Enabled);
2945 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2946 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2948 setSSELevel(Features, AVX512F, Enabled);
2949 } else if (Name == "fma") {
2951 setSSELevel(Features, AVX, Enabled);
2952 } else if (Name == "fma4") {
2953 setXOPLevel(Features, FMA4, Enabled);
2954 } else if (Name == "xop") {
2955 setXOPLevel(Features, XOP, Enabled);
2956 } else if (Name == "sse4a") {
2957 setXOPLevel(Features, SSE4A, Enabled);
2958 } else if (Name == "f16c") {
2960 setSSELevel(Features, AVX, Enabled);
2961 } else if (Name == "sha") {
2963 setSSELevel(Features, SSE2, Enabled);
2964 } else if (Name == "sse4") {
2965 // We can get here via the __target__ attribute since that's not controlled
2966 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2967 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2970 setSSELevel(Features, SSE42, Enabled);
2972 setSSELevel(Features, SSE41, Enabled);
2973 } else if (Name == "xsave") {
2975 setSSELevel(Features, AVX, Enabled);
2977 Features["xsaveopt"] = false;
2978 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
2980 Features["xsave"] = true;
2981 setSSELevel(Features, AVX, Enabled);
2986 /// handleTargetFeatures - Perform initialization based on the user
2987 /// configured set of features.
2988 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2989 DiagnosticsEngine &Diags) {
2990 for (const auto &Feature : Features) {
2991 if (Feature[0] != '+')
2994 if (Feature == "+aes") {
2996 } else if (Feature == "+pclmul") {
2998 } else if (Feature == "+lzcnt") {
3000 } else if (Feature == "+rdrnd") {
3002 } else if (Feature == "+fsgsbase") {
3004 } else if (Feature == "+bmi") {
3006 } else if (Feature == "+bmi2") {
3008 } else if (Feature == "+popcnt") {
3010 } else if (Feature == "+rtm") {
3012 } else if (Feature == "+prfchw") {
3014 } else if (Feature == "+rdseed") {
3016 } else if (Feature == "+adx") {
3018 } else if (Feature == "+tbm") {
3020 } else if (Feature == "+fma") {
3022 } else if (Feature == "+f16c") {
3024 } else if (Feature == "+avx512cd") {
3026 } else if (Feature == "+avx512er") {
3028 } else if (Feature == "+avx512pf") {
3030 } else if (Feature == "+avx512dq") {
3032 } else if (Feature == "+avx512bw") {
3034 } else if (Feature == "+avx512vl") {
3036 } else if (Feature == "+sha") {
3038 } else if (Feature == "+cx16") {
3040 } else if (Feature == "+fxsr") {
3042 } else if (Feature == "+xsave") {
3044 } else if (Feature == "+xsaveopt") {
3046 } else if (Feature == "+xsavec") {
3048 } else if (Feature == "+xsaves") {
3050 } else if (Feature == "+pku") {
3054 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3055 .Case("+avx512f", AVX512F)
3056 .Case("+avx2", AVX2)
3058 .Case("+sse4.2", SSE42)
3059 .Case("+sse4.1", SSE41)
3060 .Case("+ssse3", SSSE3)
3061 .Case("+sse3", SSE3)
3062 .Case("+sse2", SSE2)
3065 SSELevel = std::max(SSELevel, Level);
3067 MMX3DNowEnum ThreeDNowLevel =
3068 llvm::StringSwitch<MMX3DNowEnum>(Feature)
3069 .Case("+3dnowa", AMD3DNowAthlon)
3070 .Case("+3dnow", AMD3DNow)
3072 .Default(NoMMX3DNow);
3073 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3075 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3077 .Case("+fma4", FMA4)
3078 .Case("+sse4a", SSE4A)
3080 XOPLevel = std::max(XOPLevel, XLevel);
3083 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3084 // matches the selected sse level.
3085 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3086 (FPMath == FP_387 && SSELevel >= SSE1)) {
3087 Diags.Report(diag::err_target_unsupported_fpmath) <<
3088 (FPMath == FP_SSE ? "sse" : "387");
3093 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3097 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3098 /// definitions for this particular subtarget.
3099 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3100 MacroBuilder &Builder) const {
3101 // Target identification.
3102 if (getTriple().getArch() == llvm::Triple::x86_64) {
3103 Builder.defineMacro("__amd64__");
3104 Builder.defineMacro("__amd64");
3105 Builder.defineMacro("__x86_64");
3106 Builder.defineMacro("__x86_64__");
3107 if (getTriple().getArchName() == "x86_64h") {
3108 Builder.defineMacro("__x86_64h");
3109 Builder.defineMacro("__x86_64h__");
3112 DefineStd(Builder, "i386", Opts);
3115 // Subtarget options.
3116 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3117 // truly should be based on -mtune options.
3122 // The rest are coming from the i386 define above.
3123 Builder.defineMacro("__tune_i386__");
3129 defineCPUMacros(Builder, "i486");
3132 Builder.defineMacro("__pentium_mmx__");
3133 Builder.defineMacro("__tune_pentium_mmx__");
3137 defineCPUMacros(Builder, "i586");
3138 defineCPUMacros(Builder, "pentium");
3143 Builder.defineMacro("__tune_pentium3__");
3147 Builder.defineMacro("__tune_pentium2__");
3150 Builder.defineMacro("__tune_i686__");
3151 Builder.defineMacro("__tune_pentiumpro__");
3154 Builder.defineMacro("__i686");
3155 Builder.defineMacro("__i686__");
3156 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3157 Builder.defineMacro("__pentiumpro");
3158 Builder.defineMacro("__pentiumpro__");
3162 defineCPUMacros(Builder, "pentium4");
3167 defineCPUMacros(Builder, "nocona");
3171 defineCPUMacros(Builder, "core2");
3174 defineCPUMacros(Builder, "atom");
3177 defineCPUMacros(Builder, "slm");
3181 case CK_SandyBridge:
3185 // FIXME: Historically, we defined this legacy name, it would be nice to
3186 // remove it at some point. We've never exposed fine-grained names for
3187 // recent primary x86 CPUs, and we should keep it that way.
3188 defineCPUMacros(Builder, "corei7");
3191 // FIXME: Historically, we defined this legacy name, it would be nice to
3192 // remove it at some point. This is the only fine-grained CPU macro in the
3193 // main intel CPU line, and it would be better to not have these and force
3194 // people to use ISA macros.
3195 defineCPUMacros(Builder, "skx");
3198 defineCPUMacros(Builder, "knl");
3201 Builder.defineMacro("__k6_2__");
3202 Builder.defineMacro("__tune_k6_2__");
3205 if (CPU != CK_K6_2) { // In case of fallthrough
3206 // FIXME: GCC may be enabling these in cases where some other k6
3207 // architecture is specified but -m3dnow is explicitly provided. The
3208 // exact semantics need to be determined and emulated here.
3209 Builder.defineMacro("__k6_3__");
3210 Builder.defineMacro("__tune_k6_3__");
3214 defineCPUMacros(Builder, "k6");
3217 case CK_AthlonThunderbird:
3221 defineCPUMacros(Builder, "athlon");
3222 if (SSELevel != NoSSE) {
3223 Builder.defineMacro("__athlon_sse__");
3224 Builder.defineMacro("__tune_athlon_sse__");
3231 case CK_OpteronSSE3:
3233 case CK_Athlon64SSE3:
3235 defineCPUMacros(Builder, "k8");
3238 defineCPUMacros(Builder, "amdfam10");
3241 defineCPUMacros(Builder, "btver1");
3244 defineCPUMacros(Builder, "btver2");
3247 defineCPUMacros(Builder, "bdver1");
3250 defineCPUMacros(Builder, "bdver2");
3253 defineCPUMacros(Builder, "bdver3");
3256 defineCPUMacros(Builder, "bdver4");
3259 defineCPUMacros(Builder, "geode");
3263 // Target properties.
3264 Builder.defineMacro("__REGISTER_PREFIX__", "");
3266 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3267 // functions in glibc header files that use FP Stack inline asm which the
3268 // backend can't deal with (PR879).
3269 Builder.defineMacro("__NO_MATH_INLINES");
3272 Builder.defineMacro("__AES__");
3275 Builder.defineMacro("__PCLMUL__");
3278 Builder.defineMacro("__LZCNT__");
3281 Builder.defineMacro("__RDRND__");
3284 Builder.defineMacro("__FSGSBASE__");
3287 Builder.defineMacro("__BMI__");
3290 Builder.defineMacro("__BMI2__");
3293 Builder.defineMacro("__POPCNT__");
3296 Builder.defineMacro("__RTM__");
3299 Builder.defineMacro("__PRFCHW__");
3302 Builder.defineMacro("__RDSEED__");
3305 Builder.defineMacro("__ADX__");
3308 Builder.defineMacro("__TBM__");
3312 Builder.defineMacro("__XOP__");
3314 Builder.defineMacro("__FMA4__");
3316 Builder.defineMacro("__SSE4A__");
3322 Builder.defineMacro("__FMA__");
3325 Builder.defineMacro("__F16C__");
3328 Builder.defineMacro("__AVX512CD__");
3330 Builder.defineMacro("__AVX512ER__");
3332 Builder.defineMacro("__AVX512PF__");
3334 Builder.defineMacro("__AVX512DQ__");
3336 Builder.defineMacro("__AVX512BW__");
3338 Builder.defineMacro("__AVX512VL__");
3341 Builder.defineMacro("__SHA__");
3344 Builder.defineMacro("__FXSR__");
3346 Builder.defineMacro("__XSAVE__");
3348 Builder.defineMacro("__XSAVEOPT__");
3350 Builder.defineMacro("__XSAVEC__");
3352 Builder.defineMacro("__XSAVES__");
3354 Builder.defineMacro("__PKU__");
3356 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3358 // Each case falls through to the previous one here.
3361 Builder.defineMacro("__AVX512F__");
3363 Builder.defineMacro("__AVX2__");
3365 Builder.defineMacro("__AVX__");
3367 Builder.defineMacro("__SSE4_2__");
3369 Builder.defineMacro("__SSE4_1__");
3371 Builder.defineMacro("__SSSE3__");
3373 Builder.defineMacro("__SSE3__");
3375 Builder.defineMacro("__SSE2__");
3376 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
3378 Builder.defineMacro("__SSE__");
3379 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
3384 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3394 Builder.defineMacro("_M_IX86_FP", Twine(2));
3397 Builder.defineMacro("_M_IX86_FP", Twine(1));
3400 Builder.defineMacro("_M_IX86_FP", Twine(0));
3404 // Each case falls through to the previous one here.
3405 switch (MMX3DNowLevel) {
3406 case AMD3DNowAthlon:
3407 Builder.defineMacro("__3dNOW_A__");
3409 Builder.defineMacro("__3dNOW__");
3411 Builder.defineMacro("__MMX__");
3416 if (CPU >= CK_i486) {
3417 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3418 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3419 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3422 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3425 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3426 return llvm::StringSwitch<bool>(Feature)
3427 .Case("aes", HasAES)
3428 .Case("avx", SSELevel >= AVX)
3429 .Case("avx2", SSELevel >= AVX2)
3430 .Case("avx512f", SSELevel >= AVX512F)
3431 .Case("avx512cd", HasAVX512CD)
3432 .Case("avx512er", HasAVX512ER)
3433 .Case("avx512pf", HasAVX512PF)
3434 .Case("avx512dq", HasAVX512DQ)
3435 .Case("avx512bw", HasAVX512BW)
3436 .Case("avx512vl", HasAVX512VL)
3437 .Case("bmi", HasBMI)
3438 .Case("bmi2", HasBMI2)
3439 .Case("cx16", HasCX16)
3440 .Case("f16c", HasF16C)
3441 .Case("fma", HasFMA)
3442 .Case("fma4", XOPLevel >= FMA4)
3443 .Case("fsgsbase", HasFSGSBASE)
3444 .Case("fxsr", HasFXSR)
3445 .Case("lzcnt", HasLZCNT)
3446 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3447 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3448 .Case("mmx", MMX3DNowLevel >= MMX)
3449 .Case("pclmul", HasPCLMUL)
3450 .Case("popcnt", HasPOPCNT)
3451 .Case("prfchw", HasPRFCHW)
3452 .Case("rdrnd", HasRDRND)
3453 .Case("rdseed", HasRDSEED)
3454 .Case("rtm", HasRTM)
3455 .Case("sha", HasSHA)
3456 .Case("sse", SSELevel >= SSE1)
3457 .Case("sse2", SSELevel >= SSE2)
3458 .Case("sse3", SSELevel >= SSE3)
3459 .Case("ssse3", SSELevel >= SSSE3)
3460 .Case("sse4.1", SSELevel >= SSE41)
3461 .Case("sse4.2", SSELevel >= SSE42)
3462 .Case("sse4a", XOPLevel >= SSE4A)
3463 .Case("tbm", HasTBM)
3465 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3466 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3467 .Case("xop", XOPLevel >= XOP)
3468 .Case("xsave", HasXSAVE)
3469 .Case("xsavec", HasXSAVEC)
3470 .Case("xsaves", HasXSAVES)
3471 .Case("xsaveopt", HasXSAVEOPT)
3472 .Case("pku", HasPKU)
3476 // We can't use a generic validation scheme for the features accepted here
3477 // versus subtarget features accepted in the target attribute because the
3478 // bitfield structure that's initialized in the runtime only supports the
3479 // below currently rather than the full range of subtarget features. (See
3480 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3481 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3482 return llvm::StringSwitch<bool>(FeatureStr)
3485 .Case("popcnt", true)
3489 .Case("sse4.1", true)
3490 .Case("sse4.2", true)
3493 .Case("sse4a", true)
3497 .Case("avx512f", true)
3504 X86TargetInfo::validateAsmConstraint(const char *&Name,
3505 TargetInfo::ConstraintInfo &Info) const {
3507 default: return false;
3508 // Constant constraints.
3509 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
3511 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3512 // x86_64 instructions.
3514 Info.setRequiresImmediate();
3517 Info.setRequiresImmediate(0, 31);
3520 Info.setRequiresImmediate(0, 63);
3523 Info.setRequiresImmediate(-128, 127);
3526 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
3529 Info.setRequiresImmediate(0, 3);
3532 Info.setRequiresImmediate(0, 255);
3535 Info.setRequiresImmediate(0, 127);
3537 // Register constraints.
3538 case 'Y': // 'Y' is the first character for several 2-character constraints.
3539 // Shift the pointer to the second character of the constraint.
3544 case '0': // First SSE register.
3545 case 't': // Any SSE register, when SSE2 is enabled.
3546 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3547 case 'm': // Any MMX register, when inter-unit moves enabled.
3548 Info.setAllowsRegister();
3551 case 'f': // Any x87 floating point stack register.
3552 // Constraint 'f' cannot be used for output operands.
3553 if (Info.ConstraintStr[0] == '=')
3555 Info.setAllowsRegister();
3563 case 'A': // edx:eax.
3564 case 't': // Top of floating point stack.
3565 case 'u': // Second from top of floating point stack.
3566 case 'q': // Any register accessible as [r]l: a, b, c, and d.
3567 case 'y': // Any MMX register.
3568 case 'x': // Any SSE register.
3569 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3570 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3571 case 'l': // "Index" registers: any general register that can be used as an
3572 // index in a base+index memory access.
3573 Info.setAllowsRegister();
3575 // Floating point constant constraints.
3576 case 'C': // SSE floating point constant.
3577 case 'G': // x87 floating point constant.
3582 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3583 unsigned Size) const {
3584 // Strip off constraint modifiers.
3585 while (Constraint[0] == '=' ||
3586 Constraint[0] == '+' ||
3587 Constraint[0] == '&')
3588 Constraint = Constraint.substr(1);
3590 return validateOperandSize(Constraint, Size);
3593 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3594 unsigned Size) const {
3595 return validateOperandSize(Constraint, Size);
3598 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3599 unsigned Size) const {
3600 switch (Constraint[0]) {
3609 if (SSELevel >= AVX512F)
3610 // 512-bit zmm registers can be used if target supports AVX512F.
3611 return Size <= 512U;
3612 else if (SSELevel >= AVX)
3613 // 256-bit ymm registers can be used if target supports AVX.
3614 return Size <= 256U;
3615 return Size <= 128U;
3617 // 'Y' is the first character for several 2-character constraints.
3618 switch (Constraint[1]) {
3621 // 'Ym' is synonymous with 'y'.
3625 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
3626 if (SSELevel >= AVX512F)
3627 return Size <= 512U;
3628 else if (SSELevel >= AVX)
3629 return Size <= 256U;
3630 return SSELevel >= SSE2 && Size <= 128U;
3639 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3640 switch (*Constraint) {
3641 case 'a': return std::string("{ax}");
3642 case 'b': return std::string("{bx}");
3643 case 'c': return std::string("{cx}");
3644 case 'd': return std::string("{dx}");
3645 case 'S': return std::string("{si}");
3646 case 'D': return std::string("{di}");
3647 case 'p': // address
3648 return std::string("im");
3649 case 't': // top of floating point stack.
3650 return std::string("{st}");
3651 case 'u': // second from top of floating point stack.
3652 return std::string("{st(1)}"); // second from top of floating point stack.
3654 return std::string(1, *Constraint);
3658 // X86-32 generic target
3659 class X86_32TargetInfo : public X86TargetInfo {
3661 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3662 DoubleAlign = LongLongAlign = 32;
3663 LongDoubleWidth = 96;
3664 LongDoubleAlign = 32;
3665 SuitableAlign = 128;
3666 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3667 SizeType = UnsignedInt;
3668 PtrDiffType = SignedInt;
3669 IntPtrType = SignedInt;
3672 // Use fpret for all types.
3673 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3674 (1 << TargetInfo::Double) |
3675 (1 << TargetInfo::LongDouble));
3677 // x86-32 has atomics up to 8 bytes
3678 // FIXME: Check that we actually have cmpxchg8b before setting
3679 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3680 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3682 BuiltinVaListKind getBuiltinVaListKind() const override {
3683 return TargetInfo::CharPtrBuiltinVaList;
3686 int getEHDataRegisterNumber(unsigned RegNo) const override {
3687 if (RegNo == 0) return 0;
3688 if (RegNo == 1) return 2;
3691 bool validateOperandSize(StringRef Constraint,
3692 unsigned Size) const override {
3693 switch (Constraint[0]) {
3709 return X86TargetInfo::validateOperandSize(Constraint, Size);
3713 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3715 NetBSDI386TargetInfo(const llvm::Triple &Triple)
3716 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3718 unsigned getFloatEvalMethod() const override {
3719 unsigned Major, Minor, Micro;
3720 getTriple().getOSVersion(Major, Minor, Micro);
3721 // New NetBSD uses the default rounding mode.
3722 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3723 return X86_32TargetInfo::getFloatEvalMethod();
3724 // NetBSD before 6.99.26 defaults to "double" rounding.
3729 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3731 OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3732 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3733 SizeType = UnsignedLong;
3734 IntPtrType = SignedLong;
3735 PtrDiffType = SignedLong;
3739 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3741 BitrigI386TargetInfo(const llvm::Triple &Triple)
3742 : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3743 SizeType = UnsignedLong;
3744 IntPtrType = SignedLong;
3745 PtrDiffType = SignedLong;
3749 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3751 DarwinI386TargetInfo(const llvm::Triple &Triple)
3752 : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3753 LongDoubleWidth = 128;
3754 LongDoubleAlign = 128;
3755 SuitableAlign = 128;
3756 MaxVectorAlign = 256;
3757 // The watchOS simulator uses the builtin bool type for Objective-C.
3758 llvm::Triple T = llvm::Triple(Triple);
3760 UseSignedCharForObjCBool = false;
3761 SizeType = UnsignedLong;
3762 IntPtrType = SignedLong;
3763 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3764 HasAlignMac68kSupport = true;
3767 bool handleTargetFeatures(std::vector<std::string> &Features,
3768 DiagnosticsEngine &Diags) override {
3769 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
3772 // We now know the features we have: we can decide how to align vectors.
3774 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3779 // x86-32 Windows target
3780 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3782 WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3783 : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3784 WCharType = UnsignedShort;
3785 DoubleAlign = LongLongAlign = 64;
3787 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3788 DataLayoutString = IsWinCOFF
3789 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3790 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3792 void getTargetDefines(const LangOptions &Opts,
3793 MacroBuilder &Builder) const override {
3794 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3798 // x86-32 Windows Visual Studio target
3799 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3801 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3802 : WindowsX86_32TargetInfo(Triple) {
3803 LongDoubleWidth = LongDoubleAlign = 64;
3804 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3806 void getTargetDefines(const LangOptions &Opts,
3807 MacroBuilder &Builder) const override {
3808 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3809 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3810 // The value of the following reflects processor type.
3811 // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3812 // We lost the original triple, so we use the default.
3813 Builder.defineMacro("_M_IX86", "600");
3817 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3818 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang
3819 // supports __declspec natively under -fms-extensions, but we define a no-op
3820 // __declspec macro anyway for pre-processor compatibility.
3821 if (Opts.MicrosoftExt)
3822 Builder.defineMacro("__declspec", "__declspec");
3824 Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3826 if (!Opts.MicrosoftExt) {
3827 // Provide macros for all the calling convention keywords. Provide both
3828 // single and double underscore prefixed variants. These are available on
3829 // x64 as well as x86, even though they have no effect.
3830 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3831 for (const char *CC : CCs) {
3832 std::string GCCSpelling = "__attribute__((__";
3834 GCCSpelling += "__))";
3835 Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3836 Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3841 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3842 Builder.defineMacro("__MSVCRT__");
3843 Builder.defineMacro("__MINGW32__");
3844 addCygMingDefines(Opts, Builder);
3847 // x86-32 MinGW target
3848 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3850 MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3851 : WindowsX86_32TargetInfo(Triple) {}
3852 void getTargetDefines(const LangOptions &Opts,
3853 MacroBuilder &Builder) const override {
3854 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3855 DefineStd(Builder, "WIN32", Opts);
3856 DefineStd(Builder, "WINNT", Opts);
3857 Builder.defineMacro("_X86_");
3858 addMinGWDefines(Opts, Builder);
3862 // x86-32 Cygwin target
3863 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3865 CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3866 : X86_32TargetInfo(Triple) {
3867 WCharType = UnsignedShort;
3868 DoubleAlign = LongLongAlign = 64;
3869 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3871 void getTargetDefines(const LangOptions &Opts,
3872 MacroBuilder &Builder) const override {
3873 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3874 Builder.defineMacro("_X86_");
3875 Builder.defineMacro("__CYGWIN__");
3876 Builder.defineMacro("__CYGWIN32__");
3877 addCygMingDefines(Opts, Builder);
3878 DefineStd(Builder, "unix", Opts);
3880 Builder.defineMacro("_GNU_SOURCE");
3884 // x86-32 Haiku target
3885 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3887 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3888 SizeType = UnsignedLong;
3889 IntPtrType = SignedLong;
3890 PtrDiffType = SignedLong;
3891 ProcessIDType = SignedLong;
3892 this->UserLabelPrefix = "";
3893 this->TLSSupported = false;
3895 void getTargetDefines(const LangOptions &Opts,
3896 MacroBuilder &Builder) const override {
3897 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3898 Builder.defineMacro("__INTEL__");
3899 Builder.defineMacro("__HAIKU__");
3903 // X86-32 MCU target
3904 class MCUX86_32TargetInfo : public X86_32TargetInfo {
3906 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3907 LongDoubleWidth = 64;
3908 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3911 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3912 // On MCU we support only C calling convention.
3913 return CC == CC_C ? CCCR_OK : CCCR_Warning;
3916 void getTargetDefines(const LangOptions &Opts,
3917 MacroBuilder &Builder) const override {
3918 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3919 Builder.defineMacro("__iamcu");
3920 Builder.defineMacro("__iamcu__");
3925 template<typename Target>
3926 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3928 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3929 MacroBuilder &Builder) const override {
3930 // RTEMS defines; list based off of gcc output
3932 Builder.defineMacro("__rtems__");
3933 Builder.defineMacro("__ELF__");
3937 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3938 this->UserLabelPrefix = "";
3940 switch (Triple.getArch()) {
3942 case llvm::Triple::x86:
3943 // this->MCountName = ".mcount";
3945 case llvm::Triple::mips:
3946 case llvm::Triple::mipsel:
3947 case llvm::Triple::ppc:
3948 case llvm::Triple::ppc64:
3949 case llvm::Triple::ppc64le:
3950 // this->MCountName = "_mcount";
3952 case llvm::Triple::arm:
3953 // this->MCountName = "__mcount";
3959 // x86-32 RTEMS target
3960 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3962 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3963 SizeType = UnsignedLong;
3964 IntPtrType = SignedLong;
3965 PtrDiffType = SignedLong;
3966 this->UserLabelPrefix = "";
3968 void getTargetDefines(const LangOptions &Opts,
3969 MacroBuilder &Builder) const override {
3970 X86_32TargetInfo::getTargetDefines(Opts, Builder);
3971 Builder.defineMacro("__INTEL__");
3972 Builder.defineMacro("__rtems__");
3976 // x86-64 generic target
3977 class X86_64TargetInfo : public X86TargetInfo {
3979 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3980 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3982 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3983 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3984 LongDoubleWidth = 128;
3985 LongDoubleAlign = 128;
3986 LargeArrayMinWidth = 128;
3987 LargeArrayAlign = 128;
3988 SuitableAlign = 128;
3989 SizeType = IsX32 ? UnsignedInt : UnsignedLong;
3990 PtrDiffType = IsX32 ? SignedInt : SignedLong;
3991 IntPtrType = IsX32 ? SignedInt : SignedLong;
3992 IntMaxType = IsX32 ? SignedLongLong : SignedLong;
3993 Int64Type = IsX32 ? SignedLongLong : SignedLong;
3996 // Pointers are 32-bit in x32.
3997 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3999 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
4000 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
4002 // Use fpret only for long double.
4003 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
4005 // Use fp2ret for _Complex long double.
4006 ComplexLongDoubleUsesFP2Ret = true;
4008 // Make __builtin_ms_va_list available.
4009 HasBuiltinMSVaList = true;
4011 // x86-64 has atomics up to 16 bytes.
4012 MaxAtomicPromoteWidth = 128;
4013 MaxAtomicInlineWidth = 128;
4015 BuiltinVaListKind getBuiltinVaListKind() const override {
4016 return TargetInfo::X86_64ABIBuiltinVaList;
4019 int getEHDataRegisterNumber(unsigned RegNo) const override {
4020 if (RegNo == 0) return 0;
4021 if (RegNo == 1) return 1;
4025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4026 return (CC == CC_C ||
4027 CC == CC_X86VectorCall ||
4028 CC == CC_IntelOclBicc ||
4029 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
4032 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
4036 // for x32 we need it here explicitly
4037 bool hasInt128Type() const override { return true; }
4039 bool validateGlobalRegisterVariable(StringRef RegName,
4041 bool &HasSizeMismatch) const override {
4042 // rsp and rbp are the only 64-bit registers the x86 backend can currently
4044 if (RegName.equals("rsp") || RegName.equals("rbp")) {
4045 // Check that the register size is 64-bit.
4046 HasSizeMismatch = RegSize != 64;
4050 // Check if the register is a 32-bit register the backend can handle.
4051 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
4056 // x86-64 Windows target
4057 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
4059 WindowsX86_64TargetInfo(const llvm::Triple &Triple)
4060 : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
4061 WCharType = UnsignedShort;
4062 LongWidth = LongAlign = 32;
4063 DoubleAlign = LongLongAlign = 64;
4064 IntMaxType = SignedLongLong;
4065 Int64Type = SignedLongLong;
4066 SizeType = UnsignedLongLong;
4067 PtrDiffType = SignedLongLong;
4068 IntPtrType = SignedLongLong;
4069 this->UserLabelPrefix = "";
4072 void getTargetDefines(const LangOptions &Opts,
4073 MacroBuilder &Builder) const override {
4074 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
4075 Builder.defineMacro("_WIN64");
4078 BuiltinVaListKind getBuiltinVaListKind() const override {
4079 return TargetInfo::CharPtrBuiltinVaList;
4082 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4085 case CC_X86ThisCall:
4086 case CC_X86FastCall:
4089 case CC_X86VectorCall:
4090 case CC_IntelOclBicc:
4094 return CCCR_Warning;
4099 // x86-64 Windows Visual Studio target
4100 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4102 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
4103 : WindowsX86_64TargetInfo(Triple) {
4104 LongDoubleWidth = LongDoubleAlign = 64;
4105 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4107 void getTargetDefines(const LangOptions &Opts,
4108 MacroBuilder &Builder) const override {
4109 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4110 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4111 Builder.defineMacro("_M_X64", "100");
4112 Builder.defineMacro("_M_AMD64", "100");
4116 // x86-64 MinGW target
4117 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4119 MinGWX86_64TargetInfo(const llvm::Triple &Triple)
4120 : WindowsX86_64TargetInfo(Triple) {
4121 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4122 // with x86 FP ops. Weird.
4123 LongDoubleWidth = LongDoubleAlign = 128;
4124 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
4127 void getTargetDefines(const LangOptions &Opts,
4128 MacroBuilder &Builder) const override {
4129 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4130 DefineStd(Builder, "WIN64", Opts);
4131 Builder.defineMacro("__MINGW64__");
4132 addMinGWDefines(Opts, Builder);
4134 // GCC defines this macro when it is using __gxx_personality_seh0.
4135 if (!Opts.SjLjExceptions)
4136 Builder.defineMacro("__SEH__");
4140 // x86-64 Cygwin target
4141 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4143 CygwinX86_64TargetInfo(const llvm::Triple &Triple)
4144 : X86_64TargetInfo(Triple) {
4145 TLSSupported = false;
4146 WCharType = UnsignedShort;
4148 void getTargetDefines(const LangOptions &Opts,
4149 MacroBuilder &Builder) const override {
4150 X86_64TargetInfo::getTargetDefines(Opts, Builder);
4151 Builder.defineMacro("__x86_64__");
4152 Builder.defineMacro("__CYGWIN__");
4153 Builder.defineMacro("__CYGWIN64__");
4154 addCygMingDefines(Opts, Builder);
4155 DefineStd(Builder, "unix", Opts);
4157 Builder.defineMacro("_GNU_SOURCE");
4159 // GCC defines this macro when it is using __gxx_personality_seh0.
4160 if (!Opts.SjLjExceptions)
4161 Builder.defineMacro("__SEH__");
4165 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4167 DarwinX86_64TargetInfo(const llvm::Triple &Triple)
4168 : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
4169 Int64Type = SignedLongLong;
4170 // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4171 llvm::Triple T = llvm::Triple(Triple);
4173 UseSignedCharForObjCBool = false;
4174 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
4177 bool handleTargetFeatures(std::vector<std::string> &Features,
4178 DiagnosticsEngine &Diags) override {
4179 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4182 // We now know the features we have: we can decide how to align vectors.
4184 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4189 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4191 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
4192 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
4193 IntMaxType = SignedLongLong;
4194 Int64Type = SignedLongLong;
4198 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4200 BitrigX86_64TargetInfo(const llvm::Triple &Triple)
4201 : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
4202 IntMaxType = SignedLongLong;
4203 Int64Type = SignedLongLong;
4207 class ARMTargetInfo : public TargetInfo {
4208 // Possible FPU choices.
4217 // Possible HWDiv features.
4219 HWDivThumb = (1 << 0),
4223 static bool FPUModeIsVFP(FPUMode Mode) {
4224 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4227 static const TargetInfo::GCCRegAlias GCCRegAliases[];
4228 static const char * const GCCRegNames[];
4230 std::string ABI, CPU;
4232 StringRef CPUProfile;
4242 unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4243 unsigned ArchProfile;
4244 unsigned ArchVersion;
4248 unsigned IsAAPCS : 1;
4251 // Initialized via features.
4252 unsigned SoftFloat : 1;
4253 unsigned SoftFloatABI : 1;
4256 unsigned Crypto : 1;
4258 unsigned Unaligned : 1;
4261 LDREX_B = (1 << 0), /// byte (8-bit)
4262 LDREX_H = (1 << 1), /// half (16-bit)
4263 LDREX_W = (1 << 2), /// word (32-bit)
4264 LDREX_D = (1 << 3), /// double (64-bit)
4269 // ACLE 6.5.1 Hardware floating point
4271 HW_FP_HP = (1 << 1), /// half (16-bit)
4272 HW_FP_SP = (1 << 2), /// single (32-bit)
4273 HW_FP_DP = (1 << 3), /// double (64-bit)
4277 static const Builtin::Info BuiltinInfo[];
4279 void setABIAAPCS() {
4282 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4283 const llvm::Triple &T = getTriple();
4285 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4286 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4287 T.getOS() == llvm::Triple::Bitrig)
4288 SizeType = UnsignedLong;
4290 SizeType = UnsignedInt;
4292 switch (T.getOS()) {
4293 case llvm::Triple::NetBSD:
4294 WCharType = SignedInt;
4296 case llvm::Triple::Win32:
4297 WCharType = UnsignedShort;
4299 case llvm::Triple::Linux:
4301 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4302 WCharType = UnsignedInt;
4306 UseBitFieldTypeAlignment = true;
4308 ZeroLengthBitfieldBoundary = 0;
4310 // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4311 // so set preferred for small types to 32.
4312 if (T.isOSBinFormatMachO()) {
4314 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4315 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4316 } else if (T.isOSWindows()) {
4317 assert(!BigEndian && "Windows on ARM does not support big endian");
4318 DataLayoutString = "e"
4326 } else if (T.isOSNaCl()) {
4327 assert(!BigEndian && "NaCl on ARM does not support big endian");
4328 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4331 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4332 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4335 // FIXME: Enumerated types are variable width in straight AAPCS.
4338 void setABIAPCS(bool IsAAPCS16) {
4339 const llvm::Triple &T = getTriple();
4344 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4346 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4348 // size_t is unsigned int on FreeBSD.
4349 if (T.getOS() == llvm::Triple::FreeBSD)
4350 SizeType = UnsignedInt;
4352 SizeType = UnsignedLong;
4354 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4355 WCharType = SignedInt;
4357 // Do not respect the alignment of bit-field types when laying out
4358 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4359 UseBitFieldTypeAlignment = false;
4361 /// gcc forces the alignment to 4 bytes, regardless of the type of the
4362 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in
4364 ZeroLengthBitfieldBoundary = 32;
4366 if (T.isOSBinFormatMachO() && IsAAPCS16) {
4367 assert(!BigEndian && "AAPCS16 does not support big-endian");
4368 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128";
4369 } else if (T.isOSBinFormatMachO())
4372 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4373 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4377 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4378 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4380 // FIXME: Override "preferred align" for double and long long.
4383 void setArchInfo() {
4384 StringRef ArchName = getTriple().getArchName();
4386 ArchISA = llvm::ARM::parseArchISA(ArchName);
4387 CPU = llvm::ARM::getDefaultCPU(ArchName);
4388 unsigned AK = llvm::ARM::parseArch(ArchName);
4389 if (AK != llvm::ARM::AK_INVALID)
4391 setArchInfo(ArchKind);
4394 void setArchInfo(unsigned Kind) {
4397 // cache TargetParser info
4399 SubArch = llvm::ARM::getSubArch(ArchKind);
4400 ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4401 ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4403 // cache CPU related strings
4404 CPUAttr = getCPUAttr();
4405 CPUProfile = getCPUProfile();
4409 // when triple does not specify a sub arch,
4410 // then we are not using inline atomics
4411 bool ShouldUseInlineAtomic =
4412 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) ||
4413 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4414 // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4415 if (ArchProfile == llvm::ARM::PK_M) {
4416 MaxAtomicPromoteWidth = 32;
4417 if (ShouldUseInlineAtomic)
4418 MaxAtomicInlineWidth = 32;
4421 MaxAtomicPromoteWidth = 64;
4422 if (ShouldUseInlineAtomic)
4423 MaxAtomicInlineWidth = 64;
4427 bool isThumb() const {
4428 return (ArchISA == llvm::ARM::IK_THUMB);
4431 bool supportsThumb() const {
4432 return CPUAttr.count('T') || ArchVersion >= 6;
4435 bool supportsThumb2() const {
4436 return CPUAttr.equals("6T2") || ArchVersion >= 7;
4439 StringRef getCPUAttr() const {
4440 // For most sub-arches, the build attribute CPU name is enough.
4441 // For Cortex variants, it's slightly different.
4444 return llvm::ARM::getCPUAttr(ArchKind);
4445 case llvm::ARM::AK_ARMV6M:
4447 case llvm::ARM::AK_ARMV7S:
4449 case llvm::ARM::AK_ARMV7A:
4451 case llvm::ARM::AK_ARMV7R:
4453 case llvm::ARM::AK_ARMV7M:
4455 case llvm::ARM::AK_ARMV7EM:
4457 case llvm::ARM::AK_ARMV8A:
4459 case llvm::ARM::AK_ARMV8_1A:
4464 StringRef getCPUProfile() const {
4465 switch(ArchProfile) {
4466 case llvm::ARM::PK_A:
4468 case llvm::ARM::PK_R:
4470 case llvm::ARM::PK_M:
4478 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4479 : TargetInfo(Triple), FPMath(FP_Default),
4480 IsAAPCS(true), LDREX(0), HW_FP(0) {
4481 BigEndian = IsBigEndian;
4483 switch (getTriple().getOS()) {
4484 case llvm::Triple::NetBSD:
4485 PtrDiffType = SignedLong;
4488 PtrDiffType = SignedInt;
4492 // Cache arch related info.
4495 // {} in inline assembly are neon specifiers, not assembly variant
4497 NoAsmVariants = true;
4499 // FIXME: This duplicates code from the driver that sets the -target-abi
4500 // option - this code is used if -target-abi isn't passed and should
4501 // be unified in some way.
4502 if (Triple.isOSBinFormatMachO()) {
4503 // The backend is hardwired to assume AAPCS for M-class processors, ensure
4504 // the frontend matches that.
4505 if (Triple.getEnvironment() == llvm::Triple::EABI ||
4506 Triple.getOS() == llvm::Triple::UnknownOS ||
4507 StringRef(CPU).startswith("cortex-m")) {
4509 } else if (Triple.isWatchOS()) {
4514 } else if (Triple.isOSWindows()) {
4515 // FIXME: this is invalid for WindowsCE
4518 // Select the default based on the platform.
4519 switch (Triple.getEnvironment()) {
4520 case llvm::Triple::Android:
4521 case llvm::Triple::GNUEABI:
4522 case llvm::Triple::GNUEABIHF:
4523 setABI("aapcs-linux");
4525 case llvm::Triple::EABIHF:
4526 case llvm::Triple::EABI:
4529 case llvm::Triple::GNU:
4533 if (Triple.getOS() == llvm::Triple::NetBSD)
4541 // ARM targets default to using the ARM C++ ABI.
4542 TheCXXABI.set(TargetCXXABI::GenericARM);
4544 // ARM has atomics up to 8 bytes
4547 // Do force alignment of members that follow zero length bitfields. If
4548 // the alignment of the zero-length bitfield is greater than the member
4549 // that follows it, `bar', `bar' will be aligned as the type of the
4550 // zero length bitfield.
4551 UseZeroLengthBitfieldAlignment = true;
4554 StringRef getABI() const override { return ABI; }
4556 bool setABI(const std::string &Name) override {
4559 // The defaults (above) are for AAPCS, check if we need to change them.
4561 // FIXME: We need support for -meabi... we could just mangle it into the
4563 if (Name == "apcs-gnu" || Name == "aapcs16") {
4564 setABIAPCS(Name == "aapcs16");
4567 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4574 // FIXME: This should be based on Arch attributes, not CPU names.
4576 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
4578 const std::vector<std::string> &FeaturesVec) const override {
4580 std::vector<const char*> TargetFeatures;
4581 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
4583 // get default FPU features
4584 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
4585 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
4587 // get default Extension features
4588 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
4589 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
4591 for (const char *Feature : TargetFeatures)
4592 if (Feature[0] == '+')
4593 Features[Feature+1] = true;
4595 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
4598 bool handleTargetFeatures(std::vector<std::string> &Features,
4599 DiagnosticsEngine &Diags) override {
4605 SoftFloat = SoftFloatABI = false;
4608 // This does not diagnose illegal cases like having both
4609 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4610 uint32_t HW_FP_remove = 0;
4611 for (const auto &Feature : Features) {
4612 if (Feature == "+soft-float") {
4614 } else if (Feature == "+soft-float-abi") {
4615 SoftFloatABI = true;
4616 } else if (Feature == "+vfp2") {
4618 HW_FP |= HW_FP_SP | HW_FP_DP;
4619 } else if (Feature == "+vfp3") {
4621 HW_FP |= HW_FP_SP | HW_FP_DP;
4622 } else if (Feature == "+vfp4") {
4624 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4625 } else if (Feature == "+fp-armv8") {
4627 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4628 } else if (Feature == "+neon") {
4630 HW_FP |= HW_FP_SP | HW_FP_DP;
4631 } else if (Feature == "+hwdiv") {
4632 HWDiv |= HWDivThumb;
4633 } else if (Feature == "+hwdiv-arm") {
4635 } else if (Feature == "+crc") {
4637 } else if (Feature == "+crypto") {
4639 } else if (Feature == "+dsp") {
4641 } else if (Feature == "+fp-only-sp") {
4642 HW_FP_remove |= HW_FP_DP;
4643 } else if (Feature == "+strict-align") {
4645 } else if (Feature == "+fp16") {
4649 HW_FP &= ~HW_FP_remove;
4651 switch (ArchVersion) {
4653 if (ArchProfile == llvm::ARM::PK_M)
4655 else if (ArchKind == llvm::ARM::AK_ARMV6K)
4656 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4661 if (ArchProfile == llvm::ARM::PK_M)
4662 LDREX = LDREX_W | LDREX_H | LDREX_B ;
4664 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4667 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4670 if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4671 Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4675 if (FPMath == FP_Neon)
4676 Features.push_back("+neonfp");
4677 else if (FPMath == FP_VFP)
4678 Features.push_back("-neonfp");
4680 // Remove front-end specific options which the backend handles differently.
4682 std::find(Features.begin(), Features.end(), "+soft-float-abi");
4683 if (Feature != Features.end())
4684 Features.erase(Feature);
4689 bool hasFeature(StringRef Feature) const override {
4690 return llvm::StringSwitch<bool>(Feature)
4692 .Case("aarch32", true)
4693 .Case("softfloat", SoftFloat)
4694 .Case("thumb", isThumb())
4695 .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4696 .Case("hwdiv", HWDiv & HWDivThumb)
4697 .Case("hwdiv-arm", HWDiv & HWDivARM)
4701 bool setCPU(const std::string &Name) override {
4702 if (Name != "generic")
4703 setArchInfo(llvm::ARM::parseCPUArch(Name));
4705 if (ArchKind == llvm::ARM::AK_INVALID)
4712 bool setFPMath(StringRef Name) override;
4714 void getTargetDefines(const LangOptions &Opts,
4715 MacroBuilder &Builder) const override {
4716 // Target identification.
4717 Builder.defineMacro("__arm");
4718 Builder.defineMacro("__arm__");
4720 // Target properties.
4721 Builder.defineMacro("__REGISTER_PREFIX__", "");
4723 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
4724 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
4725 if (getTriple().isWatchOS())
4726 Builder.defineMacro("__ARM_ARCH_7K__", "2");
4728 if (!CPUAttr.empty())
4729 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
4731 // ACLE 6.4.1 ARM/Thumb instruction set architecture
4732 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4733 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion));
4735 if (ArchVersion >= 8) {
4736 // ACLE 6.5.7 Crypto Extension
4738 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
4739 // ACLE 6.5.8 CRC32 Extension
4741 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
4742 // ACLE 6.5.10 Numeric Maximum and Minimum
4743 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
4744 // ACLE 6.5.9 Directed Rounding
4745 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
4748 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
4749 // is not defined for the M-profile.
4750 // NOTE that the deffault profile is assumed to be 'A'
4751 if (CPUProfile.empty() || CPUProfile != "M")
4752 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4754 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4755 // Thumb ISA (including v6-M). It is set to 2 if the core supports the
4756 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4757 if (supportsThumb2())
4758 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4759 else if (supportsThumb())
4760 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4762 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4763 // instruction set such as ARM or Thumb.
4764 Builder.defineMacro("__ARM_32BIT_STATE", "1");
4766 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4768 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4769 if (!CPUProfile.empty())
4770 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4772 // ACLE 6.4.3 Unaligned access supported in hardware
4774 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
4776 // ACLE 6.4.4 LDREX/STREX
4778 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
4781 if (ArchVersion == 5 ||
4782 (ArchVersion == 6 && CPUProfile != "M") ||
4784 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
4786 // ACLE 6.5.1 Hardware Floating Point
4788 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4791 Builder.defineMacro("__ARM_ACLE", "200");
4793 // FP16 support (we currently only support IEEE format).
4794 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
4795 Builder.defineMacro("__ARM_FP16_ARGS", "1");
4797 // ACLE 6.5.3 Fused multiply-accumulate (FMA)
4798 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM"))
4799 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
4801 // Subtarget options.
4803 // FIXME: It's more complicated than this and we don't really support
4805 // Windows on ARM does not "support" interworking
4806 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
4807 Builder.defineMacro("__THUMB_INTERWORK__");
4809 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4810 // Embedded targets on Darwin follow AAPCS, but not EABI.
4811 // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4812 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4813 Builder.defineMacro("__ARM_EABI__");
4814 Builder.defineMacro("__ARM_PCS", "1");
4816 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4817 Builder.defineMacro("__ARM_PCS_VFP", "1");
4821 Builder.defineMacro("__SOFTFP__");
4823 if (CPU == "xscale")
4824 Builder.defineMacro("__XSCALE__");
4827 Builder.defineMacro("__THUMBEL__");
4828 Builder.defineMacro("__thumb__");
4829 if (supportsThumb2())
4830 Builder.defineMacro("__thumb2__");
4833 // ACLE 6.4.9 32-bit SIMD instructions
4834 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
4835 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
4837 // ACLE 6.4.10 Hardware Integer Divide
4838 if (((HWDiv & HWDivThumb) && isThumb()) ||
4839 ((HWDiv & HWDivARM) && !isThumb())) {
4840 Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
4841 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4844 // Note, this is always on in gcc, even though it doesn't make sense.
4845 Builder.defineMacro("__APCS_32__");
4847 if (FPUModeIsVFP((FPUMode) FPU)) {
4848 Builder.defineMacro("__VFP_FP__");
4850 Builder.defineMacro("__ARM_VFPV2__");
4852 Builder.defineMacro("__ARM_VFPV3__");
4854 Builder.defineMacro("__ARM_VFPV4__");
4857 // This only gets set when Neon instructions are actually available, unlike
4858 // the VFP define, hence the soft float and arch check. This is subtly
4859 // different from gcc, we follow the intent which was that it should be set
4860 // when Neon instructions are actually available.
4861 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
4862 Builder.defineMacro("__ARM_NEON", "1");
4863 Builder.defineMacro("__ARM_NEON__");
4864 // current AArch32 NEON implementations do not support double-precision
4865 // floating-point even when it is present in VFP.
4866 Builder.defineMacro("__ARM_NEON_FP",
4867 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
4870 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4871 Opts.ShortWChar ? "2" : "4");
4873 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4874 Opts.ShortEnums ? "1" : "4");
4876 if (ArchVersion >= 6 && CPUAttr != "6M") {
4877 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4878 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4879 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4880 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4883 // ACLE 6.4.7 DSP instructions
4885 Builder.defineMacro("__ARM_FEATURE_DSP", "1");
4888 // ACLE 6.4.8 Saturation instructions
4890 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
4891 Builder.defineMacro("__ARM_FEATURE_SAT", "1");
4895 // ACLE 6.4.6 Q (saturation) flag
4897 Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
4899 if (Opts.UnsafeFPMath)
4900 Builder.defineMacro("__ARM_FP_FAST", "1");
4902 if (ArchKind == llvm::ARM::AK_ARMV8_1A)
4903 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
4906 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4907 return llvm::makeArrayRef(BuiltinInfo,
4908 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
4910 bool isCLZForZeroUndef() const override { return false; }
4911 BuiltinVaListKind getBuiltinVaListKind() const override {
4913 ? AAPCSABIBuiltinVaList
4914 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList
4915 : TargetInfo::VoidPtrBuiltinVaList);
4917 ArrayRef<const char *> getGCCRegNames() const override;
4918 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
4919 bool validateAsmConstraint(const char *&Name,
4920 TargetInfo::ConstraintInfo &Info) const override {
4925 case 't': // VFP Floating point register single precision
4926 case 'w': // VFP Floating point register double precision
4927 Info.setAllowsRegister();
4936 case 'Q': // A memory address that is a single base register.
4937 Info.setAllowsMemory();
4939 case 'U': // a memory reference...
4941 case 'q': // ...ARMV4 ldrsb
4942 case 'v': // ...VFP load/store (reg+constant offset)
4943 case 'y': // ...iWMMXt load/store
4944 case 't': // address valid for load/store opaque types wider
4946 case 'n': // valid address for Neon doubleword vector load/store
4947 case 'm': // valid address for Neon element and structure load/store
4948 case 's': // valid address for non-offset loads/stores of quad-word
4949 // values in four ARM registers
4950 Info.setAllowsMemory();
4957 std::string convertConstraint(const char *&Constraint) const override {
4959 switch (*Constraint) {
4960 case 'U': // Two-character constraint; add "^" hint for later parsing.
4961 R = std::string("^") + std::string(Constraint, 2);
4964 case 'p': // 'p' should be translated to 'r' by default.
4965 R = std::string("r");
4968 return std::string(1, *Constraint);
4973 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4974 std::string &SuggestedModifier) const override {
4975 bool isOutput = (Constraint[0] == '=');
4976 bool isInOut = (Constraint[0] == '+');
4978 // Strip off constraint modifiers.
4979 while (Constraint[0] == '=' ||
4980 Constraint[0] == '+' ||
4981 Constraint[0] == '&')
4982 Constraint = Constraint.substr(1);
4984 switch (Constraint[0]) {
4989 return (isInOut || isOutput || Size <= 64);
4991 // A register of size 32 cannot fit a vector type.
4999 const char *getClobbers() const override {
5000 // FIXME: Is this really right?
5004 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5005 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
5008 int getEHDataRegisterNumber(unsigned RegNo) const override {
5009 if (RegNo == 0) return 0;
5010 if (RegNo == 1) return 1;
5014 bool hasSjLjLowering() const override {
5019 bool ARMTargetInfo::setFPMath(StringRef Name) {
5020 if (Name == "neon") {
5023 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
5031 const char * const ARMTargetInfo::GCCRegNames[] = {
5032 // Integer registers
5033 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5034 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
5037 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
5038 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
5039 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
5040 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5043 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
5044 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
5045 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
5046 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5049 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
5050 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
5053 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
5054 return llvm::makeArrayRef(GCCRegNames);
5057 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
5067 { { "v6", "rfp" }, "r9" },
5068 { { "sl" }, "r10" },
5069 { { "fp" }, "r11" },
5070 { { "ip" }, "r12" },
5071 { { "r13" }, "sp" },
5072 { { "r14" }, "lr" },
5073 { { "r15" }, "pc" },
5074 // The S, D and Q registers overlap, but aren't really aliases; we
5075 // don't want to substitute one of these for a different-sized one.
5078 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5079 return llvm::makeArrayRef(GCCRegAliases);
5082 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5083 #define BUILTIN(ID, TYPE, ATTRS) \
5084 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5085 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5086 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5087 #include "clang/Basic/BuiltinsNEON.def"
5089 #define BUILTIN(ID, TYPE, ATTRS) \
5090 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5091 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5092 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5093 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5094 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5095 #include "clang/Basic/BuiltinsARM.def"
5098 class ARMleTargetInfo : public ARMTargetInfo {
5100 ARMleTargetInfo(const llvm::Triple &Triple)
5101 : ARMTargetInfo(Triple, false) { }
5102 void getTargetDefines(const LangOptions &Opts,
5103 MacroBuilder &Builder) const override {
5104 Builder.defineMacro("__ARMEL__");
5105 ARMTargetInfo::getTargetDefines(Opts, Builder);
5109 class ARMbeTargetInfo : public ARMTargetInfo {
5111 ARMbeTargetInfo(const llvm::Triple &Triple)
5112 : ARMTargetInfo(Triple, true) { }
5113 void getTargetDefines(const LangOptions &Opts,
5114 MacroBuilder &Builder) const override {
5115 Builder.defineMacro("__ARMEB__");
5116 Builder.defineMacro("__ARM_BIG_ENDIAN");
5117 ARMTargetInfo::getTargetDefines(Opts, Builder);
5121 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5122 const llvm::Triple Triple;
5124 WindowsARMTargetInfo(const llvm::Triple &Triple)
5125 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
5126 TLSSupported = false;
5127 WCharType = UnsignedShort;
5128 SizeType = UnsignedInt;
5129 UserLabelPrefix = "";
5131 void getVisualStudioDefines(const LangOptions &Opts,
5132 MacroBuilder &Builder) const {
5133 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5135 // FIXME: this is invalid for WindowsCE
5136 Builder.defineMacro("_M_ARM_NT", "1");
5137 Builder.defineMacro("_M_ARMT", "_M_ARM");
5138 Builder.defineMacro("_M_THUMB", "_M_ARM");
5140 assert((Triple.getArch() == llvm::Triple::arm ||
5141 Triple.getArch() == llvm::Triple::thumb) &&
5142 "invalid architecture for Windows ARM target info");
5143 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5144 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5146 // TODO map the complete set of values
5147 // 31: VFPv3 40: VFPv4
5148 Builder.defineMacro("_M_ARM_FP", "31");
5150 BuiltinVaListKind getBuiltinVaListKind() const override {
5151 return TargetInfo::CharPtrBuiltinVaList;
5153 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5156 case CC_X86ThisCall:
5157 case CC_X86FastCall:
5158 case CC_X86VectorCall:
5163 return CCCR_Warning;
5168 // Windows ARM + Itanium C++ ABI Target
5169 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5171 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
5172 : WindowsARMTargetInfo(Triple) {
5173 TheCXXABI.set(TargetCXXABI::GenericARM);
5176 void getTargetDefines(const LangOptions &Opts,
5177 MacroBuilder &Builder) const override {
5178 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5180 if (Opts.MSVCCompat)
5181 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5185 // Windows ARM, MS (C++) ABI
5186 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5188 MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
5189 : WindowsARMTargetInfo(Triple) {
5190 TheCXXABI.set(TargetCXXABI::Microsoft);
5193 void getTargetDefines(const LangOptions &Opts,
5194 MacroBuilder &Builder) const override {
5195 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5196 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5201 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5203 MinGWARMTargetInfo(const llvm::Triple &Triple)
5204 : WindowsARMTargetInfo(Triple) {
5205 TheCXXABI.set(TargetCXXABI::GenericARM);
5208 void getTargetDefines(const LangOptions &Opts,
5209 MacroBuilder &Builder) const override {
5210 WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5211 DefineStd(Builder, "WIN32", Opts);
5212 DefineStd(Builder, "WINNT", Opts);
5213 Builder.defineMacro("_ARM_");
5214 addMinGWDefines(Opts, Builder);
5218 // ARM Cygwin target
5219 class CygwinARMTargetInfo : public ARMleTargetInfo {
5221 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) {
5222 TLSSupported = false;
5223 WCharType = UnsignedShort;
5224 DoubleAlign = LongLongAlign = 64;
5225 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
5227 void getTargetDefines(const LangOptions &Opts,
5228 MacroBuilder &Builder) const override {
5229 ARMleTargetInfo::getTargetDefines(Opts, Builder);
5230 Builder.defineMacro("_ARM_");
5231 Builder.defineMacro("__CYGWIN__");
5232 Builder.defineMacro("__CYGWIN32__");
5233 DefineStd(Builder, "unix", Opts);
5235 Builder.defineMacro("_GNU_SOURCE");
5239 class DarwinARMTargetInfo :
5240 public DarwinTargetInfo<ARMleTargetInfo> {
5242 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5243 MacroBuilder &Builder) const override {
5244 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5248 DarwinARMTargetInfo(const llvm::Triple &Triple)
5249 : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
5250 HasAlignMac68kSupport = true;
5251 // iOS always has 64-bit atomic instructions.
5252 // FIXME: This should be based off of the target features in
5254 MaxAtomicInlineWidth = 64;
5256 if (Triple.isWatchOS()) {
5257 // Darwin on iOS uses a variant of the ARM C++ ABI.
5258 TheCXXABI.set(TargetCXXABI::WatchOS);
5260 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5261 // size_t is long, it's a bit weird for it to be int.
5262 PtrDiffType = SignedLong;
5264 // BOOL should be a real boolean on the new ABI
5265 UseSignedCharForObjCBool = false;
5267 TheCXXABI.set(TargetCXXABI::iOS);
5271 class AArch64TargetInfo : public TargetInfo {
5272 virtual void setDataLayoutString() = 0;
5273 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5274 static const char *const GCCRegNames[];
5287 static const Builtin::Info BuiltinInfo[];
5292 AArch64TargetInfo(const llvm::Triple &Triple)
5293 : TargetInfo(Triple), ABI("aapcs") {
5295 if (getTriple().getOS() == llvm::Triple::NetBSD) {
5296 WCharType = SignedInt;
5298 // NetBSD apparently prefers consistency across ARM targets to consistency
5299 // across 64-bit targets.
5300 Int64Type = SignedLongLong;
5301 IntMaxType = SignedLongLong;
5303 WCharType = UnsignedInt;
5304 Int64Type = SignedLong;
5305 IntMaxType = SignedLong;
5308 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5309 MaxVectorAlign = 128;
5310 MaxAtomicInlineWidth = 128;
5311 MaxAtomicPromoteWidth = 128;
5313 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5314 LongDoubleFormat = &llvm::APFloat::IEEEquad;
5316 // {} in inline assembly are neon specifiers, not assembly variant
5318 NoAsmVariants = true;
5320 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5321 // contributes to the alignment of the containing aggregate in the same way
5322 // a plain (non bit-field) member of that type would, without exception for
5323 // zero-sized or anonymous bit-fields."
5324 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5325 UseZeroLengthBitfieldAlignment = true;
5327 // AArch64 targets default to using the ARM C++ ABI.
5328 TheCXXABI.set(TargetCXXABI::GenericAArch64);
5331 StringRef getABI() const override { return ABI; }
5332 bool setABI(const std::string &Name) override {
5333 if (Name != "aapcs" && Name != "darwinpcs")
5340 bool setCPU(const std::string &Name) override {
5341 bool CPUKnown = llvm::StringSwitch<bool>(Name)
5342 .Case("generic", true)
5343 .Cases("cortex-a53", "cortex-a57", "cortex-a72",
5344 "cortex-a35", "exynos-m1", true)
5345 .Case("cyclone", true)
5350 void getTargetDefines(const LangOptions &Opts,
5351 MacroBuilder &Builder) const override {
5352 // Target identification.
5353 Builder.defineMacro("__aarch64__");
5355 // Target properties.
5356 Builder.defineMacro("_LP64");
5357 Builder.defineMacro("__LP64__");
5359 // ACLE predefines. Many can only have one possible value on v8 AArch64.
5360 Builder.defineMacro("__ARM_ACLE", "200");
5361 Builder.defineMacro("__ARM_ARCH", "8");
5362 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5364 Builder.defineMacro("__ARM_64BIT_STATE", "1");
5365 Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5366 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5368 Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5369 Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5370 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5371 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5372 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility
5373 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5374 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5376 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5378 // 0xe implies support for half, single and double precision operations.
5379 Builder.defineMacro("__ARM_FP", "0xE");
5381 // PCS specifies this for SysV variants, which is all we support. Other ABIs
5382 // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5383 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5384 Builder.defineMacro("__ARM_FP16_ARGS", "1");
5386 if (Opts.UnsafeFPMath)
5387 Builder.defineMacro("__ARM_FP_FAST", "1");
5389 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5391 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5392 Opts.ShortEnums ? "1" : "4");
5394 if (FPU == NeonMode) {
5395 Builder.defineMacro("__ARM_NEON", "1");
5396 // 64-bit NEON supports half, single and double precision operations.
5397 Builder.defineMacro("__ARM_NEON_FP", "0xE");
5401 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5404 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5407 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5410 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
5412 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5413 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5419 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5420 return llvm::makeArrayRef(BuiltinInfo,
5421 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
5424 bool hasFeature(StringRef Feature) const override {
5425 return Feature == "aarch64" ||
5426 Feature == "arm64" ||
5428 (Feature == "neon" && FPU == NeonMode);
5431 bool handleTargetFeatures(std::vector<std::string> &Features,
5432 DiagnosticsEngine &Diags) override {
5439 for (const auto &Feature : Features) {
5440 if (Feature == "+neon")
5442 if (Feature == "+crc")
5444 if (Feature == "+crypto")
5446 if (Feature == "+strict-align")
5448 if (Feature == "+v8.1a")
5452 setDataLayoutString();
5457 bool isCLZForZeroUndef() const override { return false; }
5459 BuiltinVaListKind getBuiltinVaListKind() const override {
5460 return TargetInfo::AArch64ABIBuiltinVaList;
5463 ArrayRef<const char *> getGCCRegNames() const override;
5464 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5466 bool validateAsmConstraint(const char *&Name,
5467 TargetInfo::ConstraintInfo &Info) const override {
5471 case 'w': // Floating point and SIMD registers (V0-V31)
5472 Info.setAllowsRegister();
5474 case 'I': // Constant that can be used with an ADD instruction
5475 case 'J': // Constant that can be used with a SUB instruction
5476 case 'K': // Constant that can be used with a 32-bit logical instruction
5477 case 'L': // Constant that can be used with a 64-bit logical instruction
5478 case 'M': // Constant that can be used as a 32-bit MOV immediate
5479 case 'N': // Constant that can be used as a 64-bit MOV immediate
5480 case 'Y': // Floating point constant zero
5481 case 'Z': // Integer constant zero
5483 case 'Q': // A memory reference with base register and no offset
5484 Info.setAllowsMemory();
5486 case 'S': // A symbolic address
5487 Info.setAllowsRegister();
5490 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5491 // Utf: A memory address suitable for ldp/stp in TF mode.
5492 // Usa: An absolute symbolic address.
5493 // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5494 llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5495 case 'z': // Zero register, wzr or xzr
5496 Info.setAllowsRegister();
5498 case 'x': // Floating point and SIMD registers (V0-V15)
5499 Info.setAllowsRegister();
5506 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5507 std::string &SuggestedModifier) const override {
5508 // Strip off constraint modifiers.
5509 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5510 Constraint = Constraint.substr(1);
5512 switch (Constraint[0]) {
5520 // For now assume that the person knows what they're
5521 // doing with the modifier.
5524 // By default an 'r' constraint will be in the 'x'
5529 SuggestedModifier = "w";
5536 const char *getClobbers() const override { return ""; }
5538 int getEHDataRegisterNumber(unsigned RegNo) const override {
5547 const char *const AArch64TargetInfo::GCCRegNames[] = {
5548 // 32-bit Integer registers
5549 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10",
5550 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5551 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5553 // 64-bit Integer registers
5554 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10",
5555 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5556 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
5558 // 32-bit floating point regsisters
5559 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10",
5560 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5561 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5563 // 64-bit floating point regsisters
5564 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10",
5565 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5566 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5569 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10",
5570 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5571 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5574 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
5575 return llvm::makeArrayRef(GCCRegNames);
5578 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5579 { { "w31" }, "wsp" },
5580 { { "x29" }, "fp" },
5581 { { "x30" }, "lr" },
5582 { { "x31" }, "sp" },
5583 // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5584 // don't want to substitute one of these for a different-sized one.
5587 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
5588 return llvm::makeArrayRef(GCCRegAliases);
5591 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5592 #define BUILTIN(ID, TYPE, ATTRS) \
5593 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5594 #include "clang/Basic/BuiltinsNEON.def"
5596 #define BUILTIN(ID, TYPE, ATTRS) \
5597 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5598 #include "clang/Basic/BuiltinsAArch64.def"
5601 class AArch64leTargetInfo : public AArch64TargetInfo {
5602 void setDataLayoutString() override {
5603 if (getTriple().isOSBinFormatMachO())
5604 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128";
5606 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128";
5610 AArch64leTargetInfo(const llvm::Triple &Triple)
5611 : AArch64TargetInfo(Triple) {
5614 void getTargetDefines(const LangOptions &Opts,
5615 MacroBuilder &Builder) const override {
5616 Builder.defineMacro("__AARCH64EL__");
5617 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5621 class AArch64beTargetInfo : public AArch64TargetInfo {
5622 void setDataLayoutString() override {
5623 assert(!getTriple().isOSBinFormatMachO());
5624 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128";
5628 AArch64beTargetInfo(const llvm::Triple &Triple)
5629 : AArch64TargetInfo(Triple) { }
5630 void getTargetDefines(const LangOptions &Opts,
5631 MacroBuilder &Builder) const override {
5632 Builder.defineMacro("__AARCH64EB__");
5633 Builder.defineMacro("__AARCH_BIG_ENDIAN");
5634 Builder.defineMacro("__ARM_BIG_ENDIAN");
5635 AArch64TargetInfo::getTargetDefines(Opts, Builder);
5639 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5641 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5642 MacroBuilder &Builder) const override {
5643 Builder.defineMacro("__AARCH64_SIMD__");
5644 Builder.defineMacro("__ARM64_ARCH_8__");
5645 Builder.defineMacro("__ARM_NEON__");
5646 Builder.defineMacro("__LITTLE_ENDIAN__");
5647 Builder.defineMacro("__REGISTER_PREFIX__", "");
5648 Builder.defineMacro("__arm64", "1");
5649 Builder.defineMacro("__arm64__", "1");
5651 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5655 DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5656 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5657 Int64Type = SignedLongLong;
5658 WCharType = SignedInt;
5659 UseSignedCharForObjCBool = false;
5661 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5662 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5664 TheCXXABI.set(TargetCXXABI::iOS64);
5667 BuiltinVaListKind getBuiltinVaListKind() const override {
5668 return TargetInfo::CharPtrBuiltinVaList;
5672 // Hexagon abstract base class
5673 class HexagonTargetInfo : public TargetInfo {
5674 static const Builtin::Info BuiltinInfo[];
5675 static const char * const GCCRegNames[];
5676 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5678 bool HasHVX, HasHVXDouble;
5681 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5683 DataLayoutString = "e-m:e-p:32:32:32-"
5684 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-"
5685 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32";
5686 SizeType = UnsignedInt;
5687 PtrDiffType = SignedInt;
5688 IntPtrType = SignedInt;
5690 // {} in inline assembly are packet specifiers, not assembly variant
5692 NoAsmVariants = true;
5694 LargeArrayMinWidth = 64;
5695 LargeArrayAlign = 64;
5696 UseBitFieldTypeAlignment = true;
5697 ZeroLengthBitfieldBoundary = 32;
5698 HasHVX = HasHVXDouble = false;
5701 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5702 return llvm::makeArrayRef(BuiltinInfo,
5703 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
5706 bool validateAsmConstraint(const char *&Name,
5707 TargetInfo::ConstraintInfo &Info) const override {
5711 void getTargetDefines(const LangOptions &Opts,
5712 MacroBuilder &Builder) const override;
5714 bool isCLZForZeroUndef() const override { return false; }
5716 bool hasFeature(StringRef Feature) const override {
5717 return llvm::StringSwitch<bool>(Feature)
5718 .Case("hexagon", true)
5719 .Case("hvx", HasHVX)
5720 .Case("hvx-double", HasHVXDouble)
5724 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
5725 StringRef CPU, const std::vector<std::string> &FeaturesVec)
5728 bool handleTargetFeatures(std::vector<std::string> &Features,
5729 DiagnosticsEngine &Diags) override;
5731 BuiltinVaListKind getBuiltinVaListKind() const override {
5732 return TargetInfo::CharPtrBuiltinVaList;
5734 ArrayRef<const char *> getGCCRegNames() const override;
5735 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5736 const char *getClobbers() const override {
5740 static const char *getHexagonCPUSuffix(StringRef Name) {
5741 return llvm::StringSwitch<const char*>(Name)
5742 .Case("hexagonv4", "4")
5743 .Case("hexagonv5", "5")
5744 .Case("hexagonv55", "55")
5745 .Case("hexagonv60", "60")
5749 bool setCPU(const std::string &Name) override {
5750 if (!getHexagonCPUSuffix(Name))
5756 int getEHDataRegisterNumber(unsigned RegNo) const override {
5757 return RegNo < 2 ? RegNo : -1;
5761 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5762 MacroBuilder &Builder) const {
5763 Builder.defineMacro("__qdsp6__", "1");
5764 Builder.defineMacro("__hexagon__", "1");
5766 if (CPU == "hexagonv4") {
5767 Builder.defineMacro("__HEXAGON_V4__");
5768 Builder.defineMacro("__HEXAGON_ARCH__", "4");
5769 if (Opts.HexagonQdsp6Compat) {
5770 Builder.defineMacro("__QDSP6_V4__");
5771 Builder.defineMacro("__QDSP6_ARCH__", "4");
5773 } else if (CPU == "hexagonv5") {
5774 Builder.defineMacro("__HEXAGON_V5__");
5775 Builder.defineMacro("__HEXAGON_ARCH__", "5");
5776 if(Opts.HexagonQdsp6Compat) {
5777 Builder.defineMacro("__QDSP6_V5__");
5778 Builder.defineMacro("__QDSP6_ARCH__", "5");
5780 } else if (CPU == "hexagonv60") {
5781 Builder.defineMacro("__HEXAGON_V60__");
5782 Builder.defineMacro("__HEXAGON_ARCH__", "60");
5783 Builder.defineMacro("__QDSP6_V60__");
5784 Builder.defineMacro("__QDSP6_ARCH__", "60");
5788 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
5789 DiagnosticsEngine &Diags) {
5790 for (auto &F : Features) {
5793 else if (F == "-hvx")
5794 HasHVX = HasHVXDouble = false;
5795 else if (F == "+hvx-double")
5796 HasHVX = HasHVXDouble = true;
5797 else if (F == "-hvx-double")
5798 HasHVXDouble = false;
5803 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features,
5804 DiagnosticsEngine &Diags, StringRef CPU,
5805 const std::vector<std::string> &FeaturesVec) const {
5806 // Default for v60: -hvx, -hvx-double.
5807 Features["hvx"] = false;
5808 Features["hvx-double"] = false;
5810 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
5814 const char *const HexagonTargetInfo::GCCRegNames[] = {
5815 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5816 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5817 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5818 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5819 "p0", "p1", "p2", "p3",
5820 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5823 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const {
5824 return llvm::makeArrayRef(GCCRegNames);
5827 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5828 { { "sp" }, "r29" },
5829 { { "fp" }, "r30" },
5830 { { "lr" }, "r31" },
5833 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
5834 return llvm::makeArrayRef(GCCRegAliases);
5838 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5839 #define BUILTIN(ID, TYPE, ATTRS) \
5840 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5841 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5842 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5843 #include "clang/Basic/BuiltinsHexagon.def"
5846 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5847 class SparcTargetInfo : public TargetInfo {
5848 static const TargetInfo::GCCRegAlias GCCRegAliases[];
5849 static const char * const GCCRegNames[];
5852 SparcTargetInfo(const llvm::Triple &Triple)
5853 : TargetInfo(Triple), SoftFloat(false) {}
5855 bool handleTargetFeatures(std::vector<std::string> &Features,
5856 DiagnosticsEngine &Diags) override {
5857 // The backend doesn't actually handle soft float yet, but in case someone
5858 // is using the support for the front end continue to support it.
5859 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5860 if (Feature != Features.end()) {
5862 Features.erase(Feature);
5866 void getTargetDefines(const LangOptions &Opts,
5867 MacroBuilder &Builder) const override {
5868 DefineStd(Builder, "sparc", Opts);
5869 Builder.defineMacro("__REGISTER_PREFIX__", "");
5872 Builder.defineMacro("SOFT_FLOAT", "1");
5875 bool hasFeature(StringRef Feature) const override {
5876 return llvm::StringSwitch<bool>(Feature)
5877 .Case("softfloat", SoftFloat)
5878 .Case("sparc", true)
5882 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5883 // FIXME: Implement!
5886 BuiltinVaListKind getBuiltinVaListKind() const override {
5887 return TargetInfo::VoidPtrBuiltinVaList;
5889 ArrayRef<const char *> getGCCRegNames() const override;
5890 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5891 bool validateAsmConstraint(const char *&Name,
5892 TargetInfo::ConstraintInfo &info) const override {
5893 // FIXME: Implement!
5895 case 'I': // Signed 13-bit constant
5897 case 'K': // 32-bit constant with the low 12 bits clear
5898 case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5899 case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5900 case 'N': // Same as 'K' but zext (required for SIMode)
5901 case 'O': // The constant 4096
5906 const char *getClobbers() const override {
5907 // FIXME: Implement!
5911 // No Sparc V7 for now, the backend doesn't support it anyway.
5931 enum CPUGeneration {
5936 CPUGeneration getCPUGeneration(CPUKind Kind) const {
5944 case CK_SPARCLITE86X:
5950 case CK_ULTRASPARC3:
5957 llvm_unreachable("Unexpected CPU kind");
5960 CPUKind getCPUKind(StringRef Name) const {
5961 return llvm::StringSwitch<CPUKind>(Name)
5963 .Case("supersparc", CK_SUPERSPARC)
5964 .Case("sparclite", CK_SPARCLITE)
5965 .Case("f934", CK_F934)
5966 .Case("hypersparc", CK_HYPERSPARC)
5967 .Case("sparclite86x", CK_SPARCLITE86X)
5968 .Case("sparclet", CK_SPARCLET)
5969 .Case("tsc701", CK_TSC701)
5971 .Case("ultrasparc", CK_ULTRASPARC)
5972 .Case("ultrasparc3", CK_ULTRASPARC3)
5973 .Case("niagara", CK_NIAGARA)
5974 .Case("niagara2", CK_NIAGARA2)
5975 .Case("niagara3", CK_NIAGARA3)
5976 .Case("niagara4", CK_NIAGARA4)
5977 .Default(CK_GENERIC);
5980 bool setCPU(const std::string &Name) override {
5981 CPU = getCPUKind(Name);
5982 return CPU != CK_GENERIC;
5986 const char * const SparcTargetInfo::GCCRegNames[] = {
5987 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5988 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5989 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5990 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5993 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
5994 return llvm::makeArrayRef(GCCRegNames);
5997 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
6008 { { "o2" }, "r10" },
6009 { { "o3" }, "r11" },
6010 { { "o4" }, "r12" },
6011 { { "o5" }, "r13" },
6012 { { "o6", "sp" }, "r14" },
6013 { { "o7" }, "r15" },
6014 { { "l0" }, "r16" },
6015 { { "l1" }, "r17" },
6016 { { "l2" }, "r18" },
6017 { { "l3" }, "r19" },
6018 { { "l4" }, "r20" },
6019 { { "l5" }, "r21" },
6020 { { "l6" }, "r22" },
6021 { { "l7" }, "r23" },
6022 { { "i0" }, "r24" },
6023 { { "i1" }, "r25" },
6024 { { "i2" }, "r26" },
6025 { { "i3" }, "r27" },
6026 { { "i4" }, "r28" },
6027 { { "i5" }, "r29" },
6028 { { "i6", "fp" }, "r30" },
6029 { { "i7" }, "r31" },
6032 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
6033 return llvm::makeArrayRef(GCCRegAliases);
6036 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
6037 class SparcV8TargetInfo : public SparcTargetInfo {
6039 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6040 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
6041 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
6042 switch (getTriple().getOS()) {
6044 SizeType = UnsignedInt;
6045 IntPtrType = SignedInt;
6046 PtrDiffType = SignedInt;
6048 case llvm::Triple::NetBSD:
6049 case llvm::Triple::OpenBSD:
6050 SizeType = UnsignedLong;
6051 IntPtrType = SignedLong;
6052 PtrDiffType = SignedLong;
6057 void getTargetDefines(const LangOptions &Opts,
6058 MacroBuilder &Builder) const override {
6059 SparcTargetInfo::getTargetDefines(Opts, Builder);
6060 switch (getCPUGeneration(CPU)) {
6062 Builder.defineMacro("__sparcv8");
6063 if (getTriple().getOS() != llvm::Triple::Solaris)
6064 Builder.defineMacro("__sparcv8__");
6067 Builder.defineMacro("__sparcv9");
6068 if (getTriple().getOS() != llvm::Triple::Solaris) {
6069 Builder.defineMacro("__sparcv9__");
6070 Builder.defineMacro("__sparc_v9__");
6077 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
6078 class SparcV8elTargetInfo : public SparcV8TargetInfo {
6080 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
6081 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
6086 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
6087 class SparcV9TargetInfo : public SparcTargetInfo {
6089 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
6090 // FIXME: Support Sparc quad-precision long double?
6091 DataLayoutString = "E-m:e-i64:64-n32:64-S128";
6092 // This is an LP64 platform.
6093 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6095 // OpenBSD uses long long for int64_t and intmax_t.
6096 if (getTriple().getOS() == llvm::Triple::OpenBSD)
6097 IntMaxType = SignedLongLong;
6099 IntMaxType = SignedLong;
6100 Int64Type = IntMaxType;
6102 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
6103 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
6104 LongDoubleWidth = 128;
6105 LongDoubleAlign = 128;
6106 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6107 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6110 void getTargetDefines(const LangOptions &Opts,
6111 MacroBuilder &Builder) const override {
6112 SparcTargetInfo::getTargetDefines(Opts, Builder);
6113 Builder.defineMacro("__sparcv9");
6114 Builder.defineMacro("__arch64__");
6115 // Solaris doesn't need these variants, but the BSDs do.
6116 if (getTriple().getOS() != llvm::Triple::Solaris) {
6117 Builder.defineMacro("__sparc64__");
6118 Builder.defineMacro("__sparc_v9__");
6119 Builder.defineMacro("__sparcv9__");
6123 bool setCPU(const std::string &Name) override {
6124 if (!SparcTargetInfo::setCPU(Name))
6126 return getCPUGeneration(CPU) == CG_V9;
6130 class SystemZTargetInfo : public TargetInfo {
6131 static const Builtin::Info BuiltinInfo[];
6132 static const char *const GCCRegNames[];
6134 bool HasTransactionalExecution;
6138 SystemZTargetInfo(const llvm::Triple &Triple)
6139 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6141 IntMaxType = SignedLong;
6142 Int64Type = SignedLong;
6143 TLSSupported = true;
6144 IntWidth = IntAlign = 32;
6145 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6146 PointerWidth = PointerAlign = 64;
6147 LongDoubleWidth = 128;
6148 LongDoubleAlign = 64;
6149 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6150 DefaultAlignForAttributeAligned = 64;
6151 MinGlobalAlign = 16;
6152 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
6153 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6155 void getTargetDefines(const LangOptions &Opts,
6156 MacroBuilder &Builder) const override {
6157 Builder.defineMacro("__s390__");
6158 Builder.defineMacro("__s390x__");
6159 Builder.defineMacro("__zarch__");
6160 Builder.defineMacro("__LONG_DOUBLE_128__");
6162 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6163 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6164 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6165 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
6167 if (HasTransactionalExecution)
6168 Builder.defineMacro("__HTM__");
6170 Builder.defineMacro("__VEC__", "10301");
6172 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6173 return llvm::makeArrayRef(BuiltinInfo,
6174 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
6177 ArrayRef<const char *> getGCCRegNames() const override;
6178 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6182 bool validateAsmConstraint(const char *&Name,
6183 TargetInfo::ConstraintInfo &info) const override;
6184 const char *getClobbers() const override {
6185 // FIXME: Is this really right?
6188 BuiltinVaListKind getBuiltinVaListKind() const override {
6189 return TargetInfo::SystemZBuiltinVaList;
6191 bool setCPU(const std::string &Name) override {
6193 bool CPUKnown = llvm::StringSwitch<bool>(Name)
6196 .Case("zEC12", true)
6203 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6205 const std::vector<std::string> &FeaturesVec) const override {
6207 Features["transactional-execution"] = true;
6209 Features["transactional-execution"] = true;
6210 Features["vector"] = true;
6212 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6215 bool handleTargetFeatures(std::vector<std::string> &Features,
6216 DiagnosticsEngine &Diags) override {
6217 HasTransactionalExecution = false;
6218 for (const auto &Feature : Features) {
6219 if (Feature == "+transactional-execution")
6220 HasTransactionalExecution = true;
6221 else if (Feature == "+vector")
6224 // If we use the vector ABI, vector types are 64-bit aligned.
6226 MaxVectorAlign = 64;
6227 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
6228 "-v128:64-a:8:16-n32:64";
6233 bool hasFeature(StringRef Feature) const override {
6234 return llvm::StringSwitch<bool>(Feature)
6235 .Case("systemz", true)
6236 .Case("htm", HasTransactionalExecution)
6237 .Case("vx", HasVector)
6241 StringRef getABI() const override {
6247 bool useFloat128ManglingForLongDouble() const override {
6252 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
6253 #define BUILTIN(ID, TYPE, ATTRS) \
6254 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6255 #include "clang/Basic/BuiltinsSystemZ.def"
6258 const char *const SystemZTargetInfo::GCCRegNames[] = {
6259 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6260 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6261 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
6262 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15"
6265 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
6266 return llvm::makeArrayRef(GCCRegNames);
6269 bool SystemZTargetInfo::
6270 validateAsmConstraint(const char *&Name,
6271 TargetInfo::ConstraintInfo &Info) const {
6276 case 'a': // Address register
6277 case 'd': // Data register (equivalent to 'r')
6278 case 'f': // Floating-point register
6279 Info.setAllowsRegister();
6282 case 'I': // Unsigned 8-bit constant
6283 case 'J': // Unsigned 12-bit constant
6284 case 'K': // Signed 16-bit constant
6285 case 'L': // Signed 20-bit displacement (on all targets we support)
6286 case 'M': // 0x7fffffff
6289 case 'Q': // Memory with base and unsigned 12-bit displacement
6290 case 'R': // Likewise, plus an index
6291 case 'S': // Memory with base and signed 20-bit displacement
6292 case 'T': // Likewise, plus an index
6293 Info.setAllowsMemory();
6298 class MSP430TargetInfo : public TargetInfo {
6299 static const char *const GCCRegNames[];
6302 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6304 TLSSupported = false;
6309 LongAlign = LongLongAlign = 16;
6313 SizeType = UnsignedInt;
6314 IntMaxType = SignedLongLong;
6315 IntPtrType = SignedInt;
6316 PtrDiffType = SignedInt;
6317 SigAtomicType = SignedLong;
6318 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
6320 void getTargetDefines(const LangOptions &Opts,
6321 MacroBuilder &Builder) const override {
6322 Builder.defineMacro("MSP430");
6323 Builder.defineMacro("__MSP430__");
6324 // FIXME: defines for different 'flavours' of MCU
6326 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6327 // FIXME: Implement.
6330 bool hasFeature(StringRef Feature) const override {
6331 return Feature == "msp430";
6333 ArrayRef<const char *> getGCCRegNames() const override;
6334 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6338 bool validateAsmConstraint(const char *&Name,
6339 TargetInfo::ConstraintInfo &info) const override {
6342 case 'K': // the constant 1
6343 case 'L': // constant -1^20 .. 1^19
6344 case 'M': // constant 1-4:
6347 // No target constraints for now.
6350 const char *getClobbers() const override {
6351 // FIXME: Is this really right?
6354 BuiltinVaListKind getBuiltinVaListKind() const override {
6356 return TargetInfo::CharPtrBuiltinVaList;
6360 const char *const MSP430TargetInfo::GCCRegNames[] = {
6361 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6362 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
6364 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
6365 return llvm::makeArrayRef(GCCRegNames);
6368 // LLVM and Clang cannot be used directly to output native binaries for
6369 // target, but is used to compile C code to llvm bitcode with correct
6370 // type and alignment information.
6372 // TCE uses the llvm bitcode as input and uses it for generating customized
6373 // target processor and program binary. TCE co-design environment is
6374 // publicly available in http://tce.cs.tut.fi
6376 static const unsigned TCEOpenCLAddrSpaceMap[] = {
6379 5, // opencl_constant
6380 // FIXME: generic has to be added to the target
6381 0, // opencl_generic
6387 class TCETargetInfo : public TargetInfo {
6389 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6390 TLSSupported = false;
6392 LongWidth = LongLongWidth = 32;
6395 LongAlign = LongLongAlign = 32;
6398 SizeType = UnsignedInt;
6399 IntMaxType = SignedLong;
6400 IntPtrType = SignedInt;
6401 PtrDiffType = SignedInt;
6406 LongDoubleWidth = 32;
6407 LongDoubleAlign = 32;
6408 FloatFormat = &llvm::APFloat::IEEEsingle;
6409 DoubleFormat = &llvm::APFloat::IEEEsingle;
6410 LongDoubleFormat = &llvm::APFloat::IEEEsingle;
6411 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
6412 "-f64:32-v64:32-v128:32-a:0:32-n32";
6413 AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
6414 UseAddrSpaceMapMangling = true;
6417 void getTargetDefines(const LangOptions &Opts,
6418 MacroBuilder &Builder) const override {
6419 DefineStd(Builder, "tce", Opts);
6420 Builder.defineMacro("__TCE__");
6421 Builder.defineMacro("__TCE_V1__");
6423 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
6425 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6426 const char *getClobbers() const override { return ""; }
6427 BuiltinVaListKind getBuiltinVaListKind() const override {
6428 return TargetInfo::VoidPtrBuiltinVaList;
6430 ArrayRef<const char *> getGCCRegNames() const override { return None; }
6431 bool validateAsmConstraint(const char *&Name,
6432 TargetInfo::ConstraintInfo &info) const override {
6435 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6440 class BPFTargetInfo : public TargetInfo {
6442 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6443 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6444 SizeType = UnsignedLong;
6445 PtrDiffType = SignedLong;
6446 IntPtrType = SignedLong;
6447 IntMaxType = SignedLong;
6448 Int64Type = SignedLong;
6450 if (Triple.getArch() == llvm::Triple::bpfeb) {
6452 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128";
6455 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128";
6457 MaxAtomicPromoteWidth = 64;
6458 MaxAtomicInlineWidth = 64;
6459 TLSSupported = false;
6461 void getTargetDefines(const LangOptions &Opts,
6462 MacroBuilder &Builder) const override {
6463 DefineStd(Builder, "bpf", Opts);
6464 Builder.defineMacro("__BPF__");
6466 bool hasFeature(StringRef Feature) const override {
6467 return Feature == "bpf";
6470 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6471 const char *getClobbers() const override {
6474 BuiltinVaListKind getBuiltinVaListKind() const override {
6475 return TargetInfo::VoidPtrBuiltinVaList;
6477 ArrayRef<const char *> getGCCRegNames() const override {
6480 bool validateAsmConstraint(const char *&Name,
6481 TargetInfo::ConstraintInfo &info) const override {
6484 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6489 class MipsTargetInfoBase : public TargetInfo {
6490 virtual void setDataLayoutString() = 0;
6492 static const Builtin::Info BuiltinInfo[];
6499 HardFloat, SoftFloat
6511 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
6512 const std::string &CPUStr)
6513 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6514 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6515 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6516 TheCXXABI.set(TargetCXXABI::GenericMIPS);
6519 bool isNaN2008Default() const {
6520 return CPU == "mips32r6" || CPU == "mips64r6";
6523 bool isFP64Default() const {
6524 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6527 bool isNan2008() const override {
6531 StringRef getABI() const override { return ABI; }
6532 bool setCPU(const std::string &Name) override {
6533 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6534 getTriple().getArch() == llvm::Triple::mipsel;
6536 return llvm::StringSwitch<bool>(Name)
6537 .Case("mips1", IsMips32)
6538 .Case("mips2", IsMips32)
6539 .Case("mips3", true)
6540 .Case("mips4", true)
6541 .Case("mips5", true)
6542 .Case("mips32", IsMips32)
6543 .Case("mips32r2", IsMips32)
6544 .Case("mips32r3", IsMips32)
6545 .Case("mips32r5", IsMips32)
6546 .Case("mips32r6", IsMips32)
6547 .Case("mips64", true)
6548 .Case("mips64r2", true)
6549 .Case("mips64r3", true)
6550 .Case("mips64r5", true)
6551 .Case("mips64r6", true)
6552 .Case("octeon", true)
6553 .Case("p5600", true)
6556 const std::string& getCPU() const { return CPU; }
6558 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6560 const std::vector<std::string> &FeaturesVec) const override {
6561 if (CPU == "octeon")
6562 Features["mips64r2"] = Features["cnmips"] = true;
6564 Features[CPU] = true;
6565 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6568 void getTargetDefines(const LangOptions &Opts,
6569 MacroBuilder &Builder) const override {
6570 Builder.defineMacro("__mips__");
6571 Builder.defineMacro("_mips");
6573 Builder.defineMacro("mips");
6575 Builder.defineMacro("__REGISTER_PREFIX__", "");
6579 Builder.defineMacro("__mips_hard_float", Twine(1));
6582 Builder.defineMacro("__mips_soft_float", Twine(1));
6587 Builder.defineMacro("__mips_single_float", Twine(1));
6589 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6590 Builder.defineMacro("_MIPS_FPSET",
6591 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6594 Builder.defineMacro("__mips16", Twine(1));
6597 Builder.defineMacro("__mips_micromips", Twine(1));
6600 Builder.defineMacro("__mips_nan2008", Twine(1));
6606 Builder.defineMacro("__mips_dsp_rev", Twine(1));
6607 Builder.defineMacro("__mips_dsp", Twine(1));
6610 Builder.defineMacro("__mips_dsp_rev", Twine(2));
6611 Builder.defineMacro("__mips_dspr2", Twine(1));
6612 Builder.defineMacro("__mips_dsp", Twine(1));
6617 Builder.defineMacro("__mips_msa", Twine(1));
6619 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6620 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6621 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6623 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6624 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6626 // These shouldn't be defined for MIPS-I but there's no need to check
6627 // for that since MIPS-I isn't supported.
6628 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
6629 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
6630 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
6633 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6634 return llvm::makeArrayRef(BuiltinInfo,
6635 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
6637 bool hasFeature(StringRef Feature) const override {
6638 return llvm::StringSwitch<bool>(Feature)
6640 .Case("fp64", HasFP64)
6643 BuiltinVaListKind getBuiltinVaListKind() const override {
6644 return TargetInfo::VoidPtrBuiltinVaList;
6646 ArrayRef<const char *> getGCCRegNames() const override {
6647 static const char *const GCCRegNames[] = {
6648 // CPU register names
6649 // Must match second column of GCCRegAliases
6650 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
6651 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
6652 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
6653 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
6654 // Floating point register names
6655 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
6656 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6657 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6658 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6659 // Hi/lo and condition register names
6660 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6661 "$fcc5","$fcc6","$fcc7",
6662 // MSA register names
6663 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
6664 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6665 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6666 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6667 // MSA control register names
6668 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6669 "$msarequest", "$msamap", "$msaunmap"
6671 return llvm::makeArrayRef(GCCRegNames);
6673 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0;
6674 bool validateAsmConstraint(const char *&Name,
6675 TargetInfo::ConstraintInfo &Info) const override {
6679 case 'r': // CPU registers.
6680 case 'd': // Equivalent to "r" unless generating MIPS16 code.
6681 case 'y': // Equivalent to "r", backward compatibility only.
6682 case 'f': // floating-point registers.
6683 case 'c': // $25 for indirect jumps
6684 case 'l': // lo register
6685 case 'x': // hilo register pair
6686 Info.setAllowsRegister();
6688 case 'I': // Signed 16-bit constant
6689 case 'J': // Integer 0
6690 case 'K': // Unsigned 16-bit constant
6691 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6692 case 'M': // Constants not loadable via lui, addiu, or ori
6693 case 'N': // Constant -1 to -65535
6694 case 'O': // A signed 15-bit constant
6695 case 'P': // A constant between 1 go 65535
6697 case 'R': // An address that can be used in a non-macro load or store
6698 Info.setAllowsMemory();
6701 if (Name[1] == 'C') { // An address usable by ll, and sc.
6702 Info.setAllowsMemory();
6703 Name++; // Skip over 'Z'.
6710 std::string convertConstraint(const char *&Constraint) const override {
6712 switch (*Constraint) {
6713 case 'Z': // Two-character constraint; add "^" hint for later parsing.
6714 if (Constraint[1] == 'C') {
6715 R = std::string("^") + std::string(Constraint, 2);
6721 return TargetInfo::convertConstraint(Constraint);
6724 const char *getClobbers() const override {
6725 // In GCC, $1 is not widely used in generated code (it's used only in a few
6726 // specific situations), so there is no real need for users to add it to
6727 // the clobbers list if they want to use it in their inline assembly code.
6729 // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6730 // code generation, so using it in inline assembly without adding it to the
6731 // clobbers list can cause conflicts between the inline assembly code and
6732 // the surrounding generated code.
6734 // Another problem is that LLVM is allowed to choose $1 for inline assembly
6735 // operands, which will conflict with the ".set at" assembler option (which
6736 // we use only for inline assembly, in order to maintain compatibility with
6737 // GCC) and will also conflict with the user's usage of $1.
6739 // The easiest way to avoid these conflicts and keep $1 as an allocatable
6740 // register for generated code is to automatically clobber $1 for all inline
6743 // FIXME: We should automatically clobber $1 only for inline assembly code
6744 // which actually uses it. This would allow LLVM to use $1 for inline
6745 // assembly operands if the user's assembly code doesn't use it.
6749 bool handleTargetFeatures(std::vector<std::string> &Features,
6750 DiagnosticsEngine &Diags) override {
6752 IsMicromips = false;
6753 IsNan2008 = isNaN2008Default();
6754 IsSingleFloat = false;
6755 FloatABI = HardFloat;
6757 HasFP64 = isFP64Default();
6759 for (const auto &Feature : Features) {
6760 if (Feature == "+single-float")
6761 IsSingleFloat = true;
6762 else if (Feature == "+soft-float")
6763 FloatABI = SoftFloat;
6764 else if (Feature == "+mips16")
6766 else if (Feature == "+micromips")
6768 else if (Feature == "+dsp")
6769 DspRev = std::max(DspRev, DSP1);
6770 else if (Feature == "+dspr2")
6771 DspRev = std::max(DspRev, DSP2);
6772 else if (Feature == "+msa")
6774 else if (Feature == "+fp64")
6776 else if (Feature == "-fp64")
6778 else if (Feature == "+nan2008")
6780 else if (Feature == "-nan2008")
6784 setDataLayoutString();
6789 int getEHDataRegisterNumber(unsigned RegNo) const override {
6790 if (RegNo == 0) return 4;
6791 if (RegNo == 1) return 5;
6795 bool isCLZForZeroUndef() const override { return false; }
6798 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6799 #define BUILTIN(ID, TYPE, ATTRS) \
6800 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6801 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6802 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6803 #include "clang/Basic/BuiltinsMips.def"
6806 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6808 Mips32TargetInfoBase(const llvm::Triple &Triple)
6809 : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6810 SizeType = UnsignedInt;
6811 PtrDiffType = SignedInt;
6812 Int64Type = SignedLongLong;
6813 IntMaxType = Int64Type;
6814 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6816 bool setABI(const std::string &Name) override {
6817 if (Name == "o32" || Name == "eabi") {
6823 void getTargetDefines(const LangOptions &Opts,
6824 MacroBuilder &Builder) const override {
6825 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6827 Builder.defineMacro("__mips", "32");
6828 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6830 const std::string& CPUStr = getCPU();
6831 if (CPUStr == "mips32")
6832 Builder.defineMacro("__mips_isa_rev", "1");
6833 else if (CPUStr == "mips32r2")
6834 Builder.defineMacro("__mips_isa_rev", "2");
6835 else if (CPUStr == "mips32r3")
6836 Builder.defineMacro("__mips_isa_rev", "3");
6837 else if (CPUStr == "mips32r5")
6838 Builder.defineMacro("__mips_isa_rev", "5");
6839 else if (CPUStr == "mips32r6")
6840 Builder.defineMacro("__mips_isa_rev", "6");
6843 Builder.defineMacro("__mips_o32");
6844 Builder.defineMacro("_ABIO32", "1");
6845 Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6847 else if (ABI == "eabi")
6848 Builder.defineMacro("__mips_eabi");
6850 llvm_unreachable("Invalid ABI for Mips32.");
6852 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6853 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6863 { { "t2" }, "$10" },
6864 { { "t3" }, "$11" },
6865 { { "t4" }, "$12" },
6866 { { "t5" }, "$13" },
6867 { { "t6" }, "$14" },
6868 { { "t7" }, "$15" },
6869 { { "s0" }, "$16" },
6870 { { "s1" }, "$17" },
6871 { { "s2" }, "$18" },
6872 { { "s3" }, "$19" },
6873 { { "s4" }, "$20" },
6874 { { "s5" }, "$21" },
6875 { { "s6" }, "$22" },
6876 { { "s7" }, "$23" },
6877 { { "t8" }, "$24" },
6878 { { "t9" }, "$25" },
6879 { { "k0" }, "$26" },
6880 { { "k1" }, "$27" },
6881 { { "gp" }, "$28" },
6882 { { "sp","$sp" }, "$29" },
6883 { { "fp","$fp" }, "$30" },
6886 return llvm::makeArrayRef(GCCRegAliases);
6890 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6891 void setDataLayoutString() override {
6892 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6896 Mips32EBTargetInfo(const llvm::Triple &Triple)
6897 : Mips32TargetInfoBase(Triple) {
6899 void getTargetDefines(const LangOptions &Opts,
6900 MacroBuilder &Builder) const override {
6901 DefineStd(Builder, "MIPSEB", Opts);
6902 Builder.defineMacro("_MIPSEB");
6903 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6907 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6908 void setDataLayoutString() override {
6909 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6913 Mips32ELTargetInfo(const llvm::Triple &Triple)
6914 : Mips32TargetInfoBase(Triple) {
6917 void getTargetDefines(const LangOptions &Opts,
6918 MacroBuilder &Builder) const override {
6919 DefineStd(Builder, "MIPSEL", Opts);
6920 Builder.defineMacro("_MIPSEL");
6921 Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6925 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6927 Mips64TargetInfoBase(const llvm::Triple &Triple)
6928 : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6929 LongDoubleWidth = LongDoubleAlign = 128;
6930 LongDoubleFormat = &llvm::APFloat::IEEEquad;
6931 if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6932 LongDoubleWidth = LongDoubleAlign = 64;
6933 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6936 SuitableAlign = 128;
6937 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6940 void setN64ABITypes() {
6941 LongWidth = LongAlign = 64;
6942 PointerWidth = PointerAlign = 64;
6943 SizeType = UnsignedLong;
6944 PtrDiffType = SignedLong;
6945 Int64Type = SignedLong;
6946 IntMaxType = Int64Type;
6949 void setN32ABITypes() {
6950 LongWidth = LongAlign = 32;
6951 PointerWidth = PointerAlign = 32;
6952 SizeType = UnsignedInt;
6953 PtrDiffType = SignedInt;
6954 Int64Type = SignedLongLong;
6955 IntMaxType = Int64Type;
6958 bool setABI(const std::string &Name) override {
6959 if (Name == "n32") {
6964 if (Name == "n64") {
6972 void getTargetDefines(const LangOptions &Opts,
6973 MacroBuilder &Builder) const override {
6974 MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6976 Builder.defineMacro("__mips", "64");
6977 Builder.defineMacro("__mips64");
6978 Builder.defineMacro("__mips64__");
6979 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6981 const std::string& CPUStr = getCPU();
6982 if (CPUStr == "mips64")
6983 Builder.defineMacro("__mips_isa_rev", "1");
6984 else if (CPUStr == "mips64r2")
6985 Builder.defineMacro("__mips_isa_rev", "2");
6986 else if (CPUStr == "mips64r3")
6987 Builder.defineMacro("__mips_isa_rev", "3");
6988 else if (CPUStr == "mips64r5")
6989 Builder.defineMacro("__mips_isa_rev", "5");
6990 else if (CPUStr == "mips64r6")
6991 Builder.defineMacro("__mips_isa_rev", "6");
6994 Builder.defineMacro("__mips_n32");
6995 Builder.defineMacro("_ABIN32", "2");
6996 Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6998 else if (ABI == "n64") {
6999 Builder.defineMacro("__mips_n64");
7000 Builder.defineMacro("_ABI64", "3");
7001 Builder.defineMacro("_MIPS_SIM", "_ABI64");
7004 llvm_unreachable("Invalid ABI for Mips64.");
7006 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
7008 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7009 static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
7019 { { "a6" }, "$10" },
7020 { { "a7" }, "$11" },
7021 { { "t0" }, "$12" },
7022 { { "t1" }, "$13" },
7023 { { "t2" }, "$14" },
7024 { { "t3" }, "$15" },
7025 { { "s0" }, "$16" },
7026 { { "s1" }, "$17" },
7027 { { "s2" }, "$18" },
7028 { { "s3" }, "$19" },
7029 { { "s4" }, "$20" },
7030 { { "s5" }, "$21" },
7031 { { "s6" }, "$22" },
7032 { { "s7" }, "$23" },
7033 { { "t8" }, "$24" },
7034 { { "t9" }, "$25" },
7035 { { "k0" }, "$26" },
7036 { { "k1" }, "$27" },
7037 { { "gp" }, "$28" },
7038 { { "sp","$sp" }, "$29" },
7039 { { "fp","$fp" }, "$30" },
7042 return llvm::makeArrayRef(GCCRegAliases);
7045 bool hasInt128Type() const override { return true; }
7048 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
7049 void setDataLayoutString() override {
7051 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7053 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7058 Mips64EBTargetInfo(const llvm::Triple &Triple)
7059 : Mips64TargetInfoBase(Triple) {}
7060 void getTargetDefines(const LangOptions &Opts,
7061 MacroBuilder &Builder) const override {
7062 DefineStd(Builder, "MIPSEB", Opts);
7063 Builder.defineMacro("_MIPSEB");
7064 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7068 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
7069 void setDataLayoutString() override {
7071 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7073 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
7076 Mips64ELTargetInfo(const llvm::Triple &Triple)
7077 : Mips64TargetInfoBase(Triple) {
7078 // Default ABI is n64.
7081 void getTargetDefines(const LangOptions &Opts,
7082 MacroBuilder &Builder) const override {
7083 DefineStd(Builder, "MIPSEL", Opts);
7084 Builder.defineMacro("_MIPSEL");
7085 Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
7089 class PNaClTargetInfo : public TargetInfo {
7091 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7093 this->UserLabelPrefix = "";
7094 this->LongAlign = 32;
7095 this->LongWidth = 32;
7096 this->PointerAlign = 32;
7097 this->PointerWidth = 32;
7098 this->IntMaxType = TargetInfo::SignedLongLong;
7099 this->Int64Type = TargetInfo::SignedLongLong;
7100 this->DoubleAlign = 64;
7101 this->LongDoubleWidth = 64;
7102 this->LongDoubleAlign = 64;
7103 this->SizeType = TargetInfo::UnsignedInt;
7104 this->PtrDiffType = TargetInfo::SignedInt;
7105 this->IntPtrType = TargetInfo::SignedInt;
7106 this->RegParmMax = 0; // Disallow regparm
7109 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
7110 Builder.defineMacro("__le32__");
7111 Builder.defineMacro("__pnacl__");
7113 void getTargetDefines(const LangOptions &Opts,
7114 MacroBuilder &Builder) const override {
7115 getArchDefines(Opts, Builder);
7117 bool hasFeature(StringRef Feature) const override {
7118 return Feature == "pnacl";
7120 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7121 BuiltinVaListKind getBuiltinVaListKind() const override {
7122 return TargetInfo::PNaClABIBuiltinVaList;
7124 ArrayRef<const char *> getGCCRegNames() const override;
7125 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
7126 bool validateAsmConstraint(const char *&Name,
7127 TargetInfo::ConstraintInfo &Info) const override {
7131 const char *getClobbers() const override {
7136 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7140 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7144 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7145 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
7147 NaClMips32ELTargetInfo(const llvm::Triple &Triple) :
7148 Mips32ELTargetInfo(Triple) {
7151 BuiltinVaListKind getBuiltinVaListKind() const override {
7152 return TargetInfo::PNaClABIBuiltinVaList;
7156 class Le64TargetInfo : public TargetInfo {
7157 static const Builtin::Info BuiltinInfo[];
7160 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7162 NoAsmVariants = true;
7163 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7164 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7165 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
7168 void getTargetDefines(const LangOptions &Opts,
7169 MacroBuilder &Builder) const override {
7170 DefineStd(Builder, "unix", Opts);
7171 defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7172 Builder.defineMacro("__ELF__");
7174 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7175 return llvm::makeArrayRef(BuiltinInfo,
7176 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
7178 BuiltinVaListKind getBuiltinVaListKind() const override {
7179 return TargetInfo::PNaClABIBuiltinVaList;
7181 const char *getClobbers() const override { return ""; }
7182 ArrayRef<const char *> getGCCRegNames() const override {
7185 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7188 bool validateAsmConstraint(const char *&Name,
7189 TargetInfo::ConstraintInfo &Info) const override {
7193 bool hasProtectedVisibility() const override { return false; }
7196 class WebAssemblyTargetInfo : public TargetInfo {
7197 static const Builtin::Info BuiltinInfo[];
7205 explicit WebAssemblyTargetInfo(const llvm::Triple &T)
7206 : TargetInfo(T), SIMDLevel(NoSIMD) {
7208 NoAsmVariants = true;
7209 SuitableAlign = 128;
7210 LargeArrayMinWidth = 128;
7211 LargeArrayAlign = 128;
7212 SimdDefaultAlign = 128;
7213 SigAtomicType = SignedLong;
7214 LongDoubleWidth = LongDoubleAlign = 128;
7215 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7219 void getTargetDefines(const LangOptions &Opts,
7220 MacroBuilder &Builder) const override {
7221 defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
7222 if (SIMDLevel >= SIMD128)
7223 Builder.defineMacro("__wasm_simd128__");
7228 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7230 const std::vector<std::string> &FeaturesVec) const override {
7231 if (CPU == "bleeding-edge")
7232 Features["simd128"] = true;
7233 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7235 bool hasFeature(StringRef Feature) const final {
7236 return llvm::StringSwitch<bool>(Feature)
7237 .Case("simd128", SIMDLevel >= SIMD128)
7240 bool handleTargetFeatures(std::vector<std::string> &Features,
7241 DiagnosticsEngine &Diags) final {
7242 for (const auto &Feature : Features) {
7243 if (Feature == "+simd128") {
7244 SIMDLevel = std::max(SIMDLevel, SIMD128);
7247 if (Feature == "-simd128") {
7248 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
7252 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
7253 << "-target-feature";
7258 bool setCPU(const std::string &Name) final {
7259 return llvm::StringSwitch<bool>(Name)
7261 .Case("bleeding-edge", true)
7262 .Case("generic", true)
7265 ArrayRef<Builtin::Info> getTargetBuiltins() const final {
7266 return llvm::makeArrayRef(BuiltinInfo,
7267 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
7269 BuiltinVaListKind getBuiltinVaListKind() const final {
7270 return VoidPtrBuiltinVaList;
7272 ArrayRef<const char *> getGCCRegNames() const final {
7275 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
7279 validateAsmConstraint(const char *&Name,
7280 TargetInfo::ConstraintInfo &Info) const final {
7283 const char *getClobbers() const final { return ""; }
7284 bool isCLZForZeroUndef() const final { return false; }
7285 bool hasInt128Type() const final { return true; }
7286 IntType getIntTypeByWidth(unsigned BitWidth,
7287 bool IsSigned) const final {
7288 // WebAssembly prefers long long for explicitly 64-bit integers.
7289 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7290 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
7292 IntType getLeastIntTypeByWidth(unsigned BitWidth,
7293 bool IsSigned) const final {
7294 // WebAssembly uses long long for int_least64_t and int_fast64_t.
7295 return BitWidth == 64
7296 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7297 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
7301 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
7302 #define BUILTIN(ID, TYPE, ATTRS) \
7303 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7304 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7305 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7306 #include "clang/Basic/BuiltinsWebAssembly.def"
7309 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
7311 explicit WebAssembly32TargetInfo(const llvm::Triple &T)
7312 : WebAssemblyTargetInfo(T) {
7313 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7314 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128";
7318 void getTargetDefines(const LangOptions &Opts,
7319 MacroBuilder &Builder) const override {
7320 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7321 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
7325 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
7327 explicit WebAssembly64TargetInfo(const llvm::Triple &T)
7328 : WebAssemblyTargetInfo(T) {
7329 LongAlign = LongWidth = 64;
7330 PointerAlign = PointerWidth = 64;
7331 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7332 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128";
7336 void getTargetDefines(const LangOptions &Opts,
7337 MacroBuilder &Builder) const override {
7338 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7339 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
7343 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
7344 #define BUILTIN(ID, TYPE, ATTRS) \
7345 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7346 #include "clang/Basic/BuiltinsLe64.def"
7349 static const unsigned SPIRAddrSpaceMap[] = {
7352 2, // opencl_constant
7353 4, // opencl_generic
7358 class SPIRTargetInfo : public TargetInfo {
7360 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7361 assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
7362 "SPIR target must use unknown OS");
7363 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
7364 "SPIR target must use unknown environment type");
7366 TLSSupported = false;
7367 LongWidth = LongAlign = 64;
7368 AddrSpaceMap = &SPIRAddrSpaceMap;
7369 UseAddrSpaceMapMangling = true;
7370 // Define available target features
7371 // These must be defined in sorted order!
7372 NoAsmVariants = true;
7374 void getTargetDefines(const LangOptions &Opts,
7375 MacroBuilder &Builder) const override {
7376 DefineStd(Builder, "SPIR", Opts);
7378 bool hasFeature(StringRef Feature) const override {
7379 return Feature == "spir";
7382 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7383 const char *getClobbers() const override { return ""; }
7384 ArrayRef<const char *> getGCCRegNames() const override { return None; }
7385 bool validateAsmConstraint(const char *&Name,
7386 TargetInfo::ConstraintInfo &info) const override {
7389 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7392 BuiltinVaListKind getBuiltinVaListKind() const override {
7393 return TargetInfo::VoidPtrBuiltinVaList;
7396 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7397 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK
7401 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
7402 return CC_SpirFunction;
7406 class SPIR32TargetInfo : public SPIRTargetInfo {
7408 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7409 PointerWidth = PointerAlign = 32;
7410 SizeType = TargetInfo::UnsignedInt;
7411 PtrDiffType = IntPtrType = TargetInfo::SignedInt;
7412 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
7413 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7415 void getTargetDefines(const LangOptions &Opts,
7416 MacroBuilder &Builder) const override {
7417 DefineStd(Builder, "SPIR32", Opts);
7421 class SPIR64TargetInfo : public SPIRTargetInfo {
7423 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7424 PointerWidth = PointerAlign = 64;
7425 SizeType = TargetInfo::UnsignedLong;
7426 PtrDiffType = IntPtrType = TargetInfo::SignedLong;
7427 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
7428 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7430 void getTargetDefines(const LangOptions &Opts,
7431 MacroBuilder &Builder) const override {
7432 DefineStd(Builder, "SPIR64", Opts);
7436 class XCoreTargetInfo : public TargetInfo {
7437 static const Builtin::Info BuiltinInfo[];
7439 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7441 NoAsmVariants = true;
7444 DoubleAlign = LongDoubleAlign = 32;
7445 SizeType = UnsignedInt;
7446 PtrDiffType = SignedInt;
7447 IntPtrType = SignedInt;
7448 WCharType = UnsignedChar;
7449 WIntType = UnsignedInt;
7450 UseZeroLengthBitfieldAlignment = true;
7451 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
7452 "-f64:32-a:0:32-n32";
7454 void getTargetDefines(const LangOptions &Opts,
7455 MacroBuilder &Builder) const override {
7456 Builder.defineMacro("__XS1B__");
7458 ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7459 return llvm::makeArrayRef(BuiltinInfo,
7460 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
7462 BuiltinVaListKind getBuiltinVaListKind() const override {
7463 return TargetInfo::VoidPtrBuiltinVaList;
7465 const char *getClobbers() const override {
7468 ArrayRef<const char *> getGCCRegNames() const override {
7469 static const char * const GCCRegNames[] = {
7470 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7471 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
7473 return llvm::makeArrayRef(GCCRegNames);
7475 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7478 bool validateAsmConstraint(const char *&Name,
7479 TargetInfo::ConstraintInfo &Info) const override {
7482 int getEHDataRegisterNumber(unsigned RegNo) const override {
7483 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
7484 return (RegNo < 2)? RegNo : -1;
7488 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
7489 #define BUILTIN(ID, TYPE, ATTRS) \
7490 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7491 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7492 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7493 #include "clang/Basic/BuiltinsXCore.def"
7496 // x86_32 Android target
7497 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
7499 AndroidX86_32TargetInfo(const llvm::Triple &Triple)
7500 : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
7502 LongDoubleWidth = 64;
7503 LongDoubleFormat = &llvm::APFloat::IEEEdouble;
7507 // x86_64 Android target
7508 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
7510 AndroidX86_64TargetInfo(const llvm::Triple &Triple)
7511 : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
7512 LongDoubleFormat = &llvm::APFloat::IEEEquad;
7515 bool useFloat128ManglingForLongDouble() const override {
7519 } // end anonymous namespace
7521 //===----------------------------------------------------------------------===//
7523 //===----------------------------------------------------------------------===//
7525 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
7526 llvm::Triple::OSType os = Triple.getOS();
7528 switch (Triple.getArch()) {
7532 case llvm::Triple::xcore:
7533 return new XCoreTargetInfo(Triple);
7535 case llvm::Triple::hexagon:
7536 return new HexagonTargetInfo(Triple);
7538 case llvm::Triple::aarch64:
7539 if (Triple.isOSDarwin())
7540 return new DarwinAArch64TargetInfo(Triple);
7543 case llvm::Triple::CloudABI:
7544 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple);
7545 case llvm::Triple::FreeBSD:
7546 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
7547 case llvm::Triple::Linux:
7548 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
7549 case llvm::Triple::NetBSD:
7550 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
7552 return new AArch64leTargetInfo(Triple);
7555 case llvm::Triple::aarch64_be:
7557 case llvm::Triple::FreeBSD:
7558 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
7559 case llvm::Triple::Linux:
7560 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
7561 case llvm::Triple::NetBSD:
7562 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
7564 return new AArch64beTargetInfo(Triple);
7567 case llvm::Triple::arm:
7568 case llvm::Triple::thumb:
7569 if (Triple.isOSBinFormatMachO())
7570 return new DarwinARMTargetInfo(Triple);
7573 case llvm::Triple::Linux:
7574 return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
7575 case llvm::Triple::FreeBSD:
7576 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
7577 case llvm::Triple::NetBSD:
7578 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
7579 case llvm::Triple::OpenBSD:
7580 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
7581 case llvm::Triple::Bitrig:
7582 return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
7583 case llvm::Triple::RTEMS:
7584 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
7585 case llvm::Triple::NaCl:
7586 return new NaClTargetInfo<ARMleTargetInfo>(Triple);
7587 case llvm::Triple::Win32:
7588 switch (Triple.getEnvironment()) {
7589 case llvm::Triple::Cygnus:
7590 return new CygwinARMTargetInfo(Triple);
7591 case llvm::Triple::GNU:
7592 return new MinGWARMTargetInfo(Triple);
7593 case llvm::Triple::Itanium:
7594 return new ItaniumWindowsARMleTargetInfo(Triple);
7595 case llvm::Triple::MSVC:
7596 default: // Assume MSVC for unknown environments
7597 return new MicrosoftARMleTargetInfo(Triple);
7600 return new ARMleTargetInfo(Triple);
7603 case llvm::Triple::armeb:
7604 case llvm::Triple::thumbeb:
7605 if (Triple.isOSDarwin())
7606 return new DarwinARMTargetInfo(Triple);
7609 case llvm::Triple::Linux:
7610 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
7611 case llvm::Triple::FreeBSD:
7612 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
7613 case llvm::Triple::NetBSD:
7614 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
7615 case llvm::Triple::OpenBSD:
7616 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
7617 case llvm::Triple::Bitrig:
7618 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
7619 case llvm::Triple::RTEMS:
7620 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
7621 case llvm::Triple::NaCl:
7622 return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
7624 return new ARMbeTargetInfo(Triple);
7627 case llvm::Triple::bpfeb:
7628 case llvm::Triple::bpfel:
7629 return new BPFTargetInfo(Triple);
7631 case llvm::Triple::msp430:
7632 return new MSP430TargetInfo(Triple);
7634 case llvm::Triple::mips:
7636 case llvm::Triple::Linux:
7637 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
7638 case llvm::Triple::RTEMS:
7639 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
7640 case llvm::Triple::FreeBSD:
7641 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7642 case llvm::Triple::NetBSD:
7643 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7645 return new Mips32EBTargetInfo(Triple);
7648 case llvm::Triple::mipsel:
7650 case llvm::Triple::Linux:
7651 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
7652 case llvm::Triple::RTEMS:
7653 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7654 case llvm::Triple::FreeBSD:
7655 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7656 case llvm::Triple::NetBSD:
7657 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7658 case llvm::Triple::NaCl:
7659 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple);
7661 return new Mips32ELTargetInfo(Triple);
7664 case llvm::Triple::mips64:
7666 case llvm::Triple::Linux:
7667 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7668 case llvm::Triple::RTEMS:
7669 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7670 case llvm::Triple::FreeBSD:
7671 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7672 case llvm::Triple::NetBSD:
7673 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7674 case llvm::Triple::OpenBSD:
7675 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7677 return new Mips64EBTargetInfo(Triple);
7680 case llvm::Triple::mips64el:
7682 case llvm::Triple::Linux:
7683 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7684 case llvm::Triple::RTEMS:
7685 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7686 case llvm::Triple::FreeBSD:
7687 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7688 case llvm::Triple::NetBSD:
7689 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7690 case llvm::Triple::OpenBSD:
7691 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7693 return new Mips64ELTargetInfo(Triple);
7696 case llvm::Triple::le32:
7698 case llvm::Triple::NaCl:
7699 return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7704 case llvm::Triple::le64:
7705 return new Le64TargetInfo(Triple);
7707 case llvm::Triple::ppc:
7708 if (Triple.isOSDarwin())
7709 return new DarwinPPC32TargetInfo(Triple);
7711 case llvm::Triple::Linux:
7712 return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7713 case llvm::Triple::FreeBSD:
7714 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7715 case llvm::Triple::NetBSD:
7716 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7717 case llvm::Triple::OpenBSD:
7718 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7719 case llvm::Triple::RTEMS:
7720 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7722 return new PPC32TargetInfo(Triple);
7725 case llvm::Triple::ppc64:
7726 if (Triple.isOSDarwin())
7727 return new DarwinPPC64TargetInfo(Triple);
7729 case llvm::Triple::Linux:
7730 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7731 case llvm::Triple::Lv2:
7732 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7733 case llvm::Triple::FreeBSD:
7734 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7735 case llvm::Triple::NetBSD:
7736 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7738 return new PPC64TargetInfo(Triple);
7741 case llvm::Triple::ppc64le:
7743 case llvm::Triple::Linux:
7744 return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7745 case llvm::Triple::NetBSD:
7746 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7748 return new PPC64TargetInfo(Triple);
7751 case llvm::Triple::nvptx:
7752 return new NVPTX32TargetInfo(Triple);
7753 case llvm::Triple::nvptx64:
7754 return new NVPTX64TargetInfo(Triple);
7756 case llvm::Triple::amdgcn:
7757 case llvm::Triple::r600:
7758 return new AMDGPUTargetInfo(Triple);
7760 case llvm::Triple::sparc:
7762 case llvm::Triple::Linux:
7763 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7764 case llvm::Triple::Solaris:
7765 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7766 case llvm::Triple::NetBSD:
7767 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7768 case llvm::Triple::OpenBSD:
7769 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7770 case llvm::Triple::RTEMS:
7771 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7773 return new SparcV8TargetInfo(Triple);
7776 // The 'sparcel' architecture copies all the above cases except for Solaris.
7777 case llvm::Triple::sparcel:
7779 case llvm::Triple::Linux:
7780 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7781 case llvm::Triple::NetBSD:
7782 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7783 case llvm::Triple::OpenBSD:
7784 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7785 case llvm::Triple::RTEMS:
7786 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7788 return new SparcV8elTargetInfo(Triple);
7791 case llvm::Triple::sparcv9:
7793 case llvm::Triple::Linux:
7794 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7795 case llvm::Triple::Solaris:
7796 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7797 case llvm::Triple::NetBSD:
7798 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7799 case llvm::Triple::OpenBSD:
7800 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7801 case llvm::Triple::FreeBSD:
7802 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7804 return new SparcV9TargetInfo(Triple);
7807 case llvm::Triple::systemz:
7809 case llvm::Triple::Linux:
7810 return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7812 return new SystemZTargetInfo(Triple);
7815 case llvm::Triple::tce:
7816 return new TCETargetInfo(Triple);
7818 case llvm::Triple::x86:
7819 if (Triple.isOSDarwin())
7820 return new DarwinI386TargetInfo(Triple);
7823 case llvm::Triple::CloudABI:
7824 return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7825 case llvm::Triple::Linux: {
7826 switch (Triple.getEnvironment()) {
7828 return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7829 case llvm::Triple::Android:
7830 return new AndroidX86_32TargetInfo(Triple);
7833 case llvm::Triple::DragonFly:
7834 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7835 case llvm::Triple::NetBSD:
7836 return new NetBSDI386TargetInfo(Triple);
7837 case llvm::Triple::OpenBSD:
7838 return new OpenBSDI386TargetInfo(Triple);
7839 case llvm::Triple::Bitrig:
7840 return new BitrigI386TargetInfo(Triple);
7841 case llvm::Triple::FreeBSD:
7842 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7843 case llvm::Triple::KFreeBSD:
7844 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7845 case llvm::Triple::Minix:
7846 return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7847 case llvm::Triple::Solaris:
7848 return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7849 case llvm::Triple::Win32: {
7850 switch (Triple.getEnvironment()) {
7851 case llvm::Triple::Cygnus:
7852 return new CygwinX86_32TargetInfo(Triple);
7853 case llvm::Triple::GNU:
7854 return new MinGWX86_32TargetInfo(Triple);
7855 case llvm::Triple::Itanium:
7856 case llvm::Triple::MSVC:
7857 default: // Assume MSVC for unknown environments
7858 return new MicrosoftX86_32TargetInfo(Triple);
7861 case llvm::Triple::Haiku:
7862 return new HaikuX86_32TargetInfo(Triple);
7863 case llvm::Triple::RTEMS:
7864 return new RTEMSX86_32TargetInfo(Triple);
7865 case llvm::Triple::NaCl:
7866 return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7867 case llvm::Triple::ELFIAMCU:
7868 return new MCUX86_32TargetInfo(Triple);
7870 return new X86_32TargetInfo(Triple);
7873 case llvm::Triple::x86_64:
7874 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7875 return new DarwinX86_64TargetInfo(Triple);
7878 case llvm::Triple::CloudABI:
7879 return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7880 case llvm::Triple::Linux: {
7881 switch (Triple.getEnvironment()) {
7883 return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7884 case llvm::Triple::Android:
7885 return new AndroidX86_64TargetInfo(Triple);
7888 case llvm::Triple::DragonFly:
7889 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7890 case llvm::Triple::NetBSD:
7891 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7892 case llvm::Triple::OpenBSD:
7893 return new OpenBSDX86_64TargetInfo(Triple);
7894 case llvm::Triple::Bitrig:
7895 return new BitrigX86_64TargetInfo(Triple);
7896 case llvm::Triple::FreeBSD:
7897 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7898 case llvm::Triple::KFreeBSD:
7899 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7900 case llvm::Triple::Solaris:
7901 return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7902 case llvm::Triple::Win32: {
7903 switch (Triple.getEnvironment()) {
7904 case llvm::Triple::Cygnus:
7905 return new CygwinX86_64TargetInfo(Triple);
7906 case llvm::Triple::GNU:
7907 return new MinGWX86_64TargetInfo(Triple);
7908 case llvm::Triple::MSVC:
7909 default: // Assume MSVC for unknown environments
7910 return new MicrosoftX86_64TargetInfo(Triple);
7913 case llvm::Triple::NaCl:
7914 return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7915 case llvm::Triple::PS4:
7916 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7918 return new X86_64TargetInfo(Triple);
7921 case llvm::Triple::spir: {
7922 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7923 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7925 return new SPIR32TargetInfo(Triple);
7927 case llvm::Triple::spir64: {
7928 if (Triple.getOS() != llvm::Triple::UnknownOS ||
7929 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7931 return new SPIR64TargetInfo(Triple);
7933 case llvm::Triple::wasm32:
7934 if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
7936 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple);
7937 case llvm::Triple::wasm64:
7938 if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
7940 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple);
7944 /// CreateTargetInfo - Return the target info object for the specified target
7947 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7948 const std::shared_ptr<TargetOptions> &Opts) {
7949 llvm::Triple Triple(Opts->Triple);
7951 // Construct the target
7952 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7954 Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7957 Target->TargetOpts = Opts;
7959 // Set the target CPU if specified.
7960 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7961 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7965 // Set the target ABI if specified.
7966 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7967 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7971 // Set the fp math unit.
7972 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7973 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7977 // Compute the default target features, we need the target to handle this
7978 // because features may have dependencies on one another.
7979 llvm::StringMap<bool> Features;
7980 if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
7981 Opts->FeaturesAsWritten))
7984 // Add the features to the compile options.
7985 Opts->Features.clear();
7986 for (const auto &F : Features)
7987 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
7989 if (!Target->handleTargetFeatures(Opts->Features, Diags))
7992 return Target.release();