2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2003 Peter Wemm
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 * Copyright (c) 2014 Andrew Turner
13 * All rights reserved.
14 * Copyright (c) 2014-2016 The FreeBSD Foundation
15 * All rights reserved.
17 * This code is derived from software contributed to Berkeley by
18 * the Systems Programming Group of the University of Utah Computer
19 * Science Department and William Jolitz of UUNET Technologies Inc.
21 * This software was developed by Andrew Turner under sponsorship from
22 * the FreeBSD Foundation.
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
27 * 1. Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. All advertising materials mentioning features or use of this software
33 * must display the following acknowledgement:
34 * This product includes software developed by the University of
35 * California, Berkeley and its contributors.
36 * 4. Neither the name of the University nor the names of its contributors
37 * may be used to endorse or promote products derived from this software
38 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
55 * Copyright (c) 2003 Networks Associates Technology, Inc.
56 * All rights reserved.
58 * This software was developed for the FreeBSD Project by Jake Burkholder,
59 * Safeport Network Services, and Network Associates Laboratories, the
60 * Security Research Division of Network Associates, Inc. under
61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
62 * CHATS research program.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is
93 * also stored by the logical address mapping module,
94 * this module may throw away valid virtual-to-physical
95 * mappings at almost any time. However, invalidations
96 * of virtual-to-physical mappings must be done as
99 * In order to cope with hardware architectures which
100 * make virtual-to-physical map invalidates expensive,
101 * this module may delay invalidate or reduced protection
102 * operations until such time as they are actually
103 * necessary. This module is given full information as
104 * to which processors are currently using which maps,
105 * and to when physical maps must be made correct.
110 #include <sys/param.h>
111 #include <sys/bitstring.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/rwlock.h>
124 #include <sys/vmem.h>
125 #include <sys/vmmeter.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/_unrhdr.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_phys.h>
141 #include <vm/vm_radix.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/machdep.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
149 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t)))
150 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t)))
151 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t)))
152 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t)))
154 #define NUL0E L0_ENTRIES
155 #define NUL1E (NUL0E * NL1PG)
156 #define NUL2E (NUL1E * NL2PG)
158 #if !defined(DIAGNOSTIC)
159 #ifdef __GNUC_GNU_INLINE__
160 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
162 #define PMAP_INLINE extern inline
169 * These are configured by the mair_el1 register. This is set up in locore.S
171 #define DEVICE_MEMORY 0
172 #define UNCACHED_MEMORY 1
173 #define CACHED_MEMORY 2
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)])
185 #define NPV_LIST_LOCKS MAXCPU
187 #define PHYS_TO_PV_LIST_LOCK(pa) \
188 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
190 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
191 struct rwlock **_lockp = (lockp); \
192 struct rwlock *_new_lock; \
194 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
195 if (_new_lock != *_lockp) { \
196 if (*_lockp != NULL) \
197 rw_wunlock(*_lockp); \
198 *_lockp = _new_lock; \
203 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
204 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
206 #define RELEASE_PV_LIST_LOCK(lockp) do { \
207 struct rwlock **_lockp = (lockp); \
209 if (*_lockp != NULL) { \
210 rw_wunlock(*_lockp); \
215 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
216 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
218 struct pmap kernel_pmap_store;
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t kernel_vm_end = 0;
225 * Data for the pv entry allocation mechanism.
226 * Updates to pv_invl_gen are protected by the pv_list_locks[]
227 * elements, but reads are not.
229 static struct md_page *pv_table;
230 static struct md_page pv_dummy;
232 vm_paddr_t dmap_phys_base; /* The start of the dmap region */
233 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */
234 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */
236 /* This code assumes all L1 DMAP entries will be used */
237 CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS);
238 CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS);
240 #define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT)
241 extern pt_entry_t pagetable_dmap[];
243 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
245 static int superpages_enabled = 1;
246 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled,
247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0,
248 "Are large page mappings enabled?");
251 * Data for the pv entry allocation mechanism
253 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
254 static struct mtx pv_chunks_mutex;
255 static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
257 static void free_pv_chunk(struct pv_chunk *pc);
258 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
259 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
260 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
261 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
262 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
265 static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode);
266 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode);
267 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va);
268 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2,
269 vm_offset_t va, struct rwlock **lockp);
270 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va);
271 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
273 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
274 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp);
275 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva,
276 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp);
277 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
278 vm_page_t m, struct rwlock **lockp);
280 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex,
281 struct rwlock **lockp);
283 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m,
284 struct spglist *free);
285 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
286 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
289 * These load the old table data and store the new value.
290 * They need to be atomic as the System MMU may write to the table at
291 * the same time as the CPU.
293 #define pmap_load_store(table, entry) atomic_swap_64(table, entry)
294 #define pmap_set(table, mask) atomic_set_64(table, mask)
295 #define pmap_load_clear(table) atomic_swap_64(table, 0)
296 #define pmap_load(table) (*table)
298 /********************/
299 /* Inline functions */
300 /********************/
303 pagecopy(void *s, void *d)
306 memcpy(d, s, PAGE_SIZE);
309 static __inline pd_entry_t *
310 pmap_l0(pmap_t pmap, vm_offset_t va)
313 return (&pmap->pm_l0[pmap_l0_index(va)]);
316 static __inline pd_entry_t *
317 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va)
321 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
322 return (&l1[pmap_l1_index(va)]);
325 static __inline pd_entry_t *
326 pmap_l1(pmap_t pmap, vm_offset_t va)
330 l0 = pmap_l0(pmap, va);
331 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE)
334 return (pmap_l0_to_l1(l0, va));
337 static __inline pd_entry_t *
338 pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va)
342 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
343 return (&l2[pmap_l2_index(va)]);
346 static __inline pd_entry_t *
347 pmap_l2(pmap_t pmap, vm_offset_t va)
351 l1 = pmap_l1(pmap, va);
352 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE)
355 return (pmap_l1_to_l2(l1, va));
358 static __inline pt_entry_t *
359 pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va)
363 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK);
364 return (&l3[pmap_l3_index(va)]);
368 * Returns the lowest valid pde for a given virtual address.
369 * The next level may or may not point to a valid page or block.
371 static __inline pd_entry_t *
372 pmap_pde(pmap_t pmap, vm_offset_t va, int *level)
374 pd_entry_t *l0, *l1, *l2, desc;
376 l0 = pmap_l0(pmap, va);
377 desc = pmap_load(l0) & ATTR_DESCR_MASK;
378 if (desc != L0_TABLE) {
383 l1 = pmap_l0_to_l1(l0, va);
384 desc = pmap_load(l1) & ATTR_DESCR_MASK;
385 if (desc != L1_TABLE) {
390 l2 = pmap_l1_to_l2(l1, va);
391 desc = pmap_load(l2) & ATTR_DESCR_MASK;
392 if (desc != L2_TABLE) {
402 * Returns the lowest valid pte block or table entry for a given virtual
403 * address. If there are no valid entries return NULL and set the level to
404 * the first invalid level.
406 static __inline pt_entry_t *
407 pmap_pte(pmap_t pmap, vm_offset_t va, int *level)
409 pd_entry_t *l1, *l2, desc;
412 l1 = pmap_l1(pmap, va);
417 desc = pmap_load(l1) & ATTR_DESCR_MASK;
418 if (desc == L1_BLOCK) {
423 if (desc != L1_TABLE) {
428 l2 = pmap_l1_to_l2(l1, va);
429 desc = pmap_load(l2) & ATTR_DESCR_MASK;
430 if (desc == L2_BLOCK) {
435 if (desc != L2_TABLE) {
441 l3 = pmap_l2_to_l3(l2, va);
442 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE)
449 pmap_superpages_enabled(void)
452 return (superpages_enabled != 0);
456 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1,
457 pd_entry_t **l2, pt_entry_t **l3)
459 pd_entry_t *l0p, *l1p, *l2p;
461 if (pmap->pm_l0 == NULL)
464 l0p = pmap_l0(pmap, va);
467 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE)
470 l1p = pmap_l0_to_l1(l0p, va);
473 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) {
479 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE)
482 l2p = pmap_l1_to_l2(l1p, va);
485 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) {
490 *l3 = pmap_l2_to_l3(l2p, va);
496 pmap_l3_valid(pt_entry_t l3)
499 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE);
503 CTASSERT(L1_BLOCK == L2_BLOCK);
506 * Checks if the page is dirty. We currently lack proper tracking of this on
507 * arm64 so for now assume is a page mapped as rw was accessed it is.
510 pmap_page_dirty(pt_entry_t pte)
513 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) ==
514 (ATTR_AF | ATTR_AP(ATTR_AP_RW)));
518 pmap_resident_count_inc(pmap_t pmap, int count)
521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
522 pmap->pm_stats.resident_count += count;
526 pmap_resident_count_dec(pmap_t pmap, int count)
529 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
530 KASSERT(pmap->pm_stats.resident_count >= count,
531 ("pmap %p resident count underflow %ld %d", pmap,
532 pmap->pm_stats.resident_count, count));
533 pmap->pm_stats.resident_count -= count;
537 pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot,
543 l1 = (pd_entry_t *)l1pt;
544 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK;
546 /* Check locore has used a table L1 map */
547 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE,
548 ("Invalid bootstrap L1 table"));
549 /* Find the address of the L2 table */
550 l2 = (pt_entry_t *)init_pt_va;
551 *l2_slot = pmap_l2_index(va);
557 pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va)
559 u_int l1_slot, l2_slot;
562 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot);
564 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET));
568 pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa)
574 pa = dmap_phys_base = min_pa & ~L1_OFFSET;
575 va = DMAP_MIN_ADDRESS;
576 for (; va < DMAP_MAX_ADDRESS && pa < max_pa;
577 pa += L1_SIZE, va += L1_SIZE, l1_slot++) {
578 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT);
580 pmap_load_store(&pagetable_dmap[l1_slot],
581 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN |
582 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK);
585 /* Set the upper limit of the DMAP region */
593 pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start)
600 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address"));
602 l1 = (pd_entry_t *)l1pt;
603 l1_slot = pmap_l1_index(va);
606 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) {
607 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index"));
609 pa = pmap_early_vtophys(l1pt, l2pt);
610 pmap_load_store(&l1[l1_slot],
611 (pa & ~Ln_TABLE_MASK) | L1_TABLE);
615 /* Clean the L2 page table */
616 memset((void *)l2_start, 0, l2pt - l2_start);
622 pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start)
629 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address"));
631 l2 = pmap_l2(kernel_pmap, va);
632 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE);
633 l2_slot = pmap_l2_index(va);
636 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) {
637 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index"));
639 pa = pmap_early_vtophys(l1pt, l3pt);
640 pmap_load_store(&l2[l2_slot],
641 (pa & ~Ln_TABLE_MASK) | L2_TABLE);
645 /* Clean the L2 page table */
646 memset((void *)l3_start, 0, l3pt - l3_start);
652 * Bootstrap the system enough to run with virtual memory.
655 pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart,
658 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot;
661 vm_offset_t va, freemempos;
662 vm_offset_t dpcpu, msgbufpv;
663 vm_paddr_t pa, max_pa, min_pa;
666 kern_delta = KERNBASE - kernstart;
669 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen);
670 printf("%lx\n", l1pt);
671 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK);
673 /* Set this early so we can use the pagetable walking functions */
674 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt;
675 PMAP_LOCK_INIT(kernel_pmap);
677 /* Assume the address we were loaded to is a valid physical address */
678 min_pa = max_pa = KERNBASE - kern_delta;
681 * Find the minimum physical address. physmap is sorted,
682 * but may contain empty ranges.
684 for (i = 0; i < (physmap_idx * 2); i += 2) {
685 if (physmap[i] == physmap[i + 1])
687 if (physmap[i] <= min_pa)
689 if (physmap[i + 1] > max_pa)
690 max_pa = physmap[i + 1];
693 /* Create a direct map region early so we can use it for pa -> va */
694 pmap_bootstrap_dmap(l1pt, min_pa, max_pa);
697 pa = KERNBASE - kern_delta;
700 * Start to initialise phys_avail by copying from physmap
701 * up to the physical address KERNBASE points at.
703 map_slot = avail_slot = 0;
704 for (; map_slot < (physmap_idx * 2) &&
705 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) {
706 if (physmap[map_slot] == physmap[map_slot + 1])
709 if (physmap[map_slot] <= pa &&
710 physmap[map_slot + 1] > pa)
713 phys_avail[avail_slot] = physmap[map_slot];
714 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
715 physmem += (phys_avail[avail_slot + 1] -
716 phys_avail[avail_slot]) >> PAGE_SHIFT;
720 /* Add the memory before the kernel */
721 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) {
722 phys_avail[avail_slot] = physmap[map_slot];
723 phys_avail[avail_slot + 1] = pa;
724 physmem += (phys_avail[avail_slot + 1] -
725 phys_avail[avail_slot]) >> PAGE_SHIFT;
728 used_map_slot = map_slot;
731 * Read the page table to find out what is already mapped.
732 * This assumes we have mapped a block of memory from KERNBASE
733 * using a single L1 entry.
735 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot);
737 /* Sanity check the index, KERNBASE should be the first VA */
738 KASSERT(l2_slot == 0, ("The L2 index is non-zero"));
740 /* Find how many pages we have mapped */
741 for (; l2_slot < Ln_ENTRIES; l2_slot++) {
742 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0)
745 /* Check locore used L2 blocks */
746 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK,
747 ("Invalid bootstrap L2 table"));
748 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa,
749 ("Incorrect PA in L2 table"));
755 va = roundup2(va, L1_SIZE);
757 freemempos = KERNBASE + kernlen;
758 freemempos = roundup2(freemempos, PAGE_SIZE);
759 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */
760 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos);
761 /* And the l3 tables for the early devmap */
762 freemempos = pmap_bootstrap_l3(l1pt,
763 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos);
767 #define alloc_pages(var, np) \
768 (var) = freemempos; \
769 freemempos += (np * PAGE_SIZE); \
770 memset((char *)(var), 0, ((np) * PAGE_SIZE));
772 /* Allocate dynamic per-cpu area. */
773 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
774 dpcpu_init((void *)dpcpu, 0);
776 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */
777 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
778 msgbufp = (void *)msgbufpv;
780 virtual_avail = roundup2(freemempos, L1_SIZE);
781 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE;
782 kernel_vm_end = virtual_avail;
784 pa = pmap_early_vtophys(l1pt, freemempos);
786 /* Finish initialising physmap */
787 map_slot = used_map_slot;
788 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) &&
789 map_slot < (physmap_idx * 2); map_slot += 2) {
790 if (physmap[map_slot] == physmap[map_slot + 1])
793 /* Have we used the current range? */
794 if (physmap[map_slot + 1] <= pa)
797 /* Do we need to split the entry? */
798 if (physmap[map_slot] < pa) {
799 phys_avail[avail_slot] = pa;
800 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
802 phys_avail[avail_slot] = physmap[map_slot];
803 phys_avail[avail_slot + 1] = physmap[map_slot + 1];
805 physmem += (phys_avail[avail_slot + 1] -
806 phys_avail[avail_slot]) >> PAGE_SHIFT;
810 phys_avail[avail_slot] = 0;
811 phys_avail[avail_slot + 1] = 0;
814 * Maxmem isn't the "maximum memory", it's one larger than the
815 * highest page of the physical address space. It should be
816 * called something like "Maxphyspage".
818 Maxmem = atop(phys_avail[avail_slot - 1]);
824 * Initialize a vm_page's machine-dependent fields.
827 pmap_page_init(vm_page_t m)
830 TAILQ_INIT(&m->md.pv_list);
831 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK;
835 * Initialize the pmap module.
836 * Called by vm_init, to initialize any structures that the pmap
837 * system needs to map virtual memory.
846 * Are large page mappings enabled?
848 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled);
851 * Initialize the pv chunk list mutex.
853 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
856 * Initialize the pool of pv list locks.
858 for (i = 0; i < NPV_LIST_LOCKS; i++)
859 rw_init(&pv_list_locks[i], "pmap pv list");
862 * Calculate the size of the pv head table for superpages.
864 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE);
867 * Allocate memory for the pv head table for superpages.
869 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
871 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
873 for (i = 0; i < pv_npg; i++)
874 TAILQ_INIT(&pv_table[i].pv_list);
875 TAILQ_INIT(&pv_dummy.pv_list);
878 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0,
879 "2MB page mapping counters");
881 static u_long pmap_l2_demotions;
882 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD,
883 &pmap_l2_demotions, 0, "2MB page demotions");
885 static u_long pmap_l2_p_failures;
886 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD,
887 &pmap_l2_p_failures, 0, "2MB page promotion failures");
889 static u_long pmap_l2_promotions;
890 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD,
891 &pmap_l2_promotions, 0, "2MB page promotions");
894 * Invalidate a single TLB entry.
897 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
903 "tlbi vaae1is, %0 \n"
906 : : "r"(va >> PAGE_SHIFT));
911 pmap_invalidate_range_nopin(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
916 for (addr = sva; addr < eva; addr += PAGE_SIZE) {
918 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT));
926 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
930 pmap_invalidate_range_nopin(pmap, sva, eva);
935 pmap_invalidate_all(pmap_t pmap)
948 * Routine: pmap_extract
950 * Extract the physical page address associated
951 * with the given map/virtual_address pair.
954 pmap_extract(pmap_t pmap, vm_offset_t va)
956 pt_entry_t *pte, tpte;
963 * Find the block or page map for this virtual address. pmap_pte
964 * will return either a valid block/page entry, or NULL.
966 pte = pmap_pte(pmap, va, &lvl);
968 tpte = pmap_load(pte);
969 pa = tpte & ~ATTR_MASK;
972 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
973 ("pmap_extract: Invalid L1 pte found: %lx",
974 tpte & ATTR_DESCR_MASK));
975 pa |= (va & L1_OFFSET);
978 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
979 ("pmap_extract: Invalid L2 pte found: %lx",
980 tpte & ATTR_DESCR_MASK));
981 pa |= (va & L2_OFFSET);
984 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
985 ("pmap_extract: Invalid L3 pte found: %lx",
986 tpte & ATTR_DESCR_MASK));
987 pa |= (va & L3_OFFSET);
996 * Routine: pmap_extract_and_hold
998 * Atomically extract and hold the physical page
999 * with the given pmap and virtual address pair
1000 * if that mapping permits the given protection.
1003 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1005 pt_entry_t *pte, tpte;
1015 pte = pmap_pte(pmap, va, &lvl);
1017 tpte = pmap_load(pte);
1019 KASSERT(lvl > 0 && lvl <= 3,
1020 ("pmap_extract_and_hold: Invalid level %d", lvl));
1021 CTASSERT(L1_BLOCK == L2_BLOCK);
1022 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) ||
1023 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK),
1024 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl,
1025 tpte & ATTR_DESCR_MASK));
1026 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) ||
1027 ((prot & VM_PROT_WRITE) == 0)) {
1030 off = va & L1_OFFSET;
1033 off = va & L2_OFFSET;
1039 if (vm_page_pa_tryrelock(pmap,
1040 (tpte & ~ATTR_MASK) | off, &pa))
1042 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off);
1052 pmap_kextract(vm_offset_t va)
1054 pt_entry_t *pte, tpte;
1058 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
1059 pa = DMAP_TO_PHYS(va);
1062 pte = pmap_pte(kernel_pmap, va, &lvl);
1064 tpte = pmap_load(pte);
1065 pa = tpte & ~ATTR_MASK;
1068 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK,
1069 ("pmap_kextract: Invalid L1 pte found: %lx",
1070 tpte & ATTR_DESCR_MASK));
1071 pa |= (va & L1_OFFSET);
1074 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK,
1075 ("pmap_kextract: Invalid L2 pte found: %lx",
1076 tpte & ATTR_DESCR_MASK));
1077 pa |= (va & L2_OFFSET);
1080 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE,
1081 ("pmap_kextract: Invalid L3 pte found: %lx",
1082 tpte & ATTR_DESCR_MASK));
1083 pa |= (va & L3_OFFSET);
1091 /***************************************************
1092 * Low level mapping routines.....
1093 ***************************************************/
1096 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode)
1099 pt_entry_t *pte, attr;
1103 KASSERT((pa & L3_OFFSET) == 0,
1104 ("pmap_kenter: Invalid physical address"));
1105 KASSERT((sva & L3_OFFSET) == 0,
1106 ("pmap_kenter: Invalid virtual address"));
1107 KASSERT((size & PAGE_MASK) == 0,
1108 ("pmap_kenter: Mapping is not page-sized"));
1110 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE;
1111 if (mode == DEVICE_MEMORY)
1116 pde = pmap_pde(kernel_pmap, va, &lvl);
1117 KASSERT(pde != NULL,
1118 ("pmap_kenter: Invalid page entry, va: 0x%lx", va));
1119 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl));
1121 pte = pmap_l2_to_l3(pde, va);
1122 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr);
1128 pmap_invalidate_range(kernel_pmap, sva, va);
1132 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa)
1135 pmap_kenter(sva, size, pa, DEVICE_MEMORY);
1139 * Remove a page from the kernel pagetables.
1142 pmap_kremove(vm_offset_t va)
1147 pte = pmap_pte(kernel_pmap, va, &lvl);
1148 KASSERT(pte != NULL, ("pmap_kremove: Invalid address"));
1149 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl));
1151 pmap_load_clear(pte);
1152 pmap_invalidate_page(kernel_pmap, va);
1156 pmap_kremove_device(vm_offset_t sva, vm_size_t size)
1162 KASSERT((sva & L3_OFFSET) == 0,
1163 ("pmap_kremove_device: Invalid virtual address"));
1164 KASSERT((size & PAGE_MASK) == 0,
1165 ("pmap_kremove_device: Mapping is not page-sized"));
1169 pte = pmap_pte(kernel_pmap, va, &lvl);
1170 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va));
1172 ("Invalid device pagetable level: %d != 3", lvl));
1173 pmap_load_clear(pte);
1178 pmap_invalidate_range(kernel_pmap, sva, va);
1182 * Used to map a range of physical addresses into kernel
1183 * virtual address space.
1185 * The value passed in '*virt' is a suggested virtual address for
1186 * the mapping. Architectures which can support a direct-mapped
1187 * physical to virtual region can return the appropriate address
1188 * within that region, leaving '*virt' unchanged. Other
1189 * architectures should map the pages starting at '*virt' and
1190 * update '*virt' with the first usable address after the mapped
1194 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1196 return PHYS_TO_DMAP(start);
1201 * Add a list of wired pages to the kva
1202 * this routine is only used for temporary
1203 * kernel mappings that do not need to have
1204 * page modification or references recorded.
1205 * Note that old mappings are simply written
1206 * over. The page *must* be wired.
1207 * Note: SMP coherent. Uses a ranged shootdown IPI.
1210 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1213 pt_entry_t *pte, pa;
1219 for (i = 0; i < count; i++) {
1220 pde = pmap_pde(kernel_pmap, va, &lvl);
1221 KASSERT(pde != NULL,
1222 ("pmap_qenter: Invalid page entry, va: 0x%lx", va));
1224 ("pmap_qenter: Invalid level %d", lvl));
1227 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) |
1228 ATTR_IDX(m->md.pv_memattr) | L3_PAGE;
1229 if (m->md.pv_memattr == DEVICE_MEMORY)
1231 pte = pmap_l2_to_l3(pde, va);
1232 pmap_load_store(pte, pa);
1236 pmap_invalidate_range(kernel_pmap, sva, va);
1240 * This routine tears out page mappings from the
1241 * kernel -- it is meant only for temporary mappings.
1244 pmap_qremove(vm_offset_t sva, int count)
1250 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva));
1253 while (count-- > 0) {
1254 pte = pmap_pte(kernel_pmap, va, &lvl);
1256 ("Invalid device pagetable level: %d != 3", lvl));
1258 pmap_load_clear(pte);
1263 pmap_invalidate_range(kernel_pmap, sva, va);
1266 /***************************************************
1267 * Page table page management routines.....
1268 ***************************************************/
1270 * Schedule the specified unused page table page to be freed. Specifically,
1271 * add the page to the specified list of pages that will be released to the
1272 * physical memory manager after the TLB has been updated.
1274 static __inline void
1275 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1276 boolean_t set_PG_ZERO)
1280 m->flags |= PG_ZERO;
1282 m->flags &= ~PG_ZERO;
1283 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1287 * Decrements a page table page's wire count, which is used to record the
1288 * number of valid page table entries within the page. If the wire count
1289 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1290 * page table page was unmapped and FALSE otherwise.
1292 static inline boolean_t
1293 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1297 if (m->wire_count == 0) {
1298 _pmap_unwire_l3(pmap, va, m, free);
1305 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
1308 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1310 * unmap the page table page
1312 if (m->pindex >= (NUL2E + NUL1E)) {
1316 l0 = pmap_l0(pmap, va);
1317 pmap_load_clear(l0);
1318 } else if (m->pindex >= NUL2E) {
1322 l1 = pmap_l1(pmap, va);
1323 pmap_load_clear(l1);
1328 l2 = pmap_l2(pmap, va);
1329 pmap_load_clear(l2);
1331 pmap_resident_count_dec(pmap, 1);
1332 if (m->pindex < NUL2E) {
1333 /* We just released an l3, unhold the matching l2 */
1334 pd_entry_t *l1, tl1;
1337 l1 = pmap_l1(pmap, va);
1338 tl1 = pmap_load(l1);
1339 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1340 pmap_unwire_l3(pmap, va, l2pg, free);
1341 } else if (m->pindex < (NUL2E + NUL1E)) {
1342 /* We just released an l2, unhold the matching l1 */
1343 pd_entry_t *l0, tl0;
1346 l0 = pmap_l0(pmap, va);
1347 tl0 = pmap_load(l0);
1348 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1349 pmap_unwire_l3(pmap, va, l1pg, free);
1351 pmap_invalidate_page(pmap, va);
1356 * Put page on a list so that it is released after
1357 * *ALL* TLB shootdown is done
1359 pmap_add_delayed_free_list(m, free, TRUE);
1363 * After removing a page table entry, this routine is used to
1364 * conditionally free the page, and manage the hold/wire counts.
1367 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
1368 struct spglist *free)
1372 if (va >= VM_MAXUSER_ADDRESS)
1374 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
1375 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK);
1376 return (pmap_unwire_l3(pmap, va, mpte, free));
1380 pmap_pinit0(pmap_t pmap)
1383 PMAP_LOCK_INIT(pmap);
1384 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1385 pmap->pm_l0 = kernel_pmap->pm_l0;
1386 pmap->pm_root.rt_root = 0;
1390 pmap_pinit(pmap_t pmap)
1396 * allocate the l0 page
1398 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
1399 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL)
1402 l0phys = VM_PAGE_TO_PHYS(l0pt);
1403 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys);
1405 if ((l0pt->flags & PG_ZERO) == 0)
1406 pagezero(pmap->pm_l0);
1408 pmap->pm_root.rt_root = 0;
1409 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1415 * This routine is called if the desired page table page does not exist.
1417 * If page table page allocation fails, this routine may sleep before
1418 * returning NULL. It sleeps only if a lock pointer was given.
1420 * Note: If a page allocation fails at page table level two or three,
1421 * one or two pages may be held during the wait, only to be released
1422 * afterwards. This conservative approach is easily argued to avoid
1426 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
1428 vm_page_t m, l1pg, l2pg;
1430 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1433 * Allocate a page table page.
1435 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1436 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1437 if (lockp != NULL) {
1438 RELEASE_PV_LIST_LOCK(lockp);
1445 * Indicate the need to retry. While waiting, the page table
1446 * page may have been allocated.
1450 if ((m->flags & PG_ZERO) == 0)
1454 * Map the pagetable page into the process address space, if
1455 * it isn't already there.
1458 if (ptepindex >= (NUL2E + NUL1E)) {
1460 vm_pindex_t l0index;
1462 l0index = ptepindex - (NUL2E + NUL1E);
1463 l0 = &pmap->pm_l0[l0index];
1464 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE);
1465 } else if (ptepindex >= NUL2E) {
1466 vm_pindex_t l0index, l1index;
1467 pd_entry_t *l0, *l1;
1470 l1index = ptepindex - NUL2E;
1471 l0index = l1index >> L0_ENTRIES_SHIFT;
1473 l0 = &pmap->pm_l0[l0index];
1474 tl0 = pmap_load(l0);
1476 /* recurse for allocating page dir */
1477 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index,
1479 vm_page_unwire_noq(m);
1480 vm_page_free_zero(m);
1484 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK);
1488 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK);
1489 l1 = &l1[ptepindex & Ln_ADDR_MASK];
1490 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE);
1492 vm_pindex_t l0index, l1index;
1493 pd_entry_t *l0, *l1, *l2;
1494 pd_entry_t tl0, tl1;
1496 l1index = ptepindex >> Ln_ENTRIES_SHIFT;
1497 l0index = l1index >> L0_ENTRIES_SHIFT;
1499 l0 = &pmap->pm_l0[l0index];
1500 tl0 = pmap_load(l0);
1502 /* recurse for allocating page dir */
1503 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1505 vm_page_unwire_noq(m);
1506 vm_page_free_zero(m);
1509 tl0 = pmap_load(l0);
1510 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1511 l1 = &l1[l1index & Ln_ADDR_MASK];
1513 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK);
1514 l1 = &l1[l1index & Ln_ADDR_MASK];
1515 tl1 = pmap_load(l1);
1517 /* recurse for allocating page dir */
1518 if (_pmap_alloc_l3(pmap, NUL2E + l1index,
1520 vm_page_unwire_noq(m);
1521 vm_page_free_zero(m);
1525 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK);
1530 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK);
1531 l2 = &l2[ptepindex & Ln_ADDR_MASK];
1532 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE);
1535 pmap_resident_count_inc(pmap, 1);
1541 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
1543 vm_pindex_t ptepindex;
1544 pd_entry_t *pde, tpde;
1552 * Calculate pagetable page index
1554 ptepindex = pmap_l2_pindex(va);
1557 * Get the page directory entry
1559 pde = pmap_pde(pmap, va, &lvl);
1562 * If the page table page is mapped, we just increment the hold count,
1563 * and activate it. If we get a level 2 pde it will point to a level 3
1571 pte = pmap_l0_to_l1(pde, va);
1572 KASSERT(pmap_load(pte) == 0,
1573 ("pmap_alloc_l3: TODO: l0 superpages"));
1578 pte = pmap_l1_to_l2(pde, va);
1579 KASSERT(pmap_load(pte) == 0,
1580 ("pmap_alloc_l3: TODO: l1 superpages"));
1584 tpde = pmap_load(pde);
1586 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK);
1592 panic("pmap_alloc_l3: Invalid level %d", lvl);
1596 * Here if the pte page isn't mapped, or if it has been deallocated.
1598 m = _pmap_alloc_l3(pmap, ptepindex, lockp);
1599 if (m == NULL && lockp != NULL)
1606 /***************************************************
1607 * Pmap allocation/deallocation routines.
1608 ***************************************************/
1611 * Release any resources held by the given physical map.
1612 * Called when a pmap initialized by pmap_pinit is being released.
1613 * Should only be called if the map contains no valid mappings.
1616 pmap_release(pmap_t pmap)
1620 KASSERT(pmap->pm_stats.resident_count == 0,
1621 ("pmap_release: pmap resident count %ld != 0",
1622 pmap->pm_stats.resident_count));
1623 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1624 ("pmap_release: pmap has reserved page table page(s)"));
1626 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0));
1628 vm_page_unwire_noq(m);
1629 vm_page_free_zero(m);
1633 kvm_size(SYSCTL_HANDLER_ARGS)
1635 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
1637 return sysctl_handle_long(oidp, &ksize, 0, req);
1639 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
1640 0, 0, kvm_size, "LU", "Size of KVM");
1643 kvm_free(SYSCTL_HANDLER_ARGS)
1645 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
1647 return sysctl_handle_long(oidp, &kfree, 0, req);
1649 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
1650 0, 0, kvm_free, "LU", "Amount of KVM free");
1653 * grow the number of kernel page table entries, if needed
1656 pmap_growkernel(vm_offset_t addr)
1660 pd_entry_t *l0, *l1, *l2;
1662 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1664 addr = roundup2(addr, L2_SIZE);
1665 if (addr - 1 >= kernel_map->max_offset)
1666 addr = kernel_map->max_offset;
1667 while (kernel_vm_end < addr) {
1668 l0 = pmap_l0(kernel_pmap, kernel_vm_end);
1669 KASSERT(pmap_load(l0) != 0,
1670 ("pmap_growkernel: No level 0 kernel entry"));
1672 l1 = pmap_l0_to_l1(l0, kernel_vm_end);
1673 if (pmap_load(l1) == 0) {
1674 /* We need a new PDP entry */
1675 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT,
1676 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1677 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1679 panic("pmap_growkernel: no memory to grow kernel");
1680 if ((nkpg->flags & PG_ZERO) == 0)
1681 pmap_zero_page(nkpg);
1682 paddr = VM_PAGE_TO_PHYS(nkpg);
1683 pmap_load_store(l1, paddr | L1_TABLE);
1684 continue; /* try again */
1686 l2 = pmap_l1_to_l2(l1, kernel_vm_end);
1687 if ((pmap_load(l2) & ATTR_AF) != 0) {
1688 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1689 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1690 kernel_vm_end = kernel_map->max_offset;
1696 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT,
1697 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1700 panic("pmap_growkernel: no memory to grow kernel");
1701 if ((nkpg->flags & PG_ZERO) == 0)
1702 pmap_zero_page(nkpg);
1703 paddr = VM_PAGE_TO_PHYS(nkpg);
1704 pmap_load_store(l2, paddr | L2_TABLE);
1705 pmap_invalidate_page(kernel_pmap, kernel_vm_end);
1707 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET;
1708 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1709 kernel_vm_end = kernel_map->max_offset;
1716 /***************************************************
1717 * page management routines.
1718 ***************************************************/
1720 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1721 CTASSERT(_NPCM == 3);
1722 CTASSERT(_NPCPV == 168);
1724 static __inline struct pv_chunk *
1725 pv_to_chunk(pv_entry_t pv)
1728 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1731 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1733 #define PC_FREE0 0xfffffffffffffffful
1734 #define PC_FREE1 0xfffffffffffffffful
1735 #define PC_FREE2 0x000000fffffffffful
1737 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
1741 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1743 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1744 "Current number of pv entry chunks");
1745 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1746 "Current number of pv entry chunks allocated");
1747 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1748 "Current number of pv entry chunks frees");
1749 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1750 "Number of times tried to get a chunk page but failed.");
1752 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
1753 static int pv_entry_spare;
1755 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1756 "Current number of pv entry frees");
1757 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1758 "Current number of pv entry allocs");
1759 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1760 "Current number of pv entries");
1761 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1762 "Current number of spare pv entries");
1767 * We are in a serious low memory condition. Resort to
1768 * drastic measures to free some pages so we can allocate
1769 * another pv entry chunk.
1771 * Returns NULL if PV entries were reclaimed from the specified pmap.
1773 * We do not, however, unmap 2mpages because subsequent accesses will
1774 * allocate per-page pv entries until repromotion occurs, thereby
1775 * exacerbating the shortage of free pv entries.
1778 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
1780 struct pch new_tail;
1781 struct pv_chunk *pc;
1782 struct md_page *pvh;
1785 pt_entry_t *pte, tpte;
1789 struct spglist free;
1791 int bit, field, freed, lvl;
1793 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1794 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
1798 TAILQ_INIT(&new_tail);
1799 mtx_lock(&pv_chunks_mutex);
1800 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && SLIST_EMPTY(&free)) {
1801 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1802 mtx_unlock(&pv_chunks_mutex);
1803 if (pmap != pc->pc_pmap) {
1804 if (pmap != NULL && pmap != locked_pmap)
1807 /* Avoid deadlock and lock recursion. */
1808 if (pmap > locked_pmap) {
1809 RELEASE_PV_LIST_LOCK(lockp);
1811 } else if (pmap != locked_pmap &&
1812 !PMAP_TRYLOCK(pmap)) {
1814 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1815 mtx_lock(&pv_chunks_mutex);
1821 * Destroy every non-wired, 4 KB page mapping in the chunk.
1824 for (field = 0; field < _NPCM; field++) {
1825 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1826 inuse != 0; inuse &= ~(1UL << bit)) {
1827 bit = ffsl(inuse) - 1;
1828 pv = &pc->pc_pventry[field * 64 + bit];
1830 pde = pmap_pde(pmap, va, &lvl);
1833 pte = pmap_l2_to_l3(pde, va);
1834 tpte = pmap_load(pte);
1835 if ((tpte & ATTR_SW_WIRED) != 0)
1837 tpte = pmap_load_clear(pte);
1838 pmap_invalidate_page(pmap, va);
1839 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK);
1840 if (pmap_page_dirty(tpte))
1842 if ((tpte & ATTR_AF) != 0)
1843 vm_page_aflag_set(m, PGA_REFERENCED);
1844 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
1845 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
1847 if (TAILQ_EMPTY(&m->md.pv_list) &&
1848 (m->flags & PG_FICTITIOUS) == 0) {
1849 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
1850 if (TAILQ_EMPTY(&pvh->pv_list)) {
1851 vm_page_aflag_clear(m,
1855 pc->pc_map[field] |= 1UL << bit;
1856 pmap_unuse_pt(pmap, va, pmap_load(pde), &free);
1861 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1862 mtx_lock(&pv_chunks_mutex);
1865 /* Every freed mapping is for a 4 KB page. */
1866 pmap_resident_count_dec(pmap, freed);
1867 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
1868 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
1869 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
1870 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1871 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
1872 pc->pc_map[2] == PC_FREE2) {
1873 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1874 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1875 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1876 /* Entire chunk is free; return it. */
1877 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1878 dump_drop_page(m_pc->phys_addr);
1879 mtx_lock(&pv_chunks_mutex);
1882 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1883 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
1884 mtx_lock(&pv_chunks_mutex);
1885 /* One freed pv entry in locked_pmap is sufficient. */
1886 if (pmap == locked_pmap)
1889 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
1890 mtx_unlock(&pv_chunks_mutex);
1891 if (pmap != NULL && pmap != locked_pmap)
1893 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
1894 m_pc = SLIST_FIRST(&free);
1895 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
1896 /* Recycle a freed page table page. */
1897 m_pc->wire_count = 1;
1900 vm_page_free_pages_toq(&free, false);
1905 * free the pv_entry back to the free list
1908 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1910 struct pv_chunk *pc;
1911 int idx, field, bit;
1913 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1914 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
1915 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
1916 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
1917 pc = pv_to_chunk(pv);
1918 idx = pv - &pc->pc_pventry[0];
1921 pc->pc_map[field] |= 1ul << bit;
1922 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
1923 pc->pc_map[2] != PC_FREE2) {
1924 /* 98% of the time, pc is already at the head of the list. */
1925 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
1926 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1927 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1931 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1936 free_pv_chunk(struct pv_chunk *pc)
1940 mtx_lock(&pv_chunks_mutex);
1941 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1942 mtx_unlock(&pv_chunks_mutex);
1943 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
1944 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
1945 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
1946 /* entire chunk is free, return it */
1947 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
1948 dump_drop_page(m->phys_addr);
1949 vm_page_unwire_noq(m);
1954 * Returns a new PV entry, allocating a new PV chunk from the system when
1955 * needed. If this PV chunk allocation fails and a PV list lock pointer was
1956 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
1959 * The given PV list lock may be released.
1962 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
1966 struct pv_chunk *pc;
1969 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1970 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
1972 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1974 for (field = 0; field < _NPCM; field++) {
1975 if (pc->pc_map[field]) {
1976 bit = ffsl(pc->pc_map[field]) - 1;
1980 if (field < _NPCM) {
1981 pv = &pc->pc_pventry[field * 64 + bit];
1982 pc->pc_map[field] &= ~(1ul << bit);
1983 /* If this was the last item, move it to tail */
1984 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
1985 pc->pc_map[2] == 0) {
1986 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1987 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
1990 PV_STAT(atomic_add_long(&pv_entry_count, 1));
1991 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
1995 /* No free items, allocate another chunk */
1996 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1999 if (lockp == NULL) {
2000 PV_STAT(pc_chunk_tryfail++);
2003 m = reclaim_pv_chunk(pmap, lockp);
2007 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2008 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2009 dump_add_page(m->phys_addr);
2010 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2012 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
2013 pc->pc_map[1] = PC_FREE1;
2014 pc->pc_map[2] = PC_FREE2;
2015 mtx_lock(&pv_chunks_mutex);
2016 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2017 mtx_unlock(&pv_chunks_mutex);
2018 pv = &pc->pc_pventry[0];
2019 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2020 PV_STAT(atomic_add_long(&pv_entry_count, 1));
2021 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
2026 * Ensure that the number of spare PV entries in the specified pmap meets or
2027 * exceeds the given count, "needed".
2029 * The given PV list lock may be released.
2032 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
2034 struct pch new_tail;
2035 struct pv_chunk *pc;
2039 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2040 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
2043 * Newly allocated PV chunks must be stored in a private list until
2044 * the required number of PV chunks have been allocated. Otherwise,
2045 * reclaim_pv_chunk() could recycle one of these chunks. In
2046 * contrast, these chunks must be added to the pmap upon allocation.
2048 TAILQ_INIT(&new_tail);
2051 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
2052 bit_count((bitstr_t *)pc->pc_map, 0,
2053 sizeof(pc->pc_map) * NBBY, &free);
2057 if (avail >= needed)
2060 for (; avail < needed; avail += _NPCPV) {
2061 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
2064 m = reclaim_pv_chunk(pmap, lockp);
2068 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
2069 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
2070 dump_add_page(m->phys_addr);
2071 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
2073 pc->pc_map[0] = PC_FREE0;
2074 pc->pc_map[1] = PC_FREE1;
2075 pc->pc_map[2] = PC_FREE2;
2076 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2077 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
2078 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
2080 if (!TAILQ_EMPTY(&new_tail)) {
2081 mtx_lock(&pv_chunks_mutex);
2082 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
2083 mtx_unlock(&pv_chunks_mutex);
2088 * First find and then remove the pv entry for the specified pmap and virtual
2089 * address from the specified pv list. Returns the pv entry if found and NULL
2090 * otherwise. This operation can be performed on pv lists for either 4KB or
2091 * 2MB page mappings.
2093 static __inline pv_entry_t
2094 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2098 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2099 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2100 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2109 * After demotion from a 2MB page mapping to 512 4KB page mappings,
2110 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
2111 * entries for each of the 4KB page mappings.
2114 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2115 struct rwlock **lockp)
2117 struct md_page *pvh;
2118 struct pv_chunk *pc;
2120 vm_offset_t va_last;
2124 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2125 KASSERT((pa & L2_OFFSET) == 0,
2126 ("pmap_pv_demote_l2: pa is not 2mpage aligned"));
2127 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2130 * Transfer the 2mpage's pv entry for this mapping to the first
2131 * page's pv list. Once this transfer begins, the pv list lock
2132 * must not be released until the last pv entry is reinstantiated.
2134 pvh = pa_to_pvh(pa);
2135 va = va & ~L2_OFFSET;
2136 pv = pmap_pvh_remove(pvh, pmap, va);
2137 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found"));
2138 m = PHYS_TO_VM_PAGE(pa);
2139 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2141 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */
2142 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1));
2143 va_last = va + L2_SIZE - PAGE_SIZE;
2145 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2146 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
2147 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare"));
2148 for (field = 0; field < _NPCM; field++) {
2149 while (pc->pc_map[field]) {
2150 bit = ffsl(pc->pc_map[field]) - 1;
2151 pc->pc_map[field] &= ~(1ul << bit);
2152 pv = &pc->pc_pventry[field * 64 + bit];
2156 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2157 ("pmap_pv_demote_l2: page %p is not managed", m));
2158 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2164 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2165 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2168 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
2169 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2170 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2172 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1));
2173 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1));
2177 * First find and then destroy the pv entry for the specified pmap and virtual
2178 * address. This operation can be performed on pv lists for either 4KB or 2MB
2182 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2186 pv = pmap_pvh_remove(pvh, pmap, va);
2187 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2188 free_pv_entry(pmap, pv);
2192 * Conditionally create the PV entry for a 4KB page mapping if the required
2193 * memory can be allocated without resorting to reclamation.
2196 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
2197 struct rwlock **lockp)
2201 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2202 /* Pass NULL instead of the lock pointer to disable reclamation. */
2203 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
2205 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2206 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2214 * pmap_remove_l2: do the things to unmap a level 2 superpage in a process
2217 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva,
2218 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp)
2220 struct md_page *pvh;
2222 vm_offset_t eva, va;
2225 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2226 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned"));
2227 old_l2 = pmap_load_clear(l2);
2228 pmap_invalidate_range(pmap, sva, sva + L2_SIZE);
2229 if (old_l2 & ATTR_SW_WIRED)
2230 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE;
2231 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE);
2232 if (old_l2 & ATTR_SW_MANAGED) {
2233 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK);
2234 pvh = pa_to_pvh(old_l2 & ~ATTR_MASK);
2235 pmap_pvh_free(pvh, pmap, sva);
2236 eva = sva + L2_SIZE;
2237 for (va = sva, m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK);
2238 va < eva; va += PAGE_SIZE, m++) {
2239 if (pmap_page_dirty(old_l2))
2241 if (old_l2 & ATTR_AF)
2242 vm_page_aflag_set(m, PGA_REFERENCED);
2243 if (TAILQ_EMPTY(&m->md.pv_list) &&
2244 TAILQ_EMPTY(&pvh->pv_list))
2245 vm_page_aflag_clear(m, PGA_WRITEABLE);
2248 KASSERT(pmap != kernel_pmap,
2249 ("Attempting to remove an l2 kernel page"));
2250 ml3 = pmap_remove_pt_page(pmap, sva);
2252 pmap_resident_count_dec(pmap, 1);
2253 KASSERT(ml3->wire_count == NL3PG,
2254 ("pmap_remove_pages: l3 page wire count error"));
2255 ml3->wire_count = 1;
2256 vm_page_unwire_noq(ml3);
2257 pmap_add_delayed_free_list(ml3, free, FALSE);
2259 return (pmap_unuse_pt(pmap, sva, l1e, free));
2263 * pmap_remove_l3: do the things to unmap a page in a process
2266 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va,
2267 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp)
2269 struct md_page *pvh;
2273 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2274 old_l3 = pmap_load_clear(l3);
2275 pmap_invalidate_page(pmap, va);
2276 if (old_l3 & ATTR_SW_WIRED)
2277 pmap->pm_stats.wired_count -= 1;
2278 pmap_resident_count_dec(pmap, 1);
2279 if (old_l3 & ATTR_SW_MANAGED) {
2280 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK);
2281 if (pmap_page_dirty(old_l3))
2283 if (old_l3 & ATTR_AF)
2284 vm_page_aflag_set(m, PGA_REFERENCED);
2285 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
2286 pmap_pvh_free(&m->md, pmap, va);
2287 if (TAILQ_EMPTY(&m->md.pv_list) &&
2288 (m->flags & PG_FICTITIOUS) == 0) {
2289 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2290 if (TAILQ_EMPTY(&pvh->pv_list))
2291 vm_page_aflag_clear(m, PGA_WRITEABLE);
2294 return (pmap_unuse_pt(pmap, va, l2e, free));
2298 * Remove the given range of addresses from the specified map.
2300 * It is assumed that the start and end are properly
2301 * rounded to the page size.
2304 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2306 struct rwlock *lock;
2307 vm_offset_t va, va_next;
2308 pd_entry_t *l0, *l1, *l2;
2309 pt_entry_t l3_paddr, *l3;
2310 struct spglist free;
2313 * Perform an unsynchronized read. This is, however, safe.
2315 if (pmap->pm_stats.resident_count == 0)
2323 for (; sva < eva; sva = va_next) {
2325 if (pmap->pm_stats.resident_count == 0)
2328 l0 = pmap_l0(pmap, sva);
2329 if (pmap_load(l0) == 0) {
2330 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2336 l1 = pmap_l0_to_l1(l0, sva);
2337 if (pmap_load(l1) == 0) {
2338 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2345 * Calculate index for next page table.
2347 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2351 l2 = pmap_l1_to_l2(l1, sva);
2355 l3_paddr = pmap_load(l2);
2357 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) {
2358 if (sva + L2_SIZE == va_next && eva >= va_next) {
2359 pmap_remove_l2(pmap, l2, sva, pmap_load(l1),
2362 } else if (pmap_demote_l2_locked(pmap, l2,
2363 sva &~L2_OFFSET, &lock) == NULL)
2365 l3_paddr = pmap_load(l2);
2369 * Weed out invalid mappings.
2371 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE)
2375 * Limit our scan to either the end of the va represented
2376 * by the current page table page, or to the end of the
2377 * range being removed.
2383 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
2386 panic("l3 == NULL");
2387 if (pmap_load(l3) == 0) {
2388 if (va != va_next) {
2389 pmap_invalidate_range(pmap, va, sva);
2396 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free,
2403 pmap_invalidate_range(pmap, va, sva);
2408 vm_page_free_pages_toq(&free, false);
2412 * Routine: pmap_remove_all
2414 * Removes this physical page from
2415 * all physical maps in which it resides.
2416 * Reflects back modify bits to the pager.
2419 * Original versions of this routine were very
2420 * inefficient because they iteratively called
2421 * pmap_remove (slow...)
2425 pmap_remove_all(vm_page_t m)
2427 struct md_page *pvh;
2430 struct rwlock *lock;
2431 pd_entry_t *pde, tpde;
2432 pt_entry_t *pte, tpte;
2434 struct spglist free;
2435 int lvl, pvh_gen, md_gen;
2437 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2438 ("pmap_remove_all: page %p is not managed", m));
2440 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
2441 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
2442 pa_to_pvh(VM_PAGE_TO_PHYS(m));
2445 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2447 if (!PMAP_TRYLOCK(pmap)) {
2448 pvh_gen = pvh->pv_gen;
2452 if (pvh_gen != pvh->pv_gen) {
2459 pte = pmap_pte(pmap, va, &lvl);
2460 KASSERT(pte != NULL,
2461 ("pmap_remove_all: no page table entry found"));
2463 ("pmap_remove_all: invalid pte level %d", lvl));
2465 pmap_demote_l2_locked(pmap, pte, va, &lock);
2468 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2470 if (!PMAP_TRYLOCK(pmap)) {
2471 pvh_gen = pvh->pv_gen;
2472 md_gen = m->md.pv_gen;
2476 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
2482 pmap_resident_count_dec(pmap, 1);
2484 pde = pmap_pde(pmap, pv->pv_va, &lvl);
2485 KASSERT(pde != NULL,
2486 ("pmap_remove_all: no page directory entry found"));
2488 ("pmap_remove_all: invalid pde level %d", lvl));
2489 tpde = pmap_load(pde);
2491 pte = pmap_l2_to_l3(pde, pv->pv_va);
2492 tpte = pmap_load(pte);
2493 pmap_load_clear(pte);
2494 pmap_invalidate_page(pmap, pv->pv_va);
2495 if (tpte & ATTR_SW_WIRED)
2496 pmap->pm_stats.wired_count--;
2497 if ((tpte & ATTR_AF) != 0)
2498 vm_page_aflag_set(m, PGA_REFERENCED);
2501 * Update the vm_page_t clean and reference bits.
2503 if (pmap_page_dirty(tpte))
2505 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free);
2506 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2508 free_pv_entry(pmap, pv);
2511 vm_page_aflag_clear(m, PGA_WRITEABLE);
2513 vm_page_free_pages_toq(&free, false);
2517 * Set the physical protection on the
2518 * specified range of this map as requested.
2521 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2523 vm_offset_t va, va_next;
2524 pd_entry_t *l0, *l1, *l2;
2525 pt_entry_t *l3p, l3, nbits;
2527 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
2528 if (prot == VM_PROT_NONE) {
2529 pmap_remove(pmap, sva, eva);
2533 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
2534 (VM_PROT_WRITE | VM_PROT_EXECUTE))
2538 for (; sva < eva; sva = va_next) {
2540 l0 = pmap_l0(pmap, sva);
2541 if (pmap_load(l0) == 0) {
2542 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
2548 l1 = pmap_l0_to_l1(l0, sva);
2549 if (pmap_load(l1) == 0) {
2550 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
2556 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
2560 l2 = pmap_l1_to_l2(l1, sva);
2561 if (pmap_load(l2) == 0)
2564 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
2565 l3p = pmap_demote_l2(pmap, l2, sva);
2569 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
2570 ("pmap_protect: Invalid L2 entry after demotion"));
2576 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++,
2578 l3 = pmap_load(l3p);
2579 if (!pmap_l3_valid(l3))
2583 if ((prot & VM_PROT_WRITE) == 0) {
2584 if ((l3 & ATTR_SW_MANAGED) &&
2585 pmap_page_dirty(l3)) {
2586 vm_page_dirty(PHYS_TO_VM_PAGE(l3 &
2589 nbits |= ATTR_AP(ATTR_AP_RO);
2591 if ((prot & VM_PROT_EXECUTE) == 0)
2594 pmap_set(l3p, nbits);
2595 /* XXX: Use pmap_invalidate_range */
2596 pmap_invalidate_page(pmap, sva);
2603 * Inserts the specified page table page into the specified pmap's collection
2604 * of idle page table pages. Each of a pmap's page table pages is responsible
2605 * for mapping a distinct range of virtual addresses. The pmap's collection is
2606 * ordered by this virtual address range.
2609 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
2612 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2613 return (vm_radix_insert(&pmap->pm_root, mpte));
2617 * Removes the page table page mapping the specified virtual address from the
2618 * specified pmap's collection of idle page table pages, and returns it.
2619 * Otherwise, returns NULL if there is no page table page corresponding to the
2620 * specified virtual address.
2622 static __inline vm_page_t
2623 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
2626 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2627 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va)));
2631 * Performs a break-before-make update of a pmap entry. This is needed when
2632 * either promoting or demoting pages to ensure the TLB doesn't get into an
2633 * inconsistent state.
2636 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte,
2637 vm_offset_t va, vm_size_t size)
2641 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2644 * Ensure we don't get switched out with the page table in an
2645 * inconsistent state. We also need to ensure no interrupts fire
2646 * as they may make use of an address we are about to invalidate.
2648 intr = intr_disable();
2651 /* Clear the old mapping */
2652 pmap_load_clear(pte);
2653 pmap_invalidate_range_nopin(pmap, va, va + size);
2655 /* Create the new mapping */
2656 pmap_load_store(pte, newpte);
2662 #if VM_NRESERVLEVEL > 0
2664 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
2665 * replace the many pv entries for the 4KB page mappings by a single pv entry
2666 * for the 2MB page mapping.
2669 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
2670 struct rwlock **lockp)
2672 struct md_page *pvh;
2674 vm_offset_t va_last;
2677 KASSERT((pa & L2_OFFSET) == 0,
2678 ("pmap_pv_promote_l2: pa is not 2mpage aligned"));
2679 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
2682 * Transfer the first page's pv entry for this mapping to the 2mpage's
2683 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
2684 * a transfer avoids the possibility that get_pv_entry() calls
2685 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
2686 * mappings that is being promoted.
2688 m = PHYS_TO_VM_PAGE(pa);
2689 va = va & ~L2_OFFSET;
2690 pv = pmap_pvh_remove(&m->md, pmap, va);
2691 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found"));
2692 pvh = pa_to_pvh(pa);
2693 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2695 /* Free the remaining NPTEPG - 1 pv entries. */
2696 va_last = va + L2_SIZE - PAGE_SIZE;
2700 pmap_pvh_free(&m->md, pmap, va);
2701 } while (va < va_last);
2705 * Tries to promote the 512, contiguous 4KB page mappings that are within a
2706 * single level 2 table entry to a single 2MB page mapping. For promotion
2707 * to occur, two conditions must be met: (1) the 4KB page mappings must map
2708 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
2709 * identical characteristics.
2712 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va,
2713 struct rwlock **lockp)
2715 pt_entry_t *firstl3, *l3, newl2, oldl3, pa;
2719 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2721 sva = va & ~L2_OFFSET;
2722 firstl3 = pmap_l2_to_l3(l2, sva);
2723 newl2 = pmap_load(firstl3);
2725 /* Check the alingment is valid */
2726 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) {
2727 atomic_add_long(&pmap_l2_p_failures, 1);
2728 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2729 " in pmap %p", va, pmap);
2733 pa = newl2 + L2_SIZE - PAGE_SIZE;
2734 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) {
2735 oldl3 = pmap_load(l3);
2737 atomic_add_long(&pmap_l2_p_failures, 1);
2738 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx"
2739 " in pmap %p", va, pmap);
2746 * Save the page table page in its current state until the L2
2747 * mapping the superpage is demoted by pmap_demote_l2() or
2748 * destroyed by pmap_remove_l3().
2750 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK);
2751 KASSERT(mpte >= vm_page_array &&
2752 mpte < &vm_page_array[vm_page_array_size],
2753 ("pmap_promote_l2: page table page is out of range"));
2754 KASSERT(mpte->pindex == pmap_l2_pindex(va),
2755 ("pmap_promote_l2: page table page's pindex is wrong"));
2756 if (pmap_insert_pt_page(pmap, mpte)) {
2757 atomic_add_long(&pmap_l2_p_failures, 1);
2759 "pmap_promote_l2: failure for va %#lx in pmap %p", va,
2764 if ((newl2 & ATTR_SW_MANAGED) != 0)
2765 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp);
2767 newl2 &= ~ATTR_DESCR_MASK;
2770 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE);
2772 atomic_add_long(&pmap_l2_promotions, 1);
2773 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va,
2776 #endif /* VM_NRESERVLEVEL > 0 */
2779 * Insert the given physical page (p) at
2780 * the specified virtual address (v) in the
2781 * target physical map with the protection requested.
2783 * If specified, the page will be wired down, meaning
2784 * that the related pte can not be reclaimed.
2786 * NB: This is the only routine which MAY NOT lazy-evaluate
2787 * or lose information. That is, this routine must actually
2788 * insert this page into the given map NOW.
2791 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2792 u_int flags, int8_t psind __unused)
2794 struct rwlock *lock;
2796 pt_entry_t new_l3, orig_l3;
2797 pt_entry_t *l2, *l3;
2799 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa;
2800 vm_page_t mpte, om, l1_m, l2_m, l3_m;
2804 va = trunc_page(va);
2805 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2806 VM_OBJECT_ASSERT_LOCKED(m->object);
2807 pa = VM_PAGE_TO_PHYS(m);
2808 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
2810 if ((prot & VM_PROT_WRITE) == 0)
2811 new_l3 |= ATTR_AP(ATTR_AP_RO);
2812 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
2814 if ((flags & PMAP_ENTER_WIRED) != 0)
2815 new_l3 |= ATTR_SW_WIRED;
2816 if (va < VM_MAXUSER_ADDRESS)
2817 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN;
2819 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa);
2826 pde = pmap_pde(pmap, va, &lvl);
2827 if (pde != NULL && lvl == 1) {
2828 l2 = pmap_l1_to_l2(pde, va);
2829 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK &&
2830 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET,
2832 l3 = &l3[pmap_l3_index(va)];
2833 if (va < VM_MAXUSER_ADDRESS) {
2834 mpte = PHYS_TO_VM_PAGE(
2835 pmap_load(l2) & ~ATTR_MASK);
2842 if (va < VM_MAXUSER_ADDRESS) {
2843 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
2844 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock);
2845 if (mpte == NULL && nosleep) {
2846 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL");
2850 return (KERN_RESOURCE_SHORTAGE);
2852 pde = pmap_pde(pmap, va, &lvl);
2853 KASSERT(pde != NULL,
2854 ("pmap_enter: Invalid page entry, va: 0x%lx", va));
2856 ("pmap_enter: Invalid level %d", lvl));
2859 * If we get a level 2 pde it must point to a level 3 entry
2860 * otherwise we will need to create the intermediate tables
2866 /* Get the l0 pde to update */
2867 pde = pmap_l0(pmap, va);
2868 KASSERT(pde != NULL, ("..."));
2870 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2871 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2874 panic("pmap_enter: l1 pte_m == NULL");
2875 if ((l1_m->flags & PG_ZERO) == 0)
2876 pmap_zero_page(l1_m);
2878 l1_pa = VM_PAGE_TO_PHYS(l1_m);
2879 pmap_load_store(pde, l1_pa | L0_TABLE);
2882 /* Get the l1 pde to update */
2883 pde = pmap_l1_to_l2(pde, va);
2884 KASSERT(pde != NULL, ("..."));
2886 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2887 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2890 panic("pmap_enter: l2 pte_m == NULL");
2891 if ((l2_m->flags & PG_ZERO) == 0)
2892 pmap_zero_page(l2_m);
2894 l2_pa = VM_PAGE_TO_PHYS(l2_m);
2895 pmap_load_store(pde, l2_pa | L1_TABLE);
2898 /* Get the l2 pde to update */
2899 pde = pmap_l1_to_l2(pde, va);
2900 KASSERT(pde != NULL, ("..."));
2902 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2903 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2906 panic("pmap_enter: l3 pte_m == NULL");
2907 if ((l3_m->flags & PG_ZERO) == 0)
2908 pmap_zero_page(l3_m);
2910 l3_pa = VM_PAGE_TO_PHYS(l3_m);
2911 pmap_load_store(pde, l3_pa | L2_TABLE);
2916 l3 = pmap_l2_to_l3(pde, va);
2920 orig_l3 = pmap_load(l3);
2921 opa = orig_l3 & ~ATTR_MASK;
2924 * Is the specified virtual address already mapped?
2926 if (pmap_l3_valid(orig_l3)) {
2928 * Wiring change, just update stats. We don't worry about
2929 * wiring PT pages as they remain resident as long as there
2930 * are valid mappings in them. Hence, if a user page is wired,
2931 * the PT page will be also.
2933 if ((flags & PMAP_ENTER_WIRED) != 0 &&
2934 (orig_l3 & ATTR_SW_WIRED) == 0)
2935 pmap->pm_stats.wired_count++;
2936 else if ((flags & PMAP_ENTER_WIRED) == 0 &&
2937 (orig_l3 & ATTR_SW_WIRED) != 0)
2938 pmap->pm_stats.wired_count--;
2941 * Remove the extra PT page reference.
2945 KASSERT(mpte->wire_count > 0,
2946 ("pmap_enter: missing reference to page table page,"
2951 * Has the physical page changed?
2955 * No, might be a protection or wiring change.
2957 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
2958 new_l3 |= ATTR_SW_MANAGED;
2959 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) ==
2960 ATTR_AP(ATTR_AP_RW)) {
2961 vm_page_aflag_set(m, PGA_WRITEABLE);
2968 * Increment the counters.
2970 if ((new_l3 & ATTR_SW_WIRED) != 0)
2971 pmap->pm_stats.wired_count++;
2972 pmap_resident_count_inc(pmap, 1);
2975 * Enter on the PV list if part of our managed memory.
2977 if ((m->oflags & VPO_UNMANAGED) == 0) {
2978 new_l3 |= ATTR_SW_MANAGED;
2979 pv = get_pv_entry(pmap, &lock);
2981 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
2982 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2984 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
2985 vm_page_aflag_set(m, PGA_WRITEABLE);
2990 * Sync icache if exec permission and attribute VM_MEMATTR_WRITE_BACK
2991 * is set. Do it now, before the mapping is stored and made
2992 * valid for hardware table walk. If done later, then other can
2993 * access this page before caches are properly synced.
2994 * Don't do it for kernel memory which is mapped with exec
2995 * permission even if the memory isn't going to hold executable
2996 * code. The only time when icache sync is needed is after
2997 * kernel module is loaded and the relocation info is processed.
2998 * And it's done in elf_cpu_load_file().
3000 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3001 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK &&
3002 (opa != pa || (orig_l3 & ATTR_XN)))
3003 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3006 * Update the L3 entry
3008 if (pmap_l3_valid(orig_l3)) {
3011 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE);
3012 if ((orig_l3 & ATTR_SW_MANAGED) != 0) {
3013 om = PHYS_TO_VM_PAGE(opa);
3014 if (pmap_page_dirty(orig_l3))
3016 if ((orig_l3 & ATTR_AF) != 0)
3017 vm_page_aflag_set(om, PGA_REFERENCED);
3018 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
3019 pmap_pvh_free(&om->md, pmap, va);
3020 if ((om->aflags & PGA_WRITEABLE) != 0 &&
3021 TAILQ_EMPTY(&om->md.pv_list) &&
3022 ((om->flags & PG_FICTITIOUS) != 0 ||
3023 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3024 vm_page_aflag_clear(om, PGA_WRITEABLE);
3026 } else if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) {
3027 /* same PA, different attributes */
3028 pmap_load_store(l3, new_l3);
3029 pmap_invalidate_page(pmap, va);
3030 if (pmap_page_dirty(orig_l3) &&
3031 (orig_l3 & ATTR_SW_MANAGED) != 0)
3036 * This can happens if multiple threads simultaneously
3037 * access not yet mapped page. This bad for performance
3038 * since this can cause full demotion-NOP-promotion
3040 * Another possible reasons are:
3041 * - VM and pmap memory layout are diverged
3042 * - tlb flush is missing somewhere and CPU doesn't see
3045 CTR4(KTR_PMAP, "%s: already mapped page - "
3046 "pmap %p va 0x%#lx pte 0x%lx",
3047 __func__, pmap, va, new_l3);
3051 pmap_load_store(l3, new_l3);
3054 #if VM_NRESERVLEVEL > 0
3055 if (pmap != pmap_kernel() &&
3056 (mpte == NULL || mpte->wire_count == NL3PG) &&
3057 pmap_superpages_enabled() &&
3058 (m->flags & PG_FICTITIOUS) == 0 &&
3059 vm_reserv_level_iffullpop(m) == 0) {
3060 pmap_promote_l2(pmap, pde, va, &lock);
3067 return (KERN_SUCCESS);
3071 * Maps a sequence of resident pages belonging to the same object.
3072 * The sequence begins with the given page m_start. This page is
3073 * mapped at the given virtual address start. Each subsequent page is
3074 * mapped at a virtual address that is offset from start by the same
3075 * amount as the page is offset from m_start within the object. The
3076 * last page in the sequence is the page with the largest offset from
3077 * m_start that can be mapped at a virtual address less than the given
3078 * virtual address end. Not every virtual page between start and end
3079 * is mapped; only those for which a resident page exists with the
3080 * corresponding offset from m_start are mapped.
3083 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3084 vm_page_t m_start, vm_prot_t prot)
3086 struct rwlock *lock;
3089 vm_pindex_t diff, psize;
3091 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3093 psize = atop(end - start);
3098 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3099 va = start + ptoa(diff);
3100 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock);
3101 m = TAILQ_NEXT(m, listq);
3109 * this code makes some *MAJOR* assumptions:
3110 * 1. Current pmap & pmap exists.
3113 * 4. No page table pages.
3114 * but is *MUCH* faster than pmap_enter...
3118 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3120 struct rwlock *lock;
3124 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
3131 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3132 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
3134 struct spglist free;
3136 pt_entry_t *l2, *l3, l3_val;
3140 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3141 (m->oflags & VPO_UNMANAGED) != 0,
3142 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3143 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3145 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va);
3147 * In the case that a page table page is not
3148 * resident, we are creating it here.
3150 if (va < VM_MAXUSER_ADDRESS) {
3151 vm_pindex_t l2pindex;
3154 * Calculate pagetable page index
3156 l2pindex = pmap_l2_pindex(va);
3157 if (mpte && (mpte->pindex == l2pindex)) {
3163 pde = pmap_pde(pmap, va, &lvl);
3166 * If the page table page is mapped, we just increment
3167 * the hold count, and activate it. Otherwise, we
3168 * attempt to allocate a page table page. If this
3169 * attempt fails, we don't retry. Instead, we give up.
3172 l2 = pmap_l1_to_l2(pde, va);
3173 if ((pmap_load(l2) & ATTR_DESCR_MASK) ==
3177 if (lvl == 2 && pmap_load(pde) != 0) {
3179 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK);
3183 * Pass NULL instead of the PV list lock
3184 * pointer, because we don't intend to sleep.
3186 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL);
3191 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
3192 l3 = &l3[pmap_l3_index(va)];
3195 pde = pmap_pde(kernel_pmap, va, &lvl);
3196 KASSERT(pde != NULL,
3197 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx",
3200 ("pmap_enter_quick_locked: Invalid level %d", lvl));
3201 l3 = pmap_l2_to_l3(pde, va);
3204 if (pmap_load(l3) != 0) {
3213 * Enter on the PV list if part of our managed memory.
3215 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3216 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
3219 if (pmap_unwire_l3(pmap, va, mpte, &free)) {
3220 pmap_invalidate_page(pmap, va);
3221 vm_page_free_pages_toq(&free, false);
3229 * Increment counters
3231 pmap_resident_count_inc(pmap, 1);
3233 pa = VM_PAGE_TO_PHYS(m);
3234 l3_val = pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) |
3235 ATTR_AP(ATTR_AP_RO) | L3_PAGE;
3236 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY)
3238 else if (va < VM_MAXUSER_ADDRESS)
3242 * Now validate mapping with RO protection
3244 if ((m->oflags & VPO_UNMANAGED) == 0)
3245 l3_val |= ATTR_SW_MANAGED;
3247 /* Sync icache before the mapping is stored to PTE */
3248 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
3249 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK)
3250 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE);
3252 pmap_load_store(l3, l3_val);
3253 pmap_invalidate_page(pmap, va);
3258 * This code maps large physical mmap regions into the
3259 * processor address space. Note that some shortcuts
3260 * are taken, but the code works.
3263 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3264 vm_pindex_t pindex, vm_size_t size)
3267 VM_OBJECT_ASSERT_WLOCKED(object);
3268 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3269 ("pmap_object_init_pt: non-device object"));
3273 * Clear the wired attribute from the mappings for the specified range of
3274 * addresses in the given pmap. Every valid mapping within that range
3275 * must have the wired attribute set. In contrast, invalid mappings
3276 * cannot have the wired attribute set, so they are ignored.
3278 * The wired attribute of the page table entry is not a hardware feature,
3279 * so there is no need to invalidate any TLB entries.
3282 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3284 vm_offset_t va_next;
3285 pd_entry_t *l0, *l1, *l2;
3289 for (; sva < eva; sva = va_next) {
3290 l0 = pmap_l0(pmap, sva);
3291 if (pmap_load(l0) == 0) {
3292 va_next = (sva + L0_SIZE) & ~L0_OFFSET;
3298 l1 = pmap_l0_to_l1(l0, sva);
3299 if (pmap_load(l1) == 0) {
3300 va_next = (sva + L1_SIZE) & ~L1_OFFSET;
3306 va_next = (sva + L2_SIZE) & ~L2_OFFSET;
3310 l2 = pmap_l1_to_l2(l1, sva);
3311 if (pmap_load(l2) == 0)
3314 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) {
3315 l3 = pmap_demote_l2(pmap, l2, sva);
3319 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE,
3320 ("pmap_unwire: Invalid l2 entry after demotion"));
3324 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
3326 if (pmap_load(l3) == 0)
3328 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
3329 panic("pmap_unwire: l3 %#jx is missing "
3330 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
3333 * PG_W must be cleared atomically. Although the pmap
3334 * lock synchronizes access to PG_W, another processor
3335 * could be setting PG_M and/or PG_A concurrently.
3337 atomic_clear_long(l3, ATTR_SW_WIRED);
3338 pmap->pm_stats.wired_count--;
3345 * Copy the range specified by src_addr/len
3346 * from the source map to the range dst_addr/len
3347 * in the destination map.
3349 * This routine is only advisory and need not do anything.
3353 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3354 vm_offset_t src_addr)
3359 * pmap_zero_page zeros the specified hardware page by mapping
3360 * the page into KVM and using bzero to clear its contents.
3363 pmap_zero_page(vm_page_t m)
3365 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3367 pagezero((void *)va);
3371 * pmap_zero_page_area zeros the specified hardware page by mapping
3372 * the page into KVM and using bzero to clear its contents.
3374 * off and size may not cover an area beyond a single hardware page.
3377 pmap_zero_page_area(vm_page_t m, int off, int size)
3379 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3381 if (off == 0 && size == PAGE_SIZE)
3382 pagezero((void *)va);
3384 bzero((char *)va + off, size);
3388 * pmap_copy_page copies the specified (machine independent)
3389 * page by mapping the page into virtual memory and using
3390 * bcopy to copy the page, one machine dependent page at a
3394 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
3396 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
3397 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
3399 pagecopy((void *)src, (void *)dst);
3402 int unmapped_buf_allowed = 1;
3405 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
3406 vm_offset_t b_offset, int xfersize)
3410 vm_paddr_t p_a, p_b;
3411 vm_offset_t a_pg_offset, b_pg_offset;
3414 while (xfersize > 0) {
3415 a_pg_offset = a_offset & PAGE_MASK;
3416 m_a = ma[a_offset >> PAGE_SHIFT];
3417 p_a = m_a->phys_addr;
3418 b_pg_offset = b_offset & PAGE_MASK;
3419 m_b = mb[b_offset >> PAGE_SHIFT];
3420 p_b = m_b->phys_addr;
3421 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3422 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3423 if (__predict_false(!PHYS_IN_DMAP(p_a))) {
3424 panic("!DMAP a %lx", p_a);
3426 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset;
3428 if (__predict_false(!PHYS_IN_DMAP(p_b))) {
3429 panic("!DMAP b %lx", p_b);
3431 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset;
3433 bcopy(a_cp, b_cp, cnt);
3441 pmap_quick_enter_page(vm_page_t m)
3444 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3448 pmap_quick_remove_page(vm_offset_t addr)
3453 * Returns true if the pmap's pv is one of the first
3454 * 16 pvs linked to from this page. This count may
3455 * be changed upwards or downwards in the future; it
3456 * is only necessary that true be returned for a small
3457 * subset of pmaps for proper page aging.
3460 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
3462 struct md_page *pvh;
3463 struct rwlock *lock;
3468 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3469 ("pmap_page_exists_quick: page %p is not managed", m));
3471 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3473 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3474 if (PV_PMAP(pv) == pmap) {
3482 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
3483 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3484 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3485 if (PV_PMAP(pv) == pmap) {
3499 * pmap_page_wired_mappings:
3501 * Return the number of managed mappings to the given physical page
3505 pmap_page_wired_mappings(vm_page_t m)
3507 struct rwlock *lock;
3508 struct md_page *pvh;
3512 int count, lvl, md_gen, pvh_gen;
3514 if ((m->oflags & VPO_UNMANAGED) != 0)
3516 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3520 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3522 if (!PMAP_TRYLOCK(pmap)) {
3523 md_gen = m->md.pv_gen;
3527 if (md_gen != m->md.pv_gen) {
3532 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3533 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3537 if ((m->flags & PG_FICTITIOUS) == 0) {
3538 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3539 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3541 if (!PMAP_TRYLOCK(pmap)) {
3542 md_gen = m->md.pv_gen;
3543 pvh_gen = pvh->pv_gen;
3547 if (md_gen != m->md.pv_gen ||
3548 pvh_gen != pvh->pv_gen) {
3553 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3555 (pmap_load(pte) & ATTR_SW_WIRED) != 0)
3565 * Destroy all managed, non-wired mappings in the given user-space
3566 * pmap. This pmap cannot be active on any processor besides the
3569 * This function cannot be applied to the kernel pmap. Moreover, it
3570 * is not intended for general use. It is only to be used during
3571 * process termination. Consequently, it can be implemented in ways
3572 * that make it faster than pmap_remove(). First, it can more quickly
3573 * destroy mappings by iterating over the pmap's collection of PV
3574 * entries, rather than searching the page table. Second, it doesn't
3575 * have to test and clear the page table entries atomically, because
3576 * no processor is currently accessing the user address space. In
3577 * particular, a page table entry's dirty bit won't change state once
3578 * this function starts.
3581 pmap_remove_pages(pmap_t pmap)
3584 pt_entry_t *pte, tpte;
3585 struct spglist free;
3586 vm_page_t m, ml3, mt;
3588 struct md_page *pvh;
3589 struct pv_chunk *pc, *npc;
3590 struct rwlock *lock;
3592 uint64_t inuse, bitmask;
3593 int allfree, field, freed, idx, lvl;
3600 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
3603 for (field = 0; field < _NPCM; field++) {
3604 inuse = ~pc->pc_map[field] & pc_freemask[field];
3605 while (inuse != 0) {
3606 bit = ffsl(inuse) - 1;
3607 bitmask = 1UL << bit;
3608 idx = field * 64 + bit;
3609 pv = &pc->pc_pventry[idx];
3612 pde = pmap_pde(pmap, pv->pv_va, &lvl);
3613 KASSERT(pde != NULL,
3614 ("Attempting to remove an unmapped page"));
3618 pte = pmap_l1_to_l2(pde, pv->pv_va);
3619 tpte = pmap_load(pte);
3620 KASSERT((tpte & ATTR_DESCR_MASK) ==
3622 ("Attempting to remove an invalid "
3623 "block: %lx", tpte));
3624 tpte = pmap_load(pte);
3627 pte = pmap_l2_to_l3(pde, pv->pv_va);
3628 tpte = pmap_load(pte);
3629 KASSERT((tpte & ATTR_DESCR_MASK) ==
3631 ("Attempting to remove an invalid "
3632 "page: %lx", tpte));
3636 "Invalid page directory level: %d",
3641 * We cannot remove wired pages from a process' mapping at this time
3643 if (tpte & ATTR_SW_WIRED) {
3648 pa = tpte & ~ATTR_MASK;
3650 m = PHYS_TO_VM_PAGE(pa);
3651 KASSERT(m->phys_addr == pa,
3652 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
3653 m, (uintmax_t)m->phys_addr,
3656 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
3657 m < &vm_page_array[vm_page_array_size],
3658 ("pmap_remove_pages: bad pte %#jx",
3661 pmap_load_clear(pte);
3664 * Update the vm_page_t clean/reference bits.
3666 if ((tpte & ATTR_AP_RW_BIT) ==
3667 ATTR_AP(ATTR_AP_RW)) {
3670 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3679 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
3682 pc->pc_map[field] |= bitmask;
3685 pmap_resident_count_dec(pmap,
3686 L2_SIZE / PAGE_SIZE);
3687 pvh = pa_to_pvh(tpte & ~ATTR_MASK);
3688 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next);
3690 if (TAILQ_EMPTY(&pvh->pv_list)) {
3691 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++)
3692 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
3693 TAILQ_EMPTY(&mt->md.pv_list))
3694 vm_page_aflag_clear(mt, PGA_WRITEABLE);
3696 ml3 = pmap_remove_pt_page(pmap,
3699 pmap_resident_count_dec(pmap,1);
3700 KASSERT(ml3->wire_count == NL3PG,
3701 ("pmap_remove_pages: l3 page wire count error"));
3702 ml3->wire_count = 1;
3703 vm_page_unwire_noq(ml3);
3704 pmap_add_delayed_free_list(ml3,
3709 pmap_resident_count_dec(pmap, 1);
3710 TAILQ_REMOVE(&m->md.pv_list, pv,
3713 if ((m->aflags & PGA_WRITEABLE) != 0 &&
3714 TAILQ_EMPTY(&m->md.pv_list) &&
3715 (m->flags & PG_FICTITIOUS) == 0) {
3717 VM_PAGE_TO_PHYS(m));
3718 if (TAILQ_EMPTY(&pvh->pv_list))
3719 vm_page_aflag_clear(m,
3724 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde),
3729 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
3730 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
3731 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
3733 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
3737 pmap_invalidate_all(pmap);
3741 vm_page_free_pages_toq(&free, false);
3745 * This is used to check if a page has been accessed or modified. As we
3746 * don't have a bit to see if it has been modified we have to assume it
3747 * has been if the page is read/write.
3750 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
3752 struct rwlock *lock;
3754 struct md_page *pvh;
3755 pt_entry_t *pte, mask, value;
3757 int lvl, md_gen, pvh_gen;
3761 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3764 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3766 if (!PMAP_TRYLOCK(pmap)) {
3767 md_gen = m->md.pv_gen;
3771 if (md_gen != m->md.pv_gen) {
3776 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3778 ("pmap_page_test_mappings: Invalid level %d", lvl));
3782 mask |= ATTR_AP_RW_BIT;
3783 value |= ATTR_AP(ATTR_AP_RW);
3786 mask |= ATTR_AF | ATTR_DESCR_MASK;
3787 value |= ATTR_AF | L3_PAGE;
3789 rv = (pmap_load(pte) & mask) == value;
3794 if ((m->flags & PG_FICTITIOUS) == 0) {
3795 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3796 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
3798 if (!PMAP_TRYLOCK(pmap)) {
3799 md_gen = m->md.pv_gen;
3800 pvh_gen = pvh->pv_gen;
3804 if (md_gen != m->md.pv_gen ||
3805 pvh_gen != pvh->pv_gen) {
3810 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3812 ("pmap_page_test_mappings: Invalid level %d", lvl));
3816 mask |= ATTR_AP_RW_BIT;
3817 value |= ATTR_AP(ATTR_AP_RW);
3820 mask |= ATTR_AF | ATTR_DESCR_MASK;
3821 value |= ATTR_AF | L2_BLOCK;
3823 rv = (pmap_load(pte) & mask) == value;
3837 * Return whether or not the specified physical page was modified
3838 * in any physical maps.
3841 pmap_is_modified(vm_page_t m)
3844 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3845 ("pmap_is_modified: page %p is not managed", m));
3848 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3849 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3850 * is clear, no PTEs can have PG_M set.
3852 VM_OBJECT_ASSERT_WLOCKED(m->object);
3853 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3855 return (pmap_page_test_mappings(m, FALSE, TRUE));
3859 * pmap_is_prefaultable:
3861 * Return whether or not the specified virtual address is eligible
3865 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3873 pte = pmap_pte(pmap, addr, &lvl);
3874 if (pte != NULL && pmap_load(pte) != 0) {
3882 * pmap_is_referenced:
3884 * Return whether or not the specified physical page was referenced
3885 * in any physical maps.
3888 pmap_is_referenced(vm_page_t m)
3891 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3892 ("pmap_is_referenced: page %p is not managed", m));
3893 return (pmap_page_test_mappings(m, TRUE, FALSE));
3897 * Clear the write and modified bits in each of the given page's mappings.
3900 pmap_remove_write(vm_page_t m)
3902 struct md_page *pvh;
3904 struct rwlock *lock;
3905 pv_entry_t next_pv, pv;
3906 pt_entry_t oldpte, *pte;
3908 int lvl, md_gen, pvh_gen;
3910 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3911 ("pmap_remove_write: page %p is not managed", m));
3914 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3915 * set by another thread while the object is locked. Thus,
3916 * if PGA_WRITEABLE is clear, no page table entries need updating.
3918 VM_OBJECT_ASSERT_WLOCKED(m->object);
3919 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3921 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
3922 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
3923 pa_to_pvh(VM_PAGE_TO_PHYS(m));
3926 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
3928 if (!PMAP_TRYLOCK(pmap)) {
3929 pvh_gen = pvh->pv_gen;
3933 if (pvh_gen != pvh->pv_gen) {
3940 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3941 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW))
3942 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET,
3944 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
3945 ("inconsistent pv lock %p %p for page %p",
3946 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
3949 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
3951 if (!PMAP_TRYLOCK(pmap)) {
3952 pvh_gen = pvh->pv_gen;
3953 md_gen = m->md.pv_gen;
3957 if (pvh_gen != pvh->pv_gen ||
3958 md_gen != m->md.pv_gen) {
3964 pte = pmap_pte(pmap, pv->pv_va, &lvl);
3966 oldpte = pmap_load(pte);
3967 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) {
3968 if (!atomic_cmpset_long(pte, oldpte,
3969 oldpte | ATTR_AP(ATTR_AP_RO)))
3971 if ((oldpte & ATTR_AF) != 0)
3973 pmap_invalidate_page(pmap, pv->pv_va);
3978 vm_page_aflag_clear(m, PGA_WRITEABLE);
3981 static __inline boolean_t
3982 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
3989 * pmap_ts_referenced:
3991 * Return a count of reference bits for a page, clearing those bits.
3992 * It is not necessary for every reference bit to be cleared, but it
3993 * is necessary that 0 only be returned when there are truly no
3994 * reference bits set.
3996 * As an optimization, update the page's dirty field if a modified bit is
3997 * found while counting reference bits. This opportunistic update can be
3998 * performed at low cost and can eliminate the need for some future calls
3999 * to pmap_is_modified(). However, since this function stops after
4000 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
4001 * dirty pages. Those dirty pages will only be detected by a future call
4002 * to pmap_is_modified().
4005 pmap_ts_referenced(vm_page_t m)
4007 struct md_page *pvh;
4010 struct rwlock *lock;
4011 pd_entry_t *pde, tpde;
4012 pt_entry_t *pte, tpte;
4016 int cleared, md_gen, not_cleared, lvl, pvh_gen;
4017 struct spglist free;
4020 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4021 ("pmap_ts_referenced: page %p is not managed", m));
4024 pa = VM_PAGE_TO_PHYS(m);
4025 lock = PHYS_TO_PV_LIST_LOCK(pa);
4026 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
4030 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4031 goto small_mappings;
4037 if (!PMAP_TRYLOCK(pmap)) {
4038 pvh_gen = pvh->pv_gen;
4042 if (pvh_gen != pvh->pv_gen) {
4048 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4049 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found"));
4051 ("pmap_ts_referenced: invalid pde level %d", lvl));
4052 tpde = pmap_load(pde);
4053 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE,
4054 ("pmap_ts_referenced: found an invalid l1 table"));
4055 pte = pmap_l1_to_l2(pde, pv->pv_va);
4056 tpte = pmap_load(pte);
4057 if (pmap_page_dirty(tpte)) {
4059 * Although "tpte" is mapping a 2MB page, because
4060 * this function is called at a 4KB page granularity,
4061 * we only update the 4KB page under test.
4065 if ((tpte & ATTR_AF) != 0) {
4067 * Since this reference bit is shared by 512 4KB
4068 * pages, it should not be cleared every time it is
4069 * tested. Apply a simple "hash" function on the
4070 * physical page number, the virtual superpage number,
4071 * and the pmap address to select one 4KB page out of
4072 * the 512 on which testing the reference bit will
4073 * result in clearing that reference bit. This
4074 * function is designed to avoid the selection of the
4075 * same 4KB page for every 2MB page mapping.
4077 * On demotion, a mapping that hasn't been referenced
4078 * is simply destroyed. To avoid the possibility of a
4079 * subsequent page fault on a demoted wired mapping,
4080 * always leave its reference bit set. Moreover,
4081 * since the superpage is wired, the current state of
4082 * its reference bit won't affect page replacement.
4084 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^
4085 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 &&
4086 (tpte & ATTR_SW_WIRED) == 0) {
4087 if (safe_to_clear_referenced(pmap, tpte)) {
4089 * TODO: We don't handle the access
4090 * flag at all. We need to be able
4091 * to set it in the exception handler.
4094 "safe_to_clear_referenced\n");
4095 } else if (pmap_demote_l2_locked(pmap, pte,
4096 pv->pv_va, &lock) != NULL) {
4098 va += VM_PAGE_TO_PHYS(m) -
4099 (tpte & ~ATTR_MASK);
4100 l3 = pmap_l2_to_l3(pte, va);
4101 pmap_remove_l3(pmap, l3, va,
4102 pmap_load(pte), NULL, &lock);
4108 * The superpage mapping was removed
4109 * entirely and therefore 'pv' is no
4117 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4118 ("inconsistent pv lock %p %p for page %p",
4119 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4124 /* Rotate the PV list if it has more than one entry. */
4125 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4126 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4127 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4130 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
4132 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4134 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4141 if (!PMAP_TRYLOCK(pmap)) {
4142 pvh_gen = pvh->pv_gen;
4143 md_gen = m->md.pv_gen;
4147 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
4152 pde = pmap_pde(pmap, pv->pv_va, &lvl);
4153 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found"));
4155 ("pmap_ts_referenced: invalid pde level %d", lvl));
4156 tpde = pmap_load(pde);
4157 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE,
4158 ("pmap_ts_referenced: found an invalid l2 table"));
4159 pte = pmap_l2_to_l3(pde, pv->pv_va);
4160 tpte = pmap_load(pte);
4161 if (pmap_page_dirty(tpte))
4163 if ((tpte & ATTR_AF) != 0) {
4164 if (safe_to_clear_referenced(pmap, tpte)) {
4166 * TODO: We don't handle the access flag
4167 * at all. We need to be able to set it in
4168 * the exception handler.
4170 panic("ARM64TODO: safe_to_clear_referenced\n");
4171 } else if ((tpte & ATTR_SW_WIRED) == 0) {
4173 * Wired pages cannot be paged out so
4174 * doing accessed bit emulation for
4175 * them is wasted effort. We do the
4176 * hard work for unwired pages only.
4178 pmap_remove_l3(pmap, pte, pv->pv_va, tpde,
4180 pmap_invalidate_page(pmap, pv->pv_va);
4185 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
4186 ("inconsistent pv lock %p %p for page %p",
4187 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
4192 /* Rotate the PV list if it has more than one entry. */
4193 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
4194 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4195 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4198 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
4199 not_cleared < PMAP_TS_REFERENCED_MAX);
4202 vm_page_free_pages_toq(&free, false);
4203 return (cleared + not_cleared);
4207 * Apply the given advice to the specified range of addresses within the
4208 * given pmap. Depending on the advice, clear the referenced and/or
4209 * modified flags in each mapping and set the mapped page's dirty field.
4212 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4217 * Clear the modify bits on the specified physical page.
4220 pmap_clear_modify(vm_page_t m)
4223 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4224 ("pmap_clear_modify: page %p is not managed", m));
4225 VM_OBJECT_ASSERT_WLOCKED(m->object);
4226 KASSERT(!vm_page_xbusied(m),
4227 ("pmap_clear_modify: page %p is exclusive busied", m));
4230 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4231 * If the object containing the page is locked and the page is not
4232 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4234 if ((m->aflags & PGA_WRITEABLE) == 0)
4237 /* ARM64TODO: We lack support for tracking if a page is modified */
4241 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4244 return ((void *)PHYS_TO_DMAP(pa));
4248 pmap_unmapbios(vm_paddr_t pa, vm_size_t size)
4253 * Sets the memory attribute for the specified page.
4256 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4259 m->md.pv_memattr = ma;
4262 * If "m" is a normal page, update its direct mapping. This update
4263 * can be relied upon to perform any cache operations that are
4264 * required for data coherence.
4266 if ((m->flags & PG_FICTITIOUS) == 0 &&
4267 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
4268 m->md.pv_memattr) != 0)
4269 panic("memory attribute change on the direct map failed");
4273 * Changes the specified virtual address range's memory type to that given by
4274 * the parameter "mode". The specified virtual address range must be
4275 * completely contained within either the direct map or the kernel map. If
4276 * the virtual address range is contained within the kernel map, then the
4277 * memory type for each of the corresponding ranges of the direct map is also
4278 * changed. (The corresponding ranges of the direct map are those ranges that
4279 * map the same physical pages as the specified virtual address range.) These
4280 * changes to the direct map are necessary because Intel describes the
4281 * behavior of their processors as "undefined" if two or more mappings to the
4282 * same physical page have different memory types.
4284 * Returns zero if the change completed successfully, and either EINVAL or
4285 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4286 * of the virtual address range was not mapped, and ENOMEM is returned if
4287 * there was insufficient memory available to complete the change. In the
4288 * latter case, the memory type may have been changed on some part of the
4289 * virtual address range or the direct map.
4292 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4296 PMAP_LOCK(kernel_pmap);
4297 error = pmap_change_attr_locked(va, size, mode);
4298 PMAP_UNLOCK(kernel_pmap);
4303 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode)
4305 vm_offset_t base, offset, tmpva;
4306 pt_entry_t l3, *pte, *newpte;
4309 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
4310 base = trunc_page(va);
4311 offset = va & PAGE_MASK;
4312 size = round_page(offset + size);
4314 if (!VIRT_IN_DMAP(base))
4317 for (tmpva = base; tmpva < base + size; ) {
4318 pte = pmap_pte(kernel_pmap, va, &lvl);
4322 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) {
4324 * We already have the correct attribute,
4325 * ignore this entry.
4329 panic("Invalid DMAP table level: %d\n", lvl);
4331 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE;
4334 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE;
4342 * Split the entry to an level 3 table, then
4343 * set the new attribute.
4347 panic("Invalid DMAP table level: %d\n", lvl);
4349 newpte = pmap_demote_l1(kernel_pmap, pte,
4350 tmpva & ~L1_OFFSET);
4353 pte = pmap_l1_to_l2(pte, tmpva);
4355 newpte = pmap_demote_l2(kernel_pmap, pte,
4356 tmpva & ~L2_OFFSET);
4359 pte = pmap_l2_to_l3(pte, tmpva);
4361 /* Update the entry */
4362 l3 = pmap_load(pte);
4363 l3 &= ~ATTR_IDX_MASK;
4364 l3 |= ATTR_IDX(mode);
4365 if (mode == DEVICE_MEMORY)
4368 pmap_update_entry(kernel_pmap, pte, l3, tmpva,
4372 * If moving to a non-cacheable entry flush
4375 if (mode == VM_MEMATTR_UNCACHEABLE)
4376 cpu_dcache_wbinv_range(tmpva, L3_SIZE);
4388 * Create an L2 table to map all addresses within an L1 mapping.
4391 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va)
4393 pt_entry_t *l2, newl2, oldl1;
4395 vm_paddr_t l2phys, phys;
4399 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4400 oldl1 = pmap_load(l1);
4401 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK,
4402 ("pmap_demote_l1: Demoting a non-block entry"));
4403 KASSERT((va & L1_OFFSET) == 0,
4404 ("pmap_demote_l1: Invalid virtual address %#lx", va));
4405 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0,
4406 ("pmap_demote_l1: Level 1 table shouldn't be managed"));
4409 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) {
4410 tmpl1 = kva_alloc(PAGE_SIZE);
4415 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT |
4416 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
4417 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx"
4418 " in pmap %p", va, pmap);
4422 l2phys = VM_PAGE_TO_PHYS(ml2);
4423 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys);
4425 /* Address the range points at */
4426 phys = oldl1 & ~ATTR_MASK;
4427 /* The attributed from the old l1 table to be copied */
4428 newl2 = oldl1 & ATTR_MASK;
4430 /* Create the new entries */
4431 for (i = 0; i < Ln_ENTRIES; i++) {
4432 l2[i] = newl2 | phys;
4435 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK),
4436 ("Invalid l2 page (%lx != %lx)", l2[0],
4437 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK));
4440 pmap_kenter(tmpl1, PAGE_SIZE,
4441 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY);
4442 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK));
4445 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE);
4448 pmap_kremove(tmpl1);
4449 kva_free(tmpl1, PAGE_SIZE);
4456 * Create an L3 table to map all addresses within an L2 mapping.
4459 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va,
4460 struct rwlock **lockp)
4462 pt_entry_t *l3, newl3, oldl2;
4464 vm_paddr_t l3phys, phys;
4468 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4470 oldl2 = pmap_load(l2);
4471 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK,
4472 ("pmap_demote_l2: Demoting a non-block entry"));
4473 KASSERT((va & L2_OFFSET) == 0,
4474 ("pmap_demote_l2: Invalid virtual address %#lx", va));
4477 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) {
4478 tmpl2 = kva_alloc(PAGE_SIZE);
4483 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) {
4484 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va),
4485 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4486 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4488 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx"
4489 " in pmap %p", va, pmap);
4492 if (va < VM_MAXUSER_ADDRESS)
4493 pmap_resident_count_inc(pmap, 1);
4496 l3phys = VM_PAGE_TO_PHYS(ml3);
4497 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys);
4499 /* Address the range points at */
4500 phys = oldl2 & ~ATTR_MASK;
4501 /* The attributed from the old l2 table to be copied */
4502 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE;
4505 * If the page table page is new, initialize it.
4507 if (ml3->wire_count == 1) {
4508 for (i = 0; i < Ln_ENTRIES; i++) {
4509 l3[i] = newl3 | phys;
4513 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE),
4514 ("Invalid l3 page (%lx != %lx)", l3[0],
4515 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE));
4518 * Map the temporary page so we don't lose access to the l2 table.
4521 pmap_kenter(tmpl2, PAGE_SIZE,
4522 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY);
4523 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK));
4527 * The spare PV entries must be reserved prior to demoting the
4528 * mapping, that is, prior to changing the PDE. Otherwise, the state
4529 * of the L2 and the PV lists will be inconsistent, which can result
4530 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4531 * wrong PV list and pmap_pv_demote_l2() failing to find the expected
4532 * PV entry for the 2MB page mapping that is being demoted.
4534 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4535 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp);
4537 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE);
4540 * Demote the PV entry.
4542 if ((oldl2 & ATTR_SW_MANAGED) != 0)
4543 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp);
4545 atomic_add_long(&pmap_l2_demotions, 1);
4546 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx"
4547 " in pmap %p %lx", va, pmap, l3[0]);
4551 pmap_kremove(tmpl2);
4552 kva_free(tmpl2, PAGE_SIZE);
4560 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va)
4562 struct rwlock *lock;
4566 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock);
4573 * perform the pmap work for mincore
4576 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
4578 pd_entry_t *l1p, l1;
4579 pd_entry_t *l2p, l2;
4580 pt_entry_t *l3p, l3;
4591 l1p = pmap_l1(pmap, addr);
4592 if (l1p == NULL) /* No l1 */
4595 l1 = pmap_load(l1p);
4596 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
4599 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
4600 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
4601 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4602 val = MINCORE_SUPER | MINCORE_INCORE;
4603 if (pmap_page_dirty(l1))
4604 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4605 if ((l1 & ATTR_AF) == ATTR_AF)
4606 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4610 l2p = pmap_l1_to_l2(l1p, addr);
4611 if (l2p == NULL) /* No l2 */
4614 l2 = pmap_load(l2p);
4615 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
4618 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
4619 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
4620 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4621 val = MINCORE_SUPER | MINCORE_INCORE;
4622 if (pmap_page_dirty(l2))
4623 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4624 if ((l2 & ATTR_AF) == ATTR_AF)
4625 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4629 l3p = pmap_l2_to_l3(l2p, addr);
4630 if (l3p == NULL) /* No l3 */
4633 l3 = pmap_load(l2p);
4634 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
4637 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
4638 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
4639 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
4640 val = MINCORE_INCORE;
4641 if (pmap_page_dirty(l3))
4642 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
4643 if ((l3 & ATTR_AF) == ATTR_AF)
4644 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
4648 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
4649 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) {
4650 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
4651 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
4654 PA_UNLOCK_COND(*locked_pa);
4661 pmap_activate(struct thread *td)
4666 pmap = vmspace_pmap(td->td_proc->p_vmspace);
4667 td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
4668 __asm __volatile("msr ttbr0_el1, %0" : :
4669 "r"(td->td_proc->p_md.md_l0addr));
4670 pmap_invalidate_all(pmap);
4675 pmap_switch(struct thread *old, struct thread *new)
4677 pcpu_bp_harden bp_harden;
4680 /* Store the new curthread */
4681 PCPU_SET(curthread, new);
4683 /* And the new pcb */
4685 PCPU_SET(curpcb, pcb);
4688 * TODO: We may need to flush the cache here if switching
4689 * to a user process.
4693 old->td_proc->p_md.md_l0addr != new->td_proc->p_md.md_l0addr) {
4695 /* Switch to the new pmap */
4696 "msr ttbr0_el1, %0 \n"
4699 /* Invalidate the TLB */
4704 : : "r"(new->td_proc->p_md.md_l0addr));
4707 * Stop userspace from training the branch predictor against
4708 * other processes. This will call into a CPU specific
4709 * function that clears the branch predictor state.
4711 bp_harden = PCPU_GET(bp_harden);
4712 if (bp_harden != NULL)
4720 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
4723 if (va >= VM_MIN_KERNEL_ADDRESS) {
4724 cpu_icache_sync_range(va, sz);
4729 /* Find the length of data in this page to flush */
4730 offset = va & PAGE_MASK;
4731 len = imin(PAGE_SIZE - offset, sz);
4734 /* Extract the physical address & find it in the DMAP */
4735 pa = pmap_extract(pmap, va);
4737 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len);
4739 /* Move to the next page */
4742 /* Set the length for the next iteration */
4743 len = imin(PAGE_SIZE, sz);
4749 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far)
4755 switch (ESR_ELx_EXCEPTION(esr)) {
4756 case EXCP_INSN_ABORT_L:
4757 case EXCP_INSN_ABORT:
4758 case EXCP_DATA_ABORT_L:
4759 case EXCP_DATA_ABORT:
4762 return (KERN_FAILURE);
4765 /* Data and insn aborts use same encoding for FCS field. */
4767 switch (esr & ISS_DATA_DFSC_MASK) {
4768 case ISS_DATA_DFSC_TF_L0:
4769 case ISS_DATA_DFSC_TF_L1:
4770 case ISS_DATA_DFSC_TF_L2:
4771 case ISS_DATA_DFSC_TF_L3:
4772 /* Ask the MMU to check the address */
4773 intr = intr_disable();
4774 if (pmap == kernel_pmap)
4775 par = arm64_address_translate_s1e1r(far);
4777 par = arm64_address_translate_s1e0r(far);
4781 * If the translation was successful the address was invalid
4782 * due to a break-before-make sequence. We can unlock and
4783 * return success to the trap handler.
4785 if (PAR_SUCCESS(par)) {
4787 return (KERN_SUCCESS);
4796 return (KERN_FAILURE);
4800 * Increase the starting virtual address of the given mapping if a
4801 * different alignment might result in more superpage mappings.
4804 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
4805 vm_offset_t *addr, vm_size_t size)
4807 vm_offset_t superpage_offset;
4811 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
4812 offset += ptoa(object->pg_color);
4813 superpage_offset = offset & L2_OFFSET;
4814 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE ||
4815 (*addr & L2_OFFSET) == superpage_offset)
4817 if ((*addr & L2_OFFSET) < superpage_offset)
4818 *addr = (*addr & ~L2_OFFSET) + superpage_offset;
4820 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset;
4824 * Get the kernel virtual address of a set of physical pages. If there are
4825 * physical addresses not covered by the DMAP perform a transient mapping
4826 * that will be removed when calling pmap_unmap_io_transient.
4828 * \param page The pages the caller wishes to obtain the virtual
4829 * address on the kernel memory map.
4830 * \param vaddr On return contains the kernel virtual memory address
4831 * of the pages passed in the page parameter.
4832 * \param count Number of pages passed in.
4833 * \param can_fault TRUE if the thread using the mapped pages can take
4834 * page faults, FALSE otherwise.
4836 * \returns TRUE if the caller must call pmap_unmap_io_transient when
4837 * finished or FALSE otherwise.
4841 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4842 boolean_t can_fault)
4845 boolean_t needs_mapping;
4849 * Allocate any KVA space that we need, this is done in a separate
4850 * loop to prevent calling vmem_alloc while pinned.
4852 needs_mapping = FALSE;
4853 for (i = 0; i < count; i++) {
4854 paddr = VM_PAGE_TO_PHYS(page[i]);
4855 if (__predict_false(!PHYS_IN_DMAP(paddr))) {
4856 error = vmem_alloc(kernel_arena, PAGE_SIZE,
4857 M_BESTFIT | M_WAITOK, &vaddr[i]);
4858 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
4859 needs_mapping = TRUE;
4861 vaddr[i] = PHYS_TO_DMAP(paddr);
4865 /* Exit early if everything is covered by the DMAP */
4871 for (i = 0; i < count; i++) {
4872 paddr = VM_PAGE_TO_PHYS(page[i]);
4873 if (!PHYS_IN_DMAP(paddr)) {
4875 "pmap_map_io_transient: TODO: Map out of DMAP data");
4879 return (needs_mapping);
4883 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
4884 boolean_t can_fault)
4891 for (i = 0; i < count; i++) {
4892 paddr = VM_PAGE_TO_PHYS(page[i]);
4893 if (!PHYS_IN_DMAP(paddr)) {
4894 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data");