2 * Copyright (c) 2013-2015 Sandvine Inc. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <sys/fcntl.h>
38 #include <sys/ioccom.h>
40 #include <sys/linker.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/pciio.h>
44 #include <sys/queue.h>
46 #include <sys/sysctl.h>
48 #include <machine/bus.h>
49 #include <machine/stdarg.h>
52 #include <sys/iov_schema.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pci_private.h>
57 #include <dev/pci/pci_iov_private.h>
58 #include <dev/pci/schema_private.h>
63 static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations");
65 static d_ioctl_t pci_iov_ioctl;
67 static struct cdevsw iov_cdevsw = {
68 .d_version = D_VERSION,
70 .d_ioctl = pci_iov_ioctl
76 * The maximum amount of memory we will allocate for user configuration of an
77 * SR-IOV device. 1MB ought to be enough for anyone, but leave this
78 * configurable just in case.
80 static u_long pci_iov_max_config = 1024 * 1024;
81 SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN,
82 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration.");
85 #define IOV_READ(d, r, w) \
86 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
88 #define IOV_WRITE(d, r, v, w) \
89 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w)
91 static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema,
92 nvlist_t **vf_schema);
93 static void pci_iov_build_pf_schema(nvlist_t *schema,
94 nvlist_t **driver_schema);
95 static void pci_iov_build_vf_schema(nvlist_t *schema,
96 nvlist_t **driver_schema);
97 static nvlist_t *pci_iov_get_pf_subsystem_schema(void);
98 static nvlist_t *pci_iov_get_vf_subsystem_schema(void);
101 pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema,
105 struct pci_devinfo *dinfo;
106 struct pcicfg_iov *iov;
112 dinfo = device_get_ivars(dev);
113 pcib = device_get_parent(bus);
116 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
121 version = pci_read_config(dev, iov_pos, 4);
122 if (PCI_EXTCAP_VER(version) != 1) {
125 "Unsupported version of SR-IOV (%d) detected\n",
126 PCI_EXTCAP_VER(version));
131 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO);
134 if (dinfo->cfg.iov != NULL) {
138 iov->iov_pos = iov_pos;
140 schema = pci_iov_build_schema(&pf_schema, &vf_schema);
141 if (schema == NULL) {
146 error = pci_iov_validate_schema(schema);
149 iov->iov_schema = schema;
151 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev),
152 UID_ROOT, GID_WHEEL, 0600, "iov/%s", device_get_nameunit(dev));
154 if (iov->iov_cdev == NULL) {
159 dinfo->cfg.iov = iov;
160 iov->iov_cdev->si_drv1 = dinfo;
166 nvlist_destroy(schema);
167 nvlist_destroy(pf_schema);
168 nvlist_destroy(vf_schema);
175 pci_iov_detach_method(device_t bus, device_t dev)
177 struct pci_devinfo *dinfo;
178 struct pcicfg_iov *iov;
181 dinfo = device_get_ivars(dev);
182 iov = dinfo->cfg.iov;
189 if (iov->iov_num_vfs != 0 || iov->iov_flags & IOV_BUSY) {
194 dinfo->cfg.iov = NULL;
197 destroy_dev(iov->iov_cdev);
198 iov->iov_cdev = NULL;
200 nvlist_destroy(iov->iov_schema);
209 pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf)
211 nvlist_t *schema, *pf_driver, *vf_driver;
213 /* We always take ownership of the schemas. */
219 schema = pci_iov_schema_alloc_node();
223 pci_iov_build_pf_schema(schema, &pf_driver);
224 pci_iov_build_vf_schema(schema, &vf_driver);
226 if (nvlist_error(schema) != 0)
232 nvlist_destroy(schema);
233 nvlist_destroy(pf_driver);
234 nvlist_destroy(vf_driver);
239 pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema)
241 nvlist_t *pf_schema, *iov_schema;
243 pf_schema = pci_iov_schema_alloc_node();
244 if (pf_schema == NULL) {
245 nvlist_set_error(schema, ENOMEM);
249 iov_schema = pci_iov_get_pf_subsystem_schema();
252 * Note that if either *driver_schema or iov_schema is NULL, then
253 * nvlist_move_nvlist will put the schema in the error state and
254 * SR-IOV will fail to initialize later, so we don't have to explicitly
257 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema);
258 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema);
259 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema);
260 *driver_schema = NULL;
264 pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema)
266 nvlist_t *vf_schema, *iov_schema;
268 vf_schema = pci_iov_schema_alloc_node();
269 if (vf_schema == NULL) {
270 nvlist_set_error(schema, ENOMEM);
274 iov_schema = pci_iov_get_vf_subsystem_schema();
277 * Note that if either *driver_schema or iov_schema is NULL, then
278 * nvlist_move_nvlist will put the schema in the error state and
279 * SR-IOV will fail to initialize later, so we don't have to explicitly
282 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema);
283 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema);
284 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema);
285 *driver_schema = NULL;
289 pci_iov_get_pf_subsystem_schema(void)
293 pf = pci_iov_schema_alloc_node();
297 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1);
298 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL);
304 pci_iov_get_vf_subsystem_schema(void)
308 vf = pci_iov_schema_alloc_node();
312 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0);
318 pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift)
320 struct resource *res;
321 struct pcicfg_iov *iov;
327 iov = dinfo->cfg.iov;
328 dev = dinfo->cfg.dev;
329 bus = device_get_parent(dev);
330 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar);
331 bar_size = 1 << bar_shift;
333 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0ul,
334 ~0ul, 1, iov->iov_num_vfs, RF_ACTIVE);
339 iov->iov_bar[bar].res = res;
340 iov->iov_bar[bar].bar_size = bar_size;
341 iov->iov_bar[bar].bar_shift = bar_shift;
343 start = rman_get_start(res);
344 end = rman_get_end(res);
345 return (rman_manage_region(&iov->rman, start, end));
349 pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo)
351 struct pci_iov_bar *bar;
355 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
356 bar = &iov->iov_bar[i];
357 if (bar->res != NULL) {
358 bar_start = rman_get_start(bar->res) +
359 dinfo->cfg.vf.index * bar->bar_size;
361 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start,
368 pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg,
376 packed_config = NULL;
378 if (arg->len > pci_iov_max_config) {
383 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK);
385 error = copyin(arg->config, packed_config, arg->len);
389 config = nvlist_unpack(packed_config, arg->len);
390 if (config == NULL) {
395 error = pci_iov_schema_validate_config(iov->iov_schema, config);
399 error = nvlist_error(config);
407 nvlist_destroy(config);
408 free(packed_config, M_SRIOV);
413 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
414 * capability. This bit is only writeable on the lowest-numbered PF but
415 * affects all PFs on the device.
418 pci_iov_set_ari(device_t bus)
422 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
425 /* If ARI is disabled on the downstream port there is nothing to do. */
426 if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
429 error = device_get_children(bus, &devlist, &devcount);
435 for (i = 0; i < devcount; i++) {
436 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
437 dev_func = pci_get_function(devlist[i]);
438 if (lowest == NULL || dev_func < lowest_func) {
440 lowest_func = dev_func;
441 lowest_pos = iov_pos;
447 * If we called this function some device must have the SR-IOV
450 KASSERT(lowest != NULL,
451 ("Could not find child of %s with SR-IOV capability",
452 device_get_nameunit(bus)));
454 iov_ctl = pci_read_config(lowest, iov_pos + PCIR_SRIOV_CTL, 2);
455 iov_ctl |= PCIM_SRIOV_ARI_EN;
456 pci_write_config(lowest, iov_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
457 free(devlist, M_TEMP);
462 pci_iov_config_page_size(struct pci_devinfo *dinfo)
464 uint32_t page_cap, page_size;
466 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4);
469 * If the system page size is less than the smallest SR-IOV page size
470 * then round up to the smallest SR-IOV page size.
472 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT)
473 page_size = (1 << 0);
475 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT));
477 /* Check that the device supports the system page size. */
478 if (!(page_size & page_cap))
481 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4);
486 pci_init_iov(device_t dev, uint16_t num_vfs, const nvlist_t *config)
488 const nvlist_t *device, *driver_config;
490 device = nvlist_get_nvlist(config, PF_CONFIG_NAME);
491 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
492 return (PCI_INIT_IOV(dev, num_vfs, driver_config));
496 pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov)
500 iov->rman.rm_start = 0;
501 iov->rman.rm_end = ~0ul;
502 iov->rman.rm_type = RMAN_ARRAY;
503 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory",
504 device_get_nameunit(pf));
505 iov->rman.rm_descr = iov->rman_name;
507 error = rman_init(&iov->rman);
511 iov->iov_flags |= IOV_RMAN_INITED;
516 pci_iov_setup_bars(struct pci_devinfo *dinfo)
519 struct pcicfg_iov *iov;
520 pci_addr_t bar_value, testval;
521 int i, last_64, error;
523 iov = dinfo->cfg.iov;
524 dev = dinfo->cfg.dev;
527 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
529 * If a PCI BAR is a 64-bit wide BAR, then it spans two
530 * consecutive registers. Therefore if the last BAR that
531 * we looked at was a 64-bit BAR, we need to skip this
532 * register as it's the second half of the last BAR.
536 iov->iov_pos + PCIR_SRIOV_BAR(i),
537 &bar_value, &testval, &last_64);
540 error = pci_iov_alloc_bar(dinfo, i,
541 pci_mapsize(testval));
553 pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config,
554 uint16_t first_rid, uint16_t rid_stride)
556 char device_name[VF_MAX_NAME];
557 const nvlist_t *device, *driver_config, *iov_config;
558 device_t bus, dev, vf;
559 struct pcicfg_iov *iov;
560 struct pci_devinfo *vfinfo;
563 uint16_t vid, did, next_rid;
565 iov = dinfo->cfg.iov;
566 dev = dinfo->cfg.dev;
567 bus = device_get_parent(dev);
568 size = dinfo->cfg.devinfo_size;
569 next_rid = first_rid;
570 vid = pci_get_vendor(dev);
571 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2);
573 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) {
574 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i);
575 device = nvlist_get_nvlist(config, device_name);
576 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME);
577 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME);
579 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did);
584 * If we are creating passthrough devices then force the ppt
585 * driver to attach to prevent a VF driver from claiming the
588 if (nvlist_get_bool(iov_config, "passthrough"))
589 device_set_devclass(vf, "ppt");
591 vfinfo = device_get_ivars(vf);
593 vfinfo->cfg.iov = iov;
594 vfinfo->cfg.vf.index = i;
596 pci_iov_add_bars(iov, vfinfo);
598 error = PCI_ADD_VF(dev, i, driver_config);
600 device_printf(dev, "Failed to add VF %d\n", i);
601 pci_delete_child(bus, vf);
605 bus_generic_attach(bus);
609 pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg)
612 struct pci_devinfo *dinfo;
613 struct pcicfg_iov *iov;
616 uint16_t rid_off, rid_stride;
617 uint16_t first_rid, last_rid;
619 uint16_t num_vfs, total_vfs;
623 dinfo = cdev->si_drv1;
624 iov = dinfo->cfg.iov;
625 dev = dinfo->cfg.dev;
626 bus = device_get_parent(dev);
630 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) {
634 iov->iov_flags |= IOV_BUSY;
636 error = pci_iov_parse_config(iov, arg, &config);
640 num_vfs = pci_iov_config_get_num_vfs(config);
641 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2);
642 if (num_vfs > total_vfs) {
647 error = pci_iov_config_page_size(dinfo);
651 error = pci_iov_set_ari(bus);
655 error = pci_init_iov(dev, num_vfs, config);
660 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2);
662 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2);
663 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2);
665 first_rid = pci_get_rid(dev) + rid_off;
666 last_rid = first_rid + (num_vfs - 1) * rid_stride;
668 /* We don't yet support allocating extra bus numbers for VFs. */
669 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) {
674 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
675 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
676 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
678 error = pci_iov_init_rman(dev, iov);
682 iov->iov_num_vfs = num_vfs;
684 error = pci_iov_setup_bars(dinfo);
688 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
689 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE;
690 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
692 /* Per specification, we must wait 100ms before accessing VFs. */
693 pause("iov", roundup(hz, 10));
694 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride);
696 nvlist_destroy(config);
697 iov->iov_flags &= ~IOV_BUSY;
705 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
706 if (iov->iov_bar[i].res != NULL) {
707 pci_release_resource(bus, dev, SYS_RES_MEMORY,
708 iov->iov_pos + PCIR_SRIOV_BAR(i),
709 iov->iov_bar[i].res);
710 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
711 iov->iov_pos + PCIR_SRIOV_BAR(i));
712 iov->iov_bar[i].res = NULL;
716 if (iov->iov_flags & IOV_RMAN_INITED) {
717 rman_fini(&iov->rman);
718 iov->iov_flags &= ~IOV_RMAN_INITED;
721 nvlist_destroy(config);
722 iov->iov_num_vfs = 0;
723 iov->iov_flags &= ~IOV_BUSY;
728 /* Return true if child is a VF of the given PF. */
730 pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child)
732 struct pci_devinfo *vfinfo;
734 vfinfo = device_get_ivars(child);
736 if (!(vfinfo->cfg.flags & PCICFG_VF))
739 return (pf == vfinfo->cfg.iov);
743 pci_iov_delete(struct cdev *cdev)
745 device_t bus, dev, vf, *devlist;
746 struct pci_devinfo *dinfo;
747 struct pcicfg_iov *iov;
748 int i, error, devcount;
752 dinfo = cdev->si_drv1;
753 iov = dinfo->cfg.iov;
754 dev = dinfo->cfg.dev;
755 bus = device_get_parent(dev);
758 if (iov->iov_flags & IOV_BUSY) {
763 if (iov->iov_num_vfs == 0) {
768 iov->iov_flags |= IOV_BUSY;
770 error = device_get_children(bus, &devlist, &devcount);
775 for (i = 0; i < devcount; i++) {
778 if (!pci_iov_is_child_vf(iov, vf))
781 error = device_detach(vf);
784 "Could not disable SR-IOV: failed to detach VF %s\n",
785 device_get_nameunit(vf));
790 for (i = 0; i < devcount; i++) {
793 if (pci_iov_is_child_vf(iov, vf))
794 pci_delete_child(bus, vf);
798 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
799 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
800 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
801 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2);
803 iov->iov_num_vfs = 0;
805 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
806 if (iov->iov_bar[i].res != NULL) {
807 pci_release_resource(bus, dev, SYS_RES_MEMORY,
808 iov->iov_pos + PCIR_SRIOV_BAR(i),
809 iov->iov_bar[i].res);
810 pci_delete_resource(bus, dev, SYS_RES_MEMORY,
811 iov->iov_pos + PCIR_SRIOV_BAR(i));
812 iov->iov_bar[i].res = NULL;
816 if (iov->iov_flags & IOV_RMAN_INITED) {
817 rman_fini(&iov->rman);
818 iov->iov_flags &= ~IOV_RMAN_INITED;
823 free(devlist, M_TEMP);
824 iov->iov_flags &= ~IOV_BUSY;
830 pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output)
832 struct pci_devinfo *dinfo;
834 size_t output_len, size;
840 dinfo = cdev->si_drv1;
841 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size);
844 if (packed == NULL) {
849 output_len = output->len;
851 if (size <= output_len) {
852 error = copyout(packed, output->schema, size);
860 * If we return an error then the ioctl code won't copyout
861 * output back to userland, so we flag the error in the struct
864 output->error = EMSGSIZE;
869 free(packed, M_NVLIST);
875 pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
881 return (pci_iov_config(dev, (struct pci_iov_arg *)data));
883 return (pci_iov_delete(dev));
885 return (pci_iov_get_schema_ioctl(dev,
886 (struct pci_iov_schema *)data));
893 pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, u_long start,
894 u_long end, u_long count, u_int flags)
896 struct pci_devinfo *dinfo;
897 struct pcicfg_iov *iov;
899 struct resource *res;
900 struct resource_list_entry *rle;
901 u_long bar_start, bar_end;
902 pci_addr_t bar_length;
905 dinfo = device_get_ivars(child);
906 iov = dinfo->cfg.iov;
908 map = pci_find_bar(child, *rid);
912 bar_length = 1 << map->pm_size;
913 bar_start = map->pm_value;
914 bar_end = bar_start + bar_length - 1;
916 /* Make sure that the resource fits the constraints. */
917 if (bar_start >= end || bar_end <= bar_start || count != 1)
920 /* Clamp the resource to the constraints if necessary. */
921 if (bar_start < start)
925 bar_length = bar_end - bar_start + 1;
927 res = rman_reserve_resource(&iov->rman, bar_start, bar_end,
928 bar_length, flags, child);
932 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid,
933 bar_start, bar_end, 1);
935 rman_release_resource(res);
939 rman_set_rid(res, *rid);
941 if (flags & RF_ACTIVE) {
942 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res);
944 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
946 rman_release_resource(res);
956 pci_vf_release_mem_resource(device_t dev, device_t child, int rid,
959 struct pci_devinfo *dinfo;
960 struct resource_list_entry *rle;
963 dinfo = device_get_ivars(child);
965 if (rman_get_flags(r) & RF_ACTIVE) {
966 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r);
971 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid);
974 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY,
978 return (rman_release_resource(r));