From: sjg Date: Mon, 19 Nov 2012 20:07:56 +0000 (-0800) Subject: Add sysctl cpu info task X-Git-Url: https://gitweb.dragonflybsd.org/ikiwiki.git/commitdiff_plain/ff6945544c97179d8390ad0e184bc0fcc3a0a270?ds=sidebyside Add sysctl cpu info task --- diff --git a/docs/developer/ProjectsPage.mdwn b/docs/developer/ProjectsPage.mdwn index e4d234ba..673c8100 100644 --- a/docs/developer/ProjectsPage.mdwn +++ b/docs/developer/ProjectsPage.mdwn @@ -246,6 +246,100 @@ Projects that can be clearly used for Google Code-In are marked with their categ * Adjust error messages to print the spinlock desc field. * This change will require a full world & kernel recompile. +### Add informational hardware-related sysctl's +* MacOS X exports a bunch of cpu-specific sysctl's detailing sizes, layout, features, etc. Most/all of this could be detected by a userspace program, but exporting these makes the barrier of entry to cpu-conditional code lower. +* Research which of these sysctl's is the most useful and add them, using the same node names as OSX. +1. hw.vectorunit = 1 +1. hw.busfrequency = 100000000 +1. hw.cpufrequency = 3062000000 +1. hw.cachelinesize = 64 +1. hw.l1icachesize = 32768 +1. hw.l1dcachesize = 32768 +1. hw.l2settings = 1 +1. hw.l2cachesize = 262144 +1. hw.l3settings = 1 +1. hw.l3cachesize = 6291456 +1. hw.tbfrequency = 1000000000 +1. hw.activecpu: 2 +1. hw.physicalcpu: 2 +1. hw.physicalcpu_max: 2 +1. hw.logicalcpu: 2 +1. hw.logicalcpu_max: 2 +1. hw.cputype: 7 +1. hw.cpusubtype: 4 +1. hw.cpu64bit_capable: 1 +1. hw.cpufamily: 1418770316 +1. hw.cacheconfig: 2 1 1 1 0 0 0 0 0 0 +1. hw.cachesize: 2147483648 32768 262144 6291456 0 0 0 0 0 0 +1. hw.busfrequency: 100000000 +1. hw.busfrequency_min: 100000000 +1. hw.busfrequency_max: 100000000 +1. hw.cpufrequency: 3062000000 +1. hw.cpufrequency_min: 3062000000 +1. hw.cpufrequency_max: 3062000000 +1. hw.cachelinesize: 64 +1. hw.l1icachesize: 32768 +1. hw.l1dcachesize: 32768 +1. hw.l2cachesize: 262144 +1. hw.l3cachesize: 6291456 +1. hw.tbfrequency: 1000000000 +1. hw.packages: 2 +1. hw.optional.floatingpoint: 1 +1. hw.optional.mmx: 1 +1. hw.optional.sse: 1 +1. hw.optional.sse2: 1 +1. hw.optional.sse3: 1 +1. hw.optional.supplementalsse3: 1 +1. hw.optional.sse4_1: 1 +1. hw.optional.sse4_2: 1 +1. hw.optional.x86_64: 1 +1. hw.optional.aes: 1 +1. hw.optional.avx1_0: 1 +1. hw.optional.rdrand: 0 +1. hw.optional.f16c: 0 +1. hw.optional.enfstrg: 0 +1. machdep.cpu.max_basic: 13 +1. machdep.cpu.max_ext: 2147483656 +1. machdep.cpu.vendor: GenuineIntel +1. machdep.cpu.brand_string: Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz +1. machdep.cpu.family: 6 +1. machdep.cpu.model: 42 +1. machdep.cpu.extmodel: 2 +1. machdep.cpu.extfamily: 0 +1. machdep.cpu.stepping: 7 +1. machdep.cpu.feature_bits: 262929407 2660770315 +1. machdep.cpu.extfeature_bits: 672139520 1 +1. machdep.cpu.signature: 132775 +1. machdep.cpu.brand: 0 +1. machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH DS MMX FXSR SSE SSE2 SS SSE3 PCLMULQDQ MON SSSE3 CX16 SSE4.1 SSE4.2 POPCNT AES VMM XSAVE OSXSAVE AVX1.0 +1. machdep.cpu.extfeatures: SYSCALL XD EM64T LAHF RDTSCP TSCI +1. machdep.cpu.cores_per_package: 1 +1. machdep.cpu.microcode_version: 16 +1. machdep.cpu.processor_flag: 0 +1. machdep.cpu.mwait.linesize_min: 4096 +1. machdep.cpu.mwait.linesize_max: 4096 +1. machdep.cpu.mwait.extensions: 3 +1. machdep.cpu.mwait.sub_Cstates: 4384 +1. machdep.cpu.xsave.extended_state: 7 832 832 0 +1. machdep.cpu.arch_perf.version: 1 +1. machdep.cpu.arch_perf.number: 8 +1. machdep.cpu.arch_perf.width: 48 +1. machdep.cpu.arch_perf.events_number: 7 +1. machdep.cpu.arch_perf.events: 127 +1. machdep.cpu.arch_perf.fixed_number: 0 +1. machdep.cpu.arch_perf.fixed_width: 0 +1. machdep.cpu.cache.linesize: 64 +1. machdep.cpu.cache.L2_associativity: 8 +1. machdep.cpu.cache.size: 256 +1. machdep.cpu.tlb.inst.small: 128 +1. machdep.cpu.tlb.data.small: 64 +1. machdep.cpu.tlb.data.large: 32 +1. machdep.cpu.tlb.shared: 512 +1. machdep.cpu.address_bits.physical: 40 +1. machdep.cpu.address_bits.virtual: 48 +1. machdep.cpu.core_count: 1 +1. machdep.cpu.thread_count: 1 + ## Live images enhancement The live images could be made easier to use by not assuming a QWERTY keyboard layout.