drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 struct ddi_buf_trans {
  32         u32 trans1;     /* balance leg enable, de-emph level */
  33         u32 trans2;     /* vref sel, vswing */
  34         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  35 };
  36
  37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  38  * them for both DP and FDI transports, allowing those ports to
  39  * automatically adapt to HDMI connections as well
  40  */
  41 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  42         { 0x00FFFFFF, 0x0006000E, 0x0 },
  43         { 0x00D75FFF, 0x0005000A, 0x0 },
  44         { 0x00C30FFF, 0x00040006, 0x0 },
  45         { 0x80AAAFFF, 0x000B0000, 0x0 },
  46         { 0x00FFFFFF, 0x0005000A, 0x0 },
  47         { 0x00D75FFF, 0x000C0004, 0x0 },
  48         { 0x80C30FFF, 0x000B0000, 0x0 },
  49         { 0x00FFFFFF, 0x00040006, 0x0 },
  50         { 0x80D75FFF, 0x000B0000, 0x0 },
  51 };
  52
  53 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  54         { 0x00FFFFFF, 0x0007000E, 0x0 },
  55         { 0x00D75FFF, 0x000F000A, 0x0 },
  56         { 0x00C30FFF, 0x00060006, 0x0 },
  57         { 0x00AAAFFF, 0x001E0000, 0x0 },
  58         { 0x00FFFFFF, 0x000F000A, 0x0 },
  59         { 0x00D75FFF, 0x00160004, 0x0 },
  60         { 0x00C30FFF, 0x001E0000, 0x0 },
  61         { 0x00FFFFFF, 0x00060006, 0x0 },
  62         { 0x00D75FFF, 0x001E0000, 0x0 },
  63 };
  64
  65 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  66                                         /* Idx  NT mV d T mV d  db      */
  67         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  68         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  69         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  70         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  71         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  72         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  73         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  74         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  75         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  76         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  77         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  78         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  79 };
  80
  81 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  82         { 0x00FFFFFF, 0x00000012, 0x0 },
  83         { 0x00EBAFFF, 0x00020011, 0x0 },
  84         { 0x00C71FFF, 0x0006000F, 0x0 },
  85         { 0x00AAAFFF, 0x000E000A, 0x0 },
  86         { 0x00FFFFFF, 0x00020011, 0x0 },
  87         { 0x00DB6FFF, 0x0005000F, 0x0 },
  88         { 0x00BEEFFF, 0x000A000C, 0x0 },
  89         { 0x00FFFFFF, 0x0005000F, 0x0 },
  90         { 0x00DB6FFF, 0x000A000C, 0x0 },
  91 };
  92
  93 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
  94         { 0x00FFFFFF, 0x0007000E, 0x0 },
  95         { 0x00D75FFF, 0x000E000A, 0x0 },
  96         { 0x00BEFFFF, 0x00140006, 0x0 },
  97         { 0x80B2CFFF, 0x001B0002, 0x0 },
  98         { 0x00FFFFFF, 0x000E000A, 0x0 },
  99         { 0x00DB6FFF, 0x00160005, 0x0 },
 100         { 0x80C71FFF, 0x001A0002, 0x0 },
 101         { 0x00F7DFFF, 0x00180004, 0x0 },
 102         { 0x80D75FFF, 0x001B0002, 0x0 },
 103 };
 104
 105 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 106         { 0x00FFFFFF, 0x0001000E, 0x0 },
 107         { 0x00D75FFF, 0x0004000A, 0x0 },
 108         { 0x00C30FFF, 0x00070006, 0x0 },
 109         { 0x00AAAFFF, 0x000C0000, 0x0 },
 110         { 0x00FFFFFF, 0x0004000A, 0x0 },
 111         { 0x00D75FFF, 0x00090004, 0x0 },
 112         { 0x00C30FFF, 0x000C0000, 0x0 },
 113         { 0x00FFFFFF, 0x00070006, 0x0 },
 114         { 0x00D75FFF, 0x000C0000, 0x0 },
 115 };
 116
 117 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 118                                         /* Idx  NT mV d T mV df db      */
 119         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 120         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 121         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 122         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 123         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 124         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 125         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 126         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 127         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 128         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 129 };
 130
 131 /* Skylake H and S */
 132 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 133         { 0x00002016, 0x000000A0, 0x0 },
 134         { 0x00005012, 0x0000009B, 0x0 },
 135         { 0x00007011, 0x00000088, 0x0 },
 136         { 0x80009010, 0x000000C0, 0x1 },
 137         { 0x00002016, 0x0000009B, 0x0 },
 138         { 0x00005012, 0x00000088, 0x0 },
 139         { 0x80007011, 0x000000C0, 0x1 },
 140         { 0x00002016, 0x000000DF, 0x0 },
 141         { 0x80005012, 0x000000C0, 0x1 },
 142 };
 143
 144 /* Skylake U */
 145 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 146         { 0x0000201B, 0x000000A2, 0x0 },
 147         { 0x00005012, 0x00000088, 0x0 },
 148         { 0x80007011, 0x000000CD, 0x0 },
 149         { 0x80009010, 0x000000C0, 0x1 },
 150         { 0x0000201B, 0x0000009D, 0x0 },
 151         { 0x80005012, 0x000000C0, 0x1 },
 152         { 0x80007011, 0x000000C0, 0x1 },
 153         { 0x00002016, 0x00000088, 0x0 },
 154         { 0x80005012, 0x000000C0, 0x1 },
 155 };
 156
 157 /* Skylake Y */
 158 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 159         { 0x00000018, 0x000000A2, 0x0 },
 160         { 0x00005012, 0x00000088, 0x0 },
 161         { 0x80007011, 0x000000CD, 0x0 },
 162         { 0x80009010, 0x000000C0, 0x3 },
 163         { 0x00000018, 0x0000009D, 0x0 },
 164         { 0x80005012, 0x000000C0, 0x3 },
 165         { 0x80007011, 0x000000C0, 0x3 },
 166         { 0x00000018, 0x00000088, 0x0 },
 167         { 0x80005012, 0x000000C0, 0x3 },
 168 };
 169
 170 /*
 171  * Skylake H and S
 172  * eDP 1.4 low vswing translation parameters
 173  */
 174 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 175         { 0x00000018, 0x000000A8, 0x0 },
 176         { 0x00004013, 0x000000A9, 0x0 },
 177         { 0x00007011, 0x000000A2, 0x0 },
 178         { 0x00009010, 0x0000009C, 0x0 },
 179         { 0x00000018, 0x000000A9, 0x0 },
 180         { 0x00006013, 0x000000A2, 0x0 },
 181         { 0x00007011, 0x000000A6, 0x0 },
 182         { 0x00000018, 0x000000AB, 0x0 },
 183         { 0x00007013, 0x0000009F, 0x0 },
 184         { 0x00000018, 0x000000DF, 0x0 },
 185 };
 186
 187 /*
 188  * Skylake U
 189  * eDP 1.4 low vswing translation parameters
 190  */
 191 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 192         { 0x00000018, 0x000000A8, 0x0 },
 193         { 0x00004013, 0x000000A9, 0x0 },
 194         { 0x00007011, 0x000000A2, 0x0 },
 195         { 0x00009010, 0x0000009C, 0x0 },
 196         { 0x00000018, 0x000000A9, 0x0 },
 197         { 0x00006013, 0x000000A2, 0x0 },
 198         { 0x00007011, 0x000000A6, 0x0 },
 199         { 0x00002016, 0x000000AB, 0x0 },
 200         { 0x00005013, 0x0000009F, 0x0 },
 201         { 0x00000018, 0x000000DF, 0x0 },
 202 };
 203
 204 /*
 205  * Skylake Y
 206  * eDP 1.4 low vswing translation parameters
 207  */
 208 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 209         { 0x00000018, 0x000000A8, 0x0 },
 210         { 0x00004013, 0x000000AB, 0x0 },
 211         { 0x00007011, 0x000000A4, 0x0 },
 212         { 0x00009010, 0x000000DF, 0x0 },
 213         { 0x00000018, 0x000000AA, 0x0 },
 214         { 0x00006013, 0x000000A4, 0x0 },
 215         { 0x00007011, 0x0000009D, 0x0 },
 216         { 0x00000018, 0x000000A0, 0x0 },
 217         { 0x00006012, 0x000000DF, 0x0 },
 218         { 0x00000018, 0x0000008A, 0x0 },
 219 };
 220
 221 /* Skylake U, H and S */
 222 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 223         { 0x00000018, 0x000000AC, 0x0 },
 224         { 0x00005012, 0x0000009D, 0x0 },
 225         { 0x00007011, 0x00000088, 0x0 },
 226         { 0x00000018, 0x000000A1, 0x0 },
 227         { 0x00000018, 0x00000098, 0x0 },
 228         { 0x00004013, 0x00000088, 0x0 },
 229         { 0x80006012, 0x000000CD, 0x1 },
 230         { 0x00000018, 0x000000DF, 0x0 },
 231         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 232         { 0x80003015, 0x000000C0, 0x1 },
 233         { 0x80000018, 0x000000C0, 0x1 },
 234 };
 235
 236 /* Skylake Y */
 237 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 238         { 0x00000018, 0x000000A1, 0x0 },
 239         { 0x00005012, 0x000000DF, 0x0 },
 240         { 0x80007011, 0x000000CB, 0x3 },
 241         { 0x00000018, 0x000000A4, 0x0 },
 242         { 0x00000018, 0x0000009D, 0x0 },
 243         { 0x00004013, 0x00000080, 0x0 },
 244         { 0x80006013, 0x000000C0, 0x3 },
 245         { 0x00000018, 0x0000008A, 0x0 },
 246         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 247         { 0x80003015, 0x000000C0, 0x3 },
 248         { 0x80000018, 0x000000C0, 0x3 },
 249 };
 250
 251 struct bxt_ddi_buf_trans {
 252         u32 margin;     /* swing value */
 253         u32 scale;      /* scale value */
 254         u32 enable;     /* scale enable */
 255         u32 deemphasis;
 256         bool default_index; /* true if the entry represents default value */
 257 };
 258
 259 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 260                                         /* Idx  NT mV diff      db  */
 261         { 52,  0x9A, 0, 128, true  },   /* 0:   400             0   */
 262         { 78,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 263         { 104, 0x9A, 0, 64,  false },   /* 2:   400             6   */
 264         { 154, 0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 265         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 266         { 116, 0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 267         { 154, 0x9A, 0, 64,  false },   /* 6:   600             6   */
 268         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 269         { 154, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 270         { 154, 0x9A, 1, 128, false },   /* 9:   1200            0   */
 271 };
 272
 273 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 274                                         /* Idx  NT mV diff      db  */
 275         { 26, 0, 0, 128, false },       /* 0:   200             0   */
 276         { 38, 0, 0, 112, false },       /* 1:   200             1.5 */
 277         { 48, 0, 0, 96,  false },       /* 2:   200             4   */
 278         { 54, 0, 0, 69,  false },       /* 3:   200             6   */
 279         { 32, 0, 0, 128, false },       /* 4:   250             0   */
 280         { 48, 0, 0, 104, false },       /* 5:   250             1.5 */
 281         { 54, 0, 0, 85,  false },       /* 6:   250             4   */
 282         { 43, 0, 0, 128, false },       /* 7:   300             0   */
 283         { 54, 0, 0, 101, false },       /* 8:   300             1.5 */
 284         { 48, 0, 0, 128, false },       /* 9:   300             0   */
 285 };
 286
 287 /* BSpec has 2 recommended values - entries 0 and 8.
 288  * Using the entry with higher vswing.
 289  */
 290 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 291                                         /* Idx  NT mV diff      db  */
 292         { 52,  0x9A, 0, 128, false },   /* 0:   400             0   */
 293         { 52,  0x9A, 0, 85,  false },   /* 1:   400             3.5 */
 294         { 52,  0x9A, 0, 64,  false },   /* 2:   400             6   */
 295         { 42,  0x9A, 0, 43,  false },   /* 3:   400             9.5 */
 296         { 77,  0x9A, 0, 128, false },   /* 4:   600             0   */
 297         { 77,  0x9A, 0, 85,  false },   /* 5:   600             3.5 */
 298         { 77,  0x9A, 0, 64,  false },   /* 6:   600             6   */
 299         { 102, 0x9A, 0, 128, false },   /* 7:   800             0   */
 300         { 102, 0x9A, 0, 85,  false },   /* 8:   800             3.5 */
 301         { 154, 0x9A, 1, 128, true },    /* 9:   1200            0   */
 302 };
 303
 304 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
 305                                     u32 level, enum port port, int type);
 306
 307 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
 308                                  struct intel_digital_port **dig_port,
 309                                  enum port *port)
 310 {
 311         struct drm_encoder *encoder = &intel_encoder->base;
 312
 313         switch (intel_encoder->type) {
 314         case INTEL_OUTPUT_DP_MST:
 315                 *dig_port = enc_to_mst(encoder)->primary;
 316                 *port = (*dig_port)->port;
 317                 break;
 318         default:
 319                 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
 320                 /* fallthrough and treat as unknown */
 321         case INTEL_OUTPUT_DISPLAYPORT:
 322         case INTEL_OUTPUT_EDP:
 323         case INTEL_OUTPUT_HDMI:
 324         case INTEL_OUTPUT_UNKNOWN:
 325                 *dig_port = enc_to_dig_port(encoder);
 326                 *port = (*dig_port)->port;
 327                 break;
 328         case INTEL_OUTPUT_ANALOG:
 329                 *dig_port = NULL;
 330                 *port = PORT_E;
 331                 break;
 332         }
 333 }
 334
 335 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 336 {
 337         struct intel_digital_port *dig_port;
 338         enum port port;
 339
 340         ddi_get_encoder_port(intel_encoder, &dig_port, &port);
 341
 342         return port;
 343 }
 344
 345 static const struct ddi_buf_trans *
 346 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 347 {
 348         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 349                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 350                 return skl_y_ddi_translations_dp;
 351         } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 352                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 353                 return skl_u_ddi_translations_dp;
 354         } else {
 355                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 356                 return skl_ddi_translations_dp;
 357         }
 358 }
 359
 360 static const struct ddi_buf_trans *
 361 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 362 {
 363         if (dev_priv->vbt.edp.low_vswing) {
 364                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 365                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 366                         return skl_y_ddi_translations_edp;
 367                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
 368                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 369                         return skl_u_ddi_translations_edp;
 370                 } else {
 371                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 372                         return skl_ddi_translations_edp;
 373                 }
 374         }
 375
 376         return skl_get_buf_trans_dp(dev_priv, n_entries);
 377 }
 378
 379 static const struct ddi_buf_trans *
 380 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 381 {
 382         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
 383                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 384                 return skl_y_ddi_translations_hdmi;
 385         } else {
 386                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 387                 return skl_ddi_translations_hdmi;
 388         }
 389 }
 390
 391 /*
 392  * Starting with Haswell, DDI port buffers must be programmed with correct
 393  * values in advance. The buffer values are different for FDI and DP modes,
 394  * but the HDMI/DVI fields are shared among those. So we program the DDI
 395  * in either FDI or DP modes only, as HDMI connections will work with both
 396  * of those
 397  */
 398 void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
 399 {
 400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 401         u32 iboost_bit = 0;
 402         int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
 403             size;
 404         int hdmi_level;
 405         enum port port;
 406         const struct ddi_buf_trans *ddi_translations_fdi;
 407         const struct ddi_buf_trans *ddi_translations_dp;
 408         const struct ddi_buf_trans *ddi_translations_edp;
 409         const struct ddi_buf_trans *ddi_translations_hdmi;
 410         const struct ddi_buf_trans *ddi_translations;
 411
 412         port = intel_ddi_get_encoder_port(encoder);
 413         hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 414
 415         if (IS_BROXTON(dev_priv)) {
 416                 if (encoder->type != INTEL_OUTPUT_HDMI)
 417                         return;
 418
 419                 /* Vswing programming for HDMI */
 420                 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
 421                                         INTEL_OUTPUT_HDMI);
 422                 return;
 423         }
 424
 425         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
 426                 ddi_translations_fdi = NULL;
 427                 ddi_translations_dp =
 428                                 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
 429                 ddi_translations_edp =
 430                                 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
 431                 ddi_translations_hdmi =
 432                                 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
 433                 hdmi_default_entry = 8;
 434                 /* If we're boosting the current, set bit 31 of trans1 */
 435                 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
 436                     dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 437                         iboost_bit = 1<<31;
 438
 439                 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
 440                             port != PORT_A && port != PORT_E &&
 441                             n_edp_entries > 9))
 442                         n_edp_entries = 9;
 443         } else if (IS_BROADWELL(dev_priv)) {
 444                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 445                 ddi_translations_dp = bdw_ddi_translations_dp;
 446
 447                 if (dev_priv->vbt.edp.low_vswing) {
 448                         ddi_translations_edp = bdw_ddi_translations_edp;
 449                         n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 450                 } else {
 451                         ddi_translations_edp = bdw_ddi_translations_dp;
 452                         n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 453                 }
 454
 455                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 456
 457                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 458                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 459                 hdmi_default_entry = 7;
 460         } else if (IS_HASWELL(dev_priv)) {
 461                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 462                 ddi_translations_dp = hsw_ddi_translations_dp;
 463                 ddi_translations_edp = hsw_ddi_translations_dp;
 464                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 465                 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 466                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 467                 hdmi_default_entry = 6;
 468         } else {
 469                 WARN(1, "ddi translation table missing\n");
 470                 ddi_translations_edp = bdw_ddi_translations_dp;
 471                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 472                 ddi_translations_dp = bdw_ddi_translations_dp;
 473                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 474                 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 475                 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 476                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 477                 hdmi_default_entry = 7;
 478         }
 479
 480         switch (encoder->type) {
 481         case INTEL_OUTPUT_EDP:
 482                 ddi_translations = ddi_translations_edp;
 483                 size = n_edp_entries;
 484                 break;
 485         case INTEL_OUTPUT_DISPLAYPORT:
 486         case INTEL_OUTPUT_HDMI:
 487                 ddi_translations = ddi_translations_dp;
 488                 size = n_dp_entries;
 489                 break;
 490         case INTEL_OUTPUT_ANALOG:
 491                 ddi_translations = ddi_translations_fdi;
 492                 size = n_dp_entries;
 493                 break;
 494         default:
 495                 BUG();
 496         }
 497
 498         for (i = 0; i < size; i++) {
 499                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 500                            ddi_translations[i].trans1 | iboost_bit);
 501                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 502                            ddi_translations[i].trans2);
 503         }
 504
 505         if (encoder->type != INTEL_OUTPUT_HDMI)
 506                 return;
 507
 508         /* Choose a good default if VBT is badly populated */
 509         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 510             hdmi_level >= n_hdmi_entries)
 511                 hdmi_level = hdmi_default_entry;
 512
 513         /* Entry 9 is for HDMI: */
 514         I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 515                    ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
 516         I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 517                    ddi_translations_hdmi[hdmi_level].trans2);
 518 }
 519
 520 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 521                                     enum port port)
 522 {
 523         i915_reg_t reg = DDI_BUF_CTL(port);
 524         int i;
 525
 526         for (i = 0; i < 16; i++) {
 527                 udelay(1);
 528                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 529                         return;
 530         }
 531         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 532 }
 533
 534 /* Starting with Haswell, different DDI ports can work in FDI mode for
 535  * connection to the PCH-located connectors. For this, it is necessary to train
 536  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 537  *
 538  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 539  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 540  * DDI A (which is used for eDP)
 541  */
 542
 543 void hsw_fdi_link_train(struct drm_crtc *crtc)
 544 {
 545         struct drm_device *dev = crtc->dev;
 546         struct drm_i915_private *dev_priv = dev->dev_private;
 547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 548         struct intel_encoder *encoder;
 549         u32 temp, i, rx_ctl_val;
 550
 551         for_each_encoder_on_crtc(dev, crtc, encoder) {
 552                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
 553                 intel_prepare_ddi_buffer(encoder);
 554         }
 555
 556         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 557          * mode set "sequence for CRT port" document:
 558          * - TP1 to TP2 time with the default value
 559          * - FDI delay to 90h
 560          *
 561          * WaFDIAutoLinkSetTimingOverrride:hsw
 562          */
 563         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
 564                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 565                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 566
 567         /* Enable the PCH Receiver FDI PLL */
 568         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 569                      FDI_RX_PLL_ENABLE |
 570                      FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
 571         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 572         POSTING_READ(FDI_RX_CTL(PIPE_A));
 573         udelay(220);
 574
 575         /* Switch from Rawclk to PCDclk */
 576         rx_ctl_val |= FDI_PCDCLK;
 577         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 578
 579         /* Configure Port Clock Select */
 580         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
 581         WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 582
 583         /* Start the training iterating through available voltages and emphasis,
 584          * testing each value twice. */
 585         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
 586                 /* Configure DP_TP_CTL with auto-training */
 587                 I915_WRITE(DP_TP_CTL(PORT_E),
 588                                         DP_TP_CTL_FDI_AUTOTRAIN |
 589                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 590                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 591                                         DP_TP_CTL_ENABLE);
 592
 593                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 594                  * DDI E does not support port reversal, the functionality is
 595                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 596                  * port reversal bit */
 597                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 598                            DDI_BUF_CTL_ENABLE |
 599                            ((intel_crtc->config->fdi_lanes - 1) << 1) |
 600                            DDI_BUF_TRANS_SELECT(i / 2));
 601                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 602
 603                 udelay(600);
 604
 605                 /* Program PCH FDI Receiver TU */
 606                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
 607
 608                 /* Enable PCH FDI Receiver with auto-training */
 609                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 610                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 611                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 612
 613                 /* Wait for FDI receiver lane calibration */
 614                 udelay(30);
 615
 616                 /* Unset FDI_RX_MISC pwrdn lanes */
 617                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 618                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 619                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 620                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 621
 622                 /* Wait for FDI auto training time */
 623                 udelay(5);
 624
 625                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 626                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 627                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 628                         break;
 629                 }
 630
 631                 /*
 632                  * Leave things enabled even if we failed to train FDI.
 633                  * Results in less fireworks from the state checker.
 634                  */
 635                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
 636                         DRM_ERROR("FDI link training failed!\n");
 637                         break;
 638                 }
 639
 640                 rx_ctl_val &= ~FDI_RX_ENABLE;
 641                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
 642                 POSTING_READ(FDI_RX_CTL(PIPE_A));
 643
 644                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 645                 temp &= ~DDI_BUF_CTL_ENABLE;
 646                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 647                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 648
 649                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 650                 temp = I915_READ(DP_TP_CTL(PORT_E));
 651                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 652                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 653                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 654                 POSTING_READ(DP_TP_CTL(PORT_E));
 655
 656                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 657
 658                 /* Reset FDI_RX_MISC pwrdn lanes */
 659                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
 660                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 661                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 662                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
 663                 POSTING_READ(FDI_RX_MISC(PIPE_A));
 664         }
 665
 666         /* Enable normal pixel sending for FDI */
 667         I915_WRITE(DP_TP_CTL(PORT_E),
 668                    DP_TP_CTL_FDI_AUTOTRAIN |
 669                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 670                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 671                    DP_TP_CTL_ENABLE);
 672 }
 673
 674 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 675 {
 676         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 677         struct intel_digital_port *intel_dig_port =
 678                 enc_to_dig_port(&encoder->base);
 679
 680         intel_dp->DP = intel_dig_port->saved_port_bits |
 681                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 682         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 683 }
 684
 685 static struct intel_encoder *
 686 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 687 {
 688         struct drm_device *dev = crtc->dev;
 689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 690         struct intel_encoder *intel_encoder, *ret = NULL;
 691         int num_encoders = 0;
 692
 693         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 694                 ret = intel_encoder;
 695                 num_encoders++;
 696         }
 697
 698         if (num_encoders != 1)
 699                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 700                      pipe_name(intel_crtc->pipe));
 701
 702         BUG_ON(ret == NULL);
 703         return ret;
 704 }
 705
 706 struct intel_encoder *
 707 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
 708 {
 709         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 710         struct intel_encoder *ret = NULL;
 711         struct drm_atomic_state *state;
 712         struct drm_connector *connector;
 713         struct drm_connector_state *connector_state;
 714         int num_encoders = 0;
 715         int i;
 716
 717         state = crtc_state->base.state;
 718
 719         for_each_connector_in_state(state, connector, connector_state, i) {
 720                 if (connector_state->crtc != crtc_state->base.crtc)
 721                         continue;
 722
 723                 ret = to_intel_encoder(connector_state->best_encoder);
 724                 num_encoders++;
 725         }
 726
 727         WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
 728              pipe_name(crtc->pipe));
 729
 730         BUG_ON(ret == NULL);
 731         return ret;
 732 }
 733
 734 #define LC_FREQ 2700
 735
 736 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 737                                    i915_reg_t reg)
 738 {
 739         int refclk = LC_FREQ;
 740         int n, p, r;
 741         u32 wrpll;
 742
 743         wrpll = I915_READ(reg);
 744         switch (wrpll & WRPLL_PLL_REF_MASK) {
 745         case WRPLL_PLL_SSC:
 746         case WRPLL_PLL_NON_SSC:
 747                 /*
 748                  * We could calculate spread here, but our checking
 749                  * code only cares about 5% accuracy, and spread is a max of
 750                  * 0.5% downspread.
 751                  */
 752                 refclk = 135;
 753                 break;
 754         case WRPLL_PLL_LCPLL:
 755                 refclk = LC_FREQ;
 756                 break;
 757         default:
 758                 WARN(1, "bad wrpll refclk\n");
 759                 return 0;
 760         }
 761
 762         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 763         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 764         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 765
 766         /* Convert to KHz, p & r have a fixed point portion */
 767         return (refclk * n * 100) / (p * r);
 768 }
 769
 770 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 771                                uint32_t dpll)
 772 {
 773         i915_reg_t cfgcr1_reg, cfgcr2_reg;
 774         uint32_t cfgcr1_val, cfgcr2_val;
 775         uint32_t p0, p1, p2, dco_freq;
 776
 777         cfgcr1_reg = DPLL_CFGCR1(dpll);
 778         cfgcr2_reg = DPLL_CFGCR2(dpll);
 779
 780         cfgcr1_val = I915_READ(cfgcr1_reg);
 781         cfgcr2_val = I915_READ(cfgcr2_reg);
 782
 783         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
 784         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
 785
 786         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
 787                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
 788         else
 789                 p1 = 1;
 790
 791
 792         switch (p0) {
 793         case DPLL_CFGCR2_PDIV_1:
 794                 p0 = 1;
 795                 break;
 796         case DPLL_CFGCR2_PDIV_2:
 797                 p0 = 2;
 798                 break;
 799         case DPLL_CFGCR2_PDIV_3:
 800                 p0 = 3;
 801                 break;
 802         case DPLL_CFGCR2_PDIV_7:
 803                 p0 = 7;
 804                 break;
 805         }
 806
 807         switch (p2) {
 808         case DPLL_CFGCR2_KDIV_5:
 809                 p2 = 5;
 810                 break;
 811         case DPLL_CFGCR2_KDIV_2:
 812                 p2 = 2;
 813                 break;
 814         case DPLL_CFGCR2_KDIV_3:
 815                 p2 = 3;
 816                 break;
 817         case DPLL_CFGCR2_KDIV_1:
 818                 p2 = 1;
 819                 break;
 820         }
 821
 822         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
 823
 824         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
 825                 1000) / 0x8000;
 826
 827         return dco_freq / (p0 * p1 * p2 * 5);
 828 }
 829
 830 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 831 {
 832         int dotclock;
 833
 834         if (pipe_config->has_pch_encoder)
 835                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 836                                                     &pipe_config->fdi_m_n);
 837         else if (pipe_config->has_dp_encoder)
 838                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 839                                                     &pipe_config->dp_m_n);
 840         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
 841                 dotclock = pipe_config->port_clock * 2 / 3;
 842         else
 843                 dotclock = pipe_config->port_clock;
 844
 845         if (pipe_config->pixel_multiplier)
 846                 dotclock /= pipe_config->pixel_multiplier;
 847
 848         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 849 }
 850
 851 static void skl_ddi_clock_get(struct intel_encoder *encoder,
 852                                 struct intel_crtc_state *pipe_config)
 853 {
 854         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 855         int link_clock = 0;
 856         uint32_t dpll_ctl1, dpll;
 857
 858         dpll = pipe_config->ddi_pll_sel;
 859
 860         dpll_ctl1 = I915_READ(DPLL_CTRL1);
 861
 862         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
 863                 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
 864         } else {
 865                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
 866                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
 867
 868                 switch (link_clock) {
 869                 case DPLL_CTRL1_LINK_RATE_810:
 870                         link_clock = 81000;
 871                         break;
 872                 case DPLL_CTRL1_LINK_RATE_1080:
 873                         link_clock = 108000;
 874                         break;
 875                 case DPLL_CTRL1_LINK_RATE_1350:
 876                         link_clock = 135000;
 877                         break;
 878                 case DPLL_CTRL1_LINK_RATE_1620:
 879                         link_clock = 162000;
 880                         break;
 881                 case DPLL_CTRL1_LINK_RATE_2160:
 882                         link_clock = 216000;
 883                         break;
 884                 case DPLL_CTRL1_LINK_RATE_2700:
 885                         link_clock = 270000;
 886                         break;
 887                 default:
 888                         WARN(1, "Unsupported link rate\n");
 889                         break;
 890                 }
 891                 link_clock *= 2;
 892         }
 893
 894         pipe_config->port_clock = link_clock;
 895
 896         ddi_dotclock_get(pipe_config);
 897 }
 898
 899 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 900                               struct intel_crtc_state *pipe_config)
 901 {
 902         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 903         int link_clock = 0;
 904         u32 val, pll;
 905
 906         val = pipe_config->ddi_pll_sel;
 907         switch (val & PORT_CLK_SEL_MASK) {
 908         case PORT_CLK_SEL_LCPLL_810:
 909                 link_clock = 81000;
 910                 break;
 911         case PORT_CLK_SEL_LCPLL_1350:
 912                 link_clock = 135000;
 913                 break;
 914         case PORT_CLK_SEL_LCPLL_2700:
 915                 link_clock = 270000;
 916                 break;
 917         case PORT_CLK_SEL_WRPLL1:
 918                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
 919                 break;
 920         case PORT_CLK_SEL_WRPLL2:
 921                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
 922                 break;
 923         case PORT_CLK_SEL_SPLL:
 924                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 925                 if (pll == SPLL_PLL_FREQ_810MHz)
 926                         link_clock = 81000;
 927                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 928                         link_clock = 135000;
 929                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 930                         link_clock = 270000;
 931                 else {
 932                         WARN(1, "bad spll freq\n");
 933                         return;
 934                 }
 935                 break;
 936         default:
 937                 WARN(1, "bad port clock sel\n");
 938                 return;
 939         }
 940
 941         pipe_config->port_clock = link_clock * 2;
 942
 943         ddi_dotclock_get(pipe_config);
 944 }
 945
 946 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
 947                                 enum intel_dpll_id dpll)
 948 {
 949         struct intel_shared_dpll *pll;
 950         struct intel_dpll_hw_state *state;
 951         intel_clock_t clock;
 952
 953         /* For DDI ports we always use a shared PLL. */
 954         if (WARN_ON(dpll == DPLL_ID_PRIVATE))
 955                 return 0;
 956
 957         pll = &dev_priv->shared_dplls[dpll];
 958         state = &pll->config.hw_state;
 959
 960         clock.m1 = 2;
 961         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
 962         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
 963                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
 964         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
 965         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
 966         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
 967
 968         return chv_calc_dpll_params(100000, &clock);
 969 }
 970
 971 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
 972                                 struct intel_crtc_state *pipe_config)
 973 {
 974         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 975         enum port port = intel_ddi_get_encoder_port(encoder);
 976         uint32_t dpll = port;
 977
 978         pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
 979
 980         ddi_dotclock_get(pipe_config);
 981 }
 982
 983 void intel_ddi_clock_get(struct intel_encoder *encoder,
 984                          struct intel_crtc_state *pipe_config)
 985 {
 986         struct drm_device *dev = encoder->base.dev;
 987
 988         if (INTEL_INFO(dev)->gen <= 8)
 989                 hsw_ddi_clock_get(encoder, pipe_config);
 990         else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
 991                 skl_ddi_clock_get(encoder, pipe_config);
 992         else if (IS_BROXTON(dev))
 993                 bxt_ddi_clock_get(encoder, pipe_config);
 994 }
 995
 996 static bool
 997 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 998                    struct intel_crtc_state *crtc_state,
 999                    struct intel_encoder *intel_encoder)
1000 {
1001         struct intel_shared_dpll *pll;
1002
1003         pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1004                                     intel_encoder);
1005         if (!pll)
1006                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1007                                  pipe_name(intel_crtc->pipe));
1008
1009         return pll;
1010 }
1011
1012 static bool
1013 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1014                    struct intel_crtc_state *crtc_state,
1015                    struct intel_encoder *intel_encoder)
1016 {
1017         struct intel_shared_dpll *pll;
1018
1019         pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1020         if (pll == NULL) {
1021                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1022                                  pipe_name(intel_crtc->pipe));
1023                 return false;
1024         }
1025
1026         return true;
1027 }
1028
1029 static bool
1030 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1031                    struct intel_crtc_state *crtc_state,
1032                    struct intel_encoder *intel_encoder)
1033 {
1034         return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
1035 }
1036
1037 /*
1038  * Tries to find a *shared* PLL for the CRTC and store it in
1039  * intel_crtc->ddi_pll_sel.
1040  *
1041  * For private DPLLs, compute_config() should do the selection for us. This
1042  * function should be folded into compute_config() eventually.
1043  */
1044 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1045                           struct intel_crtc_state *crtc_state)
1046 {
1047         struct drm_device *dev = intel_crtc->base.dev;
1048         struct intel_encoder *intel_encoder =
1049                 intel_ddi_get_crtc_new_encoder(crtc_state);
1050
1051         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1052                 return skl_ddi_pll_select(intel_crtc, crtc_state,
1053                                           intel_encoder);
1054         else if (IS_BROXTON(dev))
1055                 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1056                                           intel_encoder);
1057         else
1058                 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1059                                           intel_encoder);
1060 }
1061
1062 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1063 {
1064         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1066         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1067         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1068         int type = intel_encoder->type;
1069         uint32_t temp;
1070
1071         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1072                 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1073
1074                 temp = TRANS_MSA_SYNC_CLK;
1075                 switch (intel_crtc->config->pipe_bpp) {
1076                 case 18:
1077                         temp |= TRANS_MSA_6_BPC;
1078                         break;
1079                 case 24:
1080                         temp |= TRANS_MSA_8_BPC;
1081                         break;
1082                 case 30:
1083                         temp |= TRANS_MSA_10_BPC;
1084                         break;
1085                 case 36:
1086                         temp |= TRANS_MSA_12_BPC;
1087                         break;
1088                 default:
1089                         BUG();
1090                 }
1091                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1092         }
1093 }
1094
1095 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1096 {
1097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1098         struct drm_device *dev = crtc->dev;
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1101         uint32_t temp;
1102         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1103         if (state == true)
1104                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1105         else
1106                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1107         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1108 }
1109
1110 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1111 {
1112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1113         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1114         struct drm_encoder *encoder = &intel_encoder->base;
1115         struct drm_device *dev = crtc->dev;
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         enum pipe pipe = intel_crtc->pipe;
1118         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1119         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1120         int type = intel_encoder->type;
1121         uint32_t temp;
1122
1123         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1124         temp = TRANS_DDI_FUNC_ENABLE;
1125         temp |= TRANS_DDI_SELECT_PORT(port);
1126
1127         switch (intel_crtc->config->pipe_bpp) {
1128         case 18:
1129                 temp |= TRANS_DDI_BPC_6;
1130                 break;
1131         case 24:
1132                 temp |= TRANS_DDI_BPC_8;
1133                 break;
1134         case 30:
1135                 temp |= TRANS_DDI_BPC_10;
1136                 break;
1137         case 36:
1138                 temp |= TRANS_DDI_BPC_12;
1139                 break;
1140         default:
1141                 BUG();
1142         }
1143
1144         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1145                 temp |= TRANS_DDI_PVSYNC;
1146         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1147                 temp |= TRANS_DDI_PHSYNC;
1148
1149         if (cpu_transcoder == TRANSCODER_EDP) {
1150                 switch (pipe) {
1151                 case PIPE_A:
1152                         /* On Haswell, can only use the always-on power well for
1153                          * eDP when not using the panel fitter, and when not
1154                          * using motion blur mitigation (which we don't
1155                          * support). */
1156                         if (IS_HASWELL(dev) &&
1157                             (intel_crtc->config->pch_pfit.enabled ||
1158                              intel_crtc->config->pch_pfit.force_thru))
1159                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1160                         else
1161                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1162                         break;
1163                 case PIPE_B:
1164                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1165                         break;
1166                 case PIPE_C:
1167                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1168                         break;
1169                 default:
1170                         BUG();
1171                         break;
1172                 }
1173         }
1174
1175         if (type == INTEL_OUTPUT_HDMI) {
1176                 if (intel_crtc->config->has_hdmi_sink)
1177                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1178                 else
1179                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1180
1181         } else if (type == INTEL_OUTPUT_ANALOG) {
1182                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1183                 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1184
1185         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1186                    type == INTEL_OUTPUT_EDP) {
1187                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1188
1189                 if (intel_dp->is_mst) {
1190                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1191                 } else
1192                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1193
1194                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1195         } else if (type == INTEL_OUTPUT_DP_MST) {
1196                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1197
1198                 if (intel_dp->is_mst) {
1199                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1200                 } else
1201                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1202
1203                 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1204         } else {
1205                 WARN(1, "Invalid encoder type %d for pipe %c\n",
1206                      intel_encoder->type, pipe_name(pipe));
1207         }
1208
1209         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1210 }
1211
1212 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1213                                        enum transcoder cpu_transcoder)
1214 {
1215         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1216         uint32_t val = I915_READ(reg);
1217
1218         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1219         val |= TRANS_DDI_PORT_NONE;
1220         I915_WRITE(reg, val);
1221 }
1222
1223 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1224 {
1225         struct drm_device *dev = intel_connector->base.dev;
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         struct intel_encoder *intel_encoder = intel_connector->encoder;
1228         int type = intel_connector->base.connector_type;
1229         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1230         enum pipe pipe = 0;
1231         enum transcoder cpu_transcoder;
1232         enum intel_display_power_domain power_domain;
1233         uint32_t tmp;
1234         bool ret;
1235
1236         power_domain = intel_display_port_power_domain(intel_encoder);
1237         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1238                 return false;
1239
1240         if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1241                 ret = false;
1242                 goto out;
1243         }
1244
1245         if (port == PORT_A)
1246                 cpu_transcoder = TRANSCODER_EDP;
1247         else
1248                 cpu_transcoder = (enum transcoder) pipe;
1249
1250         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1251
1252         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1253         case TRANS_DDI_MODE_SELECT_HDMI:
1254         case TRANS_DDI_MODE_SELECT_DVI:
1255                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1256                 break;
1257
1258         case TRANS_DDI_MODE_SELECT_DP_SST:
1259                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1260                       type == DRM_MODE_CONNECTOR_DisplayPort;
1261                 break;
1262
1263         case TRANS_DDI_MODE_SELECT_DP_MST:
1264                 /* if the transcoder is in MST state then
1265                  * connector isn't connected */
1266                 ret = false;
1267                 break;
1268
1269         case TRANS_DDI_MODE_SELECT_FDI:
1270                 ret = type == DRM_MODE_CONNECTOR_VGA;
1271                 break;
1272
1273         default:
1274                 ret = false;
1275                 break;
1276         }
1277
1278 out:
1279         intel_display_power_put(dev_priv, power_domain);
1280
1281         return ret;
1282 }
1283
1284 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1285                             enum pipe *pipe)
1286 {
1287         struct drm_device *dev = encoder->base.dev;
1288         struct drm_i915_private *dev_priv = dev->dev_private;
1289         enum port port = intel_ddi_get_encoder_port(encoder);
1290         enum intel_display_power_domain power_domain;
1291         u32 tmp;
1292         int i;
1293         bool ret;
1294
1295         power_domain = intel_display_port_power_domain(encoder);
1296         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1297                 return false;
1298
1299         ret = false;
1300
1301         tmp = I915_READ(DDI_BUF_CTL(port));
1302
1303         if (!(tmp & DDI_BUF_CTL_ENABLE))
1304                 goto out;
1305
1306         if (port == PORT_A) {
1307                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1308
1309                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1310                 case TRANS_DDI_EDP_INPUT_A_ON:
1311                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1312                         *pipe = PIPE_A;
1313                         break;
1314                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1315                         *pipe = PIPE_B;
1316                         break;
1317                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1318                         *pipe = PIPE_C;
1319                         break;
1320                 }
1321
1322                 ret = true;
1323
1324                 goto out;
1325         }
1326
1327         for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1328                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1329
1330                 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1331                         if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1332                             TRANS_DDI_MODE_SELECT_DP_MST)
1333                                 goto out;
1334
1335                         *pipe = i;
1336                         ret = true;
1337
1338                         goto out;
1339                 }
1340         }
1341
1342         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1343
1344 out:
1345         intel_display_power_put(dev_priv, power_domain);
1346
1347         return ret;
1348 }
1349
1350 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1351 {
1352         struct drm_crtc *crtc = &intel_crtc->base;
1353         struct drm_device *dev = crtc->dev;
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1356         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1357         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1358
1359         if (cpu_transcoder != TRANSCODER_EDP)
1360                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1361                            TRANS_CLK_SEL_PORT(port));
1362 }
1363
1364 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1365 {
1366         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1367         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1368
1369         if (cpu_transcoder != TRANSCODER_EDP)
1370                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1371                            TRANS_CLK_SEL_DISABLED);
1372 }
1373
1374 static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1375                                u32 level, enum port port, int type)
1376 {
1377         const struct ddi_buf_trans *ddi_translations;
1378         uint8_t iboost;
1379         uint8_t dp_iboost, hdmi_iboost;
1380         int n_entries;
1381         u32 reg;
1382
1383         /* VBT may override standard boost values */
1384         dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1385         hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1386
1387         if (type == INTEL_OUTPUT_DISPLAYPORT) {
1388                 if (dp_iboost) {
1389                         iboost = dp_iboost;
1390                 } else {
1391                         ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
1392                         iboost = ddi_translations[level].i_boost;
1393                 }
1394         } else if (type == INTEL_OUTPUT_EDP) {
1395                 if (dp_iboost) {
1396                         iboost = dp_iboost;
1397                 } else {
1398                         ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1399
1400                         if (WARN_ON(port != PORT_A &&
1401                                     port != PORT_E && n_entries > 9))
1402                                 n_entries = 9;
1403
1404                         iboost = ddi_translations[level].i_boost;
1405                 }
1406         } else if (type == INTEL_OUTPUT_HDMI) {
1407                 if (hdmi_iboost) {
1408                         iboost = hdmi_iboost;
1409                 } else {
1410                         ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1411                         iboost = ddi_translations[level].i_boost;
1412                 }
1413         } else {
1414                 return;
1415         }
1416
1417         /* Make sure that the requested I_boost is valid */
1418         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1419                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1420                 return;
1421         }
1422
1423         reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
1424         reg &= ~BALANCE_LEG_MASK(port);
1425         reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
1426
1427         if (iboost)
1428                 reg |= iboost << BALANCE_LEG_SHIFT(port);
1429         else
1430                 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
1431
1432         I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
1433 }
1434
1435 static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1436                                     u32 level, enum port port, int type)
1437 {
1438         const struct bxt_ddi_buf_trans *ddi_translations;
1439         u32 n_entries, i;
1440         uint32_t val;
1441
1442         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1443                 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1444                 ddi_translations = bxt_ddi_translations_edp;
1445         } else if (type == INTEL_OUTPUT_DISPLAYPORT
1446                         || type == INTEL_OUTPUT_EDP) {
1447                 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1448                 ddi_translations = bxt_ddi_translations_dp;
1449         } else if (type == INTEL_OUTPUT_HDMI) {
1450                 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1451                 ddi_translations = bxt_ddi_translations_hdmi;
1452         } else {
1453                 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1454                                 type);
1455                 return;
1456         }
1457
1458         /* Check if default value has to be used */
1459         if (level >= n_entries ||
1460             (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1461                 for (i = 0; i < n_entries; i++) {
1462                         if (ddi_translations[i].default_index) {
1463                                 level = i;
1464                                 break;
1465                         }
1466                 }
1467         }
1468
1469         /*
1470          * While we write to the group register to program all lanes at once we
1471          * can read only lane registers and we pick lanes 0/1 for that.
1472          */
1473         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1474         val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1475         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1476
1477         val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1478         val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1479         val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1480                ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1481         I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1482
1483         val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1484         val &= ~SCALE_DCOMP_METHOD;
1485         if (ddi_translations[level].enable)
1486                 val |= SCALE_DCOMP_METHOD;
1487
1488         if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1489                 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1490
1491         I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1492
1493         val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1494         val &= ~DE_EMPHASIS;
1495         val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1496         I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1497
1498         val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1499         val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1500         I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1501 }
1502
1503 static uint32_t translate_signal_level(int signal_levels)
1504 {
1505         uint32_t level;
1506
1507         switch (signal_levels) {
1508         default:
1509                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1510                               signal_levels);
1511         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1512                 level = 0;
1513                 break;
1514         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1515                 level = 1;
1516                 break;
1517         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1518                 level = 2;
1519                 break;
1520         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1521                 level = 3;
1522                 break;
1523
1524         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1525                 level = 4;
1526                 break;
1527         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1528                 level = 5;
1529                 break;
1530         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1531                 level = 6;
1532                 break;
1533
1534         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1535                 level = 7;
1536                 break;
1537         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1538                 level = 8;
1539                 break;
1540
1541         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1542                 level = 9;
1543                 break;
1544         }
1545
1546         return level;
1547 }
1548
1549 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1550 {
1551         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1552         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1553         struct intel_encoder *encoder = &dport->base;
1554         uint8_t train_set = intel_dp->train_set[0];
1555         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1556                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1557         enum port port = dport->port;
1558         uint32_t level;
1559
1560         level = translate_signal_level(signal_levels);
1561
1562         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1563                 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
1564         else if (IS_BROXTON(dev_priv))
1565                 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1566
1567         return DDI_BUF_TRANS_SELECT(level);
1568 }
1569
1570 void intel_ddi_clk_select(struct intel_encoder *encoder,
1571                           const struct intel_crtc_state *pipe_config)
1572 {
1573         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1574         enum port port = intel_ddi_get_encoder_port(encoder);
1575
1576         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1577                 uint32_t dpll = pipe_config->ddi_pll_sel;
1578                 uint32_t val;
1579
1580                 /* DDI -> PLL mapping  */
1581                 val = I915_READ(DPLL_CTRL2);
1582
1583                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1584                         DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1585                 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1586                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1587
1588                 I915_WRITE(DPLL_CTRL2, val);
1589
1590         } else if (INTEL_INFO(dev_priv)->gen < 9) {
1591                 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1592                 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
1593         }
1594 }
1595
1596 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1597 {
1598         struct drm_encoder *encoder = &intel_encoder->base;
1599         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1600         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1601         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1602         int type = intel_encoder->type;
1603
1604         intel_prepare_ddi_buffer(intel_encoder);
1605
1606         if (type == INTEL_OUTPUT_EDP) {
1607                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1608                 intel_edp_panel_on(intel_dp);
1609         }
1610
1611         intel_ddi_clk_select(intel_encoder, crtc->config);
1612
1613         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1614                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1615
1616                 intel_dp_set_link_params(intel_dp, crtc->config);
1617
1618                 intel_ddi_init_dp_buf_reg(intel_encoder);
1619
1620                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1621                 intel_dp_start_link_train(intel_dp);
1622                 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
1623                         intel_dp_stop_link_train(intel_dp);
1624         } else if (type == INTEL_OUTPUT_HDMI) {
1625                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1626
1627                 intel_hdmi->set_infoframes(encoder,
1628                                            crtc->config->has_hdmi_sink,
1629                                            &crtc->config->base.adjusted_mode);
1630         }
1631 }
1632
1633 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1634 {
1635         struct drm_encoder *encoder = &intel_encoder->base;
1636         struct drm_device *dev = encoder->dev;
1637         struct drm_i915_private *dev_priv = dev->dev_private;
1638         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1639         int type = intel_encoder->type;
1640         uint32_t val;
1641         bool wait = false;
1642
1643         val = I915_READ(DDI_BUF_CTL(port));
1644         if (val & DDI_BUF_CTL_ENABLE) {
1645                 val &= ~DDI_BUF_CTL_ENABLE;
1646                 I915_WRITE(DDI_BUF_CTL(port), val);
1647                 wait = true;
1648         }
1649
1650         val = I915_READ(DP_TP_CTL(port));
1651         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1652         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1653         I915_WRITE(DP_TP_CTL(port), val);
1654
1655         if (wait)
1656                 intel_wait_ddi_buf_idle(dev_priv, port);
1657
1658         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1659                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1660                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1661                 intel_edp_panel_vdd_on(intel_dp);
1662                 intel_edp_panel_off(intel_dp);
1663         }
1664
1665         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1666                 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1667                                         DPLL_CTRL2_DDI_CLK_OFF(port)));
1668         else if (INTEL_INFO(dev)->gen < 9)
1669                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1670 }
1671
1672 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1673 {
1674         struct drm_encoder *encoder = &intel_encoder->base;
1675         struct drm_crtc *crtc = encoder->crtc;
1676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1677         struct drm_device *dev = encoder->dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1680         int type = intel_encoder->type;
1681
1682         if (type == INTEL_OUTPUT_HDMI) {
1683                 struct intel_digital_port *intel_dig_port =
1684                         enc_to_dig_port(encoder);
1685
1686                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1687                  * are ignored so nothing special needs to be done besides
1688                  * enabling the port.
1689                  */
1690                 I915_WRITE(DDI_BUF_CTL(port),
1691                            intel_dig_port->saved_port_bits |
1692                            DDI_BUF_CTL_ENABLE);
1693         } else if (type == INTEL_OUTPUT_EDP) {
1694                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1695
1696                 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
1697                         intel_dp_stop_link_train(intel_dp);
1698
1699                 intel_edp_backlight_on(intel_dp);
1700                 intel_psr_enable(intel_dp);
1701                 intel_edp_drrs_enable(intel_dp);
1702         }
1703
1704         if (intel_crtc->config->has_audio) {
1705                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1706                 intel_audio_codec_enable(intel_encoder);
1707         }
1708 }
1709
1710 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1711 {
1712         struct drm_encoder *encoder = &intel_encoder->base;
1713         struct drm_crtc *crtc = encoder->crtc;
1714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1715         int type = intel_encoder->type;
1716         struct drm_device *dev = encoder->dev;
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718
1719         if (intel_crtc->config->has_audio) {
1720                 intel_audio_codec_disable(intel_encoder);
1721                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1722         }
1723
1724         if (type == INTEL_OUTPUT_EDP) {
1725                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1726
1727                 intel_edp_drrs_disable(intel_dp);
1728                 intel_psr_disable(intel_dp);
1729                 intel_edp_backlight_off(intel_dp);
1730         }
1731 }
1732
1733 static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
1734                                    enum dpio_phy phy)
1735 {
1736         if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1737                 return false;
1738
1739         if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1740              (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1741                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1742                                  phy);
1743
1744                 return false;
1745         }
1746
1747         if (phy == DPIO_PHY1 &&
1748             !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1749                 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1750
1751                 return false;
1752         }
1753
1754         if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1755                 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1756                                  phy);
1757
1758                 return false;
1759         }
1760
1761         return true;
1762 }
1763
1764 static u32 broxton_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
1765 {
1766         u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1767
1768         return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1769 }
1770
1771 static void broxton_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1772                                       enum dpio_phy phy)
1773 {
1774         if (wait_for(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE, 10))
1775                 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1776 }
1777
1778 static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv,
1779                                      enum dpio_phy phy);
1780
1781 static void broxton_phy_init(struct drm_i915_private *dev_priv,
1782                              enum dpio_phy phy)
1783 {
1784         enum port port;
1785         u32 ports, val;
1786
1787         if (broxton_phy_is_enabled(dev_priv, phy)) {
1788                 /* Still read out the GRC value for state verification */
1789                 if (phy == DPIO_PHY0)
1790                         dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, phy);
1791
1792                 if (broxton_phy_verify_state(dev_priv, phy)) {
1793                         DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1794                                          "won't reprogram it\n", phy);
1795
1796                         return;
1797                 }
1798
1799                 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1800                                  "force reprogramming it\n", phy);
1801         } else {
1802                 DRM_DEBUG_DRIVER("DDI PHY %d not enabled, enabling it\n", phy);
1803         }
1804
1805         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1806         val |= GT_DISPLAY_POWER_ON(phy);
1807         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1808
1809         /*
1810          * The PHY registers start out inaccessible and respond to reads with
1811          * all 1s.  Eventually they become accessible as they power up, then
1812          * the reserved bit will give the default 0.  Poll on the reserved bit
1813          * becoming 0 to find when the PHY is accessible.
1814          * HW team confirmed that the time to reach phypowergood status is
1815          * anywhere between 50 us and 100us.
1816          */
1817         if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1818                 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
1819                 DRM_ERROR("timeout during PHY%d power on\n", phy);
1820         }
1821
1822         if (phy == DPIO_PHY0)
1823                 ports = BIT(PORT_B) | BIT(PORT_C);
1824         else
1825                 ports = BIT(PORT_A);
1826
1827         for_each_port_masked(port, ports) {
1828                 int lane;
1829
1830                 for (lane = 0; lane < 4; lane++) {
1831                         val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
1832                         /*
1833                          * Note that on CHV this flag is called UPAR, but has
1834                          * the same function.
1835                          */
1836                         val &= ~LATENCY_OPTIM;
1837                         if (lane != 1)
1838                                 val |= LATENCY_OPTIM;
1839
1840                         I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
1841                 }
1842         }
1843
1844         /* Program PLL Rcomp code offset */
1845         val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1846         val &= ~IREF0RC_OFFSET_MASK;
1847         val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1848         I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1849
1850         val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1851         val &= ~IREF1RC_OFFSET_MASK;
1852         val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1853         I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1854
1855         /* Program power gating */
1856         val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1857         val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1858                 SUS_CLK_CONFIG;
1859         I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1860
1861         if (phy == DPIO_PHY0) {
1862                 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1863                 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1864                 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1865         }
1866
1867         val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1868         val &= ~OCL2_LDOFUSE_PWR_DIS;
1869         /*
1870          * On PHY1 disable power on the second channel, since no port is
1871          * connected there. On PHY0 both channels have a port, so leave it
1872          * enabled.
1873          * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1874          * power down the second channel on PHY0 as well.
1875          *
1876          * FIXME: Clarify programming of the following, the register is
1877          * read-only with bit 6 fixed at 0 at least in stepping A.
1878          */
1879         if (phy == DPIO_PHY1)
1880                 val |= OCL2_LDOFUSE_PWR_DIS;
1881         I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1882
1883         if (phy == DPIO_PHY0) {
1884                 uint32_t grc_code;
1885                 /*
1886                  * PHY0 isn't connected to an RCOMP resistor so copy over
1887                  * the corresponding calibrated value from PHY1, and disable
1888                  * the automatic calibration on PHY0.
1889                  */
1890                 broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1);
1891
1892                 val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv,
1893                                                               DPIO_PHY1);
1894                 grc_code = val << GRC_CODE_FAST_SHIFT |
1895                            val << GRC_CODE_SLOW_SHIFT |
1896                            val;
1897                 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1898
1899                 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1900                 val |= GRC_DIS | GRC_RDY_OVRD;
1901                 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1902         }
1903         /*
1904          * During PHY1 init delay waiting for GRC calibration to finish, since
1905          * it can happen in parallel with the subsequent PHY0 init.
1906          */
1907
1908         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1909         val |= COMMON_RESET_DIS;
1910         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1911 }
1912
1913 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv)
1914 {
1915         /* Enable PHY1 first since it provides Rcomp for PHY0 */
1916         broxton_phy_init(dev_priv, DPIO_PHY1);
1917         broxton_phy_init(dev_priv, DPIO_PHY0);
1918
1919         /*
1920          * If BIOS enabled only PHY0 and not PHY1, we skipped waiting for the
1921          * PHY1 GRC calibration to finish, so wait for it here.
1922          */
1923         broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1);
1924 }
1925
1926 static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
1927                                enum dpio_phy phy)
1928 {
1929         uint32_t val;
1930
1931         val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1932         val &= ~COMMON_RESET_DIS;
1933         I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
1934
1935         val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1936         val &= ~GT_DISPLAY_POWER_ON(phy);
1937         I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1938 }
1939
1940 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
1941 {
1942         broxton_phy_uninit(dev_priv, DPIO_PHY1);
1943         broxton_phy_uninit(dev_priv, DPIO_PHY0);
1944 }
1945
1946 static bool __printf(6, 7)
1947 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1948                        i915_reg_t reg, u32 mask, u32 expected,
1949                        const char *reg_fmt, ...)
1950 {
1951         struct va_format vaf;
1952         va_list args;
1953         u32 val;
1954
1955         val = I915_READ(reg);
1956         if ((val & mask) == expected)
1957                 return true;
1958
1959         va_start(args, reg_fmt);
1960         vaf.fmt = reg_fmt;
1961         vaf.va = &args;
1962
1963         DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1964                          "current %08x, expected %08x (mask %08x)\n",
1965                          phy, &vaf, reg.reg, val, (val & ~mask) | expected,
1966                          mask);
1967
1968         va_end(args);
1969
1970         return false;
1971 }
1972
1973 static bool broxton_phy_verify_state(struct drm_i915_private *dev_priv,
1974                                      enum dpio_phy phy)
1975 {
1976         enum port port;
1977         u32 ports;
1978         uint32_t mask;
1979         bool ok;
1980
1981 #define _CHK(reg, mask, exp, fmt, ...)                                  \
1982         __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,      \
1983                                ## __VA_ARGS__)
1984
1985         /* We expect the PHY to be always enabled */
1986         if (!broxton_phy_is_enabled(dev_priv, phy))
1987                 return false;
1988
1989         ok = true;
1990
1991         if (phy == DPIO_PHY0)
1992                 ports = BIT(PORT_B) | BIT(PORT_C);
1993         else
1994                 ports = BIT(PORT_A);
1995
1996         for_each_port_masked(port, ports) {
1997                 int lane;
1998
1999                 for (lane = 0; lane < 4; lane++)
2000                         ok &= _CHK(BXT_PORT_TX_DW14_LN(port, lane),
2001                                     LATENCY_OPTIM,
2002                                     lane != 1 ? LATENCY_OPTIM : 0,
2003                                     "BXT_PORT_TX_DW14_LN(%d, %d)", port, lane);
2004         }
2005
2006         /* PLL Rcomp code offset */
2007         ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
2008                     IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
2009                     "BXT_PORT_CL1CM_DW9(%d)", phy);
2010         ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
2011                     IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
2012                     "BXT_PORT_CL1CM_DW10(%d)", phy);
2013
2014         /* Power gating */
2015         mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
2016         ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
2017                     "BXT_PORT_CL1CM_DW28(%d)", phy);
2018
2019         if (phy == DPIO_PHY0)
2020                 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
2021                            DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
2022                            "BXT_PORT_CL2CM_DW6_BC");
2023
2024         /*
2025          * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
2026          * at least on stepping A this bit is read-only and fixed at 0.
2027          */
2028
2029         if (phy == DPIO_PHY0) {
2030                 u32 grc_code = dev_priv->bxt_phy_grc;
2031
2032                 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2033                            grc_code << GRC_CODE_SLOW_SHIFT |
2034                            grc_code;
2035                 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2036                        GRC_CODE_NOM_MASK;
2037                 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2038                             "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2039
2040                 mask = GRC_DIS | GRC_RDY_OVRD;
2041                 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2042                             "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2043         }
2044
2045         return ok;
2046 #undef _CHK
2047 }
2048
2049 void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv)
2050 {
2051         if (!broxton_phy_verify_state(dev_priv, DPIO_PHY0) ||
2052             !broxton_phy_verify_state(dev_priv, DPIO_PHY1))
2053                 i915_report_error(dev_priv, "DDI PHY state mismatch\n");
2054 }
2055
2056 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2057 {
2058         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2059         struct drm_i915_private *dev_priv =
2060                 to_i915(intel_dig_port->base.base.dev);
2061         enum port port = intel_dig_port->port;
2062         uint32_t val;
2063         bool wait = false;
2064
2065         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2066                 val = I915_READ(DDI_BUF_CTL(port));
2067                 if (val & DDI_BUF_CTL_ENABLE) {
2068                         val &= ~DDI_BUF_CTL_ENABLE;
2069                         I915_WRITE(DDI_BUF_CTL(port), val);
2070                         wait = true;
2071                 }
2072
2073                 val = I915_READ(DP_TP_CTL(port));
2074                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2075                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2076                 I915_WRITE(DP_TP_CTL(port), val);
2077                 POSTING_READ(DP_TP_CTL(port));
2078
2079                 if (wait)
2080                         intel_wait_ddi_buf_idle(dev_priv, port);
2081         }
2082
2083         val = DP_TP_CTL_ENABLE |
2084               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2085         if (intel_dp->is_mst)
2086                 val |= DP_TP_CTL_MODE_MST;
2087         else {
2088                 val |= DP_TP_CTL_MODE_SST;
2089                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2090                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2091         }
2092         I915_WRITE(DP_TP_CTL(port), val);
2093         POSTING_READ(DP_TP_CTL(port));
2094
2095         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2096         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2097         POSTING_READ(DDI_BUF_CTL(port));
2098
2099         udelay(600);
2100 }
2101
2102 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2103 {
2104         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2105         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2106         uint32_t val;
2107
2108         /*
2109          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2110          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2111          * step 13 is the correct place for it. Step 18 is where it was
2112          * originally before the BUN.
2113          */
2114         val = I915_READ(FDI_RX_CTL(PIPE_A));
2115         val &= ~FDI_RX_ENABLE;
2116         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2117
2118         intel_ddi_post_disable(intel_encoder);
2119
2120         val = I915_READ(FDI_RX_MISC(PIPE_A));
2121         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2122         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2123         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
2124
2125         val = I915_READ(FDI_RX_CTL(PIPE_A));
2126         val &= ~FDI_PCDCLK;
2127         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2128
2129         val = I915_READ(FDI_RX_CTL(PIPE_A));
2130         val &= ~FDI_RX_PLL_ENABLE;
2131         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
2132 }
2133
2134 void intel_ddi_get_config(struct intel_encoder *encoder,
2135                           struct intel_crtc_state *pipe_config)
2136 {
2137         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2138         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2139         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2140         struct intel_hdmi *intel_hdmi;
2141         u32 temp, flags = 0;
2142
2143         /* XXX: DSI transcoder paranoia */
2144         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2145                 return;
2146
2147         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2148         if (temp & TRANS_DDI_PHSYNC)
2149                 flags |= DRM_MODE_FLAG_PHSYNC;
2150         else
2151                 flags |= DRM_MODE_FLAG_NHSYNC;
2152         if (temp & TRANS_DDI_PVSYNC)
2153                 flags |= DRM_MODE_FLAG_PVSYNC;
2154         else
2155                 flags |= DRM_MODE_FLAG_NVSYNC;
2156
2157         pipe_config->base.adjusted_mode.flags |= flags;
2158
2159         switch (temp & TRANS_DDI_BPC_MASK) {
2160         case TRANS_DDI_BPC_6:
2161                 pipe_config->pipe_bpp = 18;
2162                 break;
2163         case TRANS_DDI_BPC_8:
2164                 pipe_config->pipe_bpp = 24;
2165                 break;
2166         case TRANS_DDI_BPC_10:
2167                 pipe_config->pipe_bpp = 30;
2168                 break;
2169         case TRANS_DDI_BPC_12:
2170                 pipe_config->pipe_bpp = 36;
2171                 break;
2172         default:
2173                 break;
2174         }
2175
2176         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2177         case TRANS_DDI_MODE_SELECT_HDMI:
2178                 pipe_config->has_hdmi_sink = true;
2179                 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2180
2181                 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2182                         pipe_config->has_infoframe = true;
2183                 break;
2184         case TRANS_DDI_MODE_SELECT_DVI:
2185         case TRANS_DDI_MODE_SELECT_FDI:
2186                 break;
2187         case TRANS_DDI_MODE_SELECT_DP_SST:
2188         case TRANS_DDI_MODE_SELECT_DP_MST:
2189                 pipe_config->has_dp_encoder = true;
2190                 pipe_config->lane_count =
2191                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2192                 intel_dp_get_m_n(intel_crtc, pipe_config);
2193                 break;
2194         default:
2195                 break;
2196         }
2197
2198         if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2199                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2200                 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2201                         pipe_config->has_audio = true;
2202         }
2203
2204         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2205             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2206                 /*
2207                  * This is a big fat ugly hack.
2208                  *
2209                  * Some machines in UEFI boot mode provide us a VBT that has 18
2210                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2211                  * unknown we fail to light up. Yet the same BIOS boots up with
2212                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2213                  * max, not what it tells us to use.
2214                  *
2215                  * Note: This will still be broken if the eDP panel is not lit
2216                  * up by the BIOS, and thus we can't get the mode at module
2217                  * load.
2218                  */
2219                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2220                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2221                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2222         }
2223
2224         intel_ddi_clock_get(encoder, pipe_config);
2225 }
2226
2227 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2228                                      struct intel_crtc_state *pipe_config)
2229 {
2230         int type = encoder->type;
2231         int port = intel_ddi_get_encoder_port(encoder);
2232
2233         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
2234
2235         if (port == PORT_A)
2236                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2237
2238         if (type == INTEL_OUTPUT_HDMI)
2239                 return intel_hdmi_compute_config(encoder, pipe_config);
2240         else
2241                 return intel_dp_compute_config(encoder, pipe_config);
2242 }
2243
2244 static const struct drm_encoder_funcs intel_ddi_funcs = {
2245         .reset = intel_dp_encoder_reset,
2246         .destroy = intel_dp_encoder_destroy,
2247 };
2248
2249 static struct intel_connector *
2250 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2251 {
2252         struct intel_connector *connector;
2253         enum port port = intel_dig_port->port;
2254
2255         connector = intel_connector_alloc();
2256         if (!connector)
2257                 return NULL;
2258
2259         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2260         if (!intel_dp_init_connector(intel_dig_port, connector)) {
2261                 kfree(connector);
2262                 return NULL;
2263         }
2264
2265         return connector;
2266 }
2267
2268 static struct intel_connector *
2269 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2270 {
2271         struct intel_connector *connector;
2272         enum port port = intel_dig_port->port;
2273
2274         connector = intel_connector_alloc();
2275         if (!connector)
2276                 return NULL;
2277
2278         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2279         intel_hdmi_init_connector(intel_dig_port, connector);
2280
2281         return connector;
2282 }
2283
2284 void intel_ddi_init(struct drm_device *dev, enum port port)
2285 {
2286         struct drm_i915_private *dev_priv = dev->dev_private;
2287         struct intel_digital_port *intel_dig_port;
2288         struct intel_encoder *intel_encoder;
2289         struct drm_encoder *encoder;
2290         bool init_hdmi, init_dp;
2291         int max_lanes;
2292
2293         if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2294                 switch (port) {
2295                 case PORT_A:
2296                         max_lanes = 4;
2297                         break;
2298                 case PORT_E:
2299                         max_lanes = 0;
2300                         break;
2301                 default:
2302                         max_lanes = 4;
2303                         break;
2304                 }
2305         } else {
2306                 switch (port) {
2307                 case PORT_A:
2308                         max_lanes = 2;
2309                         break;
2310                 case PORT_E:
2311                         max_lanes = 2;
2312                         break;
2313                 default:
2314                         max_lanes = 4;
2315                         break;
2316                 }
2317         }
2318
2319         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2320                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2321         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2322         if (!init_dp && !init_hdmi) {
2323                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2324                               port_name(port));
2325                 return;
2326         }
2327
2328         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2329         if (!intel_dig_port)
2330                 return;
2331
2332         intel_encoder = &intel_dig_port->base;
2333         encoder = &intel_encoder->base;
2334
2335         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2336                          DRM_MODE_ENCODER_TMDS, NULL);
2337
2338         intel_encoder->compute_config = intel_ddi_compute_config;
2339         intel_encoder->enable = intel_enable_ddi;
2340         intel_encoder->pre_enable = intel_ddi_pre_enable;
2341         intel_encoder->disable = intel_disable_ddi;
2342         intel_encoder->post_disable = intel_ddi_post_disable;
2343         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2344         intel_encoder->get_config = intel_ddi_get_config;
2345         intel_encoder->suspend = intel_dp_encoder_suspend;
2346
2347         intel_dig_port->port = port;
2348         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2349                                           (DDI_BUF_PORT_REVERSAL |
2350                                            DDI_A_4_LANES);
2351
2352         /*
2353          * Bspec says that DDI_A_4_LANES is the only supported configuration
2354          * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
2355          * wasn't lit up at boot.  Force this bit on in our internal
2356          * configuration so that we use the proper lane count for our
2357          * calculations.
2358          */
2359         if (IS_BROXTON(dev) && port == PORT_A) {
2360                 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2361                         DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2362                         intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2363                         max_lanes = 4;
2364                 }
2365         }
2366
2367         intel_dig_port->max_lanes = max_lanes;
2368
2369         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2370         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2371         intel_encoder->cloneable = 0;
2372
2373         if (init_dp) {
2374                 if (!intel_ddi_init_dp_connector(intel_dig_port))
2375                         goto err;
2376
2377                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2378                 /*
2379                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2380                  * interrupts to check the external panel connection.
2381                  */
2382                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
2383                         dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2384                 else
2385                         dev_priv->hotplug.irq_port[port] = intel_dig_port;
2386         }
2387
2388         /* In theory we don't need the encoder->type check, but leave it just in
2389          * case we have some really bad VBTs... */
2390         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2391                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2392                         goto err;
2393         }
2394
2395         return;
2396
2397 err:
2398         drm_encoder_cleanup(encoder);
2399         kfree(intel_dig_port);
2400 }