drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/etherdevice.h>
  36 #include <net/ip.h>
  37 #include <linux/slab.h>
  38 #include <linux/netdevice.h>
  39 #include <linux/vmalloc.h>
  40
  41 #include <rdma/ib_cache.h>
  42 #include <rdma/ib_pack.h>
  43 #include <rdma/ib_addr.h>
  44 #include <rdma/ib_mad.h>
  45
  46 #include <linux/mlx4/driver.h>
  47 #include <linux/mlx4/qp.h>
  48
  49 #include "mlx4_ib.h"
  50 #include <rdma/mlx4-abi.h>
  51
  52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  53                              struct mlx4_ib_cq *recv_cq);
  54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  55                                struct mlx4_ib_cq *recv_cq);
  56
  57 enum {
  58         MLX4_IB_ACK_REQ_FREQ    = 8,
  59 };
  60
  61 enum {
  62         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  63         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  64         MLX4_IB_LINK_TYPE_IB            = 0,
  65         MLX4_IB_LINK_TYPE_ETH           = 1
  66 };
  67
  68 enum {
  69         /*
  70          * Largest possible UD header: send with GRH and immediate
  71          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  72          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  73          * biggest case)
  74          */
  75         MLX4_IB_UD_HEADER_SIZE          = 82,
  76         MLX4_IB_LSO_HEADER_SPARE        = 128,
  77 };
  78
  79 struct mlx4_ib_sqp {
  80         struct mlx4_ib_qp       qp;
  81         int                     pkey_index;
  82         u32                     qkey;
  83         u32                     send_psn;
  84         struct ib_ud_header     ud_header;
  85         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  86         struct ib_qp            *roce_v2_gsi;
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 116         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 117 };
 118
 119 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 120 {
 121         return container_of(mqp, struct mlx4_ib_sqp, qp);
 122 }
 123
 124 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 125 {
 126         if (!mlx4_is_master(dev->dev))
 127                 return 0;
 128
 129         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 130                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 131                 8 * MLX4_MFUNC_MAX;
 132 }
 133
 134 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 135 {
 136         int proxy_sqp = 0;
 137         int real_sqp = 0;
 138         int i;
 139         /* PPF or Native -- real SQP */
 140         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 141                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 142                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 143         if (real_sqp)
 144                 return 1;
 145         /* VF or PF -- proxy SQP */
 146         if (mlx4_is_mfunc(dev->dev)) {
 147                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 148                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 149                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 150                                 proxy_sqp = 1;
 151                                 break;
 152                         }
 153                 }
 154         }
 155         if (proxy_sqp)
 156                 return 1;
 157
 158         return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
 159 }
 160
 161 /* used for INIT/CLOSE port logic */
 162 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 163 {
 164         int proxy_qp0 = 0;
 165         int real_qp0 = 0;
 166         int i;
 167         /* PPF or Native -- real QP0 */
 168         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 169                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 170                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 171         if (real_qp0)
 172                 return 1;
 173         /* VF or PF -- proxy QP0 */
 174         if (mlx4_is_mfunc(dev->dev)) {
 175                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 176                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 177                                 proxy_qp0 = 1;
 178                                 break;
 179                         }
 180                 }
 181         }
 182         return proxy_qp0;
 183 }
 184
 185 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 186 {
 187         return mlx4_buf_offset(&qp->buf, offset);
 188 }
 189
 190 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 191 {
 192         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 193 }
 194
 195 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 196 {
 197         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 198 }
 199
 200 /*
 201  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 202  * first four bytes of every 64 byte chunk with
 203  *     0x7FFFFFF | (invalid_ownership_value << 31).
 204  *
 205  * When the max work request size is less than or equal to the WQE
 206  * basic block size, as an optimization, we can stamp all WQEs with
 207  * 0xffffffff, and skip the very first chunk of each WQE.
 208  */
 209 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 210 {
 211         __be32 *wqe;
 212         int i;
 213         int s;
 214         int ind;
 215         void *buf;
 216         __be32 stamp;
 217         struct mlx4_wqe_ctrl_seg *ctrl;
 218
 219         if (qp->sq_max_wqes_per_wr > 1) {
 220                 s = roundup(size, 1U << qp->sq.wqe_shift);
 221                 for (i = 0; i < s; i += 64) {
 222                         ind = (i >> qp->sq.wqe_shift) + n;
 223                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 224                                                        cpu_to_be32(0xffffffff);
 225                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 226                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 227                         *wqe = stamp;
 228                 }
 229         } else {
 230                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 231                 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
 232                 for (i = 64; i < s; i += 64) {
 233                         wqe = buf + i;
 234                         *wqe = cpu_to_be32(0xffffffff);
 235                 }
 236         }
 237 }
 238
 239 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 240 {
 241         struct mlx4_wqe_ctrl_seg *ctrl;
 242         struct mlx4_wqe_inline_seg *inl;
 243         void *wqe;
 244         int s;
 245
 246         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 247         s = sizeof(struct mlx4_wqe_ctrl_seg);
 248
 249         if (qp->ibqp.qp_type == IB_QPT_UD) {
 250                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 251                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 252                 memset(dgram, 0, sizeof *dgram);
 253                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 254                 s += sizeof(struct mlx4_wqe_datagram_seg);
 255         }
 256
 257         /* Pad the remainder of the WQE with an inline data segment. */
 258         if (size > s) {
 259                 inl = wqe + s;
 260                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 261         }
 262         ctrl->srcrb_flags = 0;
 263         ctrl->qpn_vlan.fence_size = size / 16;
 264         /*
 265          * Make sure descriptor is fully written before setting ownership bit
 266          * (because HW can start executing as soon as we do).
 267          */
 268         wmb();
 269
 270         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 271                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 272
 273         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 274 }
 275
 276 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 277 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 278 {
 279         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 280         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 281                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 282                 ind += s;
 283         }
 284         return ind;
 285 }
 286
 287 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 288 {
 289         struct ib_event event;
 290         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 291
 292         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 293                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 294
 295         if (ibqp->event_handler) {
 296                 event.device     = ibqp->device;
 297                 event.element.qp = ibqp;
 298                 switch (type) {
 299                 case MLX4_EVENT_TYPE_PATH_MIG:
 300                         event.event = IB_EVENT_PATH_MIG;
 301                         break;
 302                 case MLX4_EVENT_TYPE_COMM_EST:
 303                         event.event = IB_EVENT_COMM_EST;
 304                         break;
 305                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 306                         event.event = IB_EVENT_SQ_DRAINED;
 307                         break;
 308                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 309                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 310                         break;
 311                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 312                         event.event = IB_EVENT_QP_FATAL;
 313                         break;
 314                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 315                         event.event = IB_EVENT_PATH_MIG_ERR;
 316                         break;
 317                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 318                         event.event = IB_EVENT_QP_REQ_ERR;
 319                         break;
 320                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 321                         event.event = IB_EVENT_QP_ACCESS_ERR;
 322                         break;
 323                 default:
 324                         pr_warn("Unexpected event type %d "
 325                                "on QP %06x\n", type, qp->qpn);
 326                         return;
 327                 }
 328
 329                 ibqp->event_handler(&event, ibqp->qp_context);
 330         }
 331 }
 332
 333 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 334 {
 335         /*
 336          * UD WQEs must have a datagram segment.
 337          * RC and UC WQEs might have a remote address segment.
 338          * MLX WQEs need two extra inline data segments (for the UD
 339          * header and space for the ICRC).
 340          */
 341         switch (type) {
 342         case MLX4_IB_QPT_UD:
 343                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 344                         sizeof (struct mlx4_wqe_datagram_seg) +
 345                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 346         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 347         case MLX4_IB_QPT_PROXY_SMI:
 348         case MLX4_IB_QPT_PROXY_GSI:
 349                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 350                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 351         case MLX4_IB_QPT_TUN_SMI_OWNER:
 352         case MLX4_IB_QPT_TUN_GSI:
 353                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 354                         sizeof (struct mlx4_wqe_datagram_seg);
 355
 356         case MLX4_IB_QPT_UC:
 357                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 358                         sizeof (struct mlx4_wqe_raddr_seg);
 359         case MLX4_IB_QPT_RC:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_masked_atomic_seg) +
 362                         sizeof (struct mlx4_wqe_raddr_seg);
 363         case MLX4_IB_QPT_SMI:
 364         case MLX4_IB_QPT_GSI:
 365                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 366                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 367                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 368                                            MLX4_INLINE_ALIGN) *
 369                               sizeof (struct mlx4_wqe_inline_seg),
 370                               sizeof (struct mlx4_wqe_data_seg)) +
 371                         ALIGN(4 +
 372                               sizeof (struct mlx4_wqe_inline_seg),
 373                               sizeof (struct mlx4_wqe_data_seg));
 374         default:
 375                 return sizeof (struct mlx4_wqe_ctrl_seg);
 376         }
 377 }
 378
 379 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 380                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 381 {
 382         /* Sanity check RQ size before proceeding */
 383         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 384             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 385                 return -EINVAL;
 386
 387         if (!has_rq) {
 388                 if (cap->max_recv_wr)
 389                         return -EINVAL;
 390
 391                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 392         } else {
 393                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 394                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 395                         return -EINVAL;
 396
 397                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 398                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 399                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 400         }
 401
 402         /* leave userspace return values as they were, so as not to break ABI */
 403         if (is_user) {
 404                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 405                 cap->max_recv_sge = qp->rq.max_gs;
 406         } else {
 407                 cap->max_recv_wr  = qp->rq.max_post =
 408                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 409                 cap->max_recv_sge = min(qp->rq.max_gs,
 410                                         min(dev->dev->caps.max_sq_sg,
 411                                             dev->dev->caps.max_rq_sg));
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 418                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
 419                               bool shrink_wqe)
 420 {
 421         int s;
 422
 423         /* Sanity check SQ size before proceeding */
 424         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 425             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 426             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 427             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 428                 return -EINVAL;
 429
 430         /*
 431          * For MLX transport we need 2 extra S/G entries:
 432          * one for the header and one for the checksum at the end
 433          */
 434         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 435              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 436             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 437                 return -EINVAL;
 438
 439         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 440                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 441                 send_wqe_overhead(type, qp->flags);
 442
 443         if (s > dev->dev->caps.max_sq_desc_sz)
 444                 return -EINVAL;
 445
 446         /*
 447          * Hermon supports shrinking WQEs, such that a single work
 448          * request can include multiple units of 1 << wqe_shift.  This
 449          * way, work requests can differ in size, and do not have to
 450          * be a power of 2 in size, saving memory and speeding up send
 451          * WR posting.  Unfortunately, if we do this then the
 452          * wqe_index field in CQEs can't be used to look up the WR ID
 453          * anymore, so we do this only if selective signaling is off.
 454          *
 455          * Further, on 32-bit platforms, we can't use vmap() to make
 456          * the QP buffer virtually contiguous.  Thus we have to use
 457          * constant-sized WRs to make sure a WR is always fully within
 458          * a single page-sized chunk.
 459          *
 460          * Finally, we use NOP work requests to pad the end of the
 461          * work queue, to avoid wrap-around in the middle of WR.  We
 462          * set NEC bit to avoid getting completions with error for
 463          * these NOP WRs, but since NEC is only supported starting
 464          * with firmware 2.2.232, we use constant-sized WRs for older
 465          * firmware.
 466          *
 467          * And, since MLX QPs only support SEND, we use constant-sized
 468          * WRs in this case.
 469          *
 470          * We look for the smallest value of wqe_shift such that the
 471          * resulting number of wqes does not exceed device
 472          * capabilities.
 473          *
 474          * We set WQE size to at least 64 bytes, this way stamping
 475          * invalidates each WQE.
 476          */
 477         if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 478             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 479             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 480             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 481                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 482                 qp->sq.wqe_shift = ilog2(64);
 483         else
 484                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 485
 486         for (;;) {
 487                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 488
 489                 /*
 490                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 491                  * allow HW to prefetch.
 492                  */
 493                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 494                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 495                                                     qp->sq_max_wqes_per_wr +
 496                                                     qp->sq_spare_wqes);
 497
 498                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 499                         break;
 500
 501                 if (qp->sq_max_wqes_per_wr <= 1)
 502                         return -EINVAL;
 503
 504                 ++qp->sq.wqe_shift;
 505         }
 506
 507         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 508                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 509                          send_wqe_overhead(type, qp->flags)) /
 510                 sizeof (struct mlx4_wqe_data_seg);
 511
 512         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 513                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 514         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 515                 qp->rq.offset = 0;
 516                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 517         } else {
 518                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 519                 qp->sq.offset = 0;
 520         }
 521
 522         cap->max_send_wr  = qp->sq.max_post =
 523                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 524         cap->max_send_sge = min(qp->sq.max_gs,
 525                                 min(dev->dev->caps.max_sq_sg,
 526                                     dev->dev->caps.max_rq_sg));
 527         /* We don't support inline sends for kernel QPs (yet) */
 528         cap->max_inline_data = 0;
 529
 530         return 0;
 531 }
 532
 533 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 534                             struct mlx4_ib_qp *qp,
 535                             struct mlx4_ib_create_qp *ucmd)
 536 {
 537         /* Sanity check SQ size before proceeding */
 538         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 539             ucmd->log_sq_stride >
 540                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 541             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 542                 return -EINVAL;
 543
 544         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 545         qp->sq.wqe_shift = ucmd->log_sq_stride;
 546
 547         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 548                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 549
 550         return 0;
 551 }
 552
 553 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 554 {
 555         int i;
 556
 557         qp->sqp_proxy_rcv =
 558                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 559                         GFP_KERNEL);
 560         if (!qp->sqp_proxy_rcv)
 561                 return -ENOMEM;
 562         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 563                 qp->sqp_proxy_rcv[i].addr =
 564                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 565                                 GFP_KERNEL);
 566                 if (!qp->sqp_proxy_rcv[i].addr)
 567                         goto err;
 568                 qp->sqp_proxy_rcv[i].map =
 569                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 570                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 571                                           DMA_FROM_DEVICE);
 572                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 573                         kfree(qp->sqp_proxy_rcv[i].addr);
 574                         goto err;
 575                 }
 576         }
 577         return 0;
 578
 579 err:
 580         while (i > 0) {
 581                 --i;
 582                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 583                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 584                                     DMA_FROM_DEVICE);
 585                 kfree(qp->sqp_proxy_rcv[i].addr);
 586         }
 587         kfree(qp->sqp_proxy_rcv);
 588         qp->sqp_proxy_rcv = NULL;
 589         return -ENOMEM;
 590 }
 591
 592 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 593 {
 594         int i;
 595
 596         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 597                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 598                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 599                                     DMA_FROM_DEVICE);
 600                 kfree(qp->sqp_proxy_rcv[i].addr);
 601         }
 602         kfree(qp->sqp_proxy_rcv);
 603 }
 604
 605 static int qp_has_rq(struct ib_qp_init_attr *attr)
 606 {
 607         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 608                 return 0;
 609
 610         return !attr->srq;
 611 }
 612
 613 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 614 {
 615         int i;
 616         for (i = 0; i < dev->caps.num_ports; i++) {
 617                 if (qpn == dev->caps.qp0_proxy[i])
 618                         return !!dev->caps.qp0_qkey[i];
 619         }
 620         return 0;
 621 }
 622
 623 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 624                                     struct mlx4_ib_qp *qp)
 625 {
 626         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 627         mlx4_counter_free(dev->dev, qp->counter_index->index);
 628         list_del(&qp->counter_index->list);
 629         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 630
 631         kfree(qp->counter_index);
 632         qp->counter_index = NULL;
 633 }
 634
 635 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 636                             struct ib_qp_init_attr *init_attr,
 637                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
 638                             gfp_t gfp)
 639 {
 640         int qpn;
 641         int err;
 642         struct ib_qp_cap backup_cap;
 643         struct mlx4_ib_sqp *sqp = NULL;
 644         struct mlx4_ib_qp *qp;
 645         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 646         struct mlx4_ib_cq *mcq;
 647         unsigned long flags;
 648
 649         /* When tunneling special qps, we use a plain UD qp */
 650         if (sqpn) {
 651                 if (mlx4_is_mfunc(dev->dev) &&
 652                     (!mlx4_is_master(dev->dev) ||
 653                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 654                         if (init_attr->qp_type == IB_QPT_GSI)
 655                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 656                         else {
 657                                 if (mlx4_is_master(dev->dev) ||
 658                                     qp0_enabled_vf(dev->dev, sqpn))
 659                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 660                                 else
 661                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 662                         }
 663                 }
 664                 qpn = sqpn;
 665                 /* add extra sg entry for tunneling */
 666                 init_attr->cap.max_recv_sge++;
 667         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 668                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 669                         container_of(init_attr,
 670                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 671                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 672                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 673                     !mlx4_is_master(dev->dev))
 674                         return -EINVAL;
 675                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 676                         qp_type = MLX4_IB_QPT_TUN_GSI;
 677                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 678                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 679                                              tnl_init->port))
 680                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 681                 else
 682                         qp_type = MLX4_IB_QPT_TUN_SMI;
 683                 /* we are definitely in the PPF here, since we are creating
 684                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 685                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 686                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 687                 sqpn = qpn;
 688         }
 689
 690         if (!*caller_qp) {
 691                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 692                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 693                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 694                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
 695                         if (!sqp)
 696                                 return -ENOMEM;
 697                         qp = &sqp->qp;
 698                         qp->pri.vid = 0xFFFF;
 699                         qp->alt.vid = 0xFFFF;
 700                 } else {
 701                         qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
 702                         if (!qp)
 703                                 return -ENOMEM;
 704                         qp->pri.vid = 0xFFFF;
 705                         qp->alt.vid = 0xFFFF;
 706                 }
 707         } else
 708                 qp = *caller_qp;
 709
 710         qp->mlx4_ib_qp_type = qp_type;
 711
 712         mutex_init(&qp->mutex);
 713         spin_lock_init(&qp->sq.lock);
 714         spin_lock_init(&qp->rq.lock);
 715         INIT_LIST_HEAD(&qp->gid_list);
 716         INIT_LIST_HEAD(&qp->steering_rules);
 717
 718         qp->state        = IB_QPS_RESET;
 719         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 720                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 721
 722         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 723         if (err)
 724                 goto err;
 725
 726         if (pd->uobject) {
 727                 struct mlx4_ib_create_qp ucmd;
 728
 729                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 730                         err = -EFAULT;
 731                         goto err;
 732                 }
 733
 734                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 735
 736                 err = set_user_sq_size(dev, qp, &ucmd);
 737                 if (err)
 738                         goto err;
 739
 740                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 741                                        qp->buf_size, 0, 0);
 742                 if (IS_ERR(qp->umem)) {
 743                         err = PTR_ERR(qp->umem);
 744                         goto err;
 745                 }
 746
 747                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 748                                     ilog2(qp->umem->page_size), &qp->mtt);
 749                 if (err)
 750                         goto err_buf;
 751
 752                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 753                 if (err)
 754                         goto err_mtt;
 755
 756                 if (qp_has_rq(init_attr)) {
 757                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 758                                                   ucmd.db_addr, &qp->db);
 759                         if (err)
 760                                 goto err_mtt;
 761                 }
 762         } else {
 763                 qp->sq_no_prefetch = 0;
 764
 765                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 766                         qp->flags |= MLX4_IB_QP_LSO;
 767
 768                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 769                         if (dev->steering_support ==
 770                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 771                                 qp->flags |= MLX4_IB_QP_NETIF;
 772                         else
 773                                 goto err;
 774                 }
 775
 776                 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
 777                 err = set_kernel_sq_size(dev, &init_attr->cap,
 778                                          qp_type, qp, true);
 779                 if (err)
 780                         goto err;
 781
 782                 if (qp_has_rq(init_attr)) {
 783                         err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
 784                         if (err)
 785                                 goto err;
 786
 787                         *qp->db.db = 0;
 788                 }
 789
 790                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
 791                                    &qp->buf, gfp)) {
 792                         memcpy(&init_attr->cap, &backup_cap,
 793                                sizeof(backup_cap));
 794                         err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
 795                                                  qp, false);
 796                         if (err)
 797                                 goto err_db;
 798
 799                         if (mlx4_buf_alloc(dev->dev, qp->buf_size,
 800                                            PAGE_SIZE * 2, &qp->buf, gfp)) {
 801                                 err = -ENOMEM;
 802                                 goto err_db;
 803                         }
 804                 }
 805
 806                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 807                                     &qp->mtt);
 808                 if (err)
 809                         goto err_buf;
 810
 811                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
 812                 if (err)
 813                         goto err_mtt;
 814
 815                 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
 816                                         gfp | __GFP_NOWARN);
 817                 if (!qp->sq.wrid)
 818                         qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
 819                                                 gfp, PAGE_KERNEL);
 820                 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
 821                                         gfp | __GFP_NOWARN);
 822                 if (!qp->rq.wrid)
 823                         qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
 824                                                 gfp, PAGE_KERNEL);
 825                 if (!qp->sq.wrid || !qp->rq.wrid) {
 826                         err = -ENOMEM;
 827                         goto err_wrid;
 828                 }
 829         }
 830
 831         if (sqpn) {
 832                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 833                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 834                         if (alloc_proxy_bufs(pd->device, qp)) {
 835                                 err = -ENOMEM;
 836                                 goto err_wrid;
 837                         }
 838                 }
 839         } else {
 840                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
 841                  * otherwise, the WQE BlueFlame setup flow wrongly causes
 842                  * VLAN insertion. */
 843                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 844                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
 845                                                     (init_attr->cap.max_send_wr ?
 846                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
 847                                                     (init_attr->cap.max_recv_wr ?
 848                                                      MLX4_RESERVE_A0_QP : 0));
 849                 else
 850                         if (qp->flags & MLX4_IB_QP_NETIF)
 851                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 852                         else
 853                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 854                                                             &qpn, 0);
 855                 if (err)
 856                         goto err_proxy;
 857         }
 858
 859         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 860                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 861
 862         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
 863         if (err)
 864                 goto err_qpn;
 865
 866         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 867                 qp->mqp.qpn |= (1 << 23);
 868
 869         /*
 870          * Hardware wants QPN written in big-endian order (after
 871          * shifting) for send doorbell.  Precompute this value to save
 872          * a little bit when posting sends.
 873          */
 874         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 875
 876         qp->mqp.event = mlx4_ib_qp_event;
 877         if (!*caller_qp)
 878                 *caller_qp = qp;
 879
 880         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
 881         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
 882                          to_mcq(init_attr->recv_cq));
 883         /* Maintain device to QPs access, needed for further handling
 884          * via reset flow
 885          */
 886         list_add_tail(&qp->qps_list, &dev->qp_list);
 887         /* Maintain CQ to QPs access, needed for further handling
 888          * via reset flow
 889          */
 890         mcq = to_mcq(init_attr->send_cq);
 891         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
 892         mcq = to_mcq(init_attr->recv_cq);
 893         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
 894         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
 895                            to_mcq(init_attr->recv_cq));
 896         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
 897         return 0;
 898
 899 err_qpn:
 900         if (!sqpn) {
 901                 if (qp->flags & MLX4_IB_QP_NETIF)
 902                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 903                 else
 904                         mlx4_qp_release_range(dev->dev, qpn, 1);
 905         }
 906 err_proxy:
 907         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 908                 free_proxy_bufs(pd->device, qp);
 909 err_wrid:
 910         if (pd->uobject) {
 911                 if (qp_has_rq(init_attr))
 912                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 913         } else {
 914                 kvfree(qp->sq.wrid);
 915                 kvfree(qp->rq.wrid);
 916         }
 917
 918 err_mtt:
 919         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 920
 921 err_buf:
 922         if (pd->uobject)
 923                 ib_umem_release(qp->umem);
 924         else
 925                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 926
 927 err_db:
 928         if (!pd->uobject && qp_has_rq(init_attr))
 929                 mlx4_db_free(dev->dev, &qp->db);
 930
 931 err:
 932         if (sqp)
 933                 kfree(sqp);
 934         else if (!*caller_qp)
 935                 kfree(qp);
 936         return err;
 937 }
 938
 939 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 940 {
 941         switch (state) {
 942         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 943         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 944         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 945         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 946         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 947         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 948         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 949         default:                return -1;
 950         }
 951 }
 952
 953 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 954         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 955 {
 956         if (send_cq == recv_cq) {
 957                 spin_lock(&send_cq->lock);
 958                 __acquire(&recv_cq->lock);
 959         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 960                 spin_lock(&send_cq->lock);
 961                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 962         } else {
 963                 spin_lock(&recv_cq->lock);
 964                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 965         }
 966 }
 967
 968 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 969         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 970 {
 971         if (send_cq == recv_cq) {
 972                 __release(&recv_cq->lock);
 973                 spin_unlock(&send_cq->lock);
 974         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 975                 spin_unlock(&recv_cq->lock);
 976                 spin_unlock(&send_cq->lock);
 977         } else {
 978                 spin_unlock(&send_cq->lock);
 979                 spin_unlock(&recv_cq->lock);
 980         }
 981 }
 982
 983 static void del_gid_entries(struct mlx4_ib_qp *qp)
 984 {
 985         struct mlx4_ib_gid_entry *ge, *tmp;
 986
 987         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 988                 list_del(&ge->list);
 989                 kfree(ge);
 990         }
 991 }
 992
 993 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 994 {
 995         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 996                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 997         else
 998                 return to_mpd(qp->ibqp.pd);
 999 }
1000
1001 static void get_cqs(struct mlx4_ib_qp *qp,
1002                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1003 {
1004         switch (qp->ibqp.qp_type) {
1005         case IB_QPT_XRC_TGT:
1006                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1007                 *recv_cq = *send_cq;
1008                 break;
1009         case IB_QPT_XRC_INI:
1010                 *send_cq = to_mcq(qp->ibqp.send_cq);
1011                 *recv_cq = *send_cq;
1012                 break;
1013         default:
1014                 *send_cq = to_mcq(qp->ibqp.send_cq);
1015                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1016                 break;
1017         }
1018 }
1019
1020 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1021                               int is_user)
1022 {
1023         struct mlx4_ib_cq *send_cq, *recv_cq;
1024         unsigned long flags;
1025
1026         if (qp->state != IB_QPS_RESET) {
1027                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1028                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1029                         pr_warn("modify QP %06x to RESET failed.\n",
1030                                qp->mqp.qpn);
1031                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1032                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1033                         qp->pri.smac = 0;
1034                         qp->pri.smac_port = 0;
1035                 }
1036                 if (qp->alt.smac) {
1037                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1038                         qp->alt.smac = 0;
1039                 }
1040                 if (qp->pri.vid < 0x1000) {
1041                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1042                         qp->pri.vid = 0xFFFF;
1043                         qp->pri.candidate_vid = 0xFFFF;
1044                         qp->pri.update_vid = 0;
1045                 }
1046                 if (qp->alt.vid < 0x1000) {
1047                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1048                         qp->alt.vid = 0xFFFF;
1049                         qp->alt.candidate_vid = 0xFFFF;
1050                         qp->alt.update_vid = 0;
1051                 }
1052         }
1053
1054         get_cqs(qp, &send_cq, &recv_cq);
1055
1056         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1057         mlx4_ib_lock_cqs(send_cq, recv_cq);
1058
1059         /* del from lists under both locks above to protect reset flow paths */
1060         list_del(&qp->qps_list);
1061         list_del(&qp->cq_send_list);
1062         list_del(&qp->cq_recv_list);
1063         if (!is_user) {
1064                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1065                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1066                 if (send_cq != recv_cq)
1067                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1068         }
1069
1070         mlx4_qp_remove(dev->dev, &qp->mqp);
1071
1072         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1073         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1074
1075         mlx4_qp_free(dev->dev, &qp->mqp);
1076
1077         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1078                 if (qp->flags & MLX4_IB_QP_NETIF)
1079                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1080                 else
1081                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1082         }
1083
1084         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1085
1086         if (is_user) {
1087                 if (qp->rq.wqe_cnt)
1088                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1089                                               &qp->db);
1090                 ib_umem_release(qp->umem);
1091         } else {
1092                 kvfree(qp->sq.wrid);
1093                 kvfree(qp->rq.wrid);
1094                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1095                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1096                         free_proxy_bufs(&dev->ib_dev, qp);
1097                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1098                 if (qp->rq.wqe_cnt)
1099                         mlx4_db_free(dev->dev, &qp->db);
1100         }
1101
1102         del_gid_entries(qp);
1103 }
1104
1105 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1106 {
1107         /* Native or PPF */
1108         if (!mlx4_is_mfunc(dev->dev) ||
1109             (mlx4_is_master(dev->dev) &&
1110              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1111                 return  dev->dev->phys_caps.base_sqpn +
1112                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1113                         attr->port_num - 1;
1114         }
1115         /* PF or VF -- creating proxies */
1116         if (attr->qp_type == IB_QPT_SMI)
1117                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1118         else
1119                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1120 }
1121
1122 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1123                                         struct ib_qp_init_attr *init_attr,
1124                                         struct ib_udata *udata)
1125 {
1126         struct mlx4_ib_qp *qp = NULL;
1127         int err;
1128         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1129         u16 xrcdn = 0;
1130         gfp_t gfp;
1131
1132         gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1133                 GFP_NOIO : GFP_KERNEL;
1134         /*
1135          * We only support LSO, vendor flag1, and multicast loopback blocking,
1136          * and only for kernel UD QPs.
1137          */
1138         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1139                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1140                                         MLX4_IB_SRIOV_TUNNEL_QP |
1141                                         MLX4_IB_SRIOV_SQP |
1142                                         MLX4_IB_QP_NETIF |
1143                                         MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1144                                         MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1145                 return ERR_PTR(-EINVAL);
1146
1147         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1148                 if (init_attr->qp_type != IB_QPT_UD)
1149                         return ERR_PTR(-EINVAL);
1150         }
1151
1152         if (init_attr->create_flags) {
1153                 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1154                         return ERR_PTR(-EINVAL);
1155
1156                 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1157                                                  MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1158                                                  MLX4_IB_QP_CREATE_ROCE_V2_GSI  |
1159                                                  MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1160                      init_attr->qp_type != IB_QPT_UD) ||
1161                     (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1162                      init_attr->qp_type > IB_QPT_GSI) ||
1163                     (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1164                      init_attr->qp_type != IB_QPT_GSI))
1165                         return ERR_PTR(-EINVAL);
1166         }
1167
1168         switch (init_attr->qp_type) {
1169         case IB_QPT_XRC_TGT:
1170                 pd = to_mxrcd(init_attr->xrcd)->pd;
1171                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1172                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1173                 /* fall through */
1174         case IB_QPT_XRC_INI:
1175                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1176                         return ERR_PTR(-ENOSYS);
1177                 init_attr->recv_cq = init_attr->send_cq;
1178                 /* fall through */
1179         case IB_QPT_RC:
1180         case IB_QPT_UC:
1181         case IB_QPT_RAW_PACKET:
1182                 qp = kzalloc(sizeof *qp, gfp);
1183                 if (!qp)
1184                         return ERR_PTR(-ENOMEM);
1185                 qp->pri.vid = 0xFFFF;
1186                 qp->alt.vid = 0xFFFF;
1187                 /* fall through */
1188         case IB_QPT_UD:
1189         {
1190                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1191                                        udata, 0, &qp, gfp);
1192                 if (err) {
1193                         kfree(qp);
1194                         return ERR_PTR(err);
1195                 }
1196
1197                 qp->ibqp.qp_num = qp->mqp.qpn;
1198                 qp->xrcdn = xrcdn;
1199
1200                 break;
1201         }
1202         case IB_QPT_SMI:
1203         case IB_QPT_GSI:
1204         {
1205                 int sqpn;
1206
1207                 /* Userspace is not allowed to create special QPs: */
1208                 if (udata)
1209                         return ERR_PTR(-EINVAL);
1210                 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1211                         int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0);
1212
1213                         if (res)
1214                                 return ERR_PTR(res);
1215                 } else {
1216                         sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1217                 }
1218
1219                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1220                                        sqpn,
1221                                        &qp, gfp);
1222                 if (err)
1223                         return ERR_PTR(err);
1224
1225                 qp->port        = init_attr->port_num;
1226                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1227                         init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1228                 break;
1229         }
1230         default:
1231                 /* Don't support raw QPs */
1232                 return ERR_PTR(-EINVAL);
1233         }
1234
1235         return &qp->ibqp;
1236 }
1237
1238 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1239                                 struct ib_qp_init_attr *init_attr,
1240                                 struct ib_udata *udata) {
1241         struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1242         struct ib_qp *ibqp;
1243         struct mlx4_ib_dev *dev = to_mdev(device);
1244
1245         ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1246
1247         if (!IS_ERR(ibqp) &&
1248             (init_attr->qp_type == IB_QPT_GSI) &&
1249             !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1250                 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1251                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1252
1253                 if (is_eth &&
1254                     dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1255                         init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1256                         sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1257
1258                         if (IS_ERR(sqp->roce_v2_gsi)) {
1259                                 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1260                                 sqp->roce_v2_gsi = NULL;
1261                         } else {
1262                                 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1263                                 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1264                         }
1265
1266                         init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1267                 }
1268         }
1269         return ibqp;
1270 }
1271
1272 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1273 {
1274         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1275         struct mlx4_ib_qp *mqp = to_mqp(qp);
1276         struct mlx4_ib_pd *pd;
1277
1278         if (is_qp0(dev, mqp))
1279                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1280
1281         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1282             dev->qp1_proxy[mqp->port - 1] == mqp) {
1283                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1284                 dev->qp1_proxy[mqp->port - 1] = NULL;
1285                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1286         }
1287
1288         if (mqp->counter_index)
1289                 mlx4_ib_free_qp_counter(dev, mqp);
1290
1291         pd = get_pd(mqp);
1292         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1293
1294         if (is_sqp(dev, mqp))
1295                 kfree(to_msqp(mqp));
1296         else
1297                 kfree(mqp);
1298
1299         return 0;
1300 }
1301
1302 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1303 {
1304         struct mlx4_ib_qp *mqp = to_mqp(qp);
1305
1306         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1307                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1308
1309                 if (sqp->roce_v2_gsi)
1310                         ib_destroy_qp(sqp->roce_v2_gsi);
1311         }
1312
1313         return _mlx4_ib_destroy_qp(qp);
1314 }
1315
1316 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1317 {
1318         switch (type) {
1319         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1320         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1321         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1322         case MLX4_IB_QPT_XRC_INI:
1323         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1324         case MLX4_IB_QPT_SMI:
1325         case MLX4_IB_QPT_GSI:
1326         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1327
1328         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1329         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1330                                                 MLX4_QP_ST_MLX : -1);
1331         case MLX4_IB_QPT_PROXY_SMI:
1332         case MLX4_IB_QPT_TUN_SMI:
1333         case MLX4_IB_QPT_PROXY_GSI:
1334         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1335                                                 MLX4_QP_ST_UD : -1);
1336         default:                        return -1;
1337         }
1338 }
1339
1340 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1341                                    int attr_mask)
1342 {
1343         u8 dest_rd_atomic;
1344         u32 access_flags;
1345         u32 hw_access_flags = 0;
1346
1347         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1348                 dest_rd_atomic = attr->max_dest_rd_atomic;
1349         else
1350                 dest_rd_atomic = qp->resp_depth;
1351
1352         if (attr_mask & IB_QP_ACCESS_FLAGS)
1353                 access_flags = attr->qp_access_flags;
1354         else
1355                 access_flags = qp->atomic_rd_en;
1356
1357         if (!dest_rd_atomic)
1358                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1359
1360         if (access_flags & IB_ACCESS_REMOTE_READ)
1361                 hw_access_flags |= MLX4_QP_BIT_RRE;
1362         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1363                 hw_access_flags |= MLX4_QP_BIT_RAE;
1364         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1365                 hw_access_flags |= MLX4_QP_BIT_RWE;
1366
1367         return cpu_to_be32(hw_access_flags);
1368 }
1369
1370 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1371                             int attr_mask)
1372 {
1373         if (attr_mask & IB_QP_PKEY_INDEX)
1374                 sqp->pkey_index = attr->pkey_index;
1375         if (attr_mask & IB_QP_QKEY)
1376                 sqp->qkey = attr->qkey;
1377         if (attr_mask & IB_QP_SQ_PSN)
1378                 sqp->send_psn = attr->sq_psn;
1379 }
1380
1381 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1382 {
1383         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1384 }
1385
1386 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1387                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1388                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1389 {
1390         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1391                 IB_LINK_LAYER_ETHERNET;
1392         int vidx;
1393         int smac_index;
1394         int err;
1395
1396
1397         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1398         path->rlid          = cpu_to_be16(ah->dlid);
1399         if (ah->static_rate) {
1400                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1401                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1402                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1403                         --path->static_rate;
1404         } else
1405                 path->static_rate = 0;
1406
1407         if (ah->ah_flags & IB_AH_GRH) {
1408                 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1409                                                                       port,
1410                                                                       ah->grh.sgid_index);
1411
1412                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1413                         pr_err("sgid_index (%u) too large. max is %d\n",
1414                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1415                         return -1;
1416                 }
1417
1418                 path->grh_mylmc |= 1 << 7;
1419                 path->mgid_index = real_sgid_index;
1420                 path->hop_limit  = ah->grh.hop_limit;
1421                 path->tclass_flowlabel =
1422                         cpu_to_be32((ah->grh.traffic_class << 20) |
1423                                     (ah->grh.flow_label));
1424                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1425         }
1426
1427         if (is_eth) {
1428                 if (!(ah->ah_flags & IB_AH_GRH))
1429                         return -1;
1430
1431                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1432                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1433
1434                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1435                 if (vlan_tag < 0x1000) {
1436                         if (smac_info->vid < 0x1000) {
1437                                 /* both valid vlan ids */
1438                                 if (smac_info->vid != vlan_tag) {
1439                                         /* different VIDs.  unreg old and reg new */
1440                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1441                                         if (err)
1442                                                 return err;
1443                                         smac_info->candidate_vid = vlan_tag;
1444                                         smac_info->candidate_vlan_index = vidx;
1445                                         smac_info->candidate_vlan_port = port;
1446                                         smac_info->update_vid = 1;
1447                                         path->vlan_index = vidx;
1448                                 } else {
1449                                         path->vlan_index = smac_info->vlan_index;
1450                                 }
1451                         } else {
1452                                 /* no current vlan tag in qp */
1453                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1454                                 if (err)
1455                                         return err;
1456                                 smac_info->candidate_vid = vlan_tag;
1457                                 smac_info->candidate_vlan_index = vidx;
1458                                 smac_info->candidate_vlan_port = port;
1459                                 smac_info->update_vid = 1;
1460                                 path->vlan_index = vidx;
1461                         }
1462                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1463                         path->fl = 1 << 6;
1464                 } else {
1465                         /* have current vlan tag. unregister it at modify-qp success */
1466                         if (smac_info->vid < 0x1000) {
1467                                 smac_info->candidate_vid = 0xFFFF;
1468                                 smac_info->update_vid = 1;
1469                         }
1470                 }
1471
1472                 /* get smac_index for RoCE use.
1473                  * If no smac was yet assigned, register one.
1474                  * If one was already assigned, but the new mac differs,
1475                  * unregister the old one and register the new one.
1476                 */
1477                 if ((!smac_info->smac && !smac_info->smac_port) ||
1478                     smac_info->smac != smac) {
1479                         /* register candidate now, unreg if needed, after success */
1480                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1481                         if (smac_index >= 0) {
1482                                 smac_info->candidate_smac_index = smac_index;
1483                                 smac_info->candidate_smac = smac;
1484                                 smac_info->candidate_smac_port = port;
1485                         } else {
1486                                 return -EINVAL;
1487                         }
1488                 } else {
1489                         smac_index = smac_info->smac_index;
1490                 }
1491
1492                 memcpy(path->dmac, ah->dmac, 6);
1493                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1494                 /* put MAC table smac index for IBoE */
1495                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1496         } else {
1497                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1498                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1499         }
1500
1501         return 0;
1502 }
1503
1504 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1505                          enum ib_qp_attr_mask qp_attr_mask,
1506                          struct mlx4_ib_qp *mqp,
1507                          struct mlx4_qp_path *path, u8 port,
1508                          u16 vlan_id, u8 *smac)
1509 {
1510         return _mlx4_set_path(dev, &qp->ah_attr,
1511                               mlx4_mac_to_u64(smac),
1512                               vlan_id,
1513                               path, &mqp->pri, port);
1514 }
1515
1516 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1517                              const struct ib_qp_attr *qp,
1518                              enum ib_qp_attr_mask qp_attr_mask,
1519                              struct mlx4_ib_qp *mqp,
1520                              struct mlx4_qp_path *path, u8 port)
1521 {
1522         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1523                               0,
1524                               0xffff,
1525                               path, &mqp->alt, port);
1526 }
1527
1528 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1529 {
1530         struct mlx4_ib_gid_entry *ge, *tmp;
1531
1532         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1533                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1534                         ge->added = 1;
1535                         ge->port = qp->port;
1536                 }
1537         }
1538 }
1539
1540 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1541                                     struct mlx4_ib_qp *qp,
1542                                     struct mlx4_qp_context *context)
1543 {
1544         u64 u64_mac;
1545         int smac_index;
1546
1547         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1548
1549         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1550         if (!qp->pri.smac && !qp->pri.smac_port) {
1551                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1552                 if (smac_index >= 0) {
1553                         qp->pri.candidate_smac_index = smac_index;
1554                         qp->pri.candidate_smac = u64_mac;
1555                         qp->pri.candidate_smac_port = qp->port;
1556                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1557                 } else {
1558                         return -ENOENT;
1559                 }
1560         }
1561         return 0;
1562 }
1563
1564 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1565 {
1566         struct counter_index *new_counter_index;
1567         int err;
1568         u32 tmp_idx;
1569
1570         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1571             IB_LINK_LAYER_ETHERNET ||
1572             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1573             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1574                 return 0;
1575
1576         err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1577         if (err)
1578                 return err;
1579
1580         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1581         if (!new_counter_index) {
1582                 mlx4_counter_free(dev->dev, tmp_idx);
1583                 return -ENOMEM;
1584         }
1585
1586         new_counter_index->index = tmp_idx;
1587         new_counter_index->allocated = 1;
1588         qp->counter_index = new_counter_index;
1589
1590         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1591         list_add_tail(&new_counter_index->list,
1592                       &dev->counters_table[qp->port - 1].counters_list);
1593         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1594
1595         return 0;
1596 }
1597
1598 enum {
1599         MLX4_QPC_ROCE_MODE_1 = 0,
1600         MLX4_QPC_ROCE_MODE_2 = 2,
1601         MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1602 };
1603
1604 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1605 {
1606         switch (gid_type) {
1607         case IB_GID_TYPE_ROCE:
1608                 return MLX4_QPC_ROCE_MODE_1;
1609         case IB_GID_TYPE_ROCE_UDP_ENCAP:
1610                 return MLX4_QPC_ROCE_MODE_2;
1611         default:
1612                 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1613         }
1614 }
1615
1616 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1617                                const struct ib_qp_attr *attr, int attr_mask,
1618                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1619 {
1620         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1621         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1622         struct mlx4_ib_pd *pd;
1623         struct mlx4_ib_cq *send_cq, *recv_cq;
1624         struct mlx4_qp_context *context;
1625         enum mlx4_qp_optpar optpar = 0;
1626         int sqd_event;
1627         int steer_qp = 0;
1628         int err = -EINVAL;
1629         int counter_index;
1630
1631         /* APM is not supported under RoCE */
1632         if (attr_mask & IB_QP_ALT_PATH &&
1633             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1634             IB_LINK_LAYER_ETHERNET)
1635                 return -ENOTSUPP;
1636
1637         context = kzalloc(sizeof *context, GFP_KERNEL);
1638         if (!context)
1639                 return -ENOMEM;
1640
1641         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1642                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1643
1644         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1645                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1646         else {
1647                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1648                 switch (attr->path_mig_state) {
1649                 case IB_MIG_MIGRATED:
1650                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1651                         break;
1652                 case IB_MIG_REARM:
1653                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1654                         break;
1655                 case IB_MIG_ARMED:
1656                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1657                         break;
1658                 }
1659         }
1660
1661         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1662                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1663         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1664                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1665         else if (ibqp->qp_type == IB_QPT_UD) {
1666                 if (qp->flags & MLX4_IB_QP_LSO)
1667                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1668                                               ilog2(dev->dev->caps.max_gso_sz);
1669                 else
1670                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1671         } else if (attr_mask & IB_QP_PATH_MTU) {
1672                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1673                         pr_err("path MTU (%u) is invalid\n",
1674                                attr->path_mtu);
1675                         goto out;
1676                 }
1677                 context->mtu_msgmax = (attr->path_mtu << 5) |
1678                         ilog2(dev->dev->caps.max_msg_sz);
1679         }
1680
1681         if (qp->rq.wqe_cnt)
1682                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1683         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1684
1685         if (qp->sq.wqe_cnt)
1686                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1687         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1688
1689         if (new_state == IB_QPS_RESET && qp->counter_index)
1690                 mlx4_ib_free_qp_counter(dev, qp);
1691
1692         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1693                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1694                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1695                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1696                         context->param3 |= cpu_to_be32(1 << 30);
1697         }
1698
1699         if (qp->ibqp.uobject)
1700                 context->usr_page = cpu_to_be32(
1701                         mlx4_to_hw_uar_index(dev->dev,
1702                                              to_mucontext(ibqp->uobject->context)->uar.index));
1703         else
1704                 context->usr_page = cpu_to_be32(
1705                         mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
1706
1707         if (attr_mask & IB_QP_DEST_QPN)
1708                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1709
1710         if (attr_mask & IB_QP_PORT) {
1711                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1712                     !(attr_mask & IB_QP_AV)) {
1713                         mlx4_set_sched(&context->pri_path, attr->port_num);
1714                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1715                 }
1716         }
1717
1718         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1719                 err = create_qp_lb_counter(dev, qp);
1720                 if (err)
1721                         goto out;
1722
1723                 counter_index =
1724                         dev->counters_table[qp->port - 1].default_counter;
1725                 if (qp->counter_index)
1726                         counter_index = qp->counter_index->index;
1727
1728                 if (counter_index != -1) {
1729                         context->pri_path.counter_index = counter_index;
1730                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1731                         if (qp->counter_index) {
1732                                 context->pri_path.fl |=
1733                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
1734                                 context->pri_path.vlan_control |=
1735                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1736                         }
1737                 } else
1738                         context->pri_path.counter_index =
1739                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
1740
1741                 if (qp->flags & MLX4_IB_QP_NETIF) {
1742                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1743                         steer_qp = 1;
1744                 }
1745
1746                 if (ibqp->qp_type == IB_QPT_GSI) {
1747                         enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
1748                                 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
1749                         u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
1750
1751                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1752                 }
1753         }
1754
1755         if (attr_mask & IB_QP_PKEY_INDEX) {
1756                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1757                         context->pri_path.disable_pkey_check = 0x40;
1758                 context->pri_path.pkey_index = attr->pkey_index;
1759                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1760         }
1761
1762         if (attr_mask & IB_QP_AV) {
1763                 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1764                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1765                 union ib_gid gid;
1766                 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
1767                 u16 vlan = 0xffff;
1768                 u8 smac[ETH_ALEN];
1769                 int status = 0;
1770                 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1771                         attr->ah_attr.ah_flags & IB_AH_GRH;
1772
1773                 if (is_eth && attr->ah_attr.ah_flags & IB_AH_GRH) {
1774                         int index = attr->ah_attr.grh.sgid_index;
1775
1776                         status = ib_get_cached_gid(ibqp->device, port_num,
1777                                                    index, &gid, &gid_attr);
1778                         if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1779                                 status = -ENOENT;
1780                         if (!status && gid_attr.ndev) {
1781                                 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1782                                 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1783                                 dev_put(gid_attr.ndev);
1784                         }
1785                 }
1786                 if (status)
1787                         goto out;
1788
1789                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1790                                   port_num, vlan, smac))
1791                         goto out;
1792
1793                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1794                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1795
1796                 if (is_eth &&
1797                     (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1798                         u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1799
1800                         if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1801                                 err = -EINVAL;
1802                                 goto out;
1803                         }
1804                         context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1805                 }
1806
1807         }
1808
1809         if (attr_mask & IB_QP_TIMEOUT) {
1810                 context->pri_path.ackto |= attr->timeout << 3;
1811                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1812         }
1813
1814         if (attr_mask & IB_QP_ALT_PATH) {
1815                 if (attr->alt_port_num == 0 ||
1816                     attr->alt_port_num > dev->dev->caps.num_ports)
1817                         goto out;
1818
1819                 if (attr->alt_pkey_index >=
1820                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1821                         goto out;
1822
1823                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1824                                       &context->alt_path,
1825                                       attr->alt_port_num))
1826                         goto out;
1827
1828                 context->alt_path.pkey_index = attr->alt_pkey_index;
1829                 context->alt_path.ackto = attr->alt_timeout << 3;
1830                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1831         }
1832
1833         pd = get_pd(qp);
1834         get_cqs(qp, &send_cq, &recv_cq);
1835         context->pd       = cpu_to_be32(pd->pdn);
1836         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1837         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1838         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1839
1840         /* Set "fast registration enabled" for all kernel QPs */
1841         if (!qp->ibqp.uobject)
1842                 context->params1 |= cpu_to_be32(1 << 11);
1843
1844         if (attr_mask & IB_QP_RNR_RETRY) {
1845                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1846                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1847         }
1848
1849         if (attr_mask & IB_QP_RETRY_CNT) {
1850                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1851                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1852         }
1853
1854         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1855                 if (attr->max_rd_atomic)
1856                         context->params1 |=
1857                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1858                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1859         }
1860
1861         if (attr_mask & IB_QP_SQ_PSN)
1862                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1863
1864         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1865                 if (attr->max_dest_rd_atomic)
1866                         context->params2 |=
1867                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1868                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1869         }
1870
1871         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1872                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1873                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1874         }
1875
1876         if (ibqp->srq)
1877                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1878
1879         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1880                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1881                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1882         }
1883         if (attr_mask & IB_QP_RQ_PSN)
1884                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1885
1886         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1887         if (attr_mask & IB_QP_QKEY) {
1888                 if (qp->mlx4_ib_qp_type &
1889                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1890                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1891                 else {
1892                         if (mlx4_is_mfunc(dev->dev) &&
1893                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1894                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1895                             MLX4_RESERVED_QKEY_BASE) {
1896                                 pr_err("Cannot use reserved QKEY"
1897                                        " 0x%x (range 0xffff0000..0xffffffff"
1898                                        " is reserved)\n", attr->qkey);
1899                                 err = -EINVAL;
1900                                 goto out;
1901                         }
1902                         context->qkey = cpu_to_be32(attr->qkey);
1903                 }
1904                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1905         }
1906
1907         if (ibqp->srq)
1908                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1909
1910         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1911                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1912
1913         if (cur_state == IB_QPS_INIT &&
1914             new_state == IB_QPS_RTR  &&
1915             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1916              ibqp->qp_type == IB_QPT_UD ||
1917              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1918                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1919                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1920                     qp->mlx4_ib_qp_type &
1921                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1922                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1923                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1924                                 context->pri_path.fl = 0x80;
1925                 } else {
1926                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1927                                 context->pri_path.fl = 0x80;
1928                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1929                 }
1930                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1931                     IB_LINK_LAYER_ETHERNET) {
1932                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1933                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1934                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1935                         /* handle smac_index */
1936                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1937                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1938                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1939                                 err = handle_eth_ud_smac_index(dev, qp, context);
1940                                 if (err) {
1941                                         err = -EINVAL;
1942                                         goto out;
1943                                 }
1944                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1945                                         dev->qp1_proxy[qp->port - 1] = qp;
1946                         }
1947                 }
1948         }
1949
1950         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1951                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1952                                         MLX4_IB_LINK_TYPE_ETH;
1953                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1954                         /* set QP to receive both tunneled & non-tunneled packets */
1955                         if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1956                                 context->srqn = cpu_to_be32(7 << 28);
1957                 }
1958         }
1959
1960         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1961                 int is_eth = rdma_port_get_link_layer(
1962                                 &dev->ib_dev, qp->port) ==
1963                                 IB_LINK_LAYER_ETHERNET;
1964                 if (is_eth) {
1965                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1966                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1967                 }
1968         }
1969
1970
1971         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1972             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1973                 sqd_event = 1;
1974         else
1975                 sqd_event = 0;
1976
1977         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1978                 context->rlkey_roce_mode |= (1 << 4);
1979
1980         /*
1981          * Before passing a kernel QP to the HW, make sure that the
1982          * ownership bits of the send queue are set and the SQ
1983          * headroom is stamped so that the hardware doesn't start
1984          * processing stale work requests.
1985          */
1986         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1987                 struct mlx4_wqe_ctrl_seg *ctrl;
1988                 int i;
1989
1990                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1991                         ctrl = get_send_wqe(qp, i);
1992                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1993                         if (qp->sq_max_wqes_per_wr == 1)
1994                                 ctrl->qpn_vlan.fence_size =
1995                                                 1 << (qp->sq.wqe_shift - 4);
1996
1997                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1998                 }
1999         }
2000
2001         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2002                              to_mlx4_state(new_state), context, optpar,
2003                              sqd_event, &qp->mqp);
2004         if (err)
2005                 goto out;
2006
2007         qp->state = new_state;
2008
2009         if (attr_mask & IB_QP_ACCESS_FLAGS)
2010                 qp->atomic_rd_en = attr->qp_access_flags;
2011         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2012                 qp->resp_depth = attr->max_dest_rd_atomic;
2013         if (attr_mask & IB_QP_PORT) {
2014                 qp->port = attr->port_num;
2015                 update_mcg_macs(dev, qp);
2016         }
2017         if (attr_mask & IB_QP_ALT_PATH)
2018                 qp->alt_port = attr->alt_port_num;
2019
2020         if (is_sqp(dev, qp))
2021                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2022
2023         /*
2024          * If we moved QP0 to RTR, bring the IB link up; if we moved
2025          * QP0 to RESET or ERROR, bring the link back down.
2026          */
2027         if (is_qp0(dev, qp)) {
2028                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2029                         if (mlx4_INIT_PORT(dev->dev, qp->port))
2030                                 pr_warn("INIT_PORT failed for port %d\n",
2031                                        qp->port);
2032
2033                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2034                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2035                         mlx4_CLOSE_PORT(dev->dev, qp->port);
2036         }
2037
2038         /*
2039          * If we moved a kernel QP to RESET, clean up all old CQ
2040          * entries and reinitialize the QP.
2041          */
2042         if (new_state == IB_QPS_RESET) {
2043                 if (!ibqp->uobject) {
2044                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2045                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2046                         if (send_cq != recv_cq)
2047                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2048
2049                         qp->rq.head = 0;
2050                         qp->rq.tail = 0;
2051                         qp->sq.head = 0;
2052                         qp->sq.tail = 0;
2053                         qp->sq_next_wqe = 0;
2054                         if (qp->rq.wqe_cnt)
2055                                 *qp->db.db  = 0;
2056
2057                         if (qp->flags & MLX4_IB_QP_NETIF)
2058                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2059                 }
2060                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2061                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2062                         qp->pri.smac = 0;
2063                         qp->pri.smac_port = 0;
2064                 }
2065                 if (qp->alt.smac) {
2066                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2067                         qp->alt.smac = 0;
2068                 }
2069                 if (qp->pri.vid < 0x1000) {
2070                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2071                         qp->pri.vid = 0xFFFF;
2072                         qp->pri.candidate_vid = 0xFFFF;
2073                         qp->pri.update_vid = 0;
2074                 }
2075
2076                 if (qp->alt.vid < 0x1000) {
2077                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2078                         qp->alt.vid = 0xFFFF;
2079                         qp->alt.candidate_vid = 0xFFFF;
2080                         qp->alt.update_vid = 0;
2081                 }
2082         }
2083 out:
2084         if (err && qp->counter_index)
2085                 mlx4_ib_free_qp_counter(dev, qp);
2086         if (err && steer_qp)
2087                 mlx4_ib_steer_qp_reg(dev, qp, 0);
2088         kfree(context);
2089         if (qp->pri.candidate_smac ||
2090             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2091                 if (err) {
2092                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2093                 } else {
2094                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2095                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2096                         qp->pri.smac = qp->pri.candidate_smac;
2097                         qp->pri.smac_index = qp->pri.candidate_smac_index;
2098                         qp->pri.smac_port = qp->pri.candidate_smac_port;
2099                 }
2100                 qp->pri.candidate_smac = 0;
2101                 qp->pri.candidate_smac_index = 0;
2102                 qp->pri.candidate_smac_port = 0;
2103         }
2104         if (qp->alt.candidate_smac) {
2105                 if (err) {
2106                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2107                 } else {
2108                         if (qp->alt.smac)
2109                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2110                         qp->alt.smac = qp->alt.candidate_smac;
2111                         qp->alt.smac_index = qp->alt.candidate_smac_index;
2112                         qp->alt.smac_port = qp->alt.candidate_smac_port;
2113                 }
2114                 qp->alt.candidate_smac = 0;
2115                 qp->alt.candidate_smac_index = 0;
2116                 qp->alt.candidate_smac_port = 0;
2117         }
2118
2119         if (qp->pri.update_vid) {
2120                 if (err) {
2121                         if (qp->pri.candidate_vid < 0x1000)
2122                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2123                                                      qp->pri.candidate_vid);
2124                 } else {
2125                         if (qp->pri.vid < 0x1000)
2126                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2127                                                      qp->pri.vid);
2128                         qp->pri.vid = qp->pri.candidate_vid;
2129                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2130                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
2131                 }
2132                 qp->pri.candidate_vid = 0xFFFF;
2133                 qp->pri.update_vid = 0;
2134         }
2135
2136         if (qp->alt.update_vid) {
2137                 if (err) {
2138                         if (qp->alt.candidate_vid < 0x1000)
2139                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2140                                                      qp->alt.candidate_vid);
2141                 } else {
2142                         if (qp->alt.vid < 0x1000)
2143                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2144                                                      qp->alt.vid);
2145                         qp->alt.vid = qp->alt.candidate_vid;
2146                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2147                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2148                 }
2149                 qp->alt.candidate_vid = 0xFFFF;
2150                 qp->alt.update_vid = 0;
2151         }
2152
2153         return err;
2154 }
2155
2156 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2157                               int attr_mask, struct ib_udata *udata)
2158 {
2159         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2160         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2161         enum ib_qp_state cur_state, new_state;
2162         int err = -EINVAL;
2163         int ll;
2164         mutex_lock(&qp->mutex);
2165
2166         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2167         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2168
2169         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2170                 ll = IB_LINK_LAYER_UNSPECIFIED;
2171         } else {
2172                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2173                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2174         }
2175
2176         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2177                                 attr_mask, ll)) {
2178                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2179                          "for transition %d to %d. qp_type %d,"
2180                          " attr_mask 0x%x\n",
2181                          ibqp->qp_num, cur_state, new_state,
2182                          ibqp->qp_type, attr_mask);
2183                 goto out;
2184         }
2185
2186         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2187                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2188                         if ((ibqp->qp_type == IB_QPT_RC) ||
2189                             (ibqp->qp_type == IB_QPT_UD) ||
2190                             (ibqp->qp_type == IB_QPT_UC) ||
2191                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2192                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2193                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2194                         }
2195                 } else {
2196                         /* no sense in changing port_num
2197                          * when ports are bonded */
2198                         attr_mask &= ~IB_QP_PORT;
2199                 }
2200         }
2201
2202         if ((attr_mask & IB_QP_PORT) &&
2203             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2204                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2205                          "for transition %d to %d. qp_type %d\n",
2206                          ibqp->qp_num, attr->port_num, cur_state,
2207                          new_state, ibqp->qp_type);
2208                 goto out;
2209         }
2210
2211         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2212             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2213              IB_LINK_LAYER_ETHERNET))
2214                 goto out;
2215
2216         if (attr_mask & IB_QP_PKEY_INDEX) {
2217                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2218                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2219                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2220                                  "for transition %d to %d. qp_type %d\n",
2221                                  ibqp->qp_num, attr->pkey_index, cur_state,
2222                                  new_state, ibqp->qp_type);
2223                         goto out;
2224                 }
2225         }
2226
2227         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2228             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2229                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2230                          "Transition %d to %d. qp_type %d\n",
2231                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2232                          new_state, ibqp->qp_type);
2233                 goto out;
2234         }
2235
2236         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2237             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2238                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2239                          "Transition %d to %d. qp_type %d\n",
2240                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2241                          new_state, ibqp->qp_type);
2242                 goto out;
2243         }
2244
2245         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2246                 err = 0;
2247                 goto out;
2248         }
2249
2250         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2251
2252         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2253                 attr->port_num = 1;
2254
2255 out:
2256         mutex_unlock(&qp->mutex);
2257         return err;
2258 }
2259
2260 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2261                       int attr_mask, struct ib_udata *udata)
2262 {
2263         struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2264         int ret;
2265
2266         ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2267
2268         if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2269                 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2270                 int err = 0;
2271
2272                 if (sqp->roce_v2_gsi)
2273                         err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2274                 if (err)
2275                         pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2276                                err);
2277         }
2278         return ret;
2279 }
2280
2281 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2282 {
2283         int i;
2284         for (i = 0; i < dev->caps.num_ports; i++) {
2285                 if (qpn == dev->caps.qp0_proxy[i] ||
2286                     qpn == dev->caps.qp0_tunnel[i]) {
2287                         *qkey = dev->caps.qp0_qkey[i];
2288                         return 0;
2289                 }
2290         }
2291         return -EINVAL;
2292 }
2293
2294 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2295                                   struct ib_ud_wr *wr,
2296                                   void *wqe, unsigned *mlx_seg_len)
2297 {
2298         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2299         struct ib_device *ib_dev = &mdev->ib_dev;
2300         struct mlx4_wqe_mlx_seg *mlx = wqe;
2301         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2302         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2303         u16 pkey;
2304         u32 qkey;
2305         int send_size;
2306         int header_size;
2307         int spc;
2308         int i;
2309
2310         if (wr->wr.opcode != IB_WR_SEND)
2311                 return -EINVAL;
2312
2313         send_size = 0;
2314
2315         for (i = 0; i < wr->wr.num_sge; ++i)
2316                 send_size += wr->wr.sg_list[i].length;
2317
2318         /* for proxy-qp0 sends, need to add in size of tunnel header */
2319         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2320         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2321                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2322
2323         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2324
2325         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2326                 sqp->ud_header.lrh.service_level =
2327                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2328                 sqp->ud_header.lrh.destination_lid =
2329                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2330                 sqp->ud_header.lrh.source_lid =
2331                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2332         }
2333
2334         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2335
2336         /* force loopback */
2337         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2338         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2339
2340         sqp->ud_header.lrh.virtual_lane    = 0;
2341         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2342         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2343         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2344         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2345                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2346         else
2347                 sqp->ud_header.bth.destination_qpn =
2348                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2349
2350         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2351         if (mlx4_is_master(mdev->dev)) {
2352                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2353                         return -EINVAL;
2354         } else {
2355                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2356                         return -EINVAL;
2357         }
2358         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2359         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2360
2361         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2362         sqp->ud_header.immediate_present = 0;
2363
2364         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2365
2366         /*
2367          * Inline data segments may not cross a 64 byte boundary.  If
2368          * our UD header is bigger than the space available up to the
2369          * next 64 byte boundary in the WQE, use two inline data
2370          * segments to hold the UD header.
2371          */
2372         spc = MLX4_INLINE_ALIGN -
2373               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2374         if (header_size <= spc) {
2375                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2376                 memcpy(inl + 1, sqp->header_buf, header_size);
2377                 i = 1;
2378         } else {
2379                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2380                 memcpy(inl + 1, sqp->header_buf, spc);
2381
2382                 inl = (void *) (inl + 1) + spc;
2383                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2384                 /*
2385                  * Need a barrier here to make sure all the data is
2386                  * visible before the byte_count field is set.
2387                  * Otherwise the HCA prefetcher could grab the 64-byte
2388                  * chunk with this inline segment and get a valid (!=
2389                  * 0xffffffff) byte count but stale data, and end up
2390                  * generating a packet with bad headers.
2391                  *
2392                  * The first inline segment's byte_count field doesn't
2393                  * need a barrier, because it comes after a
2394                  * control/MLX segment and therefore is at an offset
2395                  * of 16 mod 64.
2396                  */
2397                 wmb();
2398                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2399                 i = 2;
2400         }
2401
2402         *mlx_seg_len =
2403         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2404         return 0;
2405 }
2406
2407 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2408 {
2409         union sl2vl_tbl_to_u64 tmp_vltab;
2410         u8 vl;
2411
2412         if (sl > 15)
2413                 return 0xf;
2414         tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2415         vl = tmp_vltab.sl8[sl >> 1];
2416         if (sl & 1)
2417                 vl &= 0x0f;
2418         else
2419                 vl >>= 4;
2420         return vl;
2421 }
2422
2423 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2424                                 int index, union ib_gid *gid,
2425                                 enum ib_gid_type *gid_type)
2426 {
2427         struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2428         struct mlx4_port_gid_table *port_gid_table;
2429         unsigned long flags;
2430
2431         port_gid_table = &iboe->gids[port_num - 1];
2432         spin_lock_irqsave(&iboe->lock, flags);
2433         memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2434         *gid_type = port_gid_table->gids[index].gid_type;
2435         spin_unlock_irqrestore(&iboe->lock, flags);
2436         if (!memcmp(gid, &zgid, sizeof(*gid)))
2437                 return -ENOENT;
2438
2439         return 0;
2440 }
2441
2442 #define MLX4_ROCEV2_QP1_SPORT 0xC000
2443 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2444                             void *wqe, unsigned *mlx_seg_len)
2445 {
2446         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2447         struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
2448         struct mlx4_wqe_mlx_seg *mlx = wqe;
2449         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2450         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2451         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2452         union ib_gid sgid;
2453         u16 pkey;
2454         int send_size;
2455         int header_size;
2456         int spc;
2457         int i;
2458         int err = 0;
2459         u16 vlan = 0xffff;
2460         bool is_eth;
2461         bool is_vlan = false;
2462         bool is_grh;
2463         bool is_udp = false;
2464         int ip_version = 0;
2465
2466         send_size = 0;
2467         for (i = 0; i < wr->wr.num_sge; ++i)
2468                 send_size += wr->wr.sg_list[i].length;
2469
2470         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2471         is_grh = mlx4_ib_ah_grh_present(ah);
2472         if (is_eth) {
2473                 enum ib_gid_type gid_type;
2474                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2475                         /* When multi-function is enabled, the ib_core gid
2476                          * indexes don't necessarily match the hw ones, so
2477                          * we must use our own cache */
2478                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2479                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2480                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2481                         if (err)
2482                                 return err;
2483                 } else  {
2484                         err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
2485                                             ah->av.ib.gid_index,
2486                                             &sgid, &gid_type);
2487                         if (!err) {
2488                                 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2489                                 if (is_udp) {
2490                                         if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2491                                                 ip_version = 4;
2492                                         else
2493                                                 ip_version = 6;
2494                                         is_grh = false;
2495                                 }
2496                         } else {
2497                                 return err;
2498                         }
2499                 }
2500                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2501                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2502                         is_vlan = 1;
2503                 }
2504         }
2505         err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
2506                           ip_version, is_udp, 0, &sqp->ud_header);
2507         if (err)
2508                 return err;
2509
2510         if (!is_eth) {
2511                 sqp->ud_header.lrh.service_level =
2512                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2513                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2514                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2515         }
2516
2517         if (is_grh || (ip_version == 6)) {
2518                 sqp->ud_header.grh.traffic_class =
2519                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2520                 sqp->ud_header.grh.flow_label    =
2521                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2522                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2523                 if (is_eth) {
2524                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2525                 } else {
2526                         if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2527                                 /* When multi-function is enabled, the ib_core gid
2528                                  * indexes don't necessarily match the hw ones, so
2529                                  * we must use our own cache
2530                                  */
2531                                 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2532                                         cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
2533                                                                     demux[sqp->qp.port - 1].
2534                                                                     subnet_prefix)));
2535                                 sqp->ud_header.grh.source_gid.global.interface_id =
2536                                         to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2537                                                        guid_cache[ah->av.ib.gid_index];
2538                         } else {
2539                                 ib_get_cached_gid(ib_dev,
2540                                                   be32_to_cpu(ah->av.ib.port_pd) >> 24,
2541                                                   ah->av.ib.gid_index,
2542                                                   &sqp->ud_header.grh.source_gid, NULL);
2543                         }
2544                 }
2545                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2546                        ah->av.ib.dgid, 16);
2547         }
2548
2549         if (ip_version == 4) {
2550                 sqp->ud_header.ip4.tos =
2551                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2552                 sqp->ud_header.ip4.id = 0;
2553                 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2554                 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2555
2556                 memcpy(&sqp->ud_header.ip4.saddr,
2557                        sgid.raw + 12, 4);
2558                 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2559                 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2560         }
2561
2562         if (is_udp) {
2563                 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2564                 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2565                 sqp->ud_header.udp.csum = 0;
2566         }
2567
2568         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2569
2570         if (!is_eth) {
2571                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2572                                           (sqp->ud_header.lrh.destination_lid ==
2573                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2574                                           (sqp->ud_header.lrh.service_level << 8));
2575                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2576                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2577                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2578         }
2579
2580         switch (wr->wr.opcode) {
2581         case IB_WR_SEND:
2582                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2583                 sqp->ud_header.immediate_present = 0;
2584                 break;
2585         case IB_WR_SEND_WITH_IMM:
2586                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2587                 sqp->ud_header.immediate_present = 1;
2588                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
2589                 break;
2590         default:
2591                 return -EINVAL;
2592         }
2593
2594         if (is_eth) {
2595                 struct in6_addr in6;
2596                 u16 ether_type;
2597                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2598
2599                 ether_type = (!is_udp) ? ETH_P_IBOE:
2600                         (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2601
2602                 mlx->sched_prio = cpu_to_be16(pcp);
2603
2604                 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
2605                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2606                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2607                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2608                 memcpy(&in6, sgid.raw, sizeof(in6));
2609
2610
2611                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2612                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2613                 if (!is_vlan) {
2614                         sqp->ud_header.eth.type = cpu_to_be16(ether_type);
2615                 } else {
2616                         sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
2617                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2618                 }
2619         } else {
2620                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 :
2621                                                         sl_to_vl(to_mdev(ib_dev),
2622                                                                  sqp->ud_header.lrh.service_level,
2623                                                                  sqp->qp.port);
2624                 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
2625                         return -EINVAL;
2626                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2627                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2628         }
2629         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2630         if (!sqp->qp.ibqp.qp_num)
2631                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2632         else
2633                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
2634         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2635         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2636         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2637         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2638                                                sqp->qkey : wr->remote_qkey);
2639         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2640
2641         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2642
2643         if (0) {
2644                 pr_err("built UD header of size %d:\n", header_size);
2645                 for (i = 0; i < header_size / 4; ++i) {
2646                         if (i % 8 == 0)
2647                                 pr_err("  [%02x] ", i * 4);
2648                         pr_cont(" %08x",
2649                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2650                         if ((i + 1) % 8 == 0)
2651                                 pr_cont("\n");
2652                 }
2653                 pr_err("\n");
2654         }
2655
2656         /*
2657          * Inline data segments may not cross a 64 byte boundary.  If
2658          * our UD header is bigger than the space available up to the
2659          * next 64 byte boundary in the WQE, use two inline data
2660          * segments to hold the UD header.
2661          */
2662         spc = MLX4_INLINE_ALIGN -
2663                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2664         if (header_size <= spc) {
2665                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2666                 memcpy(inl + 1, sqp->header_buf, header_size);
2667                 i = 1;
2668         } else {
2669                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2670                 memcpy(inl + 1, sqp->header_buf, spc);
2671
2672                 inl = (void *) (inl + 1) + spc;
2673                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2674                 /*
2675                  * Need a barrier here to make sure all the data is
2676                  * visible before the byte_count field is set.
2677                  * Otherwise the HCA prefetcher could grab the 64-byte
2678                  * chunk with this inline segment and get a valid (!=
2679                  * 0xffffffff) byte count but stale data, and end up
2680                  * generating a packet with bad headers.
2681                  *
2682                  * The first inline segment's byte_count field doesn't
2683                  * need a barrier, because it comes after a
2684                  * control/MLX segment and therefore is at an offset
2685                  * of 16 mod 64.
2686                  */
2687                 wmb();
2688                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2689                 i = 2;
2690         }
2691
2692         *mlx_seg_len =
2693                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2694         return 0;
2695 }
2696
2697 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2698 {
2699         unsigned cur;
2700         struct mlx4_ib_cq *cq;
2701
2702         cur = wq->head - wq->tail;
2703         if (likely(cur + nreq < wq->max_post))
2704                 return 0;
2705
2706         cq = to_mcq(ib_cq);
2707         spin_lock(&cq->lock);
2708         cur = wq->head - wq->tail;
2709         spin_unlock(&cq->lock);
2710
2711         return cur + nreq >= wq->max_post;
2712 }
2713
2714 static __be32 convert_access(int acc)
2715 {
2716         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2717                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2718                (acc & IB_ACCESS_REMOTE_WRITE  ?
2719                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2720                (acc & IB_ACCESS_REMOTE_READ   ?
2721                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2722                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2723                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2724 }
2725
2726 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2727                         struct ib_reg_wr *wr)
2728 {
2729         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2730
2731         fseg->flags             = convert_access(wr->access);
2732         fseg->mem_key           = cpu_to_be32(wr->key);
2733         fseg->buf_list          = cpu_to_be64(mr->page_map);
2734         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
2735         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
2736         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2737         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
2738         fseg->reserved[0]       = 0;
2739         fseg->reserved[1]       = 0;
2740 }
2741
2742 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2743 {
2744         memset(iseg, 0, sizeof(*iseg));
2745         iseg->mem_key = cpu_to_be32(rkey);
2746 }
2747
2748 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2749                                           u64 remote_addr, u32 rkey)
2750 {
2751         rseg->raddr    = cpu_to_be64(remote_addr);
2752         rseg->rkey     = cpu_to_be32(rkey);
2753         rseg->reserved = 0;
2754 }
2755
2756 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2757                 struct ib_atomic_wr *wr)
2758 {
2759         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2760                 aseg->swap_add = cpu_to_be64(wr->swap);
2761                 aseg->compare  = cpu_to_be64(wr->compare_add);
2762         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2763                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2764                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
2765         } else {
2766                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2767                 aseg->compare  = 0;
2768         }
2769
2770 }
2771
2772 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2773                                   struct ib_atomic_wr *wr)
2774 {
2775         aseg->swap_add          = cpu_to_be64(wr->swap);
2776         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
2777         aseg->compare           = cpu_to_be64(wr->compare_add);
2778         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
2779 }
2780
2781 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2782                              struct ib_ud_wr *wr)
2783 {
2784         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2785         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2786         dseg->qkey = cpu_to_be32(wr->remote_qkey);
2787         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2788         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2789 }
2790
2791 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2792                                     struct mlx4_wqe_datagram_seg *dseg,
2793                                     struct ib_ud_wr *wr,
2794                                     enum mlx4_ib_qp_type qpt)
2795 {
2796         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2797         struct mlx4_av sqp_av = {0};
2798         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2799
2800         /* force loopback */
2801         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2802         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2803         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2804                         cpu_to_be32(0xf0000000);
2805
2806         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2807         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2808                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2809         else
2810                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2811         /* Use QKEY from the QP context, which is set by master */
2812         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2813 }
2814
2815 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2816 {
2817         struct mlx4_wqe_inline_seg *inl = wqe;
2818         struct mlx4_ib_tunnel_header hdr;
2819         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2820         int spc;
2821         int i;
2822
2823         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2824         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2825         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2826         hdr.qkey = cpu_to_be32(wr->remote_qkey);
2827         memcpy(hdr.mac, ah->av.eth.mac, 6);
2828         hdr.vlan = ah->av.eth.vlan;
2829
2830         spc = MLX4_INLINE_ALIGN -
2831                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2832         if (sizeof (hdr) <= spc) {
2833                 memcpy(inl + 1, &hdr, sizeof (hdr));
2834                 wmb();
2835                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2836                 i = 1;
2837         } else {
2838                 memcpy(inl + 1, &hdr, spc);
2839                 wmb();
2840                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2841
2842                 inl = (void *) (inl + 1) + spc;
2843                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2844                 wmb();
2845                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2846                 i = 2;
2847         }
2848
2849         *mlx_seg_len =
2850                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2851 }
2852
2853 static void set_mlx_icrc_seg(void *dseg)
2854 {
2855         u32 *t = dseg;
2856         struct mlx4_wqe_inline_seg *iseg = dseg;
2857
2858         t[1] = 0;
2859
2860         /*
2861          * Need a barrier here before writing the byte_count field to
2862          * make sure that all the data is visible before the
2863          * byte_count field is set.  Otherwise, if the segment begins
2864          * a new cacheline, the HCA prefetcher could grab the 64-byte
2865          * chunk and get a valid (!= * 0xffffffff) byte count but
2866          * stale data, and end up sending the wrong data.
2867          */
2868         wmb();
2869
2870         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2871 }
2872
2873 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2874 {
2875         dseg->lkey       = cpu_to_be32(sg->lkey);
2876         dseg->addr       = cpu_to_be64(sg->addr);
2877
2878         /*
2879          * Need a barrier here before writing the byte_count field to
2880          * make sure that all the data is visible before the
2881          * byte_count field is set.  Otherwise, if the segment begins
2882          * a new cacheline, the HCA prefetcher could grab the 64-byte
2883          * chunk and get a valid (!= * 0xffffffff) byte count but
2884          * stale data, and end up sending the wrong data.
2885          */
2886         wmb();
2887
2888         dseg->byte_count = cpu_to_be32(sg->length);
2889 }
2890
2891 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2892 {
2893         dseg->byte_count = cpu_to_be32(sg->length);
2894         dseg->lkey       = cpu_to_be32(sg->lkey);
2895         dseg->addr       = cpu_to_be64(sg->addr);
2896 }
2897
2898 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2899                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2900                          __be32 *lso_hdr_sz, __be32 *blh)
2901 {
2902         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2903
2904         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2905                 *blh = cpu_to_be32(1 << 6);
2906
2907         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2908                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2909                 return -EINVAL;
2910
2911         memcpy(wqe->header, wr->header, wr->hlen);
2912
2913         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
2914         *lso_seg_len = halign;
2915         return 0;
2916 }
2917
2918 static __be32 send_ieth(struct ib_send_wr *wr)
2919 {
2920         switch (wr->opcode) {
2921         case IB_WR_SEND_WITH_IMM:
2922         case IB_WR_RDMA_WRITE_WITH_IMM:
2923                 return wr->ex.imm_data;
2924
2925         case IB_WR_SEND_WITH_INV:
2926                 return cpu_to_be32(wr->ex.invalidate_rkey);
2927
2928         default:
2929                 return 0;
2930         }
2931 }
2932
2933 static void add_zero_len_inline(void *wqe)
2934 {
2935         struct mlx4_wqe_inline_seg *inl = wqe;
2936         memset(wqe, 0, 16);
2937         inl->byte_count = cpu_to_be32(1 << 31);
2938 }
2939
2940 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2941                       struct ib_send_wr **bad_wr)
2942 {
2943         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2944         void *wqe;
2945         struct mlx4_wqe_ctrl_seg *ctrl;
2946         struct mlx4_wqe_data_seg *dseg;
2947         unsigned long flags;
2948         int nreq;
2949         int err = 0;
2950         unsigned ind;
2951         int uninitialized_var(stamp);
2952         int uninitialized_var(size);
2953         unsigned uninitialized_var(seglen);
2954         __be32 dummy;
2955         __be32 *lso_wqe;
2956         __be32 uninitialized_var(lso_hdr_sz);
2957         __be32 blh;
2958         int i;
2959         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2960
2961         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2962                 struct mlx4_ib_sqp *sqp = to_msqp(qp);
2963
2964                 if (sqp->roce_v2_gsi) {
2965                         struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
2966                         enum ib_gid_type gid_type;
2967                         union ib_gid gid;
2968
2969                         if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
2970                                            ah->av.ib.gid_index,
2971                                            &gid, &gid_type))
2972                                 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
2973                                                 to_mqp(sqp->roce_v2_gsi) : qp;
2974                         else
2975                                 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
2976                                        ah->av.ib.gid_index);
2977                 }
2978         }
2979
2980         spin_lock_irqsave(&qp->sq.lock, flags);
2981         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2982                 err = -EIO;
2983                 *bad_wr = wr;
2984                 nreq = 0;
2985                 goto out;
2986         }
2987
2988         ind = qp->sq_next_wqe;
2989
2990         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2991                 lso_wqe = &dummy;
2992                 blh = 0;
2993
2994                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2995                         err = -ENOMEM;
2996                         *bad_wr = wr;
2997                         goto out;
2998                 }
2999
3000                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3001                         err = -EINVAL;
3002                         *bad_wr = wr;
3003                         goto out;
3004                 }
3005
3006                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3007                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3008
3009                 ctrl->srcrb_flags =
3010                         (wr->send_flags & IB_SEND_SIGNALED ?
3011                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3012                         (wr->send_flags & IB_SEND_SOLICITED ?
3013                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3014                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
3015                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3016                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3017                         qp->sq_signal_bits;
3018
3019                 ctrl->imm = send_ieth(wr);
3020
3021                 wqe += sizeof *ctrl;
3022                 size = sizeof *ctrl / 16;
3023
3024                 switch (qp->mlx4_ib_qp_type) {
3025                 case MLX4_IB_QPT_RC:
3026                 case MLX4_IB_QPT_UC:
3027                         switch (wr->opcode) {
3028                         case IB_WR_ATOMIC_CMP_AND_SWP:
3029                         case IB_WR_ATOMIC_FETCH_AND_ADD:
3030                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3031                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3032                                               atomic_wr(wr)->rkey);
3033                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3034
3035                                 set_atomic_seg(wqe, atomic_wr(wr));
3036                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
3037
3038                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3039                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3040
3041                                 break;
3042
3043                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3044                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3045                                               atomic_wr(wr)->rkey);
3046                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3047
3048                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
3049                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
3050
3051                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3052                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3053
3054                                 break;
3055
3056                         case IB_WR_RDMA_READ:
3057                         case IB_WR_RDMA_WRITE:
3058                         case IB_WR_RDMA_WRITE_WITH_IMM:
3059                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3060                                               rdma_wr(wr)->rkey);
3061                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
3062                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3063                                 break;
3064
3065                         case IB_WR_LOCAL_INV:
3066                                 ctrl->srcrb_flags |=
3067                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3068                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3069                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
3070                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3071                                 break;
3072
3073                         case IB_WR_REG_MR:
3074                                 ctrl->srcrb_flags |=
3075                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3076                                 set_reg_seg(wqe, reg_wr(wr));
3077                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
3078                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3079                                 break;
3080
3081                         default:
3082                                 /* No extra segments required for sends */
3083                                 break;
3084                         }
3085                         break;
3086
3087                 case MLX4_IB_QPT_TUN_SMI_OWNER:
3088                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3089                                         ctrl, &seglen);
3090                         if (unlikely(err)) {
3091                                 *bad_wr = wr;
3092                                 goto out;
3093                         }
3094                         wqe  += seglen;
3095                         size += seglen / 16;
3096                         break;
3097                 case MLX4_IB_QPT_TUN_SMI:
3098                 case MLX4_IB_QPT_TUN_GSI:
3099                         /* this is a UD qp used in MAD responses to slaves. */
3100                         set_datagram_seg(wqe, ud_wr(wr));
3101                         /* set the forced-loopback bit in the data seg av */
3102                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3103                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3104                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3105                         break;
3106                 case MLX4_IB_QPT_UD:
3107                         set_datagram_seg(wqe, ud_wr(wr));
3108                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3109                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3110
3111                         if (wr->opcode == IB_WR_LSO) {
3112                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3113                                                 &lso_hdr_sz, &blh);
3114                                 if (unlikely(err)) {
3115                                         *bad_wr = wr;
3116                                         goto out;
3117                                 }
3118                                 lso_wqe = (__be32 *) wqe;
3119                                 wqe  += seglen;
3120                                 size += seglen / 16;
3121                         }
3122                         break;
3123
3124                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3125                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3126                                         ctrl, &seglen);
3127                         if (unlikely(err)) {
3128                                 *bad_wr = wr;
3129                                 goto out;
3130                         }
3131                         wqe  += seglen;
3132                         size += seglen / 16;
3133                         /* to start tunnel header on a cache-line boundary */
3134                         add_zero_len_inline(wqe);
3135                         wqe += 16;
3136                         size++;
3137                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3138                         wqe  += seglen;
3139                         size += seglen / 16;
3140                         break;
3141                 case MLX4_IB_QPT_PROXY_SMI:
3142                 case MLX4_IB_QPT_PROXY_GSI:
3143                         /* If we are tunneling special qps, this is a UD qp.
3144                          * In this case we first add a UD segment targeting
3145                          * the tunnel qp, and then add a header with address
3146                          * information */
3147                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3148                                                 ud_wr(wr),
3149                                                 qp->mlx4_ib_qp_type);
3150                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
3151                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3152                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
3153                         wqe  += seglen;
3154                         size += seglen / 16;
3155                         break;
3156
3157                 case MLX4_IB_QPT_SMI:
3158                 case MLX4_IB_QPT_GSI:
3159                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3160                                         &seglen);
3161                         if (unlikely(err)) {
3162                                 *bad_wr = wr;
3163                                 goto out;
3164                         }
3165                         wqe  += seglen;
3166                         size += seglen / 16;
3167                         break;
3168
3169                 default:
3170                         break;
3171                 }
3172
3173                 /*
3174                  * Write data segments in reverse order, so as to
3175                  * overwrite cacheline stamp last within each
3176                  * cacheline.  This avoids issues with WQE
3177                  * prefetching.
3178                  */
3179
3180                 dseg = wqe;
3181                 dseg += wr->num_sge - 1;
3182                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3183
3184                 /* Add one more inline data segment for ICRC for MLX sends */
3185                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3186                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3187                              qp->mlx4_ib_qp_type &
3188                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3189                         set_mlx_icrc_seg(dseg + 1);
3190                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
3191                 }
3192
3193                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3194                         set_data_seg(dseg, wr->sg_list + i);
3195
3196                 /*
3197                  * Possibly overwrite stamping in cacheline with LSO
3198                  * segment only after making sure all data segments
3199                  * are written.
3200                  */
3201                 wmb();
3202                 *lso_wqe = lso_hdr_sz;
3203
3204                 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3205                                              MLX4_WQE_CTRL_FENCE : 0) | size;
3206
3207                 /*
3208                  * Make sure descriptor is fully written before
3209                  * setting ownership bit (because HW can start
3210                  * executing as soon as we do).
3211                  */
3212                 wmb();
3213
3214                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3215                         *bad_wr = wr;
3216                         err = -EINVAL;
3217                         goto out;
3218                 }
3219
3220                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3221                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3222
3223                 stamp = ind + qp->sq_spare_wqes;
3224                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3225
3226                 /*
3227                  * We can improve latency by not stamping the last
3228                  * send queue WQE until after ringing the doorbell, so
3229                  * only stamp here if there are still more WQEs to post.
3230                  *
3231                  * Same optimization applies to padding with NOP wqe
3232                  * in case of WQE shrinking (used to prevent wrap-around
3233                  * in the middle of WR).
3234                  */
3235                 if (wr->next) {
3236                         stamp_send_wqe(qp, stamp, size * 16);
3237                         ind = pad_wraparound(qp, ind);
3238                 }
3239         }
3240
3241 out:
3242         if (likely(nreq)) {
3243                 qp->sq.head += nreq;
3244
3245                 /*
3246                  * Make sure that descriptors are written before
3247                  * doorbell record.
3248                  */
3249                 wmb();
3250
3251                 writel(qp->doorbell_qpn,
3252                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3253
3254                 /*
3255                  * Make sure doorbells don't leak out of SQ spinlock
3256                  * and reach the HCA out of order.
3257                  */
3258                 mmiowb();
3259
3260                 stamp_send_wqe(qp, stamp, size * 16);
3261
3262                 ind = pad_wraparound(qp, ind);
3263                 qp->sq_next_wqe = ind;
3264         }
3265
3266         spin_unlock_irqrestore(&qp->sq.lock, flags);
3267
3268         return err;
3269 }
3270
3271 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3272                       struct ib_recv_wr **bad_wr)
3273 {
3274         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3275         struct mlx4_wqe_data_seg *scat;
3276         unsigned long flags;
3277         int err = 0;
3278         int nreq;
3279         int ind;
3280         int max_gs;
3281         int i;
3282         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3283
3284         max_gs = qp->rq.max_gs;
3285         spin_lock_irqsave(&qp->rq.lock, flags);
3286
3287         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3288                 err = -EIO;
3289                 *bad_wr = wr;
3290                 nreq = 0;
3291                 goto out;
3292         }
3293
3294         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3295
3296         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3297                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3298                         err = -ENOMEM;
3299                         *bad_wr = wr;
3300                         goto out;
3301                 }
3302
3303                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3304                         err = -EINVAL;
3305                         *bad_wr = wr;
3306                         goto out;
3307                 }
3308
3309                 scat = get_recv_wqe(qp, ind);
3310
3311                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3312                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3313                         ib_dma_sync_single_for_device(ibqp->device,
3314                                                       qp->sqp_proxy_rcv[ind].map,
3315                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3316                                                       DMA_FROM_DEVICE);
3317                         scat->byte_count =
3318                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3319                         /* use dma lkey from upper layer entry */
3320                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3321                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3322                         scat++;
3323                         max_gs--;
3324                 }
3325
3326                 for (i = 0; i < wr->num_sge; ++i)
3327                         __set_data_seg(scat + i, wr->sg_list + i);
3328
3329                 if (i < max_gs) {
3330                         scat[i].byte_count = 0;
3331                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3332                         scat[i].addr       = 0;
3333                 }
3334
3335                 qp->rq.wrid[ind] = wr->wr_id;
3336
3337                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3338         }
3339
3340 out:
3341         if (likely(nreq)) {
3342                 qp->rq.head += nreq;
3343
3344                 /*
3345                  * Make sure that descriptors are written before
3346                  * doorbell record.
3347                  */
3348                 wmb();
3349
3350                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3351         }
3352
3353         spin_unlock_irqrestore(&qp->rq.lock, flags);
3354
3355         return err;
3356 }
3357
3358 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3359 {
3360         switch (mlx4_state) {
3361         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3362         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3363         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3364         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3365         case MLX4_QP_STATE_SQ_DRAINING:
3366         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3367         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3368         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3369         default:                     return -1;
3370         }
3371 }
3372
3373 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3374 {
3375         switch (mlx4_mig_state) {
3376         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3377         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
3378         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3379         default: return -1;
3380         }
3381 }
3382
3383 static int to_ib_qp_access_flags(int mlx4_flags)
3384 {
3385         int ib_flags = 0;
3386
3387         if (mlx4_flags & MLX4_QP_BIT_RRE)
3388                 ib_flags |= IB_ACCESS_REMOTE_READ;
3389         if (mlx4_flags & MLX4_QP_BIT_RWE)
3390                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3391         if (mlx4_flags & MLX4_QP_BIT_RAE)
3392                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3393
3394         return ib_flags;
3395 }
3396
3397 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3398                                 struct mlx4_qp_path *path)
3399 {
3400         struct mlx4_dev *dev = ibdev->dev;
3401         int is_eth;
3402
3403         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3404         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
3405
3406         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3407                 return;
3408
3409         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3410                 IB_LINK_LAYER_ETHERNET;
3411         if (is_eth)
3412                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3413                 ((path->sched_queue & 4) << 1);
3414         else
3415                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3416
3417         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3418         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3419         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3420         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3421         if (ib_ah_attr->ah_flags) {
3422                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3423                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3424                 ib_ah_attr->grh.traffic_class =
3425                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3426                 ib_ah_attr->grh.flow_label =
3427                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3428                 memcpy(ib_ah_attr->grh.dgid.raw,
3429                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3430         }
3431 }
3432
3433 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3434                      struct ib_qp_init_attr *qp_init_attr)
3435 {
3436         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3437         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3438         struct mlx4_qp_context context;
3439         int mlx4_state;
3440         int err = 0;
3441
3442         mutex_lock(&qp->mutex);
3443
3444         if (qp->state == IB_QPS_RESET) {
3445                 qp_attr->qp_state = IB_QPS_RESET;
3446                 goto done;
3447         }
3448
3449         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3450         if (err) {
3451                 err = -EINVAL;
3452                 goto out;
3453         }
3454
3455         mlx4_state = be32_to_cpu(context.flags) >> 28;
3456
3457         qp->state                    = to_ib_qp_state(mlx4_state);
3458         qp_attr->qp_state            = qp->state;
3459         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3460         qp_attr->path_mig_state      =
3461                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3462         qp_attr->qkey                = be32_to_cpu(context.qkey);
3463         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3464         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3465         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3466         qp_attr->qp_access_flags     =
3467                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3468
3469         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3470                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3471                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3472                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3473                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3474         }
3475
3476         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3477         if (qp_attr->qp_state == IB_QPS_INIT)
3478                 qp_attr->port_num = qp->port;
3479         else
3480                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3481
3482         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3483         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3484
3485         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3486
3487         qp_attr->max_dest_rd_atomic =
3488                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3489         qp_attr->min_rnr_timer      =
3490                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3491         qp_attr->timeout            = context.pri_path.ackto >> 3;
3492         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3493         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3494         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3495
3496 done:
3497         qp_attr->cur_qp_state        = qp_attr->qp_state;
3498         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3499         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3500
3501         if (!ibqp->uobject) {
3502                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3503                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3504         } else {
3505                 qp_attr->cap.max_send_wr  = 0;
3506                 qp_attr->cap.max_send_sge = 0;
3507         }
3508
3509         /*
3510          * We don't support inline sends for kernel QPs (yet), and we
3511          * don't know what userspace's value should be.
3512          */
3513         qp_attr->cap.max_inline_data = 0;
3514
3515         qp_init_attr->cap            = qp_attr->cap;
3516
3517         qp_init_attr->create_flags = 0;
3518         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3519                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3520
3521         if (qp->flags & MLX4_IB_QP_LSO)
3522                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3523
3524         if (qp->flags & MLX4_IB_QP_NETIF)
3525                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3526
3527         qp_init_attr->sq_sig_type =
3528                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3529                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3530
3531 out:
3532         mutex_unlock(&qp->mutex);
3533         return err;
3534 }
3535