cpufreq: x86: Disable interrupts during MSRs reading
authorDoug Smythies <doug.smythies@gmail.com>
Tue, 8 Aug 2017 21:12:49 +0000 (14:12 -0700)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Thu, 10 Aug 2017 23:27:41 +0000 (01:27 +0200)
commit8e2f3bce05e056575c2c84a344a8291fdabb5f21
tree0a68d4997d6c9d4e9b77faceca9132ab1d9120d8
parentaae4e7a8bc44722fe70d58920a36916b1043195e
cpufreq: x86: Disable interrupts during MSRs reading

According to Intel 64 and IA-32 Architectures SDM, Volume 3,
Chapter 14.2, "Software needs to exercise care to avoid delays
between the two RDMSRs (for example interrupts)".

So, disable interrupts during reading MSRs IA32_APERF and IA32_MPERF.

See also: commit 4ab60c3f32c7 (cpufreq: intel_pstate: Disable
interrupts during MSRs reading).

Signed-off-by: Doug Smythies <dsmythies@telus.net>
Reviewed-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
arch/x86/kernel/cpu/aperfmperf.c