2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.50 2006/12/23 00:27:03 swildner Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/eventhandler.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
70 #include <sys/machintr.h>
72 #include <machine/clock.h>
73 #ifdef CLK_CALIBRATION_LOOP
75 #include <machine/cputypes.h>
76 #include <machine/frame.h>
77 #include <machine/ipl.h>
78 #include <machine/limits.h>
79 #include <machine/md_var.h>
80 #include <machine/psl.h>
81 #include <machine/segments.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
85 #include <machine_base/icu/icu.h>
86 #include <bus/isa/i386/isa.h>
87 #include <bus/isa/rtc.h>
88 #include <machine_base/isa/timerreg.h>
90 #include <machine_base/isa/intr_machdep.h>
93 /* The interrupt triggered by the 8254 (timer) chip */
95 static void setup_8254_mixed_mode (void);
97 static void i8254_restore(void);
98 static void resettodr_on_shutdown(void *arg __unused);
101 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
102 * can use a simple formula for leap years.
104 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
105 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
108 #define TIMER_FREQ 1193182
111 static uint8_t i8254_walltimer_sel;
112 static uint16_t i8254_walltimer_cntr;
114 int adjkerntz; /* local offset from GMT in seconds */
115 int disable_rtc_set; /* disable resettodr() if != 0 */
116 int statclock_disable = 1; /* we don't use the statclock right now */
118 u_int tsc_freq; /* XXX obsolete, convert users */
119 int64_t tsc_frequency;
121 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
123 enum tstate { RELEASED, ACQUIRED };
124 enum tstate timer0_state;
125 enum tstate timer1_state;
126 enum tstate timer2_state;
128 static int beeping = 0;
129 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
130 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
131 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
132 static int rtc_loaded;
134 static int i8254_cputimer_div;
136 static struct callout sysbeepstop_ch;
138 static sysclock_t i8254_cputimer_count(void);
139 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
140 static void i8254_cputimer_destruct(struct cputimer *cputimer);
142 static struct cputimer i8254_cputimer = {
143 SLIST_ENTRY_INITIALIZER,
147 i8254_cputimer_count,
148 cputimer_default_fromhz,
149 cputimer_default_fromus,
150 i8254_cputimer_construct,
151 i8254_cputimer_destruct,
157 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
158 * counting as of this interrupt. We use timer1 in free-running mode (not
159 * generating any interrupts) as our main counter. Each cpu has timeouts
162 * This code is INTR_MPSAFE and may be called without the BGL held.
165 clkintr(void *dummy, void *frame_arg)
167 static sysclock_t sysclock_count; /* NOTE! Must be static */
168 struct globaldata *gd = mycpu;
170 struct globaldata *gscan;
175 * SWSTROBE mode is a one-shot, the timer is no longer running
180 * XXX the dispatcher needs work. right now we call systimer_intr()
181 * directly or via IPI for any cpu with systimers queued, which is
182 * usually *ALL* of them. We need to use the LAPIC timer for this.
184 sysclock_count = sys_cputimer->count();
186 for (n = 0; n < ncpus; ++n) {
187 gscan = globaldata_find(n);
188 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
191 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
194 systimer_intr(&sysclock_count, 0, frame_arg);
198 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
199 systimer_intr(&sysclock_count, 0, frame_arg);
208 acquire_timer2(int mode)
210 if (timer2_state != RELEASED)
212 timer2_state = ACQUIRED;
215 * This access to the timer registers is as atomic as possible
216 * because it is a single instruction. We could do better if we
219 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
226 if (timer2_state != ACQUIRED)
228 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
229 timer2_state = RELEASED;
234 * This routine receives statistical clock interrupts from the RTC.
235 * As explained above, these occur at 128 interrupts per second.
236 * When profiling, we receive interrupts at a rate of 1024 Hz.
238 * This does not actually add as much overhead as it sounds, because
239 * when the statistical clock is active, the hardclock driver no longer
240 * needs to keep (inaccurate) statistics on its own. This decouples
241 * statistics gathering from scheduling interrupts.
243 * The RTC chip requires that we read status register C (RTC_INTR)
244 * to acknowledge an interrupt, before it will generate the next one.
245 * Under high interrupt load, rtcintr() can be indefinitely delayed and
246 * the clock can tick immediately after the read from RTC_INTR. In this
247 * case, the mc146818A interrupt signal will not drop for long enough
248 * to register with the 8259 PIC. If an interrupt is missed, the stat
249 * clock will halt, considerably degrading system performance. This is
250 * why we use 'while' rather than a more straightforward 'if' below.
251 * Stat clock ticks can still be lost, causing minor loss of accuracy
252 * in the statistics, but the stat clock will no longer stop.
255 rtcintr(void *dummy, void *frame)
257 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
259 /* statclock(frame); no longer used */
266 DB_SHOW_COMMAND(rtc, rtc)
268 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
269 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
270 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
271 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
276 * Return the current cpu timer count as a 32 bit integer.
280 i8254_cputimer_count(void)
282 static __uint16_t cputimer_last;
287 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
288 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
289 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
290 count = -count; /* -> countup */
291 if (count < cputimer_last) /* rollover */
292 i8254_cputimer.base += 0x00010000;
293 ret = i8254_cputimer.base | count;
294 cputimer_last = count;
300 * This function is called whenever the system timebase changes, allowing
301 * us to calculate what is needed to convert a system timebase tick
302 * into an 8254 tick for the interrupt timer. If we can convert to a
303 * simple shift, multiplication, or division, we do so. Otherwise 64
304 * bit arithmatic is required every time the interrupt timer is reloaded.
307 cputimer_intr_config(struct cputimer *timer)
313 * Will a simple divide do the trick?
315 div = (timer->freq + (i8254_cputimer.freq / 2)) / i8254_cputimer.freq;
316 freq = i8254_cputimer.freq * div;
318 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
319 i8254_cputimer_div = div;
321 i8254_cputimer_div = 0;
325 * Reload for the next timeout. It is possible for the reload value
326 * to be 0 or negative, indicating that an immediate timer interrupt
327 * is desired. For now make the minimum 2 ticks.
329 * We may have to convert from the system timebase to the 8254 timebase.
332 cputimer_intr_reload(sysclock_t reload)
336 if (i8254_cputimer_div)
337 reload /= i8254_cputimer_div;
339 reload = (int64_t)reload * i8254_cputimer.freq / sys_cputimer->freq;
345 if (timer0_running) {
346 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
347 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
348 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
349 if (reload < count) {
350 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
351 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
352 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
357 reload = 0; /* full count */
358 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
359 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
360 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
366 * Wait "n" microseconds.
367 * Relies on timer 1 counting down from (cputimer_freq / hz)
368 * Note: timer had better have been programmed before this is first used!
373 int delta, prev_tick, tick, ticks_left;
378 static int state = 0;
382 for (n1 = 1; n1 <= 10000000; n1 *= 10)
387 kprintf("DELAY(%d)...", n);
390 * Guard against the timer being uninitialized if we are called
391 * early for console i/o.
393 if (timer0_state == RELEASED)
397 * Read the counter first, so that the rest of the setup overhead is
398 * counted. Then calculate the number of hardware timer ticks
399 * required, rounding up to be sure we delay at least the requested
400 * number of microseconds.
402 prev_tick = sys_cputimer->count();
403 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
409 while (ticks_left > 0) {
410 tick = sys_cputimer->count();
414 delta = tick - prev_tick;
422 kprintf(" %d calls to getit() at %d usec each\n",
423 getit_calls, (n + 5) / getit_calls);
428 sysbeepstop(void *chan)
430 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
436 sysbeep(int pitch, int period)
438 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
441 * Nobody else is using timer2, we do not need the clock lock
443 outb(TIMER_CNTR2, pitch);
444 outb(TIMER_CNTR2, (pitch>>8));
446 /* enable counter2 output to speaker */
447 outb(IO_PPI, inb(IO_PPI) | 3);
449 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
455 * RTC support routines
466 val = inb(IO_RTC + 1);
473 writertc(u_char reg, u_char val)
479 outb(IO_RTC + 1, val);
480 inb(0x84); /* XXX work around wrong order in rtcin() */
487 return(bcd2bin(rtcin(port)));
491 calibrate_clocks(void)
494 u_int count, prev_count, tot_count;
495 int sec, start_sec, timeout;
498 kprintf("Calibrating clock(s) ... ");
499 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
503 /* Read the mc146818A seconds counter. */
505 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
506 sec = rtcin(RTC_SEC);
513 /* Wait for the mC146818A seconds counter to change. */
516 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
517 sec = rtcin(RTC_SEC);
518 if (sec != start_sec)
525 /* Start keeping track of the i8254 counter. */
526 prev_count = sys_cputimer->count();
532 old_tsc = 0; /* shut up gcc */
535 * Wait for the mc146818A seconds counter to change. Read the i8254
536 * counter for each iteration since this is convenient and only
537 * costs a few usec of inaccuracy. The timing of the final reads
538 * of the counters almost matches the timing of the initial reads,
539 * so the main cause of inaccuracy is the varying latency from
540 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
541 * rtcin(RTC_SEC) that returns a changed seconds count. The
542 * maximum inaccuracy from this cause is < 10 usec on 486's.
546 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
547 sec = rtcin(RTC_SEC);
548 count = sys_cputimer->count();
549 tot_count += (int)(count - prev_count);
551 if (sec != start_sec)
558 * Read the cpu cycle counter. The timing considerations are
559 * similar to those for the i8254 clock.
562 tsc_frequency = rdtsc() - old_tsc;
563 tsc_freq = (u_int)tsc_frequency; /* XXX */
567 kprintf("TSC clock: %u Hz, ", tsc_freq);
568 kprintf("i8254 clock: %u Hz\n", tot_count);
572 kprintf("failed, using default i8254 clock of %u Hz\n",
573 i8254_cputimer.freq);
574 return (i8254_cputimer.freq);
580 timer0_state = ACQUIRED;
585 * Timer0 is our fine-grained variable clock interrupt
587 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
588 outb(TIMER_CNTR0, 2); /* lsb */
589 outb(TIMER_CNTR0, 0); /* msb */
593 * Timer1 or timer2 is our free-running clock, but only if another
594 * has not been selected.
596 cputimer_register(&i8254_cputimer);
597 cputimer_select(&i8254_cputimer, 0);
601 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
606 * Should we use timer 1 or timer 2 ?
609 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
610 if (which != 1 && which != 2)
615 timer->name = "i8254_timer1";
616 timer->type = CPUTIMER_8254_SEL1;
617 i8254_walltimer_sel = TIMER_SEL1;
618 i8254_walltimer_cntr = TIMER_CNTR1;
619 timer1_state = ACQUIRED;
622 timer->name = "i8254_timer2";
623 timer->type = CPUTIMER_8254_SEL2;
624 i8254_walltimer_sel = TIMER_SEL2;
625 i8254_walltimer_cntr = TIMER_CNTR2;
626 timer2_state = ACQUIRED;
630 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
633 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
634 outb(i8254_walltimer_cntr, 0); /* lsb */
635 outb(i8254_walltimer_cntr, 0); /* msb */
636 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
641 i8254_cputimer_destruct(struct cputimer *timer)
643 switch(timer->type) {
644 case CPUTIMER_8254_SEL1:
645 timer1_state = RELEASED;
647 case CPUTIMER_8254_SEL2:
648 timer2_state = RELEASED;
659 /* Restore all of the RTC's "status" (actually, control) registers. */
660 writertc(RTC_STATUSB, RTCSB_24HR);
661 writertc(RTC_STATUSA, rtc_statusa);
662 writertc(RTC_STATUSB, rtc_statusb);
666 * Restore all the timers.
668 * This function is called to resynchronize our core timekeeping after a
669 * long halt, e.g. from apm_default_resume() and friends. It is also
670 * called if after a BIOS call we have detected munging of the 8254.
671 * It is necessary because cputimer_count() counter's delta may have grown
672 * too large for nanouptime() and friends to handle, or (in the case of 8254
673 * munging) might cause the SYSTIMER code to prematurely trigger.
679 i8254_restore(); /* restore timer_freq and hz */
680 rtc_restore(); /* reenable RTC interrupts */
685 * Initialize 8254 timer 0 early so that it can be used in DELAY().
693 * Can we use the TSC?
695 if (cpu_feature & CPUID_TSC)
701 * Initial RTC state, don't do anything unexpected
703 writertc(RTC_STATUSA, rtc_statusa);
704 writertc(RTC_STATUSB, RTCSB_24HR);
707 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
708 * generate an interrupt, which we will ignore for now.
710 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
711 * (so it counts a full 2^16 and repeats). We will use this timer
715 freq = calibrate_clocks();
716 #ifdef CLK_CALIBRATION_LOOP
719 "Press a key on the console to abort clock calibration\n");
720 while (cncheckc() == -1)
726 * Use the calibrated i8254 frequency if it seems reasonable.
727 * Otherwise use the default, and don't use the calibrated i586
730 delta = freq > i8254_cputimer.freq ?
731 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
732 if (delta < i8254_cputimer.freq / 100) {
733 #ifndef CLK_USE_I8254_CALIBRATION
736 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
737 freq = i8254_cputimer.freq;
739 cputimer_set_frequency(&i8254_cputimer, freq);
743 "%d Hz differs from default of %d Hz by more than 1%%\n",
744 freq, i8254_cputimer.freq);
749 #ifndef CLK_USE_TSC_CALIBRATION
753 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
758 if (tsc_present && tsc_frequency == 0) {
760 * Calibration of the i586 clock relative to the mc146818A
761 * clock failed. Do a less accurate calibration relative
762 * to the i8254 clock.
764 u_int64_t old_tsc = rdtsc();
767 tsc_frequency = rdtsc() - old_tsc;
768 tsc_freq = (u_int)tsc_frequency;
769 #ifdef CLK_USE_TSC_CALIBRATION
771 kprintf("TSC clock: %u Hz (Method B)\n", tsc_freq);
775 EVENTHANDLER_REGISTER(shutdown_final, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
779 * We can not use the TSC in SMP mode, until we figure out a
780 * cheap (impossible), reliable and precise (yeah right!) way
781 * to synchronize the TSCs of all the CPUs.
782 * Curse Intel for leaving the counter out of the I/O APIC.
787 * We can not use the TSC if we support APM. Precise timekeeping
788 * on an APM'ed machine is at best a fools pursuit, since
789 * any and all of the time spent in various SMM code can't
790 * be reliably accounted for. Reading the RTC is your only
791 * source of reliable time info. The i8254 looses too of course
792 * but we need to have some kind of time...
793 * We don't know at this point whether APM is going to be used
794 * or not, nor when it might be activated. Play it safe.
797 #endif /* NAPM > 0 */
799 #endif /* !defined(SMP) */
803 * Sync the time of day back to the RTC on shutdown, but only if
804 * we have already loaded it and have not crashed.
807 resettodr_on_shutdown(void *arg __unused)
809 if (rtc_loaded && panicstr == NULL) {
815 * Initialize the time of day register, based on the time base which is, e.g.
819 inittodr(time_t base)
821 unsigned long sec, days;
833 /* Look if we have a RTC present and the time is valid */
834 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
837 /* wait for time update to complete */
838 /* If RTCSA_TUP is zero, we have at least 244us before next update */
840 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
846 #ifdef USE_RTC_CENTURY
847 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
849 year = readrtc(RTC_YEAR) + 1900;
857 month = readrtc(RTC_MONTH);
858 for (m = 1; m < month; m++)
859 days += daysinmonth[m-1];
860 if ((month > 2) && LEAPYEAR(year))
862 days += readrtc(RTC_DAY) - 1;
864 for (y = 1970; y < year; y++)
865 days += DAYSPERYEAR + LEAPYEAR(y);
866 sec = ((( days * 24 +
867 readrtc(RTC_HRS)) * 60 +
868 readrtc(RTC_MIN)) * 60 +
870 /* sec now contains the number of seconds, since Jan 1 1970,
871 in the local time zone */
873 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
875 y = time_second - sec;
876 if (y <= -2 || y >= 2) {
877 /* badly off, adjust it */
887 kprintf("Invalid time in real time clock.\n");
888 kprintf("Check and reset the date immediately!\n");
892 * Write system time back to RTC
909 /* Disable RTC updates and interrupts. */
910 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
912 /* Calculate local time to put in RTC */
914 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
916 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
917 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
918 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
920 /* We have now the days since 01-01-1970 in tm */
921 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
922 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
924 y++, m = DAYSPERYEAR + LEAPYEAR(y))
927 /* Now we have the years in y and the day-of-the-year in tm */
928 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
929 #ifdef USE_RTC_CENTURY
930 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
936 if (m == 1 && LEAPYEAR(y))
943 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
944 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
946 /* Reenable RTC updates and interrupts. */
947 writertc(RTC_STATUSB, rtc_statusb);
953 * Start both clocks running. DragonFly note: the stat clock is no longer
954 * used. Instead, 8254 based systimers are used for all major clock
955 * interrupts. statclock_disable is set by default.
966 if (statclock_disable) {
968 * The stat interrupt mask is different without the
969 * statistics clock. Also, don't set the interrupt
970 * flag which would normally cause the RTC to generate
973 rtc_statusb = RTCSB_24HR;
975 /* Setting stathz to nonzero early helps avoid races. */
976 stathz = RTC_NOPROFRATE;
977 profhz = RTC_PROFRATE;
980 /* Finish initializing 8253 timer 0. */
983 apic_8254_intr = isa_apic_irq(0);
985 if (apic_8254_intr >= 0 ) {
986 if (apic_int_type(0, 0) == 3)
989 /* look for ExtInt on pin 0 */
990 if (apic_int_type(0, 0) == 3) {
991 apic_8254_intr = apic_irq(0, 0);
992 setup_8254_mixed_mode();
994 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
997 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
999 INTR_EXCL | INTR_FAST |
1000 INTR_NOPOLL | INTR_MPSAFE |
1002 machintr_intren(apic_8254_intr);
1006 register_int(0, clkintr, NULL, "clk", NULL,
1007 INTR_EXCL | INTR_FAST |
1008 INTR_NOPOLL | INTR_MPSAFE |
1010 machintr_intren(ICU_IRQ0);
1012 #endif /* APIC_IO */
1014 /* Initialize RTC. */
1015 writertc(RTC_STATUSA, rtc_statusa);
1016 writertc(RTC_STATUSB, RTCSB_24HR);
1018 if (statclock_disable == 0) {
1019 diag = rtcin(RTC_DIAG);
1021 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1024 if (isa_apic_irq(8) != 8)
1025 panic("APIC RTC != 8");
1026 #endif /* APIC_IO */
1028 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
1029 INTR_EXCL | INTR_FAST | INTR_NOPOLL |
1033 writertc(RTC_STATUSB, rtc_statusb);
1037 if (apic_8254_trial) {
1041 lastcnt = get_interrupt_counter(apic_8254_intr);
1044 * XXX this assumes the 8254 is the cpu timer. Force an
1045 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
1046 * then see if we got it.
1048 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1049 cputimer_intr_reload(2); /* XXX assumes 8254 */
1050 base = sys_cputimer->count();
1051 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1053 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1055 * The MP table is broken.
1056 * The 8254 was not connected to the specified pin
1058 * Workaround: Limited variant of mixed mode.
1060 machintr_intrdis(apic_8254_intr);
1061 unregister_int(clkdesc);
1062 kprintf("APIC_IO: Broken MP table detected: "
1063 "8254 is not connected to "
1064 "IOAPIC #%d intpin %d\n",
1065 int_to_apicintpin[apic_8254_intr].ioapic,
1066 int_to_apicintpin[apic_8254_intr].int_pin);
1068 * Revoke current ISA IRQ 0 assignment and
1069 * configure a fallback interrupt routing from
1070 * the 8254 Timer via the 8259 PIC to the
1071 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1072 * We reuse the low level interrupt handler number.
1074 if (apic_irq(0, 0) < 0) {
1075 revoke_apic_irq(apic_8254_intr);
1076 assign_apic_irq(0, 0, apic_8254_intr);
1078 apic_8254_intr = apic_irq(0, 0);
1079 setup_8254_mixed_mode();
1080 register_int(apic_8254_intr, clkintr, NULL, "clk",
1082 INTR_EXCL | INTR_FAST |
1083 INTR_NOPOLL | INTR_MPSAFE |
1085 machintr_intren(apic_8254_intr);
1089 if (apic_int_type(0, 0) != 3 ||
1090 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1091 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1092 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1093 int_to_apicintpin[apic_8254_intr].ioapic,
1094 int_to_apicintpin[apic_8254_intr].int_pin);
1097 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1100 callout_init(&sysbeepstop_ch);
1106 setup_8254_mixed_mode(void)
1109 * Allow 8254 timer to INTerrupt 8259:
1110 * re-initialize master 8259:
1111 * reset; prog 4 bytes, single ICU, edge triggered
1113 outb(IO_ICU1, 0x13);
1114 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1115 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1116 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1117 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1119 /* program IO APIC for type 3 INT on INT0 */
1120 if (ext_int_setup(0, 0) < 0)
1121 panic("8254 redirect via APIC pin0 impossible!");
1126 setstatclockrate(int newhz)
1128 if (newhz == RTC_PROFRATE)
1129 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1131 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1132 writertc(RTC_STATUSA, rtc_statusa);
1137 tsc_get_timecount(struct timecounter *tc)
1143 #ifdef KERN_TIMESTAMP
1144 #define KERN_TIMESTAMP_SIZE 16384
1145 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1146 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1147 sizeof(tsc), "LU", "Kernel timestamps");
1153 tsc[i] = (u_int32_t)rdtsc();
1156 if (i >= KERN_TIMESTAMP_SIZE)
1158 tsc[i] = 0; /* mark last entry */
1160 #endif /* KERN_TIMESTAMP */
1167 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1174 if (sys_cputimer == &i8254_cputimer)
1175 count = sys_cputimer->count();
1183 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1184 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1187 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1188 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1190 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1191 0, 0, hw_i8254_timestamp, "A", "");