2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/i386/initcpu.c,v 1.19.2.9 2003/04/05 13:47:19 dwmalone Exp $
34 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/systm.h>
37 #include <sys/sysctl.h>
39 #include <machine/cputypes.h>
40 #include <machine/md_var.h>
41 #include <machine/specialreg.h>
43 void initializecpu(void);
44 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
45 void enable_K5_wt_alloc(void);
46 void enable_K6_wt_alloc(void);
47 void enable_K6_2_wt_alloc(void);
51 static void init_5x86(void);
52 static void init_bluelightning(void);
53 static void init_486dlc(void);
54 static void init_cy486dx(void);
55 #ifdef CPU_I486_ON_386
56 static void init_i486_on_386(void);
58 static void init_6x86(void);
62 static void init_6x86MX(void);
63 static void init_ppro(void);
64 static void init_mendocino(void);
67 static int hw_instruction_sse;
68 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
69 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
72 u_int cpu_fxsr; /* SSE enabled */
80 init_bluelightning(void)
84 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
85 need_post_dma_flush = 1;
88 eflags = read_eflags();
91 load_cr0(rcr0() | CR0_CD | CR0_NW);
94 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
95 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
97 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
99 /* Enables 13MB and 0-640KB cache. */
100 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
101 #ifdef CPU_BLUELIGHTNING_3X
102 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
104 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
107 /* Enable caching in CR0. */
108 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
110 write_eflags(eflags);
114 * Cyrix 486SLC/DLC/SR/DR series
122 eflags = read_eflags();
126 ccr0 = read_cyrix_reg(CCR0);
127 #ifndef CYRIX_CACHE_WORKS
128 ccr0 |= CCR0_NC1 | CCR0_BARB;
129 write_cyrix_reg(CCR0, ccr0);
133 #ifndef CYRIX_CACHE_REALLY_WORKS
134 ccr0 |= CCR0_NC1 | CCR0_BARB;
138 #ifdef CPU_DIRECT_MAPPED_CACHE
139 ccr0 |= CCR0_CO; /* Direct mapped mode. */
141 write_cyrix_reg(CCR0, ccr0);
143 /* Clear non-cacheable region. */
144 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
145 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
146 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
147 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
149 write_cyrix_reg(0, 0); /* dummy write */
151 /* Enable caching in CR0. */
152 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
154 #endif /* !CYRIX_CACHE_WORKS */
155 write_eflags(eflags);
160 * Cyrix 486S/DX series
168 eflags = read_eflags();
172 ccr2 = read_cyrix_reg(CCR2);
174 ccr2 |= CCR2_SUSP_HLT;
178 /* Enables WB cache interface pin and Lock NW bit in CR0. */
179 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
180 /* Unlock NW bit in CR0. */
181 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
182 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
185 write_cyrix_reg(CCR2, ccr2);
186 write_eflags(eflags);
197 u_char ccr2, ccr3, ccr4, pcr0;
199 eflags = read_eflags();
202 load_cr0(rcr0() | CR0_CD | CR0_NW);
205 (void)read_cyrix_reg(CCR3); /* dummy */
207 /* Initialize CCR2. */
208 ccr2 = read_cyrix_reg(CCR2);
211 ccr2 |= CCR2_SUSP_HLT;
213 ccr2 &= ~CCR2_SUSP_HLT;
216 write_cyrix_reg(CCR2, ccr2);
218 /* Initialize CCR4. */
219 ccr3 = read_cyrix_reg(CCR3);
220 write_cyrix_reg(CCR3, CCR3_MAPEN0);
222 ccr4 = read_cyrix_reg(CCR4);
225 #ifdef CPU_FASTER_5X86_FPU
226 ccr4 |= CCR4_FASTFPE;
228 ccr4 &= ~CCR4_FASTFPE;
230 ccr4 &= ~CCR4_IOMASK;
231 /********************************************************************
232 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
233 * should be 0 for errata fix.
234 ********************************************************************/
236 ccr4 |= CPU_IORT & CCR4_IOMASK;
238 write_cyrix_reg(CCR4, ccr4);
240 /* Initialize PCR0. */
241 /****************************************************************
242 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
243 * BTB_EN might make your system unstable.
244 ****************************************************************/
245 pcr0 = read_cyrix_reg(PCR0);
262 /****************************************************************
263 * WARNING: if you use a memory mapped I/O device, don't use
264 * DISABLE_5X86_LSSER option, which may reorder memory mapped
266 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
267 ****************************************************************/
268 #ifdef CPU_DISABLE_5X86_LSSER
273 write_cyrix_reg(PCR0, pcr0);
276 write_cyrix_reg(CCR3, ccr3);
278 (void)read_cyrix_reg(0x80); /* dummy */
280 /* Unlock NW bit in CR0. */
281 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
282 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
283 /* Lock NW bit in CR0. */
284 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
286 write_eflags(eflags);
289 #ifdef CPU_I486_ON_386
291 * There are i486 based upgrade products for i386 machines.
292 * In this case, BIOS doesn't enables CPU cache.
295 init_i486_on_386(void)
299 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
300 need_post_dma_flush = 1;
303 eflags = read_eflags();
306 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
308 write_eflags(eflags);
315 * XXX - What should I do here? Please let me know.
323 eflags = read_eflags();
326 load_cr0(rcr0() | CR0_CD | CR0_NW);
329 /* Initialize CCR0. */
330 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
332 /* Initialize CCR1. */
333 #ifdef CPU_CYRIX_NO_LOCK
334 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
336 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
339 /* Initialize CCR2. */
341 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
343 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
346 ccr3 = read_cyrix_reg(CCR3);
347 write_cyrix_reg(CCR3, CCR3_MAPEN0);
349 /* Initialize CCR4. */
350 ccr4 = read_cyrix_reg(CCR4);
352 ccr4 &= ~CCR4_IOMASK;
354 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
356 write_cyrix_reg(CCR4, ccr4 | 7);
359 /* Initialize CCR5. */
361 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
365 write_cyrix_reg(CCR3, ccr3);
367 /* Unlock NW bit in CR0. */
368 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
371 * Earlier revision of the 6x86 CPU could crash the system if
372 * L1 cache is in write-back mode.
374 if ((cyrix_did & 0xff00) > 0x1600)
375 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
377 /* Revision 2.6 and lower. */
378 #ifdef CYRIX_CACHE_REALLY_WORKS
379 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
381 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
385 /* Lock NW bit in CR0. */
386 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
388 write_eflags(eflags);
390 #endif /* I486_CPU */
394 * Cyrix 6x86MX (code-named M2)
396 * XXX - What should I do here? Please let me know.
404 eflags = read_eflags();
407 load_cr0(rcr0() | CR0_CD | CR0_NW);
410 /* Initialize CCR0. */
411 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
413 /* Initialize CCR1. */
414 #ifdef CPU_CYRIX_NO_LOCK
415 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
417 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
420 /* Initialize CCR2. */
422 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
424 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
427 ccr3 = read_cyrix_reg(CCR3);
428 write_cyrix_reg(CCR3, CCR3_MAPEN0);
430 /* Initialize CCR4. */
431 ccr4 = read_cyrix_reg(CCR4);
432 ccr4 &= ~CCR4_IOMASK;
434 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
436 write_cyrix_reg(CCR4, ccr4 | 7);
439 /* Initialize CCR5. */
441 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
445 write_cyrix_reg(CCR3, ccr3);
447 /* Unlock NW bit in CR0. */
448 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
450 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
452 /* Lock NW bit in CR0. */
453 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
455 write_eflags(eflags);
465 * Local APIC should be diabled in UP kernel.
467 apicbase = rdmsr(0x1b);
468 apicbase &= ~0x800LL;
469 wrmsr(0x1b, apicbase);
474 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
480 #ifdef CPU_PPRO2CELERON
482 u_int64_t bbl_cr_ctl3;
484 eflags = read_eflags();
487 load_cr0(rcr0() | CR0_CD | CR0_NW);
490 bbl_cr_ctl3 = rdmsr(0x11e);
492 /* If the L2 cache is configured, do nothing. */
493 if (!(bbl_cr_ctl3 & 1)) {
494 bbl_cr_ctl3 = 0x134052bLL;
496 /* Set L2 Cache Latency (Default: 5). */
497 #ifdef CPU_CELERON_L2_LATENCY
498 #if CPU_L2_LATENCY > 15
499 #error invalid CPU_L2_LATENCY.
501 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
503 bbl_cr_ctl3 |= 5 << 1;
505 wrmsr(0x11e, bbl_cr_ctl3);
508 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
509 write_eflags(eflags);
510 #endif /* CPU_PPRO2CELERON */
513 #endif /* I686_CPU */
516 * Initialize CR4 (Control register 4) to enable SSE instructions.
521 #if defined(CPU_ENABLE_SSE)
522 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
523 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
524 cpu_fxsr = hw_instruction_sse = 1;
536 init_bluelightning();
547 #ifdef CPU_I486_ON_386
555 #endif /* I486_CPU */
561 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
562 switch (cpu_id & 0xff0) {
570 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
571 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
573 * Sometimes the BIOS doesn't enable SSE instructions.
574 * According to AMD document 20734, the mobile
575 * Duron, the (mobile) Athlon 4 and the Athlon MP
576 * support SSE. These correspond to cpu_id 0x66X
579 if ((cpu_feature & CPUID_XMM) == 0 &&
580 ((cpu_id & ~0xf) == 0x660 ||
581 (cpu_id & ~0xf) == 0x670 ||
582 (cpu_id & ~0xf) == 0x680)) {
584 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
586 cpu_feature = regs[3];
597 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
599 * OS should flush L1 cache by itself because no PC-98 supports
600 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
601 * when need_pre_dma_flush = 1, use invd instruction after DMA
602 * transfer when need_post_dma_flush = 1. If your CPU upgrade
603 * product supports hardware cache control, you can add the
604 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
605 * This option eliminates unneeded cache flush instruction(s).
607 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
611 need_post_dma_flush = 1;
614 need_pre_dma_flush = 1;
617 need_pre_dma_flush = 1;
618 #ifdef CPU_I486_ON_386
619 need_post_dma_flush = 1;
626 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
627 switch (cpu_id & 0xFF0) {
628 case 0x470: /* Enhanced Am486DX2 WB */
629 case 0x490: /* Enhanced Am486DX4 WB */
630 case 0x4F0: /* Am5x86 WB */
631 need_pre_dma_flush = 1;
634 } else if (strcmp(cpu_vendor, "IBM") == 0) {
635 need_post_dma_flush = 1;
637 #ifdef CPU_I486_ON_386
638 need_pre_dma_flush = 1;
641 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
644 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
646 * Enable write allocate feature of AMD processors.
647 * Following two functions require the Maxmem variable being set.
650 enable_K5_wt_alloc(void)
655 * Write allocate is supported only on models 1, 2, and 3, with
656 * a stepping of 4 or greater.
658 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
660 msr = rdmsr(0x83); /* HWCR */
661 wrmsr(0x83, msr & !(0x10));
664 * We have to tell the chip where the top of memory is,
665 * since video cards could have frame bufferes there,
666 * memory-mapped I/O could be there, etc.
672 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
674 if (!(inb(0x43b) & 4)) {
675 wrmsr(0x86, 0x0ff00f0);
676 msr |= AMD_WT_ALLOC_PRE;
680 * There is no way to know wheter 15-16M hole exists or not.
681 * Therefore, we disable write allocate for this range.
683 wrmsr(0x86, 0x0ff00f0);
684 msr |= AMD_WT_ALLOC_PRE;
689 wrmsr(0x83, msr|0x10); /* enable write allocate */
696 enable_K6_wt_alloc(void)
702 eflags = read_eflags();
706 #ifdef CPU_DISABLE_CACHE
708 * Certain K6-2 box becomes unstable when write allocation is
712 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
713 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
714 * All other bits in TR12 have no effect on the processer's operation.
715 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
718 wrmsr(0x0000000e, (u_int64_t)0x0008);
720 /* Don't assume that memory size is aligned with 4M. */
722 size = ((Maxmem >> 8) + 3) >> 2;
726 /* Limit is 508M bytes. */
729 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
731 #if defined(PC98) || defined(NO_MEMORY_HOLE)
732 if (whcr & (0x7fLL << 1)) {
735 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
738 if (!(inb(0x43b) & 4))
746 * There is no way to know wheter 15-16M hole exists or not.
747 * Therefore, we disable write allocate for this range.
751 wrmsr(0x0c0000082, whcr);
753 write_eflags(eflags);
758 enable_K6_2_wt_alloc(void)
764 eflags = read_eflags();
768 #ifdef CPU_DISABLE_CACHE
770 * Certain K6-2 box becomes unstable when write allocation is
774 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
775 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
776 * All other bits in TR12 have no effect on the processer's operation.
777 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
780 wrmsr(0x0000000e, (u_int64_t)0x0008);
782 /* Don't assume that memory size is aligned with 4M. */
784 size = ((Maxmem >> 8) + 3) >> 2;
788 /* Limit is 4092M bytes. */
791 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
793 #if defined(PC98) || defined(NO_MEMORY_HOLE)
794 if (whcr & (0x3ffLL << 22)) {
797 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
800 if (!(inb(0x43b) & 4))
801 whcr &= ~(1LL << 16);
808 * There is no way to know wheter 15-16M hole exists or not.
809 * Therefore, we disable write allocate for this range.
811 whcr &= ~(1LL << 16);
813 wrmsr(0x0c0000082, whcr);
815 write_eflags(eflags);
818 #endif /* I585_CPU && CPU_WT_ALLOC */
824 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
828 u_char ccr1, ccr2, ccr3;
829 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
832 if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
833 eflags = read_eflags();
837 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
838 ccr0 = read_cyrix_reg(CCR0);
840 ccr1 = read_cyrix_reg(CCR1);
841 ccr2 = read_cyrix_reg(CCR2);
842 ccr3 = read_cyrix_reg(CCR3);
843 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
844 write_cyrix_reg(CCR3, CCR3_MAPEN0);
845 ccr4 = read_cyrix_reg(CCR4);
846 if ((cpu == CPU_M1) || (cpu == CPU_M2))
847 ccr5 = read_cyrix_reg(CCR5);
849 pcr0 = read_cyrix_reg(PCR0);
850 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
852 write_eflags(eflags);
854 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
855 printf("CCR0=%x, ", (u_int)ccr0);
857 printf("CCR1=%x, CCR2=%x, CCR3=%x",
858 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
859 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
860 printf(", CCR4=%x, ", (u_int)ccr4);
862 printf("PCR0=%x\n", pcr0);
864 printf("CCR5=%x\n", ccr5);
867 printf("CR0=%x\n", cr0);