2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
48 #include "opt_msgbuf.h"
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/sysproto.h>
54 #include <sys/signalvar.h>
55 #include <sys/kernel.h>
56 #include <sys/linker.h>
57 #include <sys/malloc.h>
61 #include <sys/reboot.h>
63 #include <sys/msgbuf.h>
64 #include <sys/sysent.h>
65 #include <sys/sysctl.h>
66 #include <sys/vmmeter.h>
68 #include <sys/usched.h>
71 #include <sys/ctype.h>
72 #include <sys/serialize.h>
73 #include <sys/systimer.h>
76 #include <vm/vm_param.h>
78 #include <vm/vm_kern.h>
79 #include <vm/vm_object.h>
80 #include <vm/vm_page.h>
81 #include <vm/vm_map.h>
82 #include <vm/vm_pager.h>
83 #include <vm/vm_extern.h>
85 #include <sys/thread2.h>
86 #include <sys/mplock2.h>
87 #include <sys/mutex2.h>
97 #include <machine/cpu.h>
98 #include <machine/clock.h>
99 #include <machine/specialreg.h>
101 #include <machine/bootinfo.h>
103 #include <machine/md_var.h>
104 #include <machine/metadata.h>
105 #include <machine/pc/bios.h>
106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
107 #include <machine/globaldata.h> /* CPU_prvspace */
108 #include <machine/smp.h>
109 #include <machine/cputypes.h>
110 #include <machine/intr_machdep.h>
111 #include <machine/framebuffer.h>
114 #include <bus/isa/isa_device.h>
116 #include <machine_base/isa/isa_intr.h>
117 #include <bus/isa/rtc.h>
118 #include <sys/random.h>
119 #include <sys/ptrace.h>
120 #include <machine/sigframe.h>
122 #include <sys/machintr.h>
123 #include <machine_base/icu/icu_abi.h>
124 #include <machine_base/icu/elcr_var.h>
125 #include <machine_base/apic/lapic.h>
126 #include <machine_base/apic/ioapic.h>
127 #include <machine_base/apic/ioapic_abi.h>
128 #include <machine/mptable.h>
130 #define PHYSMAP_ENTRIES 10
132 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
134 extern void printcpuinfo(void); /* XXX header file */
135 extern void identify_cpu(void);
137 extern void finishidentcpu(void);
139 extern void panicifcpuunsupported(void);
141 static void cpu_startup(void *);
142 static void pic_finish(void *);
143 static void cpu_finish(void *);
145 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
147 static void init_locks(void);
149 extern void pcpu_timer_always(struct intrframe *);
151 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
152 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL);
153 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL);
156 extern vm_offset_t ksym_start, ksym_end;
159 struct privatespace CPU_prvspace_bsp __aligned(4096);
160 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp };
162 vm_paddr_t efi_systbl_phys;
163 int _udatasel, _ucodesel, _ucode32sel;
165 int64_t tsc_offsets[MAXCPU];
166 cpumask_t smp_idleinvl_mask;
167 cpumask_t smp_idleinvl_reqs;
169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
171 #if defined(SWTCH_OPTIM_STATS)
172 extern int swtch_optim_stats;
173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
174 CTLFLAG_RD, &swtch_optim_stats, 0, "");
175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
176 CTLFLAG_RD, &tlb_flush_count, 0, "");
178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
181 "monitor/mwait target state");
183 #define CPU_MWAIT_HAS_CX \
184 ((cpu_feature2 & CPUID2_MON) && \
185 (cpu_mwait_feature & CPUID_MWAIT_EXT))
187 #define CPU_MWAIT_CX_NAMELEN 16
189 #define CPU_MWAIT_C1 1
190 #define CPU_MWAIT_C2 2
191 #define CPU_MWAIT_C3 3
192 #define CPU_MWAIT_CX_MAX 8
194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
200 struct cpu_mwait_cx {
203 struct sysctl_ctx_list sysctl_ctx;
204 struct sysctl_oid *sysctl_tree;
206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
207 static char cpu_mwait_cx_supported[256];
209 static int cpu_mwait_c1_hints_cnt;
210 static int cpu_mwait_hints_cnt;
211 static int *cpu_mwait_hints;
213 static int cpu_mwait_deep_hints_cnt;
214 static int *cpu_mwait_deep_hints;
216 #define CPU_IDLE_REPEAT_DEFAULT 750
218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
220 static u_int cpu_mwait_repeat_shift = 1;
222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
225 static int cpu_mwait_c3_preamble =
226 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
227 CPU_MWAIT_C3_PREAMBLE_BM_STS;
229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
230 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
231 SYSCTL_INT(_machdep_mwait_CX, OID_AUTO, c3_preamble, CTLFLAG_RD,
232 &cpu_mwait_c3_preamble, 0, "C3+ preamble mask");
234 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
236 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
237 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS);
238 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
241 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
242 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
243 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
244 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
245 &cpu_mwait_repeat_shift, 0, "");
249 u_long ebda_addr = 0;
251 int imcr_present = 0;
253 int naps = 0; /* # of Applications processors */
258 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
260 u_long pmem = ctob(physmem);
262 int error = sysctl_handle_long(oidp, &pmem, 0, req);
266 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
267 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
270 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
272 int error = sysctl_handle_int(oidp, 0,
273 ctob(physmem - vmstats.v_wire_count), req);
277 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
278 0, 0, sysctl_hw_usermem, "IU", "");
281 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
283 int error = sysctl_handle_int(oidp, 0,
284 x86_64_btop(avail_end - avail_start), req);
288 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
289 0, 0, sysctl_hw_availpages, "I", "");
295 * The number of PHYSMAP entries must be one less than the number of
296 * PHYSSEG entries because the PHYSMAP entry that spans the largest
297 * physical address that is accessible by ISA DMA is split into two
300 vm_phystable_t phys_avail[VM_PHYSSEG_MAX + 1];
301 vm_phystable_t dump_avail[VM_PHYSSEG_MAX + 1];
303 /* must be 1 less so 0 0 can signal end of chunks */
304 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 1)
305 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 1)
307 static vm_offset_t buffer_sva, buffer_eva;
308 vm_offset_t clean_sva, clean_eva;
309 static vm_offset_t pager_sva, pager_eva;
310 static struct trapframe proc0_tf;
313 cpu_startup(void *dummy)
317 vm_offset_t firstaddr;
320 * Good {morning,afternoon,evening,night}.
322 kprintf("%s", version);
325 panicifcpuunsupported();
326 kprintf("real memory = %ju (%ju MB)\n",
328 (intmax_t)Realmem / 1024 / 1024);
330 * Display any holes after the first chunk of extended memory.
335 kprintf("Physical memory chunk(s):\n");
336 for (indx = 0; phys_avail[indx].phys_end != 0; ++indx) {
339 size1 = phys_avail[indx].phys_end -
340 phys_avail[indx].phys_beg;
342 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
343 (intmax_t)phys_avail[indx].phys_beg,
344 (intmax_t)phys_avail[indx].phys_end - 1,
346 (intmax_t)(size1 / PAGE_SIZE));
351 * Allocate space for system data structures.
352 * The first available kernel virtual address is in "v".
353 * As pages of kernel virtual memory are allocated, "v" is incremented.
354 * As pages of memory are allocated and cleared,
355 * "firstaddr" is incremented.
356 * An index into the kernel page table corresponding to the
357 * virtual memory address maintained in "v" is kept in "mapaddr".
361 * Make two passes. The first pass calculates how much memory is
362 * needed and allocates it. The second pass assigns virtual
363 * addresses to the various data structures.
367 v = (caddr_t)firstaddr;
369 #define valloc(name, type, num) \
370 (name) = (type *)v; v = (caddr_t)((name)+(num))
371 #define valloclim(name, type, num, lim) \
372 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
375 * The nominal buffer size (and minimum KVA allocation) is MAXBSIZE.
376 * For the first 64MB of ram nominally allocate sufficient buffers to
377 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
378 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
379 * the buffer cache we limit the eventual kva reservation to
382 * factor represents the 1/4 x ram conversion.
385 long factor = 4 * NBUFCALCSIZE / 1024;
386 long kbytes = physmem * (PAGE_SIZE / 1024);
390 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
392 nbuf += (kbytes - 65536) * 2 / (factor * 5);
393 if (maxbcache && nbuf > maxbcache / NBUFCALCSIZE)
394 nbuf = maxbcache / NBUFCALCSIZE;
398 * Do not allow the buffer_map to be more then 1/2 the size of the
401 if (nbuf > (virtual_end - virtual_start +
402 virtual2_end - virtual2_start) / (MAXBSIZE * 2)) {
403 nbuf = (virtual_end - virtual_start +
404 virtual2_end - virtual2_start) / (MAXBSIZE * 2);
405 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
409 * Do not allow the buffer_map to use more than 50% of available
410 * physical-equivalent memory. Since the VM pages which back
411 * individual buffers are typically wired, having too many bufs
412 * can prevent the system from paging properly.
414 if (nbuf > physmem * PAGE_SIZE / (NBUFCALCSIZE * 2)) {
415 nbuf = physmem * PAGE_SIZE / (NBUFCALCSIZE * 2);
416 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
420 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
421 * the valloc space which is just the virtual_end - virtual_start
422 * section. We use valloc() to allocate the buf header array.
424 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
425 nbuf = (virtual_end - virtual_start) /
426 sizeof(struct buf) / 2;
427 kprintf("Warning: nbufs capped at %ld due to valloc "
428 "considerations\n", nbuf);
431 nswbuf_mem = lmax(lmin(nbuf / 32, 512), 8);
433 if (nswbuf_mem < NSWBUF_MIN)
434 nswbuf_mem = NSWBUF_MIN;
436 nswbuf_kva = lmax(lmin(nbuf / 4, 512), 16);
438 if (nswbuf_kva < NSWBUF_MIN)
439 nswbuf_kva = NSWBUF_MIN;
442 valloc(swbuf_mem, struct buf, nswbuf_mem);
443 valloc(swbuf_kva, struct buf, nswbuf_kva);
444 valloc(buf, struct buf, nbuf);
447 * End of first pass, size has been calculated so allocate memory
449 if (firstaddr == 0) {
450 size = (vm_size_t)(v - firstaddr);
451 firstaddr = kmem_alloc(&kernel_map, round_page(size),
454 panic("startup: no room for tables");
459 * End of second pass, addresses have been assigned
461 * nbuf is an int, make sure we don't overflow the field.
463 * On 64-bit systems we always reserve maximal allocations for
464 * buffer cache buffers and there are no fragmentation issues,
465 * so the KVA segment does not have to be excessively oversized.
467 if ((vm_size_t)(v - firstaddr) != size)
468 panic("startup: table size inconsistency");
470 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
471 ((vm_offset_t)(nbuf + 16) * MAXBSIZE) +
472 ((nswbuf_mem + nswbuf_kva) * MAXPHYS) + pager_map_size);
473 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
474 ((vm_offset_t)(nbuf + 16) * MAXBSIZE));
475 buffer_map.system_map = 1;
476 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
477 ((vm_offset_t)(nswbuf_mem + nswbuf_kva) * MAXPHYS) +
479 pager_map.system_map = 1;
480 kprintf("avail memory = %ju (%ju MB)\n",
481 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
482 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
486 struct cpu_idle_stat {
494 u_long mwait_cx[CPU_MWAIT_CX_MAX];
497 #define CPU_IDLE_STAT_HALT -1
498 #define CPU_IDLE_STAT_SPIN -2
500 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
503 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
505 int idx = arg2, cpu, error;
508 if (idx == CPU_IDLE_STAT_HALT) {
509 for (cpu = 0; cpu < ncpus; ++cpu)
510 val += cpu_idle_stats[cpu].halt;
511 } else if (idx == CPU_IDLE_STAT_SPIN) {
512 for (cpu = 0; cpu < ncpus; ++cpu)
513 val += cpu_idle_stats[cpu].spin;
515 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
516 ("invalid index %d", idx));
517 for (cpu = 0; cpu < ncpus; ++cpu)
518 val += cpu_idle_stats[cpu].mwait_cx[idx];
521 error = sysctl_handle_quad(oidp, &val, 0, req);
522 if (error || req->newptr == NULL)
525 if (idx == CPU_IDLE_STAT_HALT) {
526 for (cpu = 0; cpu < ncpus; ++cpu)
527 cpu_idle_stats[cpu].halt = 0;
528 cpu_idle_stats[0].halt = val;
529 } else if (idx == CPU_IDLE_STAT_SPIN) {
530 for (cpu = 0; cpu < ncpus; ++cpu)
531 cpu_idle_stats[cpu].spin = 0;
532 cpu_idle_stats[0].spin = val;
534 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
535 ("invalid index %d", idx));
536 for (cpu = 0; cpu < ncpus; ++cpu)
537 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
538 cpu_idle_stats[0].mwait_cx[idx] = val;
544 cpu_mwait_attach(void)
549 if (!CPU_MWAIT_HAS_CX)
552 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
553 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
554 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
555 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
559 * Pentium dual-core, Core 2 and beyond do not need any
560 * additional activities to enter deep C-state, i.e. C3(+).
562 cpu_mwait_cx_no_bmarb();
564 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
566 cpu_mwait_cx_no_bmsts();
569 sbuf_new(&sb, cpu_mwait_cx_supported,
570 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
572 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
573 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
576 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
578 sysctl_ctx_init(&cx->sysctl_ctx);
579 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
580 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
581 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
582 if (cx->sysctl_tree == NULL)
585 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
586 SYSCTL_ADD_INT(&cx->sysctl_ctx,
587 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
588 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
590 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
591 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
592 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
593 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
595 for (sub = 0; sub < cx->subcnt; ++sub)
596 sbuf_printf(&sb, "C%d/%d ", i, sub);
604 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
605 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
606 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
607 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
611 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
614 subcnt = cpu_mwait_cx_info[i].subcnt;
615 for (j = 0; j < subcnt; ++j) {
616 KASSERT(hint_idx < cpu_mwait_hints_cnt,
617 ("invalid mwait hint index %d", hint_idx));
618 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
622 KASSERT(hint_idx == cpu_mwait_hints_cnt,
623 ("mwait hint count %d != index %d",
624 cpu_mwait_hints_cnt, hint_idx));
627 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
628 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
629 int hint = cpu_mwait_hints[i];
631 kprintf(" C%d/%d hint 0x%04x\n",
632 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
640 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
641 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
642 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
646 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
649 subcnt = cpu_mwait_cx_info[i].subcnt;
650 for (j = 0; j < subcnt; ++j) {
651 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
652 ("invalid mwait deep hint index %d", hint_idx));
653 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
657 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
658 ("mwait deep hint count %d != index %d",
659 cpu_mwait_deep_hints_cnt, hint_idx));
662 kprintf("MWAIT deep hints:\n");
663 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
664 int hint = cpu_mwait_deep_hints[i];
666 kprintf(" C%d/%d hint 0x%04x\n",
667 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
671 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
673 for (i = 0; i < ncpus; ++i) {
676 ksnprintf(name, sizeof(name), "idle%d", i);
677 SYSCTL_ADD_PROC(NULL,
678 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO,
679 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i],
680 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", "");
685 cpu_finish(void *dummy __unused)
692 pic_finish(void *dummy __unused)
694 /* Log ELCR information */
697 /* Log MPTABLE information */
698 mptable_pci_int_dump();
701 MachIntrABI.finalize();
705 * Send an interrupt to process.
707 * Stack is set up to allow sigcode stored
708 * at top to call routine, followed by kcall
709 * to sigreturn routine below. After sigreturn
710 * resets the signal mask, the stack, and the
711 * frame pointer, it returns to the user
715 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
717 struct lwp *lp = curthread->td_lwp;
718 struct proc *p = lp->lwp_proc;
719 struct trapframe *regs;
720 struct sigacts *psp = p->p_sigacts;
721 struct sigframe sf, *sfp;
725 regs = lp->lwp_md.md_regs;
726 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
728 /* Save user context */
729 bzero(&sf, sizeof(struct sigframe));
730 sf.sf_uc.uc_sigmask = *mask;
731 sf.sf_uc.uc_stack = lp->lwp_sigstk;
732 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
733 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
734 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
736 /* Make the size of the saved context visible to userland */
737 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
739 /* Allocate and validate space for the signal handler context. */
740 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
741 SIGISMEMBER(psp->ps_sigonstack, sig)) {
742 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
743 sizeof(struct sigframe));
744 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
746 /* We take red zone into account */
747 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
751 * XXX AVX needs 64-byte alignment but sigframe has other fields and
752 * the embedded ucontext is not at the front, so aligning this won't
753 * help us. Fortunately we bcopy in/out of the sigframe, so the
756 * The problem though is if userland winds up trying to use the
759 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
761 /* Translate the signal is appropriate */
762 if (p->p_sysent->sv_sigtbl) {
763 if (sig <= p->p_sysent->sv_sigsize)
764 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
768 * Build the argument list for the signal handler.
770 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
772 regs->tf_rdi = sig; /* argument 1 */
773 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
775 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
777 * Signal handler installed with SA_SIGINFO.
779 * action(signo, siginfo, ucontext)
781 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
782 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
783 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
785 /* fill siginfo structure */
786 sf.sf_si.si_signo = sig;
787 sf.sf_si.si_code = code;
788 sf.sf_si.si_addr = (void *)regs->tf_addr;
791 * Old FreeBSD-style arguments.
793 * handler (signo, code, [uc], addr)
795 regs->tf_rsi = (register_t)code; /* argument 2 */
796 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
797 sf.sf_ahu.sf_handler = catcher;
801 * If we're a vm86 process, we want to save the segment registers.
802 * We also change eflags to be our emulated eflags, not the actual
806 if (regs->tf_eflags & PSL_VM) {
807 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
808 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
810 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
811 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
812 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
813 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
815 if (vm86->vm86_has_vme == 0)
816 sf.sf_uc.uc_mcontext.mc_eflags =
817 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
818 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
821 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
822 * syscalls made by the signal handler. This just avoids
823 * wasting time for our lazy fixup of such faults. PSL_NT
824 * does nothing in vm86 mode, but vm86 programs can set it
825 * almost legitimately in probes for old cpu types.
827 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
832 * Save the FPU state and reinit the FP unit
834 npxpush(&sf.sf_uc.uc_mcontext);
837 * Copy the sigframe out to the user's stack.
839 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
841 * Something is wrong with the stack pointer.
842 * ...Kill the process.
847 regs->tf_rsp = (register_t)sfp;
848 regs->tf_rip = trunc_page64(PS_STRINGS - *(p->p_sysent->sv_szsigcode));
849 regs->tf_rip -= SZSIGCODE_EXTRA_BYTES;
852 * i386 abi specifies that the direction flag must be cleared
855 regs->tf_rflags &= ~(PSL_T | PSL_D);
858 * 64 bit mode has a code and stack selector but
859 * no data or extra selector. %fs and %gs are not
862 regs->tf_cs = _ucodesel;
863 regs->tf_ss = _udatasel;
868 * Sanitize the trapframe for a virtual kernel passing control to a custom
869 * VM context. Remove any items that would otherwise create a privilage
872 * XXX at the moment we allow userland to set the resume flag. Is this a
876 cpu_sanitize_frame(struct trapframe *frame)
878 frame->tf_cs = _ucodesel;
879 frame->tf_ss = _udatasel;
880 /* XXX VM (8086) mode not supported? */
881 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
882 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
888 * Sanitize the tls so loading the descriptor does not blow up
889 * on us. For x86_64 we don't have to do anything.
892 cpu_sanitize_tls(struct savetls *tls)
898 * sigreturn(ucontext_t *sigcntxp)
900 * System call to cleanup state after a signal
901 * has been taken. Reset signal mask and
902 * stack state from context left by sendsig (above).
903 * Return to previous pc and psl as specified by
904 * context left by sendsig. Check carefully to
905 * make sure that the user has not modified the
906 * state to gain improper privileges.
910 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
911 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
914 sys_sigreturn(struct sigreturn_args *uap)
916 struct lwp *lp = curthread->td_lwp;
917 struct trapframe *regs;
925 * We have to copy the information into kernel space so userland
926 * can't modify it while we are sniffing it.
928 regs = lp->lwp_md.md_regs;
929 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
933 rflags = ucp->uc_mcontext.mc_rflags;
935 /* VM (8086) mode not supported */
936 rflags &= ~PSL_VM_UNSUPP;
939 if (eflags & PSL_VM) {
940 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
941 struct vm86_kernel *vm86;
944 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
945 * set up the vm86 area, and we can't enter vm86 mode.
947 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
949 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
950 if (vm86->vm86_inited == 0)
953 /* go back to user mode if both flags are set */
954 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
955 trapsignal(lp, SIGBUS, 0);
957 if (vm86->vm86_has_vme) {
958 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
959 (eflags & VME_USERCHANGE) | PSL_VM;
961 vm86->vm86_eflags = eflags; /* save VIF, VIP */
962 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
963 (eflags & VM_USERCHANGE) | PSL_VM;
965 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
966 tf->tf_eflags = eflags;
967 tf->tf_vm86_ds = tf->tf_ds;
968 tf->tf_vm86_es = tf->tf_es;
969 tf->tf_vm86_fs = tf->tf_fs;
970 tf->tf_vm86_gs = tf->tf_gs;
971 tf->tf_ds = _udatasel;
972 tf->tf_es = _udatasel;
973 tf->tf_fs = _udatasel;
974 tf->tf_gs = _udatasel;
979 * Don't allow users to change privileged or reserved flags.
982 * XXX do allow users to change the privileged flag PSL_RF.
983 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
984 * should sometimes set it there too. tf_eflags is kept in
985 * the signal context during signal handling and there is no
986 * other place to remember it, so the PSL_RF bit may be
987 * corrupted by the signal handler without us knowing.
988 * Corruption of the PSL_RF bit at worst causes one more or
989 * one less debugger trap, so allowing it is fairly harmless.
991 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
992 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
997 * Don't allow users to load a valid privileged %cs. Let the
998 * hardware check for invalid selectors, excess privilege in
999 * other selectors, invalid %eip's and invalid %esp's.
1001 cs = ucp->uc_mcontext.mc_cs;
1002 if (!CS_SECURE(cs)) {
1003 kprintf("sigreturn: cs = 0x%x\n", cs);
1004 trapsignal(lp, SIGBUS, T_PROTFLT);
1007 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
1011 * Restore the FPU state from the frame
1014 npxpop(&ucp->uc_mcontext);
1016 if (ucp->uc_mcontext.mc_onstack & 1)
1017 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1019 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1021 lp->lwp_sigmask = ucp->uc_sigmask;
1022 SIG_CANTMASK(lp->lwp_sigmask);
1025 return(EJUSTRETURN);
1029 * Machine dependent boot() routine
1031 * I haven't seen anything to put here yet
1032 * Possibly some stuff might be grafted back here from boot()
1040 * Shutdown the CPU as much as possible
1046 __asm__ __volatile("hlt");
1050 * cpu_idle() represents the idle LWKT. You cannot return from this function
1051 * (unless you want to blow things up!). Instead we look for runnable threads
1052 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1054 * The main loop is entered with a critical section held, we must release
1055 * the critical section before doing anything else. lwkt_switch() will
1056 * check for pending interrupts due to entering and exiting its own
1059 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1060 * However, there are cases where the idlethread will be entered with
1061 * the possibility that no IPI will occur and in such cases
1062 * lwkt_switch() sets TDF_IDLE_NOHLT.
1064 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1065 * must occur before it starts using ACPI halt.
1067 * NOTE: Value overridden in hammer_time().
1069 static int cpu_idle_hlt = 2;
1070 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1071 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1072 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1073 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1075 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1076 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1077 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1078 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1081 cpu_idle_default_hook(void)
1084 * We must guarentee that hlt is exactly the instruction
1085 * following the sti.
1087 __asm __volatile("sti; hlt");
1090 /* Other subsystems (e.g., ACPI) can hook this later. */
1091 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1094 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1103 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1104 cpu_mwait_repeat_shift;
1105 if (idx >= cpu_mwait_c1_hints_cnt) {
1106 /* Step up faster, once we walked through all C1 states */
1107 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1109 if (hint == CPU_MWAIT_HINT_AUTODEEP) {
1110 if (idx >= cpu_mwait_deep_hints_cnt)
1111 idx = cpu_mwait_deep_hints_cnt - 1;
1112 hint = cpu_mwait_deep_hints[idx];
1114 if (idx >= cpu_mwait_hints_cnt)
1115 idx = cpu_mwait_hints_cnt - 1;
1116 hint = cpu_mwait_hints[idx];
1119 cx_idx = MWAIT_EAX_TO_CX(hint);
1120 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1121 stat->mwait_cx[cx_idx]++;
1128 globaldata_t gd = mycpu;
1129 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1130 struct thread *td __debugvar = gd->gd_curthread;
1134 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1137 KKASSERT(td->td_critcount == 0);
1141 * See if there are any LWKTs ready to go.
1146 * When halting inside a cli we must check for reqflags
1147 * races, particularly [re]schedule requests. Running
1148 * splz() does the job.
1151 * 0 Never halt, just spin
1153 * 1 Always use MONITOR/MWAIT if avail, HLT
1156 * Better default for modern (Haswell+) Intel
1159 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1160 * use the ACPI halt (default). This is a hybrid
1161 * approach. See machdep.cpu_idle_repeat.
1163 * Better default for modern AMD cpus and older
1166 * 3 Always use the ACPI halt. This typically
1167 * eats the least amount of power but the cpu
1168 * will be slow waking up. Slows down e.g.
1169 * compiles and other pipe/event oriented stuff.
1171 * Usually the best default for AMD cpus.
1177 * NOTE: Interrupts are enabled and we are not in a critical
1180 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1181 * don't bother capping gd_idle_repeat, it is ok if
1184 * Implement optimized invltlb operations when halted
1185 * in idle. By setting the bit in smp_idleinvl_mask
1186 * we inform other cpus that they can set _reqs to
1187 * request an invltlb. Current the code to do that
1188 * sets the bits in _reqs anyway, but then check _mask
1189 * to determine if they can assume the invltlb will execute.
1191 * A critical section is required to ensure that interrupts
1192 * do not fully run until after we've had a chance to execute
1195 if (gd->gd_idle_repeat == 0) {
1196 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1197 if (stat->repeat > cpu_idle_repeat_max)
1198 stat->repeat = cpu_idle_repeat_max;
1199 stat->repeat_last = 0;
1200 stat->repeat_delta = 0;
1202 ++stat->repeat_last;
1204 ++gd->gd_idle_repeat;
1205 reqflags = gd->gd_reqflags;
1206 quick = (cpu_idle_hlt == 1) ||
1207 (cpu_idle_hlt == 2 &&
1208 gd->gd_idle_repeat < cpu_idle_repeat);
1210 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1211 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1214 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid);
1215 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1216 cpu_mwait_cx_hint(stat), 0);
1218 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid);
1219 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs,
1225 } else if (cpu_idle_hlt) {
1226 __asm __volatile("cli");
1229 ATOMIC_CPUMASK_ORBIT(smp_idleinvl_mask, gd->gd_cpuid);
1230 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1231 if (cpu_idle_hlt == 5) {
1232 __asm __volatile("sti");
1233 } else if (quick || cpu_idle_hlt == 4) {
1234 cpu_idle_default_hook();
1239 __asm __volatile("sti");
1241 ATOMIC_CPUMASK_NANDBIT(smp_idleinvl_mask, gd->gd_cpuid);
1242 if (ATOMIC_CPUMASK_TESTANDCLR(smp_idleinvl_reqs,
1250 __asm __volatile("sti");
1259 * Called in a loop indirectly via Xcpustop
1262 cpu_smp_stopped(void)
1264 globaldata_t gd = mycpu;
1265 volatile __uint64_t *ptr;
1268 ptr = CPUMASK_ADDR(started_cpus, gd->gd_cpuid);
1270 if ((ovalue & CPUMASK_SIMPLE(gd->gd_cpuid & 63)) == 0) {
1271 if (cpu_mi_feature & CPU_MI_MONITOR) {
1272 if (cpu_mwait_hints) {
1273 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr),
1275 cpu_mwait_hints[CPU_MWAIT_C1], 0);
1277 cpu_mmw_pause_long(__DEVOLATILE(void *, ptr),
1281 cpu_halt(); /* depend on lapic timer */
1287 * This routine is called if a spinlock has been held through the
1288 * exponential backoff period and is seriously contested. On a real cpu
1292 cpu_spinlock_contested(void)
1298 * Clear registers on exec
1301 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1303 struct thread *td = curthread;
1304 struct lwp *lp = td->td_lwp;
1305 struct pcb *pcb = td->td_pcb;
1306 struct trapframe *regs = lp->lwp_md.md_regs;
1308 /* was i386_user_cleanup() in NetBSD */
1312 bzero((char *)regs, sizeof(struct trapframe));
1313 regs->tf_rip = entry;
1314 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1315 regs->tf_rdi = stack; /* argv */
1316 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1317 regs->tf_ss = _udatasel;
1318 regs->tf_cs = _ucodesel;
1319 regs->tf_rbx = ps_strings;
1322 * Reset the hardware debug registers if they were in use.
1323 * They won't have any meaning for the newly exec'd process.
1325 if (pcb->pcb_flags & PCB_DBREGS) {
1331 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1332 if (pcb == td->td_pcb) {
1334 * Clear the debug registers on the running
1335 * CPU, otherwise they will end up affecting
1336 * the next process we switch to.
1340 pcb->pcb_flags &= ~PCB_DBREGS;
1344 * Initialize the math emulator (if any) for the current process.
1345 * Actually, just clear the bit that says that the emulator has
1346 * been initialized. Initialization is delayed until the process
1347 * traps to the emulator (if it is done at all) mainly because
1348 * emulators don't provide an entry point for initialization.
1350 pcb->pcb_flags &= ~FP_SOFTFP;
1353 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1354 * gd_npxthread. Otherwise a preemptive interrupt thread
1355 * may panic in npxdna().
1358 load_cr0(rcr0() | CR0_MP);
1361 * NOTE: The MSR values must be correct so we can return to
1362 * userland. gd_user_fs/gs must be correct so the switch
1363 * code knows what the current MSR values are.
1365 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1366 pcb->pcb_gsbase = 0;
1367 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1368 mdcpu->gd_user_gs = 0;
1369 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1370 wrmsr(MSR_KGSBASE, 0);
1372 /* Initialize the npx (if any) for the current process. */
1376 pcb->pcb_ds = _udatasel;
1377 pcb->pcb_es = _udatasel;
1378 pcb->pcb_fs = _udatasel;
1379 pcb->pcb_gs = _udatasel;
1388 cr0 |= CR0_NE; /* Done by npxinit() */
1389 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1390 cr0 |= CR0_WP | CR0_AM;
1396 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1399 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1401 if (!error && req->newptr)
1406 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1407 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1409 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1410 CTLFLAG_RW, &disable_rtc_set, 0, "");
1413 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1414 CTLFLAG_RD, &bootinfo, bootinfo, "");
1417 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1418 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1421 efi_map_sysctl_handler(SYSCTL_HANDLER_ARGS)
1423 struct efi_map_header *efihdr;
1427 kmdp = preload_search_by_type("elf kernel");
1429 kmdp = preload_search_by_type("elf64 kernel");
1430 efihdr = (struct efi_map_header *)preload_search_info(kmdp,
1431 MODINFO_METADATA | MODINFOMD_EFI_MAP);
1434 efisize = *((uint32_t *)efihdr - 1);
1435 return (SYSCTL_OUT(req, efihdr, efisize));
1437 SYSCTL_PROC(_machdep, OID_AUTO, efi_map, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0,
1438 efi_map_sysctl_handler, "S,efi_map_header", "Raw EFI Memory Map");
1441 * Initialize 386 and configure to run kernel
1445 * Initialize segments & interrupt table
1449 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1450 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1452 union descriptor ldt[NLDT]; /* local descriptor table */
1455 /* table descriptors - used to load tables by cpu */
1456 struct region_descriptor r_gdt;
1457 struct region_descriptor r_idt_arr[MAXCPU];
1459 /* JG proc0paddr is a virtual address */
1462 char proc0paddr_buff[LWKT_THREAD_STACK];
1465 /* software prototypes -- in more palatable form */
1466 struct soft_segment_descriptor gdt_segs[] = {
1467 /* GNULL_SEL 0 Null Descriptor */
1468 { 0x0, /* segment base address */
1470 0, /* segment type */
1471 0, /* segment descriptor priority level */
1472 0, /* segment descriptor present */
1474 0, /* default 32 vs 16 bit size */
1475 0 /* limit granularity (byte/page units)*/ },
1476 /* GCODE_SEL 1 Code Descriptor for kernel */
1477 { 0x0, /* segment base address */
1478 0xfffff, /* length - all address space */
1479 SDT_MEMERA, /* segment type */
1480 SEL_KPL, /* segment descriptor priority level */
1481 1, /* segment descriptor present */
1483 0, /* default 32 vs 16 bit size */
1484 1 /* limit granularity (byte/page units)*/ },
1485 /* GDATA_SEL 2 Data Descriptor for kernel */
1486 { 0x0, /* segment base address */
1487 0xfffff, /* length - all address space */
1488 SDT_MEMRWA, /* segment type */
1489 SEL_KPL, /* segment descriptor priority level */
1490 1, /* segment descriptor present */
1492 0, /* default 32 vs 16 bit size */
1493 1 /* limit granularity (byte/page units)*/ },
1494 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1495 { 0x0, /* segment base address */
1496 0xfffff, /* length - all address space */
1497 SDT_MEMERA, /* segment type */
1498 SEL_UPL, /* segment descriptor priority level */
1499 1, /* segment descriptor present */
1501 1, /* default 32 vs 16 bit size */
1502 1 /* limit granularity (byte/page units)*/ },
1503 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1504 { 0x0, /* segment base address */
1505 0xfffff, /* length - all address space */
1506 SDT_MEMRWA, /* segment type */
1507 SEL_UPL, /* segment descriptor priority level */
1508 1, /* segment descriptor present */
1510 1, /* default 32 vs 16 bit size */
1511 1 /* limit granularity (byte/page units)*/ },
1512 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1513 { 0x0, /* segment base address */
1514 0xfffff, /* length - all address space */
1515 SDT_MEMERA, /* segment type */
1516 SEL_UPL, /* segment descriptor priority level */
1517 1, /* segment descriptor present */
1519 0, /* default 32 vs 16 bit size */
1520 1 /* limit granularity (byte/page units)*/ },
1521 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1523 0x0, /* segment base address */
1524 sizeof(struct x86_64tss)-1,/* length - all address space */
1525 SDT_SYSTSS, /* segment type */
1526 SEL_KPL, /* segment descriptor priority level */
1527 1, /* segment descriptor present */
1529 0, /* unused - default 32 vs 16 bit size */
1530 0 /* limit granularity (byte/page units)*/ },
1531 /* Actually, the TSS is a system descriptor which is double size */
1532 { 0x0, /* segment base address */
1534 0, /* segment type */
1535 0, /* segment descriptor priority level */
1536 0, /* segment descriptor present */
1538 0, /* default 32 vs 16 bit size */
1539 0 /* limit granularity (byte/page units)*/ },
1540 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1541 { 0x0, /* segment base address */
1542 0xfffff, /* length - all address space */
1543 SDT_MEMRWA, /* segment type */
1544 SEL_UPL, /* segment descriptor priority level */
1545 1, /* segment descriptor present */
1547 1, /* default 32 vs 16 bit size */
1548 1 /* limit granularity (byte/page units)*/ },
1552 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1556 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1557 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1559 ip->gd_looffset = (uintptr_t)func;
1560 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1566 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1571 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1573 struct gate_descriptor *ip;
1575 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1577 ip = &idt_arr[cpu][idx];
1578 ip->gd_looffset = (uintptr_t)func;
1579 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1585 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1588 #define IDTVEC(name) __CONCAT(X,name)
1591 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1592 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1593 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1594 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1595 IDTVEC(xmm), IDTVEC(dblfault),
1596 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1599 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1601 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1602 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1603 ssd->ssd_type = sd->sd_type;
1604 ssd->ssd_dpl = sd->sd_dpl;
1605 ssd->ssd_p = sd->sd_p;
1606 ssd->ssd_def32 = sd->sd_def32;
1607 ssd->ssd_gran = sd->sd_gran;
1611 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1614 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1615 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1616 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1617 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1618 sd->sd_type = ssd->ssd_type;
1619 sd->sd_dpl = ssd->ssd_dpl;
1620 sd->sd_p = ssd->ssd_p;
1621 sd->sd_long = ssd->ssd_long;
1622 sd->sd_def32 = ssd->ssd_def32;
1623 sd->sd_gran = ssd->ssd_gran;
1627 ssdtosyssd(struct soft_segment_descriptor *ssd,
1628 struct system_segment_descriptor *sd)
1631 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1632 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1633 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1634 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1635 sd->sd_type = ssd->ssd_type;
1636 sd->sd_dpl = ssd->ssd_dpl;
1637 sd->sd_p = ssd->ssd_p;
1638 sd->sd_gran = ssd->ssd_gran;
1642 * Populate the (physmap) array with base/bound pairs describing the
1643 * available physical memory in the system, then test this memory and
1644 * build the phys_avail array describing the actually-available memory.
1646 * If we cannot accurately determine the physical memory map, then use
1647 * value from the 0xE801 call, and failing that, the RTC.
1649 * Total memory size may be set by the kernel environment variable
1650 * hw.physmem or the compile-time define MAXMEM.
1652 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1653 * of PAGE_SIZE. This also greatly reduces the memory test time
1654 * which would otherwise be excessive on machines with > 8G of ram.
1656 * XXX first should be vm_paddr_t.
1659 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1660 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1661 #define PHYSMAP_SIZE VM_PHYSSEG_MAX
1663 vm_paddr_t physmap[PHYSMAP_SIZE];
1664 struct bios_smap *smapbase, *smap, *smapend;
1665 struct efi_map_header *efihdrbase;
1668 #define PHYSMAP_HANDWAVE (vm_paddr_t)(2 * 1024 * 1024)
1669 #define PHYSMAP_HANDWAVE_MASK (PHYSMAP_HANDWAVE - 1)
1672 add_smap_entries(int *physmap_idx)
1676 smapsize = *((u_int32_t *)smapbase - 1);
1677 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1679 for (smap = smapbase; smap < smapend; smap++) {
1680 if (boothowto & RB_VERBOSE)
1681 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1682 smap->type, smap->base, smap->length);
1684 if (smap->type != SMAP_TYPE_MEMORY)
1687 if (smap->length == 0)
1690 for (i = 0; i <= *physmap_idx; i += 2) {
1691 if (smap->base < physmap[i + 1]) {
1692 if (boothowto & RB_VERBOSE) {
1693 kprintf("Overlapping or non-monotonic "
1694 "memory region, ignoring "
1700 if (i <= *physmap_idx)
1703 Realmem += smap->length;
1705 if (smap->base == physmap[*physmap_idx + 1]) {
1706 physmap[*physmap_idx + 1] += smap->length;
1711 if (*physmap_idx == PHYSMAP_SIZE) {
1712 kprintf("Too many segments in the physical "
1713 "address map, giving up\n");
1716 physmap[*physmap_idx] = smap->base;
1717 physmap[*physmap_idx + 1] = smap->base + smap->length;
1722 add_efi_map_entries(int *physmap_idx)
1724 struct efi_md *map, *p;
1729 static const char *types[] = {
1735 "RuntimeServicesCode",
1736 "RuntimeServicesData",
1737 "ConventionalMemory",
1739 "ACPIReclaimMemory",
1742 "MemoryMappedIOPortSpace",
1747 * Memory map data provided by UEFI via the GetMemoryMap
1748 * Boot Services API.
1750 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf;
1751 map = (struct efi_md *)((uint8_t *)efihdrbase + efisz);
1753 if (efihdrbase->descriptor_size == 0)
1755 ndesc = efihdrbase->memory_size / efihdrbase->descriptor_size;
1757 if (boothowto & RB_VERBOSE)
1758 kprintf("%23s %12s %12s %8s %4s\n",
1759 "Type", "Physical", "Virtual", "#Pages", "Attr");
1761 for (i = 0, p = map; i < ndesc; i++,
1762 p = efi_next_descriptor(p, efihdrbase->descriptor_size)) {
1763 if (boothowto & RB_VERBOSE) {
1764 if (p->md_type <= EFI_MD_TYPE_PALCODE)
1765 type = types[p->md_type];
1768 kprintf("%23s %012lx %12p %08lx ", type, p->md_phys,
1769 p->md_virt, p->md_pages);
1770 if (p->md_attr & EFI_MD_ATTR_UC)
1772 if (p->md_attr & EFI_MD_ATTR_WC)
1774 if (p->md_attr & EFI_MD_ATTR_WT)
1776 if (p->md_attr & EFI_MD_ATTR_WB)
1778 if (p->md_attr & EFI_MD_ATTR_UCE)
1780 if (p->md_attr & EFI_MD_ATTR_WP)
1782 if (p->md_attr & EFI_MD_ATTR_RP)
1784 if (p->md_attr & EFI_MD_ATTR_XP)
1786 if (p->md_attr & EFI_MD_ATTR_RT)
1791 switch (p->md_type) {
1792 case EFI_MD_TYPE_CODE:
1793 case EFI_MD_TYPE_DATA:
1794 case EFI_MD_TYPE_BS_CODE:
1795 case EFI_MD_TYPE_BS_DATA:
1796 case EFI_MD_TYPE_FREE:
1798 * We're allowed to use any entry with these types.
1805 Realmem += p->md_pages * PAGE_SIZE;
1807 if (p->md_phys == physmap[*physmap_idx + 1]) {
1808 physmap[*physmap_idx + 1] += p->md_pages * PAGE_SIZE;
1813 if (*physmap_idx == PHYSMAP_SIZE) {
1814 kprintf("Too many segments in the physical "
1815 "address map, giving up\n");
1818 physmap[*physmap_idx] = p->md_phys;
1819 physmap[*physmap_idx + 1] = p->md_phys + p->md_pages * PAGE_SIZE;
1823 struct fb_info efi_fb_info;
1824 static int have_efi_framebuffer = 0;
1827 efi_fb_init_vaddr(int direct_map)
1830 vm_offset_t addr, v;
1832 v = efi_fb_info.vaddr;
1833 sz = efi_fb_info.stride * efi_fb_info.height;
1836 addr = PHYS_TO_DMAP(efi_fb_info.paddr);
1837 if (addr >= DMAP_MIN_ADDRESS && addr + sz < DMAP_MAX_ADDRESS)
1838 efi_fb_info.vaddr = addr;
1840 efi_fb_info.vaddr = (vm_offset_t)pmap_mapdev_attr(
1841 efi_fb_info.paddr, sz, PAT_WRITE_COMBINING);
1846 efifb_color_depth(struct efi_fb *efifb)
1851 mask = efifb->fb_mask_red | efifb->fb_mask_green |
1852 efifb->fb_mask_blue | efifb->fb_mask_reserved;
1855 for (depth = 1; mask != 1; depth++)
1861 probe_efi_fb(int early)
1863 struct efi_fb *efifb;
1867 if (have_efi_framebuffer) {
1869 (efi_fb_info.vaddr == 0 ||
1870 efi_fb_info.vaddr == PHYS_TO_DMAP(efi_fb_info.paddr)))
1871 efi_fb_init_vaddr(0);
1875 kmdp = preload_search_by_type("elf kernel");
1877 kmdp = preload_search_by_type("elf64 kernel");
1878 efifb = (struct efi_fb *)preload_search_info(kmdp,
1879 MODINFO_METADATA | MODINFOMD_EFI_FB);
1883 depth = efifb_color_depth(efifb);
1885 * Our bootloader should already notice, when we won't be able to
1886 * use the UEFI framebuffer.
1888 if (depth != 24 && depth != 32)
1891 have_efi_framebuffer = 1;
1893 efi_fb_info.is_vga_boot_display = 1;
1894 efi_fb_info.width = efifb->fb_width;
1895 efi_fb_info.height = efifb->fb_height;
1896 efi_fb_info.depth = depth;
1897 efi_fb_info.stride = efifb->fb_stride * (depth / 8);
1898 efi_fb_info.paddr = efifb->fb_addr;
1900 efi_fb_info.vaddr = 0;
1902 efi_fb_init_vaddr(0);
1904 efi_fb_info.fbops.fb_set_par = NULL;
1905 efi_fb_info.fbops.fb_blank = NULL;
1906 efi_fb_info.fbops.fb_debug_enter = NULL;
1907 efi_fb_info.device = NULL;
1913 efifb_startup(void *arg)
1918 SYSINIT(efi_fb_info, SI_BOOT1_POST, SI_ORDER_FIRST, efifb_startup, NULL);
1921 getmemsize(caddr_t kmdp, u_int64_t first)
1923 int off, physmap_idx, pa_indx, da_indx;
1926 vm_paddr_t msgbuf_size;
1927 u_long physmem_tunable;
1929 quad_t dcons_addr, dcons_size;
1931 bzero(physmap, sizeof(physmap));
1935 * get memory map from INT 15:E820, kindly supplied by the loader.
1937 * subr_module.c says:
1938 * "Consumer may safely assume that size value precedes data."
1939 * ie: an int32_t immediately precedes smap.
1941 efihdrbase = (struct efi_map_header *)preload_search_info(kmdp,
1942 MODINFO_METADATA | MODINFOMD_EFI_MAP);
1943 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1944 MODINFO_METADATA | MODINFOMD_SMAP);
1945 if (smapbase == NULL && efihdrbase == NULL)
1946 panic("No BIOS smap or EFI map info from loader!");
1948 if (efihdrbase == NULL)
1949 add_smap_entries(&physmap_idx);
1951 add_efi_map_entries(&physmap_idx);
1953 base_memory = physmap[1] / 1024;
1954 /* make hole for AP bootstrap code */
1955 physmap[1] = mp_bootaddress(base_memory);
1957 /* Save EBDA address, if any */
1958 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1962 * Maxmem isn't the "maximum memory", it's one larger than the
1963 * highest page of the physical address space. It should be
1964 * called something like "Maxphyspage". We may adjust this
1965 * based on ``hw.physmem'' and the results of the memory test.
1967 Maxmem = atop(physmap[physmap_idx + 1]);
1970 Maxmem = MAXMEM / 4;
1973 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1974 Maxmem = atop(physmem_tunable);
1977 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1980 if (Maxmem > atop(physmap[physmap_idx + 1]))
1981 Maxmem = atop(physmap[physmap_idx + 1]);
1984 * Blowing out the DMAP will blow up the system.
1986 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1987 kprintf("Limiting Maxmem due to DMAP size\n");
1988 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1991 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1992 (boothowto & RB_VERBOSE)) {
1993 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1997 * Call pmap initialization to make new kernel address space
2001 pmap_bootstrap(&first);
2002 physmap[0] = PAGE_SIZE;
2005 * Align the physmap to PHYSMAP_ALIGN and cut out anything
2008 for (i = j = 0; i <= physmap_idx; i += 2) {
2009 if (physmap[i+1] > ptoa(Maxmem))
2010 physmap[i+1] = ptoa(Maxmem);
2011 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
2012 ~PHYSMAP_ALIGN_MASK;
2013 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
2015 physmap[j] = physmap[i];
2016 physmap[j+1] = physmap[i+1];
2018 if (physmap[i] < physmap[i+1])
2021 physmap_idx = j - 2;
2024 * Align anything else used in the validation loop.
2026 * Also make sure that our 2MB kernel text+data+bss mappings
2027 * do not overlap potentially allocatable space.
2029 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
2032 * Size up each available chunk of physical memory.
2036 phys_avail[pa_indx].phys_beg = physmap[0];
2037 phys_avail[pa_indx].phys_end = physmap[0];
2038 dump_avail[da_indx].phys_beg = 0;
2039 dump_avail[da_indx].phys_end = physmap[0];
2043 * Get dcons buffer address
2045 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
2046 kgetenv_quad("dcons.size", &dcons_size) == 0)
2050 * Validate the physical memory. The physical memory segments
2051 * have already been aligned to PHYSMAP_ALIGN which is a multiple
2054 * We no longer perform an exhaustive memory test. Instead we
2055 * simply test the first and last word in each physmap[]
2058 for (i = 0; i <= physmap_idx; i += 2) {
2062 end = physmap[i + 1];
2064 for (pa = physmap[i]; pa < end; pa += incr) {
2066 volatile uint64_t *ptr = (uint64_t *)CADDR1;
2072 * Calculate incr. Just test the first and
2073 * last page in each physmap[] segment.
2075 if (pa == end - PAGE_SIZE)
2078 incr = end - pa - PAGE_SIZE;
2081 * Make sure we don't skip blacked out areas.
2083 if (pa < 0x200000 && 0x200000 < end) {
2084 incr = 0x200000 - pa;
2086 if (dcons_addr > 0 &&
2089 incr = dcons_addr - pa;
2093 * Block out kernel memory as not available.
2095 if (pa >= 0x200000 && pa < first) {
2101 * Block out the dcons buffer if it exists.
2103 if (dcons_addr > 0 &&
2104 pa >= trunc_page(dcons_addr) &&
2105 pa < dcons_addr + dcons_size) {
2106 incr = dcons_addr + dcons_size - pa;
2107 incr = (incr + PAGE_MASK) &
2108 ~(vm_paddr_t)PAGE_MASK;
2115 * Map the page non-cacheable for the memory
2119 kernel_pmap.pmap_bits[PG_V_IDX] |
2120 kernel_pmap.pmap_bits[PG_RW_IDX] |
2121 kernel_pmap.pmap_bits[PG_N_IDX];
2122 cpu_invlpg(__DEVOLATILE(void *, ptr));
2126 * Save original value for restoration later.
2131 * Test for alternating 1's and 0's
2133 *ptr = 0xaaaaaaaaaaaaaaaaLLU;
2135 if (*ptr != 0xaaaaaaaaaaaaaaaaLLU)
2138 * Test for alternating 0's and 1's
2140 *ptr = 0x5555555555555555LLU;
2142 if (*ptr != 0x5555555555555555LLU)
2147 *ptr = 0xffffffffffffffffLLU;
2149 if (*ptr != 0xffffffffffffffffLLU)
2160 * Restore original value.
2165 * Adjust array of valid/good pages.
2167 if (page_bad == TRUE) {
2173 * Collapse page address into phys_avail[]. Do a
2174 * continuation of the current phys_avail[] index
2177 if (phys_avail[pa_indx].phys_end == pa) {
2181 phys_avail[pa_indx].phys_end += incr;
2182 } else if (phys_avail[pa_indx].phys_beg ==
2183 phys_avail[pa_indx].phys_end) {
2185 * Current phys_avail is completely empty,
2188 phys_avail[pa_indx].phys_beg = pa;
2189 phys_avail[pa_indx].phys_end = pa + incr;
2192 * Allocate next phys_avail index.
2195 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
2197 "Too many holes in the physical address space, giving up\n");
2202 phys_avail[pa_indx].phys_beg = pa;
2203 phys_avail[pa_indx].phys_end = pa + incr;
2205 physmem += incr / PAGE_SIZE;
2208 * pa available for dumping
2211 if (dump_avail[da_indx].phys_end == pa) {
2212 dump_avail[da_indx].phys_end += incr;
2215 if (da_indx == DUMP_AVAIL_ARRAY_END) {
2219 dump_avail[da_indx].phys_beg = pa;
2220 dump_avail[da_indx].phys_end = pa + incr;
2232 * The last chunk must contain at least one page plus the message
2233 * buffer to avoid complicating other code (message buffer address
2234 * calculation, etc.).
2236 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
2238 while (phys_avail[pa_indx].phys_beg + PHYSMAP_ALIGN + msgbuf_size >=
2239 phys_avail[pa_indx].phys_end) {
2240 physmem -= atop(phys_avail[pa_indx].phys_end -
2241 phys_avail[pa_indx].phys_beg);
2242 phys_avail[pa_indx].phys_beg = 0;
2243 phys_avail[pa_indx].phys_end = 0;
2247 Maxmem = atop(phys_avail[pa_indx].phys_end);
2249 /* Trim off space for the message buffer. */
2250 phys_avail[pa_indx].phys_end -= msgbuf_size;
2252 avail_end = phys_avail[pa_indx].phys_end;
2254 /* Map the message buffer. */
2255 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
2256 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2258 /* Try to get EFI framebuffer working as early as possible */
2259 if (have_efi_framebuffer)
2260 efi_fb_init_vaddr(1);
2263 struct machintr_abi MachIntrABI;
2274 * 7 Device Not Available (x87)
2276 * 9 Coprocessor Segment overrun (unsupported, reserved)
2278 * 11 Segment not present
2280 * 13 General Protection
2283 * 16 x87 FP Exception pending
2284 * 17 Alignment Check
2286 * 19 SIMD floating point
2288 * 32-255 INTn/external sources
2291 hammer_time(u_int64_t modulep, u_int64_t physfree)
2294 int gsel_tss, x, cpu;
2296 int metadata_missing, off;
2298 struct mdglobaldata *gd;
2302 * Prevent lowering of the ipl if we call tsleep() early.
2304 gd = &CPU_prvspace[0]->mdglobaldata;
2305 bzero(gd, sizeof(*gd));
2308 * Note: on both UP and SMP curthread must be set non-NULL
2309 * early in the boot sequence because the system assumes
2310 * that 'curthread' is never NULL.
2313 gd->mi.gd_curthread = &thread0;
2314 thread0.td_gd = &gd->mi;
2316 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
2319 metadata_missing = 0;
2320 if (bootinfo.bi_modulep) {
2321 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
2322 preload_bootstrap_relocate(KERNBASE);
2324 metadata_missing = 1;
2326 if (bootinfo.bi_envp)
2327 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
2330 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
2331 preload_bootstrap_relocate(PTOV_OFFSET);
2332 kmdp = preload_search_by_type("elf kernel");
2334 kmdp = preload_search_by_type("elf64 kernel");
2335 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
2336 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
2338 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
2339 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
2341 efi_systbl_phys = MD_FETCH(kmdp, MODINFOMD_FW_HANDLE, vm_paddr_t);
2343 if (boothowto & RB_VERBOSE)
2347 * Default MachIntrABI to ICU
2349 MachIntrABI = MachIntrABI_ICU;
2352 * start with one cpu. Note: with one cpu, ncpus_fit_mask remain 0.
2356 /* Init basic tunables, hz etc */
2360 * make gdt memory segments
2362 gdt_segs[GPROC0_SEL].ssd_base =
2363 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss;
2365 gd->mi.gd_prvspace = CPU_prvspace[0];
2367 for (x = 0; x < NGDT; x++) {
2368 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
2369 ssdtosd(&gdt_segs[x], &gdt[x]);
2371 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2372 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
2374 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2375 r_gdt.rd_base = (long) gdt;
2378 wrmsr(MSR_FSBASE, 0); /* User value */
2379 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
2380 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
2382 mi_gdinit(&gd->mi, 0);
2384 proc0paddr = proc0paddr_buff;
2385 mi_proc0init(&gd->mi, proc0paddr);
2386 safepri = TDPRI_MAX;
2388 /* spinlocks and the BGL */
2392 for (x = 0; x < NIDT; x++)
2393 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2394 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2395 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2396 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2397 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2398 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2399 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2400 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2401 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2402 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2403 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2404 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2405 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2406 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2407 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2408 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2409 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2410 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2411 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2412 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2414 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2415 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2416 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2419 lidt(&r_idt_arr[0]);
2422 * Initialize the console before we print anything out.
2427 if (metadata_missing)
2428 kprintf("WARNING: loader(8) metadata is missing!\n");
2438 * Initialize IRQ mapping
2441 * SHOULD be after elcr_probe()
2443 MachIntrABI_ICU.initmap();
2444 MachIntrABI_IOAPIC.initmap();
2448 if (boothowto & RB_KDB)
2449 Debugger("Boot flags requested debugger");
2453 finishidentcpu(); /* Final stage of CPU initialization */
2454 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2455 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2457 identify_cpu(); /* Final stage of CPU initialization */
2458 initializecpu(0); /* Initialize CPU registers */
2461 * On modern Intel cpus, haswell or later, cpu_idle_hlt=1 is better
2462 * because the cpu does significant power management in MWAIT
2463 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP).
2465 * On modern AMD cpus cpu_idle_hlt=3 is better, because the cpu does
2466 * significant power management only when using ACPI halt mode.
2468 * On older AMD or Intel cpus, cpu_idle_hlt=2 is better because ACPI
2469 * is needed to reduce power consumption, but wakeup times are often
2472 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
2473 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */
2476 if (cpu_vendor_id == CPU_VENDOR_AMD) {
2477 if (CPUID_TO_FAMILY(cpu_id) >= 0x17) {
2478 /* Ryzen or later */
2480 } else if (CPUID_TO_FAMILY(cpu_id) >= 0x14) {
2481 /* Bobcat or later */
2486 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2487 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2488 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2489 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt);
2492 * Some of the virtual machines do not work w/ I/O APIC
2493 * enabled. If the user does not explicitly enable or
2494 * disable the I/O APIC (ioapic_enable < 0), then we
2495 * disable I/O APIC on all virtual machines.
2498 * This must be done after identify_cpu(), which sets
2501 if (ioapic_enable < 0) {
2502 if (cpu_feature2 & CPUID2_VMM)
2508 /* make an initial tss so cpu can get interrupt stack on syscall! */
2509 gd->gd_common_tss.tss_rsp0 =
2510 (register_t)(thread0.td_kstack +
2511 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2512 /* Ensure the stack is aligned to 16 bytes */
2513 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2515 /* double fault stack */
2516 gd->gd_common_tss.tss_ist1 =
2517 (long)&gd->mi.gd_prvspace->idlestack[
2518 sizeof(gd->mi.gd_prvspace->idlestack)];
2520 /* Set the IO permission bitmap (empty due to tss seg limit) */
2521 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2523 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2524 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2525 gd->gd_common_tssd = *gd->gd_tss_gdt;
2528 /* Set up the fast syscall stuff */
2529 msr = rdmsr(MSR_EFER) | EFER_SCE;
2530 wrmsr(MSR_EFER, msr);
2531 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2532 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2533 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2534 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2535 wrmsr(MSR_STAR, msr);
2536 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2538 getmemsize(kmdp, physfree);
2539 init_param2(physmem);
2541 /* now running on new page tables, configured,and u/iom is accessible */
2543 /* Map the message buffer. */
2545 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2546 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2549 msgbufinit(msgbufp, MSGBUF_SIZE);
2552 /* transfer to user mode */
2554 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2555 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2556 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2562 /* setup proc 0's pcb */
2563 thread0.td_pcb->pcb_flags = 0;
2564 thread0.td_pcb->pcb_cr3 = KPML4phys;
2565 thread0.td_pcb->pcb_ext = NULL;
2566 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2568 /* Location of kernel stack for locore */
2569 return ((u_int64_t)thread0.td_pcb);
2573 * Initialize machine-dependant portions of the global data structure.
2574 * Note that the global data area and cpu0's idlestack in the private
2575 * data space were allocated in locore.
2577 * Note: the idlethread's cpl is 0
2579 * WARNING! Called from early boot, 'mycpu' may not work yet.
2582 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2585 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2587 lwkt_init_thread(&gd->mi.gd_idlethread,
2588 gd->mi.gd_prvspace->idlestack,
2589 sizeof(gd->mi.gd_prvspace->idlestack),
2591 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2592 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2593 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2594 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2598 * We only have to check for DMAP bounds, the globaldata space is
2599 * actually part of the kernel_map so we don't have to waste time
2600 * checking CPU_prvspace[*].
2603 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2606 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2607 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2611 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2617 globaldata_find(int cpu)
2619 KKASSERT(cpu >= 0 && cpu < ncpus);
2620 return(&CPU_prvspace[cpu]->mdglobaldata.mi);
2624 * This path should be safe from the SYSRET issue because only stopped threads
2625 * can have their %rip adjusted this way (and all heavy weight thread switches
2626 * clear QUICKREF and thus do not use SYSRET). However, the code path is
2627 * convoluted so add a safety by forcing %rip to be cannonical.
2630 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2632 if (addr & 0x0000800000000000LLU)
2633 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU;
2635 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU;
2640 ptrace_single_step(struct lwp *lp)
2642 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2647 fill_regs(struct lwp *lp, struct reg *regs)
2649 struct trapframe *tp;
2651 if ((tp = lp->lwp_md.md_regs) == NULL)
2653 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2658 set_regs(struct lwp *lp, struct reg *regs)
2660 struct trapframe *tp;
2662 tp = lp->lwp_md.md_regs;
2663 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2664 !CS_SECURE(regs->r_cs))
2666 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2672 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2674 struct env87 *penv_87 = &sv_87->sv_env;
2675 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2678 /* FPU control/status */
2679 penv_87->en_cw = penv_xmm->en_cw;
2680 penv_87->en_sw = penv_xmm->en_sw;
2681 penv_87->en_tw = penv_xmm->en_tw;
2682 penv_87->en_fip = penv_xmm->en_fip;
2683 penv_87->en_fcs = penv_xmm->en_fcs;
2684 penv_87->en_opcode = penv_xmm->en_opcode;
2685 penv_87->en_foo = penv_xmm->en_foo;
2686 penv_87->en_fos = penv_xmm->en_fos;
2689 for (i = 0; i < 8; ++i)
2690 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2694 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2696 struct env87 *penv_87 = &sv_87->sv_env;
2697 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2700 /* FPU control/status */
2701 penv_xmm->en_cw = penv_87->en_cw;
2702 penv_xmm->en_sw = penv_87->en_sw;
2703 penv_xmm->en_tw = penv_87->en_tw;
2704 penv_xmm->en_fip = penv_87->en_fip;
2705 penv_xmm->en_fcs = penv_87->en_fcs;
2706 penv_xmm->en_opcode = penv_87->en_opcode;
2707 penv_xmm->en_foo = penv_87->en_foo;
2708 penv_xmm->en_fos = penv_87->en_fos;
2711 for (i = 0; i < 8; ++i)
2712 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2716 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2718 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2721 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2722 (struct save87 *)fpregs);
2725 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2730 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2733 set_fpregs_xmm((struct save87 *)fpregs,
2734 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2737 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2742 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2747 dbregs->dr[0] = rdr0();
2748 dbregs->dr[1] = rdr1();
2749 dbregs->dr[2] = rdr2();
2750 dbregs->dr[3] = rdr3();
2751 dbregs->dr[4] = rdr4();
2752 dbregs->dr[5] = rdr5();
2753 dbregs->dr[6] = rdr6();
2754 dbregs->dr[7] = rdr7();
2757 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2759 dbregs->dr[0] = pcb->pcb_dr0;
2760 dbregs->dr[1] = pcb->pcb_dr1;
2761 dbregs->dr[2] = pcb->pcb_dr2;
2762 dbregs->dr[3] = pcb->pcb_dr3;
2765 dbregs->dr[6] = pcb->pcb_dr6;
2766 dbregs->dr[7] = pcb->pcb_dr7;
2771 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2774 load_dr0(dbregs->dr[0]);
2775 load_dr1(dbregs->dr[1]);
2776 load_dr2(dbregs->dr[2]);
2777 load_dr3(dbregs->dr[3]);
2778 load_dr4(dbregs->dr[4]);
2779 load_dr5(dbregs->dr[5]);
2780 load_dr6(dbregs->dr[6]);
2781 load_dr7(dbregs->dr[7]);
2784 struct ucred *ucred;
2786 uint64_t mask1, mask2;
2789 * Don't let an illegal value for dr7 get set. Specifically,
2790 * check for undefined settings. Setting these bit patterns
2791 * result in undefined behaviour and can lead to an unexpected
2794 /* JG this loop looks unreadable */
2795 /* Check 4 2-bit fields for invalid patterns.
2796 * These fields are R/Wi, for i = 0..3
2798 /* Is 10 in LENi allowed when running in compatibility mode? */
2799 /* Pattern 10 in R/Wi might be used to indicate
2800 * breakpoint on I/O. Further analysis should be
2801 * carried to decide if it is safe and useful to
2802 * provide access to that capability
2804 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2805 i++, mask1 <<= 4, mask2 <<= 4)
2806 if ((dbregs->dr[7] & mask1) == mask2)
2809 pcb = lp->lwp_thread->td_pcb;
2810 ucred = lp->lwp_proc->p_ucred;
2813 * Don't let a process set a breakpoint that is not within the
2814 * process's address space. If a process could do this, it
2815 * could halt the system by setting a breakpoint in the kernel
2816 * (if ddb was enabled). Thus, we need to check to make sure
2817 * that no breakpoints are being enabled for addresses outside
2818 * process's address space, unless, perhaps, we were called by
2821 * XXX - what about when the watched area of the user's
2822 * address space is written into from within the kernel
2823 * ... wouldn't that still cause a breakpoint to be generated
2824 * from within kernel mode?
2827 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2828 if (dbregs->dr[7] & 0x3) {
2829 /* dr0 is enabled */
2830 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2834 if (dbregs->dr[7] & (0x3<<2)) {
2835 /* dr1 is enabled */
2836 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2840 if (dbregs->dr[7] & (0x3<<4)) {
2841 /* dr2 is enabled */
2842 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2846 if (dbregs->dr[7] & (0x3<<6)) {
2847 /* dr3 is enabled */
2848 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2853 pcb->pcb_dr0 = dbregs->dr[0];
2854 pcb->pcb_dr1 = dbregs->dr[1];
2855 pcb->pcb_dr2 = dbregs->dr[2];
2856 pcb->pcb_dr3 = dbregs->dr[3];
2857 pcb->pcb_dr6 = dbregs->dr[6];
2858 pcb->pcb_dr7 = dbregs->dr[7];
2860 pcb->pcb_flags |= PCB_DBREGS;
2867 * Return > 0 if a hardware breakpoint has been hit, and the
2868 * breakpoint was in user space. Return 0, otherwise.
2871 user_dbreg_trap(void)
2873 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2874 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2875 int nbp; /* number of breakpoints that triggered */
2876 caddr_t addr[4]; /* breakpoint addresses */
2880 if ((dr7 & 0xff) == 0) {
2882 * all GE and LE bits in the dr7 register are zero,
2883 * thus the trap couldn't have been caused by the
2884 * hardware debug registers
2895 * None of the breakpoint bits are set meaning this
2896 * trap was not caused by any of the debug registers
2902 * at least one of the breakpoints were hit, check to see
2903 * which ones and if any of them are user space addresses
2907 addr[nbp++] = (caddr_t)rdr0();
2910 addr[nbp++] = (caddr_t)rdr1();
2913 addr[nbp++] = (caddr_t)rdr2();
2916 addr[nbp++] = (caddr_t)rdr3();
2919 for (i=0; i<nbp; i++) {
2921 (caddr_t)VM_MAX_USER_ADDRESS) {
2923 * addr[i] is in user space
2930 * None of the breakpoints are in user space.
2938 Debugger(const char *msg)
2940 kprintf("Debugger(\"%s\") called.\n", msg);
2947 * Provide inb() and outb() as functions. They are normally only
2948 * available as macros calling inlined functions, thus cannot be
2949 * called inside DDB.
2951 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2957 /* silence compiler warnings */
2959 void outb(u_int, u_char);
2966 * We use %%dx and not %1 here because i/o is done at %dx and not at
2967 * %edx, while gcc generates inferior code (movw instead of movl)
2968 * if we tell it to load (u_short) port.
2970 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2975 outb(u_int port, u_char data)
2979 * Use an unnecessary assignment to help gcc's register allocator.
2980 * This make a large difference for gcc-1.40 and a tiny difference
2981 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2982 * best results. gcc-2.6.0 can't handle this.
2985 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2993 * initialize all the SMP locks
2996 /* critical region when masking or unmasking interupts */
2997 struct spinlock_deprecated imen_spinlock;
2999 /* lock region used by kernel profiling */
3000 struct spinlock_deprecated mcount_spinlock;
3002 /* locks com (tty) data/hardware accesses: a FASTINTR() */
3003 struct spinlock_deprecated com_spinlock;
3005 /* lock regions around the clock hardware */
3006 struct spinlock_deprecated clock_spinlock;
3012 * Get the initial mplock with a count of 1 for the BSP.
3013 * This uses a LOGICAL cpu ID, ie BSP == 0.
3015 cpu_get_initial_mplock();
3017 spin_init_deprecated(&mcount_spinlock);
3018 spin_init_deprecated(&imen_spinlock);
3019 spin_init_deprecated(&com_spinlock);
3020 spin_init_deprecated(&clock_spinlock);
3022 /* our token pool needs to work early */
3023 lwkt_token_pool_init();
3027 cpu_mwait_hint_valid(uint32_t hint)
3031 cx_idx = MWAIT_EAX_TO_CX(hint);
3032 if (cx_idx >= CPU_MWAIT_CX_MAX)
3035 sub = MWAIT_EAX_TO_CX_SUB(hint);
3036 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
3043 cpu_mwait_cx_no_bmsts(void)
3045 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
3049 cpu_mwait_cx_no_bmarb(void)
3051 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB);
3055 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto)
3057 int old_cx_idx, sub = 0;
3060 old_cx_idx = MWAIT_EAX_TO_CX(hint);
3061 sub = MWAIT_EAX_TO_CX_SUB(hint);
3062 } else if (hint == CPU_MWAIT_HINT_AUTO) {
3063 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
3064 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
3065 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
3067 old_cx_idx = CPU_MWAIT_CX_MAX;
3070 if (!CPU_MWAIT_HAS_CX)
3071 strlcpy(name, "NONE", namelen);
3072 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
3073 strlcpy(name, "AUTO", namelen);
3074 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
3075 strlcpy(name, "AUTODEEP", namelen);
3076 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
3077 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
3078 strlcpy(name, "INVALID", namelen);
3080 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub);
3086 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto)
3088 int cx_idx, sub, hint;
3091 if (allow_auto && strcmp(name, "AUTO") == 0) {
3092 hint = CPU_MWAIT_HINT_AUTO;
3093 cx_idx = CPU_MWAIT_C2;
3096 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
3097 hint = CPU_MWAIT_HINT_AUTODEEP;
3098 cx_idx = CPU_MWAIT_C3;
3102 if (strlen(name) < 4 || toupper(name[0]) != 'C')
3107 cx_idx = strtol(start, &ptr, 10);
3108 if (ptr == start || *ptr != '/')
3110 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
3116 sub = strtol(start, &ptr, 10);
3119 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
3122 hint = MWAIT_EAX_HINT(cx_idx, sub);
3129 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx)
3131 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
3133 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
3136 error = cputimer_intr_powersave_addreq();
3139 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
3140 cputimer_intr_powersave_remreq();
3146 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
3147 boolean_t allow_auto)
3149 int error, cx_idx, old_cx_idx, hint;
3150 char name[CPU_MWAIT_CX_NAMELEN];
3153 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name),
3156 error = sysctl_handle_string(oidp, name, sizeof(name), req);
3157 if (error != 0 || req->newptr == NULL)
3160 if (!CPU_MWAIT_HAS_CX)
3163 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto);
3167 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
3176 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name)
3178 int error, cx_idx, old_cx_idx, hint;
3179 char name[CPU_MWAIT_CX_NAMELEN];
3181 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension"));
3184 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
3186 strlcpy(name, cx_name, sizeof(name));
3187 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
3191 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
3200 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
3202 int hint = cpu_mwait_halt_global;
3203 int error, cx_idx, cpu;
3204 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN];
3206 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
3208 error = sysctl_handle_string(oidp, name, sizeof(name), req);
3209 if (error != 0 || req->newptr == NULL)
3212 if (!CPU_MWAIT_HAS_CX)
3215 /* Save name for later per-cpu CX configuration */
3216 strlcpy(cx_name, name, sizeof(cx_name));
3218 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
3222 /* Change per-cpu CX configuration */
3223 for (cpu = 0; cpu < ncpus; ++cpu) {
3224 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name);
3229 cpu_mwait_halt_global = hint;
3234 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
3236 struct cpu_idle_stat *stat = arg1;
3239 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3245 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
3249 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
3250 &cpu_mwait_spin, FALSE);
3255 * This manual debugging code is called unconditionally from Xtimer
3256 * (the per-cpu timer interrupt) whether the current thread is in a
3257 * critical section or not) and can be useful in tracking down lockups.
3259 * NOTE: MANUAL DEBUG CODE
3262 static int saveticks[SMP_MAXCPU];
3263 static int savecounts[SMP_MAXCPU];
3267 pcpu_timer_always(struct intrframe *frame)
3270 globaldata_t gd = mycpu;
3271 int cpu = gd->gd_cpuid;
3277 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
3278 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
3281 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
3282 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
3284 for (i = 0; buf[i]; ++i) {
3285 gptr[i] = 0x0700 | (unsigned char)buf[i];
3289 if (saveticks[gd->gd_cpuid] != ticks) {
3290 saveticks[gd->gd_cpuid] = ticks;
3291 savecounts[gd->gd_cpuid] = 0;
3293 ++savecounts[gd->gd_cpuid];
3294 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
3295 panic("cpud %d panicing on ticks failure",
3298 for (i = 0; i < ncpus; ++i) {
3300 if (saveticks[i] && panicstr == NULL) {
3301 delta = saveticks[i] - ticks;
3302 if (delta < -10 || delta > 10) {
3303 panic("cpu %d panicing on cpu %d watchdog",